From patchwork Fri Jul 26 00:12:05 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Lucas De Marchi X-Patchwork-Id: 11060069 Return-Path: Received: from mail.wl.linuxfoundation.org (pdx-wl-mail.web.codeaurora.org [172.30.200.125]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id 9AF4014DB for ; Fri, 26 Jul 2019 00:12:22 +0000 (UTC) Received: from mail.wl.linuxfoundation.org (localhost [127.0.0.1]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id 8AB23200E5 for ; Fri, 26 Jul 2019 00:12:22 +0000 (UTC) Received: by mail.wl.linuxfoundation.org (Postfix, from userid 486) id 7EC7D28A71; Fri, 26 Jul 2019 00:12:22 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on pdx-wl-mail.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-5.2 required=2.0 tests=BAYES_00,MAILING_LIST_MULTI, RCVD_IN_DNSWL_MED autolearn=ham version=3.3.1 Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher DHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.wl.linuxfoundation.org (Postfix) with ESMTPS id 1FE08200E5 for ; Fri, 26 Jul 2019 00:12:22 +0000 (UTC) Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id 2023E6E83B; Fri, 26 Jul 2019 00:12:21 +0000 (UTC) X-Original-To: intel-gfx@lists.freedesktop.org Delivered-To: intel-gfx@lists.freedesktop.org Received: from mga14.intel.com (mga14.intel.com [192.55.52.115]) by gabe.freedesktop.org (Postfix) with ESMTPS id 0176B6E839 for ; Fri, 26 Jul 2019 00:12:16 +0000 (UTC) X-Amp-Result: SKIPPED(no attachment in message) X-Amp-File-Uploaded: False Received: from fmsmga003.fm.intel.com ([10.253.24.29]) by fmsmga103.fm.intel.com with ESMTP/TLS/DHE-RSA-AES256-GCM-SHA384; 25 Jul 2019 17:12:16 -0700 X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.64,308,1559545200"; d="scan'208";a="178181702" Received: from ldmartin-desk1.jf.intel.com (HELO ldmartin-desk1.intel.com) ([10.24.9.40]) by FMSMGA003.fm.intel.com with ESMTP; 25 Jul 2019 17:12:16 -0700 From: Lucas De Marchi To: intel-gfx@lists.freedesktop.org Date: Thu, 25 Jul 2019 17:12:05 -0700 Message-Id: <20190726001208.6971-2-lucas.demarchi@intel.com> X-Mailer: git-send-email 2.21.0 In-Reply-To: <20190726001208.6971-1-lucas.demarchi@intel.com> References: <20190726001208.6971-1-lucas.demarchi@intel.com> MIME-Version: 1.0 Subject: [Intel-gfx] [PATCH 1/4] drm/i915/tgl: Move fault registers to their new offset X-BeenThere: intel-gfx@lists.freedesktop.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: Intel graphics driver community testing & development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: intel-gfx-bounces@lists.freedesktop.org Sender: "Intel-gfx" X-Virus-Scanned: ClamAV using ClamSMTP The fault registers moved to another offset. The old location is now taken by the global MOCS registers, to be added in a follow up change. Based on previous patches by Michel Thierry . Cc: Daniele Ceraolo Spurio Signed-off-by: Lucas De Marchi Reviewed-by: Daniele Ceraolo Spurio --- drivers/gpu/drm/i915/gt/intel_gt.c | 24 ++++++++++++++++++++---- drivers/gpu/drm/i915/i915_gpu_error.c | 12 ++++++++++-- drivers/gpu/drm/i915/i915_reg.h | 3 +++ 3 files changed, 33 insertions(+), 6 deletions(-) diff --git a/drivers/gpu/drm/i915/gt/intel_gt.c b/drivers/gpu/drm/i915/gt/intel_gt.c index f7e69db4019d..caa07eb20a64 100644 --- a/drivers/gpu/drm/i915/gt/intel_gt.c +++ b/drivers/gpu/drm/i915/gt/intel_gt.c @@ -79,7 +79,10 @@ intel_gt_clear_error_registers(struct intel_gt *gt, I915_MASTER_ERROR_INTERRUPT); } - if (INTEL_GEN(i915) >= 8) { + if (INTEL_GEN(i915) >= 12) { + rmw_clear(uncore, GEN12_RING_FAULT_REG, RING_FAULT_VALID); + intel_uncore_posting_read(uncore, GEN12_RING_FAULT_REG); + } else if (INTEL_GEN(i915) >= 8) { rmw_clear(uncore, GEN8_RING_FAULT_REG, RING_FAULT_VALID); intel_uncore_posting_read(uncore, GEN8_RING_FAULT_REG); } else if (INTEL_GEN(i915) >= 6) { @@ -117,14 +120,27 @@ static void gen6_check_faults(struct intel_gt *gt) static void gen8_check_faults(struct intel_gt *gt) { struct intel_uncore *uncore = gt->uncore; - u32 fault = intel_uncore_read(uncore, GEN8_RING_FAULT_REG); + i915_reg_t fault_reg, fault_data0_reg, fault_data1_reg; + u32 fault; + + if (INTEL_GEN(gt->i915) >= 12) { + fault_reg = GEN12_RING_FAULT_REG; + fault_data0_reg = GEN12_FAULT_TLB_DATA0; + fault_data1_reg = GEN12_FAULT_TLB_DATA1; + } else { + fault_reg = GEN8_RING_FAULT_REG; + fault_data0_reg = GEN8_FAULT_TLB_DATA0; + fault_data1_reg = GEN8_FAULT_TLB_DATA1; + } + fault = intel_uncore_read(uncore, fault_reg); if (fault & RING_FAULT_VALID) { u32 fault_data0, fault_data1; u64 fault_addr; - fault_data0 = intel_uncore_read(uncore, GEN8_FAULT_TLB_DATA0); - fault_data1 = intel_uncore_read(uncore, GEN8_FAULT_TLB_DATA1); + fault_data0 = intel_uncore_read(uncore, fault_data0_reg); + fault_data1 = intel_uncore_read(uncore, fault_data1_reg); + fault_addr = ((u64)(fault_data1 & FAULT_VA_HIGH_BITS) << 44) | ((u64)fault_data0 << 12); diff --git a/drivers/gpu/drm/i915/i915_gpu_error.c b/drivers/gpu/drm/i915/i915_gpu_error.c index 56dfc2650836..41a14f40a8c7 100644 --- a/drivers/gpu/drm/i915/i915_gpu_error.c +++ b/drivers/gpu/drm/i915/i915_gpu_error.c @@ -1106,7 +1106,10 @@ static void error_record_engine_registers(struct i915_gpu_state *error, if (INTEL_GEN(dev_priv) >= 6) { ee->rc_psmi = ENGINE_READ(engine, RING_PSMI_CTL); - if (INTEL_GEN(dev_priv) >= 8) + + if (INTEL_GEN(dev_priv) >= 12) + ee->fault_reg = I915_READ(GEN12_RING_FAULT_REG); + else if (INTEL_GEN(dev_priv) >= 8) ee->fault_reg = I915_READ(GEN8_RING_FAULT_REG); else ee->fault_reg = GEN6_RING_FAULT_REG_READ(engine); @@ -1497,7 +1500,12 @@ static void capture_reg_state(struct i915_gpu_state *error) if (IS_GEN(i915, 7)) error->err_int = intel_uncore_read(uncore, GEN7_ERR_INT); - if (INTEL_GEN(i915) >= 8) { + if (INTEL_GEN(i915) >= 12) { + error->fault_data0 = intel_uncore_read(uncore, + GEN12_FAULT_TLB_DATA0); + error->fault_data1 = intel_uncore_read(uncore, + GEN12_FAULT_TLB_DATA1); + } else if (INTEL_GEN(i915) >= 8) { error->fault_data0 = intel_uncore_read(uncore, GEN8_FAULT_TLB_DATA0); error->fault_data1 = intel_uncore_read(uncore, diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h index 24f2a52a2b42..19e72f0c73d8 100644 --- a/drivers/gpu/drm/i915/i915_reg.h +++ b/drivers/gpu/drm/i915/i915_reg.h @@ -2490,6 +2490,7 @@ enum i915_power_well_id { #define RENDER_HWS_PGA_GEN7 _MMIO(0x04080) #define RING_FAULT_REG(engine) _MMIO(0x4094 + 0x100 * (engine)->hw_id) #define GEN8_RING_FAULT_REG _MMIO(0x4094) +#define GEN12_RING_FAULT_REG _MMIO(0xcec4) #define GEN8_RING_FAULT_ENGINE_ID(x) (((x) >> 12) & 0x7) #define RING_FAULT_GTTSEL_MASK (1 << 11) #define RING_FAULT_SRCID(x) (((x) >> 3) & 0xff) @@ -2633,6 +2634,8 @@ enum i915_power_well_id { #define GEN8_FAULT_TLB_DATA0 _MMIO(0x4b10) #define GEN8_FAULT_TLB_DATA1 _MMIO(0x4b14) +#define GEN12_FAULT_TLB_DATA0 _MMIO(0xceb8) +#define GEN12_FAULT_TLB_DATA1 _MMIO(0xcebc) #define FAULT_VA_HIGH_BITS (0xf << 0) #define FAULT_GTT_SEL (1 << 4) From patchwork Fri Jul 26 00:12:06 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Lucas De Marchi X-Patchwork-Id: 11060071 Return-Path: Received: from mail.wl.linuxfoundation.org (pdx-wl-mail.web.codeaurora.org [172.30.200.125]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id 8450D912 for ; Fri, 26 Jul 2019 00:12:23 +0000 (UTC) Received: from mail.wl.linuxfoundation.org (localhost [127.0.0.1]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id 747BB200E5 for ; Fri, 26 Jul 2019 00:12:23 +0000 (UTC) Received: by mail.wl.linuxfoundation.org (Postfix, from userid 486) id 68BEA28A71; Fri, 26 Jul 2019 00:12:23 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on pdx-wl-mail.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-5.2 required=2.0 tests=BAYES_00,MAILING_LIST_MULTI, RCVD_IN_DNSWL_MED autolearn=ham version=3.3.1 Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher DHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.wl.linuxfoundation.org (Postfix) with ESMTPS id 095BD200E5 for ; Fri, 26 Jul 2019 00:12:23 +0000 (UTC) Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id DAF0F6E83C; Fri, 26 Jul 2019 00:12:20 +0000 (UTC) X-Original-To: intel-gfx@lists.freedesktop.org Delivered-To: intel-gfx@lists.freedesktop.org Received: from mga14.intel.com (mga14.intel.com [192.55.52.115]) by gabe.freedesktop.org (Postfix) with ESMTPS id 5E5A46E82C for ; Fri, 26 Jul 2019 00:12:17 +0000 (UTC) X-Amp-Result: SKIPPED(no attachment in message) X-Amp-File-Uploaded: False Received: from fmsmga003.fm.intel.com ([10.253.24.29]) by fmsmga103.fm.intel.com with ESMTP/TLS/DHE-RSA-AES256-GCM-SHA384; 25 Jul 2019 17:12:17 -0700 X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.64,308,1559545200"; d="scan'208";a="178181705" Received: from ldmartin-desk1.jf.intel.com (HELO ldmartin-desk1.intel.com) ([10.24.9.40]) by FMSMGA003.fm.intel.com with ESMTP; 25 Jul 2019 17:12:16 -0700 From: Lucas De Marchi To: intel-gfx@lists.freedesktop.org Date: Thu, 25 Jul 2019 17:12:06 -0700 Message-Id: <20190726001208.6971-3-lucas.demarchi@intel.com> X-Mailer: git-send-email 2.21.0 In-Reply-To: <20190726001208.6971-1-lucas.demarchi@intel.com> References: <20190726001208.6971-1-lucas.demarchi@intel.com> MIME-Version: 1.0 Subject: [Intel-gfx] [PATCH 2/4] drm/i915/tgl: Define MOCS entries for Tigerlake X-BeenThere: intel-gfx@lists.freedesktop.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: Intel graphics driver community testing & development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Mika Kuoppala Errors-To: intel-gfx-bounces@lists.freedesktop.org Sender: "Intel-gfx" X-Virus-Scanned: ClamAV using ClamSMTP From: Tomasz Lis The MOCS table is published as part of bspec, and versioned. Entries are supposed to never be modified, but new ones can be added. Adding entries increases table version. The patch includes version 1 entries. Two of the 3 legacy entries used for gen9 are no longer expected to work. Although we are changing the gen11 table, those changes are supposed to be backward compatible since we are only touching previously undefined entries. v2: Add the missing entries in 49-51 range and replace "HW reserved" terminology to what it actually is: L1 is implicitly enabled (from Daniele) Cc: Joonas Lahtinen Cc: Mika Kuoppala Cc: Daniele Ceraolo Spurio Signed-off-by: Tomasz Lis Signed-off-by: Lucas De Marchi --- drivers/gpu/drm/i915/gt/intel_mocs.c | 37 +++++++++++++++++++++++++--- 1 file changed, 34 insertions(+), 3 deletions(-) diff --git a/drivers/gpu/drm/i915/gt/intel_mocs.c b/drivers/gpu/drm/i915/gt/intel_mocs.c index 290a5e9b90b9..ca370c7487f9 100644 --- a/drivers/gpu/drm/i915/gt/intel_mocs.c +++ b/drivers/gpu/drm/i915/gt/intel_mocs.c @@ -62,6 +62,10 @@ struct drm_i915_mocs_table { #define GEN11_NUM_MOCS_ENTRIES 64 /* 63-64 are reserved, but configured. */ /* (e)LLC caching options */ +/* + * Note: LE_0_PAGETABLE works only up to Gen11; for newer gens it means + * the same as LE_UC + */ #define LE_0_PAGETABLE _LE_CACHEABILITY(0) #define LE_1_UC _LE_CACHEABILITY(1) #define LE_2_WT _LE_CACHEABILITY(2) @@ -100,8 +104,9 @@ struct drm_i915_mocs_table { * of bspec. * * Entries not part of the following tables are undefined as far as - * userspace is concerned and shouldn't be relied upon. For the time - * being they will be initialized to PTE. + * userspace is concerned and shouldn't be relied upon. For Gen < 12 + * they will be initialized to PTE. Gen >= 12 onwards don't have a setting for + * PTE. We use the same value, but that actually means Uncached. * * The last two entries are reserved by the hardware. For ICL+ they * should be initialized according to bspec and never used, for older @@ -137,11 +142,13 @@ static const struct drm_i915_mocs_entry broxton_mocs_table[] = { }; #define GEN11_MOCS_ENTRIES \ - /* Base - Uncached (Deprecated) */ \ + /* Gen11: Base - Uncached (Deprecated) */ \ + /* Gen12+: Base - Error (Reserved for Non-Use) */ \ MOCS_ENTRY(I915_MOCS_UNCACHED, \ LE_1_UC | LE_TC_1_LLC, \ L3_1_UC), \ /* Base - L3 + LeCC:PAT (Deprecated) */ \ + /* Gen12+: Base - Reserved */ \ MOCS_ENTRY(I915_MOCS_PTE, \ LE_0_PAGETABLE | LE_TC_1_LLC, \ L3_3_WB), \ @@ -233,6 +240,30 @@ static const struct drm_i915_mocs_entry broxton_mocs_table[] = { MOCS_ENTRY(23, \ LE_3_WB | LE_TC_1_LLC | LE_LRUM(3) | LE_RSC(1) | LE_SCC(7), \ L3_3_WB), \ + /* Gen12+: Implicitly enable L1 - HDC:L1 + L3 + LLC */ \ + MOCS_ENTRY(48, \ + LE_3_WB | LE_TC_1_LLC | LE_LRUM(3), \ + L3_3_WB), \ + /* Gen12+: Implicitly enable L1 - HDC:L1 + L3 */ \ + MOCS_ENTRY(49, \ + LE_1_UC | LE_TC_1_LLC, \ + L3_3_WB), \ + /* Gen12+: Implicitly enable L1 - HDC:L1 + LLC */ \ + MOCS_ENTRY(50, \ + LE_3_WB | LE_TC_1_LLC | LE_LRUM(3), \ + L3_1_UC), \ + /* Gen12+: Implicitly enable L1 - HDC:L1 */ \ + MOCS_ENTRY(51, \ + LE_1_UC | LE_TC_1_LLC, \ + L3_1_UC), \ + /* Gen12+: HW Reserved - HW Special Case (CCS) */ \ + MOCS_ENTRY(60, \ + LE_3_WB | LE_TC_1_LLC | LE_LRUM(3), \ + L3_1_UC), \ + /* Gen12+: HW Reserved - HW Special Case (Displayable) */ \ + MOCS_ENTRY(61, \ + LE_1_UC | LE_TC_1_LLC | LE_SCF(1), \ + L3_3_WB), \ /* HW Reserved - SW program but never use */ \ MOCS_ENTRY(62, \ LE_3_WB | LE_TC_1_LLC | LE_LRUM(3), \ From patchwork Fri Jul 26 00:12:07 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Lucas De Marchi X-Patchwork-Id: 11060073 Return-Path: Received: from mail.wl.linuxfoundation.org (pdx-wl-mail.web.codeaurora.org [172.30.200.125]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id A9AED14DB for ; Fri, 26 Jul 2019 00:12:30 +0000 (UTC) Received: from mail.wl.linuxfoundation.org (localhost [127.0.0.1]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id 99D9028A74 for ; Fri, 26 Jul 2019 00:12:30 +0000 (UTC) Received: by mail.wl.linuxfoundation.org (Postfix, from userid 486) id 8D3E628A78; Fri, 26 Jul 2019 00:12:30 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on pdx-wl-mail.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-5.2 required=2.0 tests=BAYES_00,MAILING_LIST_MULTI, RCVD_IN_DNSWL_MED autolearn=ham version=3.3.1 Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher DHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.wl.linuxfoundation.org (Postfix) with ESMTPS id EEB1428A74 for ; Fri, 26 Jul 2019 00:12:29 +0000 (UTC) Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id 87C176E83D; Fri, 26 Jul 2019 00:12:29 +0000 (UTC) X-Original-To: intel-gfx@lists.freedesktop.org Delivered-To: intel-gfx@lists.freedesktop.org Received: from mga14.intel.com (mga14.intel.com [192.55.52.115]) by gabe.freedesktop.org (Postfix) with ESMTPS id D1AA56E839 for ; Fri, 26 Jul 2019 00:12:17 +0000 (UTC) X-Amp-Result: SKIPPED(no attachment in message) X-Amp-File-Uploaded: False Received: from fmsmga003.fm.intel.com ([10.253.24.29]) by fmsmga103.fm.intel.com with ESMTP/TLS/DHE-RSA-AES256-GCM-SHA384; 25 Jul 2019 17:12:17 -0700 X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.64,308,1559545200"; d="scan'208";a="178181709" Received: from ldmartin-desk1.jf.intel.com (HELO ldmartin-desk1.intel.com) ([10.24.9.40]) by FMSMGA003.fm.intel.com with ESMTP; 25 Jul 2019 17:12:17 -0700 From: Lucas De Marchi To: intel-gfx@lists.freedesktop.org Date: Thu, 25 Jul 2019 17:12:07 -0700 Message-Id: <20190726001208.6971-4-lucas.demarchi@intel.com> X-Mailer: git-send-email 2.21.0 In-Reply-To: <20190726001208.6971-1-lucas.demarchi@intel.com> References: <20190726001208.6971-1-lucas.demarchi@intel.com> MIME-Version: 1.0 Subject: [Intel-gfx] [PATCH 3/4] drm/i915/tgl: Tigerlake only has global MOCS registers X-BeenThere: intel-gfx@lists.freedesktop.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: Intel graphics driver community testing & development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Michel Thierry Errors-To: intel-gfx-bounces@lists.freedesktop.org Sender: "Intel-gfx" X-Virus-Scanned: ClamAV using ClamSMTP From: Michel Thierry Until Icelake, each engine had its own set of 64 MOCS registers. In order to simplify, Tigerlake moves to only 64 Global MOCS registers, which are no longer part of the engine context. Since these registers are now global, they also only need to be initialized once. From Gen12 onwards, MOCS must specify the target cache (3:2) and LRU management (5:4) fields and cannot be programmed to 'use the value from Private PAT', because these fields are no longer part of the PPAT. Also cacheability control (1:0) field has changed, 00 no longer means 'use controls from page table', but uncacheable (UC). v2: Move the changes to the fault registers to a separate commit - the old ones overlap with the range used by the new global MOCS (requested by Daniele) Cc: Daniele Ceraolo Spurio Cc: Tomasz Lis Signed-off-by: Michel Thierry Signed-off-by: Tvrtko Ursulin Signed-off-by: Lucas De Marchi --- drivers/gpu/drm/i915/gt/intel_mocs.c | 47 ++++++++++++++++++++++++ drivers/gpu/drm/i915/gt/intel_mocs.h | 1 + drivers/gpu/drm/i915/i915_drv.h | 2 + drivers/gpu/drm/i915/i915_gem.c | 1 + drivers/gpu/drm/i915/i915_gpu_error.c | 6 ++- drivers/gpu/drm/i915/i915_pci.c | 3 +- drivers/gpu/drm/i915/i915_reg.h | 2 + drivers/gpu/drm/i915/intel_device_info.h | 1 + 8 files changed, 60 insertions(+), 3 deletions(-) diff --git a/drivers/gpu/drm/i915/gt/intel_mocs.c b/drivers/gpu/drm/i915/gt/intel_mocs.c index ca370c7487f9..9399c0ec08f1 100644 --- a/drivers/gpu/drm/i915/gt/intel_mocs.c +++ b/drivers/gpu/drm/i915/gt/intel_mocs.c @@ -377,6 +377,10 @@ void intel_mocs_init_engine(struct intel_engine_cs *engine) unsigned int index; u32 unused_value; + /* Platforms with global MOCS do not need per-engine initialization. */ + if (HAS_GLOBAL_MOCS_REGISTERS(gt->i915)) + return; + /* Called under a blanket forcewake */ assert_forcewakes_active(uncore, FORCEWAKE_ALL); @@ -401,6 +405,46 @@ void intel_mocs_init_engine(struct intel_engine_cs *engine) unused_value); } +/** + * intel_mocs_init_global() - program the global mocs registers + * gt: pointer to struct intel_gt + * + * This function initializes the MOCS global registers. + */ +void intel_mocs_init_global(struct intel_gt *gt) +{ + struct intel_uncore *uncore = gt->uncore; + struct drm_i915_mocs_table table; + unsigned int index; + + if (!HAS_GLOBAL_MOCS_REGISTERS(gt->i915)) + return; + + if (!get_mocs_settings(gt, &table)) + return; + + if (GEM_DEBUG_WARN_ON(table.size > table.n_entries)) + return; + + for (index = 0; index < table.size; index++) + intel_uncore_write(uncore, + GEN12_GLOBAL_MOCS(index), + table.table[index].control_value); + + /* + * Ok, now set the unused entries to uncached. These entries + * are officially undefined and no contract for the contents + * and settings is given for these entries. + * + * Entry 0 in the table is uncached - so we are just writing + * that value to all the used entries. + */ + for (; index < table.n_entries; index++) + intel_uncore_write(uncore, + GEN12_GLOBAL_MOCS(index), + table.table[0].control_value); +} + /** * emit_mocs_control_table() - emit the mocs control table * @rq: Request to set up the MOCS table for. @@ -604,6 +648,9 @@ int intel_rcs_context_init_mocs(struct i915_request *rq) struct drm_i915_mocs_table t; int ret; + if (HAS_GLOBAL_MOCS_REGISTERS(rq->i915)) + return 0; + if (get_mocs_settings(rq->engine->gt, &t)) { /* Program the RCS control registers */ ret = emit_mocs_control_table(rq, &t); diff --git a/drivers/gpu/drm/i915/gt/intel_mocs.h b/drivers/gpu/drm/i915/gt/intel_mocs.h index 8b9813e6f9ac..aa3a2df07c82 100644 --- a/drivers/gpu/drm/i915/gt/intel_mocs.h +++ b/drivers/gpu/drm/i915/gt/intel_mocs.h @@ -56,6 +56,7 @@ struct intel_gt; int intel_rcs_context_init_mocs(struct i915_request *rq); void intel_mocs_init_l3cc_table(struct intel_gt *gt); +void intel_mocs_init_global(struct intel_gt *gt); void intel_mocs_init_engine(struct intel_engine_cs *engine); #endif diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h index 59d4a1146039..a9509bdeb2fa 100644 --- a/drivers/gpu/drm/i915/i915_drv.h +++ b/drivers/gpu/drm/i915/i915_drv.h @@ -2280,6 +2280,8 @@ IS_SUBPLATFORM(const struct drm_i915_private *i915, #define HAS_POOLED_EU(dev_priv) (INTEL_INFO(dev_priv)->has_pooled_eu) +#define HAS_GLOBAL_MOCS_REGISTERS(dev_priv) (INTEL_INFO(dev_priv)->has_global_mocs) + #define INTEL_PCH_DEVICE_ID_MASK 0xff80 #define INTEL_PCH_IBX_DEVICE_ID_TYPE 0x3b00 #define INTEL_PCH_CPT_DEVICE_ID_TYPE 0x1c00 diff --git a/drivers/gpu/drm/i915/i915_gem.c b/drivers/gpu/drm/i915/i915_gem.c index 01dd0d1d9bf6..323218854b94 100644 --- a/drivers/gpu/drm/i915/i915_gem.c +++ b/drivers/gpu/drm/i915/i915_gem.c @@ -1252,6 +1252,7 @@ int i915_gem_init_hw(struct drm_i915_private *i915) goto out; } + intel_mocs_init_global(gt); intel_mocs_init_l3cc_table(gt); intel_engines_set_scheduler_caps(i915); diff --git a/drivers/gpu/drm/i915/i915_gpu_error.c b/drivers/gpu/drm/i915/i915_gpu_error.c index 41a14f40a8c7..146be1ce5ab8 100644 --- a/drivers/gpu/drm/i915/i915_gpu_error.c +++ b/drivers/gpu/drm/i915/i915_gpu_error.c @@ -1524,8 +1524,10 @@ static void capture_reg_state(struct i915_gpu_state *error) if (INTEL_GEN(i915) >= 6) { error->derrmr = intel_uncore_read(uncore, DERRMR); - error->error = intel_uncore_read(uncore, ERROR_GEN6); - error->done_reg = intel_uncore_read(uncore, DONE_REG); + if (INTEL_GEN(i915) < 12) { + error->error = intel_uncore_read(uncore, ERROR_GEN6); + error->done_reg = intel_uncore_read(uncore, DONE_REG); + } } if (INTEL_GEN(i915) >= 5) diff --git a/drivers/gpu/drm/i915/i915_pci.c b/drivers/gpu/drm/i915/i915_pci.c index bd9211b3d76e..a7e1cde4a6d9 100644 --- a/drivers/gpu/drm/i915/i915_pci.c +++ b/drivers/gpu/drm/i915/i915_pci.c @@ -783,7 +783,8 @@ static const struct intel_device_info intel_elkhartlake_info = { [TRANSCODER_D] = TRANSCODER_D_OFFSET, \ [TRANSCODER_DSI_0] = TRANSCODER_DSI0_OFFSET, \ [TRANSCODER_DSI_1] = TRANSCODER_DSI1_OFFSET, \ - } + }, \ + .has_global_mocs = 1 static const struct intel_device_info intel_tigerlake_12_info = { GEN12_FEATURES, diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h index 19e72f0c73d8..3bb83e14661c 100644 --- a/drivers/gpu/drm/i915/i915_reg.h +++ b/drivers/gpu/drm/i915/i915_reg.h @@ -11210,6 +11210,8 @@ enum skl_power_gate { #define PMFLUSH_GAPL3UNBLOCK (1 << 21) #define PMFLUSHDONE_LNEBLK (1 << 22) +#define GEN12_GLOBAL_MOCS(i) _MMIO(0x4000 + (i) * 4) /* Global MOCS regs */ + /* gamt regs */ #define GEN8_L3_LRA_1_GPGPU _MMIO(0x4dd4) #define GEN8_L3_LRA_1_GPGPU_DEFAULT_VALUE_BDW 0x67F1427F /* max/min for LRA1/2 */ diff --git a/drivers/gpu/drm/i915/intel_device_info.h b/drivers/gpu/drm/i915/intel_device_info.h index 4f58e8d71b67..92e0c2e0954c 100644 --- a/drivers/gpu/drm/i915/intel_device_info.h +++ b/drivers/gpu/drm/i915/intel_device_info.h @@ -112,6 +112,7 @@ enum intel_ppgtt_type { func(gpu_reset_clobbers_display); \ func(has_reset_engine); \ func(has_fpga_dbg); \ + func(has_global_mocs); \ func(has_gt_uc); \ func(has_l3_dpf); \ func(has_llc); \ From patchwork Fri Jul 26 00:12:08 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Lucas De Marchi X-Patchwork-Id: 11060067 Return-Path: Received: from mail.wl.linuxfoundation.org (pdx-wl-mail.web.codeaurora.org [172.30.200.125]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id 375D0912 for ; Fri, 26 Jul 2019 00:12:21 +0000 (UTC) Received: from mail.wl.linuxfoundation.org (localhost [127.0.0.1]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id 25D3D28A74 for ; Fri, 26 Jul 2019 00:12:21 +0000 (UTC) Received: by mail.wl.linuxfoundation.org (Postfix, from userid 486) id 1A27228A77; Fri, 26 Jul 2019 00:12:21 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on pdx-wl-mail.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-5.2 required=2.0 tests=BAYES_00,MAILING_LIST_MULTI, RCVD_IN_DNSWL_MED autolearn=ham version=3.3.1 Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher DHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.wl.linuxfoundation.org (Postfix) with ESMTPS id B9380200E5 for ; Fri, 26 Jul 2019 00:12:20 +0000 (UTC) Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id 47F006E839; Fri, 26 Jul 2019 00:12:20 +0000 (UTC) X-Original-To: intel-gfx@lists.freedesktop.org Delivered-To: intel-gfx@lists.freedesktop.org Received: from mga14.intel.com (mga14.intel.com [192.55.52.115]) by gabe.freedesktop.org (Postfix) with ESMTPS id 42CC76E839 for ; Fri, 26 Jul 2019 00:12:18 +0000 (UTC) X-Amp-Result: SKIPPED(no attachment in message) X-Amp-File-Uploaded: False Received: from fmsmga003.fm.intel.com ([10.253.24.29]) by fmsmga103.fm.intel.com with ESMTP/TLS/DHE-RSA-AES256-GCM-SHA384; 25 Jul 2019 17:12:18 -0700 X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.64,308,1559545200"; d="scan'208";a="178181712" Received: from ldmartin-desk1.jf.intel.com (HELO ldmartin-desk1.intel.com) ([10.24.9.40]) by FMSMGA003.fm.intel.com with ESMTP; 25 Jul 2019 17:12:17 -0700 From: Lucas De Marchi To: intel-gfx@lists.freedesktop.org Date: Thu, 25 Jul 2019 17:12:08 -0700 Message-Id: <20190726001208.6971-5-lucas.demarchi@intel.com> X-Mailer: git-send-email 2.21.0 In-Reply-To: <20190726001208.6971-1-lucas.demarchi@intel.com> References: <20190726001208.6971-1-lucas.demarchi@intel.com> MIME-Version: 1.0 Subject: [Intel-gfx] [PATCH 4/4] drm/i915: Move MOCS setup to intel_mocs.c X-BeenThere: intel-gfx@lists.freedesktop.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: Intel graphics driver community testing & development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: intel-gfx-bounces@lists.freedesktop.org Sender: "Intel-gfx" X-Virus-Scanned: ClamAV using ClamSMTP From: Tvrtko Ursulin Hide the details of MOCS setup from i915_gem by moving both current calls into one in intel_mocs_init. Cc: Stuart Summers Signed-off-by: Tvrtko Ursulin Signed-off-by: Lucas De Marchi Reviewed-by: Stuart Summers Link: https://patchwork.freedesktop.org/patch/msgid/20190713010940.17711-21-lucas.demarchi@intel.com --- drivers/gpu/drm/i915/gt/intel_mocs.c | 15 +++++++++++---- drivers/gpu/drm/i915/gt/intel_mocs.h | 3 +-- drivers/gpu/drm/i915/i915_gem.c | 3 +-- 3 files changed, 13 insertions(+), 8 deletions(-) diff --git a/drivers/gpu/drm/i915/gt/intel_mocs.c b/drivers/gpu/drm/i915/gt/intel_mocs.c index 9399c0ec08f1..d437d35f3347 100644 --- a/drivers/gpu/drm/i915/gt/intel_mocs.c +++ b/drivers/gpu/drm/i915/gt/intel_mocs.c @@ -411,14 +411,13 @@ void intel_mocs_init_engine(struct intel_engine_cs *engine) * * This function initializes the MOCS global registers. */ -void intel_mocs_init_global(struct intel_gt *gt) +static void intel_mocs_init_global(struct intel_gt *gt) { struct intel_uncore *uncore = gt->uncore; struct drm_i915_mocs_table table; unsigned int index; - if (!HAS_GLOBAL_MOCS_REGISTERS(gt->i915)) - return; + GEM_BUG_ON(!HAS_GLOBAL_MOCS_REGISTERS(gt->i915)); if (!get_mocs_settings(gt, &table)) return; @@ -587,7 +586,7 @@ static int emit_mocs_l3cc_table(struct i915_request *rq, * * Return: Nothing. */ -void intel_mocs_init_l3cc_table(struct intel_gt *gt) +static void intel_mocs_init_l3cc_table(struct intel_gt *gt) { struct intel_uncore *uncore = gt->uncore; struct drm_i915_mocs_table table; @@ -665,3 +664,11 @@ int intel_rcs_context_init_mocs(struct i915_request *rq) return 0; } + +void intel_mocs_init(struct intel_gt *gt) +{ + intel_mocs_init_l3cc_table(gt); + + if (HAS_GLOBAL_MOCS_REGISTERS(gt->i915)) + intel_mocs_init_global(gt); +} diff --git a/drivers/gpu/drm/i915/gt/intel_mocs.h b/drivers/gpu/drm/i915/gt/intel_mocs.h index aa3a2df07c82..2c5cbf213819 100644 --- a/drivers/gpu/drm/i915/gt/intel_mocs.h +++ b/drivers/gpu/drm/i915/gt/intel_mocs.h @@ -55,8 +55,7 @@ struct intel_engine_cs; struct intel_gt; int intel_rcs_context_init_mocs(struct i915_request *rq); -void intel_mocs_init_l3cc_table(struct intel_gt *gt); -void intel_mocs_init_global(struct intel_gt *gt); +void intel_mocs_init(struct intel_gt *gt); void intel_mocs_init_engine(struct intel_engine_cs *engine); #endif diff --git a/drivers/gpu/drm/i915/i915_gem.c b/drivers/gpu/drm/i915/i915_gem.c index 323218854b94..f57ce0d560dd 100644 --- a/drivers/gpu/drm/i915/i915_gem.c +++ b/drivers/gpu/drm/i915/i915_gem.c @@ -1252,8 +1252,7 @@ int i915_gem_init_hw(struct drm_i915_private *i915) goto out; } - intel_mocs_init_global(gt); - intel_mocs_init_l3cc_table(gt); + intel_mocs_init(gt); intel_engines_set_scheduler_caps(i915);