From patchwork Fri Jul 26 15:58:03 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Michal Wajdeczko X-Patchwork-Id: 11061317 Return-Path: Received: from mail.wl.linuxfoundation.org (pdx-wl-mail.web.codeaurora.org [172.30.200.125]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id 77FE4912 for ; Fri, 26 Jul 2019 15:58:42 +0000 (UTC) Received: from mail.wl.linuxfoundation.org (localhost [127.0.0.1]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id 6784E2889C for ; Fri, 26 Jul 2019 15:58:42 +0000 (UTC) Received: by mail.wl.linuxfoundation.org (Postfix, from userid 486) id 5BD192896F; Fri, 26 Jul 2019 15:58:42 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on pdx-wl-mail.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-5.2 required=2.0 tests=BAYES_00,MAILING_LIST_MULTI, RCVD_IN_DNSWL_MED autolearn=ham version=3.3.1 Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher DHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.wl.linuxfoundation.org (Postfix) with ESMTPS id DB6D02889C for ; Fri, 26 Jul 2019 15:58:41 +0000 (UTC) Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id EB6A56EDB3; Fri, 26 Jul 2019 15:58:40 +0000 (UTC) X-Original-To: intel-gfx@lists.freedesktop.org Delivered-To: intel-gfx@lists.freedesktop.org Received: from mga04.intel.com (mga04.intel.com [192.55.52.120]) by gabe.freedesktop.org (Postfix) with ESMTPS id 6C9FC6EDB1 for ; Fri, 26 Jul 2019 15:58:39 +0000 (UTC) X-Amp-Result: SKIPPED(no attachment in message) X-Amp-File-Uploaded: False Received: from orsmga002.jf.intel.com ([10.7.209.21]) by fmsmga104.fm.intel.com with ESMTP/TLS/DHE-RSA-AES256-GCM-SHA384; 26 Jul 2019 08:58:39 -0700 X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.64,311,1559545200"; d="scan'208";a="181910434" Received: from irvmail001.ir.intel.com ([163.33.26.43]) by orsmga002.jf.intel.com with ESMTP; 26 Jul 2019 08:58:37 -0700 Received: from mwajdecz-MOBL1.ger.corp.intel.com (mwajdecz-mobl1.ger.corp.intel.com [172.28.174.50]) by irvmail001.ir.intel.com (8.14.3/8.13.6/MailSET/Hub) with ESMTP id x6QFwa8L030808; Fri, 26 Jul 2019 16:58:36 +0100 From: Michal Wajdeczko To: intel-gfx@lists.freedesktop.org Date: Fri, 26 Jul 2019 15:58:03 +0000 Message-Id: <20190726155805.2736-1-michal.wajdeczko@intel.com> X-Mailer: git-send-email 2.21.0.windows.1 MIME-Version: 1.0 Subject: [Intel-gfx] [PATCH 1/3] drm/i915/uc: Remove redundant header_offset/size definitions X-BeenThere: intel-gfx@lists.freedesktop.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: Intel graphics driver community testing & development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: intel-gfx-bounces@lists.freedesktop.org Sender: "Intel-gfx" X-Virus-Scanned: ClamAV using ClamSMTP According to Firmware layout definition, CSS header is located in front of the firmware blob, so header offset is always 0. Similarly, size of the CSS header is constant and is 128. While here, move type/status enums up and keep them together. Signed-off-by: Michal Wajdeczko Cc: Daniele Ceraolo Spurio Reviewed-by: Daniele Ceraolo Spurio --- drivers/gpu/drm/i915/gt/uc/intel_uc_fw.c | 23 ++++++++------------ drivers/gpu/drm/i915/gt/uc/intel_uc_fw.h | 9 ++++---- drivers/gpu/drm/i915/gt/uc/intel_uc_fw_abi.h | 2 ++ 3 files changed, 15 insertions(+), 19 deletions(-) diff --git a/drivers/gpu/drm/i915/gt/uc/intel_uc_fw.c b/drivers/gpu/drm/i915/gt/uc/intel_uc_fw.c index 5fbdd17a864b..66bda0c514a3 100644 --- a/drivers/gpu/drm/i915/gt/uc/intel_uc_fw.c +++ b/drivers/gpu/drm/i915/gt/uc/intel_uc_fw.c @@ -218,21 +218,18 @@ void intel_uc_fw_fetch(struct intel_uc_fw *uc_fw, struct drm_i915_private *i915) css = (struct uc_css_header *)fw->data; - /* Firmware bits always start from header */ - uc_fw->header_offset = 0; - uc_fw->header_size = (css->header_size_dw - css->modulus_size_dw - - css->key_size_dw - css->exponent_size_dw) * - sizeof(u32); - - if (uc_fw->header_size != sizeof(struct uc_css_header)) { + /* Check integrity of size values inside CSS header */ + size = (css->header_size_dw - css->key_size_dw - css->modulus_size_dw - + css->exponent_size_dw) * sizeof(u32); + if (size != sizeof(struct uc_css_header)) { DRM_WARN("%s: Mismatched firmware header definition\n", intel_uc_fw_type_repr(uc_fw->type)); err = -ENOEXEC; goto fail; } - /* then, uCode */ - uc_fw->ucode_offset = uc_fw->header_offset + uc_fw->header_size; + /* Firmware blob always starts with the header, then uCode */ + uc_fw->ucode_offset = sizeof(struct uc_css_header); uc_fw->ucode_size = (css->size_dw - css->header_size_dw) * sizeof(u32); /* now RSA */ @@ -246,7 +243,7 @@ void intel_uc_fw_fetch(struct intel_uc_fw *uc_fw, struct drm_i915_private *i915) uc_fw->rsa_size = css->key_size_dw * sizeof(u32); /* At least, it should have header, uCode and RSA. Size of all three. */ - size = uc_fw->header_size + uc_fw->ucode_size + uc_fw->rsa_size; + size = sizeof(struct uc_css_header) + uc_fw->ucode_size + uc_fw->rsa_size; if (fw->size < size) { DRM_WARN("%s: Truncated firmware (%zu, expected %zu)\n", intel_uc_fw_type_repr(uc_fw->type), fw->size, size); @@ -371,7 +368,7 @@ static int uc_fw_xfer(struct intel_uc_fw *uc_fw, struct intel_gt *gt, intel_uncore_forcewake_get(uncore, FORCEWAKE_ALL); /* Set the source address for the uCode */ - offset = uc_fw_ggtt_offset(uc_fw, gt->ggtt) + uc_fw->header_offset; + offset = uc_fw_ggtt_offset(uc_fw, gt->ggtt); GEM_BUG_ON(upper_32_bits(offset) & 0xFFFF0000); intel_uncore_write_fw(uncore, DMA_ADDR_0_LOW, lower_32_bits(offset)); intel_uncore_write_fw(uncore, DMA_ADDR_0_HIGH, upper_32_bits(offset)); @@ -385,7 +382,7 @@ static int uc_fw_xfer(struct intel_uc_fw *uc_fw, struct intel_gt *gt, * via DMA, excluding any other components */ intel_uncore_write_fw(uncore, DMA_COPY_SIZE, - uc_fw->header_size + uc_fw->ucode_size); + uc_fw->ucode_offset + uc_fw->ucode_size); /* Start the DMA */ intel_uncore_write_fw(uncore, DMA_CTRL, @@ -539,8 +536,6 @@ void intel_uc_fw_dump(const struct intel_uc_fw *uc_fw, struct drm_printer *p) drm_printf(p, "\tversion: wanted %u.%u, found %u.%u\n", uc_fw->major_ver_wanted, uc_fw->minor_ver_wanted, uc_fw->major_ver_found, uc_fw->minor_ver_found); - drm_printf(p, "\theader: offset %u, size %u\n", - uc_fw->header_offset, uc_fw->header_size); drm_printf(p, "\tuCode: offset %u, size %u\n", uc_fw->ucode_offset, uc_fw->ucode_size); drm_printf(p, "\tRSA: offset %u, size %u\n", diff --git a/drivers/gpu/drm/i915/gt/uc/intel_uc_fw.h b/drivers/gpu/drm/i915/gt/uc/intel_uc_fw.h index eddbb237fabe..a8048f91f0da 100644 --- a/drivers/gpu/drm/i915/gt/uc/intel_uc_fw.h +++ b/drivers/gpu/drm/i915/gt/uc/intel_uc_fw.h @@ -26,6 +26,7 @@ #define _INTEL_UC_FW_H_ #include +#include "intel_uc_fw_abi.h" #include "i915_gem.h" struct drm_printer; @@ -57,10 +58,11 @@ enum intel_uc_fw_type { * of fetching, caching, and loading the firmware image into the uC. */ struct intel_uc_fw { + enum intel_uc_fw_type type; + enum intel_uc_fw_status status; const char *path; size_t size; struct drm_i915_gem_object *obj; - enum intel_uc_fw_status status; /* * The firmware build process will generate a version header file with major and @@ -72,9 +74,6 @@ struct intel_uc_fw { u16 major_ver_found; u16 minor_ver_found; - enum intel_uc_fw_type type; - u32 header_size; - u32 header_offset; u32 rsa_size; u32 rsa_offset; u32 ucode_size; @@ -163,7 +162,7 @@ static inline u32 intel_uc_fw_get_upload_size(struct intel_uc_fw *uc_fw) if (!intel_uc_fw_is_available(uc_fw)) return 0; - return uc_fw->header_size + uc_fw->ucode_size; + return sizeof(struct uc_css_header) + uc_fw->ucode_size; } void intel_uc_fw_init_early(struct intel_uc_fw *uc_fw, diff --git a/drivers/gpu/drm/i915/gt/uc/intel_uc_fw_abi.h b/drivers/gpu/drm/i915/gt/uc/intel_uc_fw_abi.h index 545e86c52a9e..ae58e8a8c53b 100644 --- a/drivers/gpu/drm/i915/gt/uc/intel_uc_fw_abi.h +++ b/drivers/gpu/drm/i915/gt/uc/intel_uc_fw_abi.h @@ -7,6 +7,7 @@ #define _INTEL_UC_FW_ABI_H #include +#include /** * DOC: Firmware Layout @@ -76,5 +77,6 @@ struct uc_css_header { u32 reserved[14]; u32 header_info; } __packed; +static_assert(sizeof(struct uc_css_header) == 128); #endif /* _INTEL_UC_FW_ABI_H */ From patchwork Fri Jul 26 15:58:04 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Michal Wajdeczko X-Patchwork-Id: 11061315 Return-Path: Received: from mail.wl.linuxfoundation.org (pdx-wl-mail.web.codeaurora.org [172.30.200.125]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id 472D9912 for ; Fri, 26 Jul 2019 15:58:41 +0000 (UTC) Received: from mail.wl.linuxfoundation.org (localhost [127.0.0.1]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id 368AA2889C for ; Fri, 26 Jul 2019 15:58:41 +0000 (UTC) Received: by mail.wl.linuxfoundation.org (Postfix, from userid 486) id 2A8F52896F; Fri, 26 Jul 2019 15:58:41 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on pdx-wl-mail.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-5.2 required=2.0 tests=BAYES_00,MAILING_LIST_MULTI, RCVD_IN_DNSWL_MED autolearn=ham version=3.3.1 Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher DHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.wl.linuxfoundation.org (Postfix) with ESMTPS id C6D532889C for ; Fri, 26 Jul 2019 15:58:40 +0000 (UTC) Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id 4B8316EDB1; Fri, 26 Jul 2019 15:58:40 +0000 (UTC) X-Original-To: intel-gfx@lists.freedesktop.org Delivered-To: intel-gfx@lists.freedesktop.org Received: from mga04.intel.com (mga04.intel.com [192.55.52.120]) by gabe.freedesktop.org (Postfix) with ESMTPS id 894A36EDB2 for ; Fri, 26 Jul 2019 15:58:39 +0000 (UTC) X-Amp-Result: SKIPPED(no attachment in message) X-Amp-File-Uploaded: False Received: from orsmga002.jf.intel.com ([10.7.209.21]) by fmsmga104.fm.intel.com with ESMTP/TLS/DHE-RSA-AES256-GCM-SHA384; 26 Jul 2019 08:58:39 -0700 X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.64,311,1559545200"; d="scan'208";a="181910439" Received: from irvmail001.ir.intel.com ([163.33.26.43]) by orsmga002.jf.intel.com with ESMTP; 26 Jul 2019 08:58:38 -0700 Received: from mwajdecz-MOBL1.ger.corp.intel.com (mwajdecz-mobl1.ger.corp.intel.com [172.28.174.50]) by irvmail001.ir.intel.com (8.14.3/8.13.6/MailSET/Hub) with ESMTP id x6QFwa8M030808; Fri, 26 Jul 2019 16:58:37 +0100 From: Michal Wajdeczko To: intel-gfx@lists.freedesktop.org Date: Fri, 26 Jul 2019 15:58:04 +0000 Message-Id: <20190726155805.2736-2-michal.wajdeczko@intel.com> X-Mailer: git-send-email 2.21.0.windows.1 In-Reply-To: <20190726155805.2736-1-michal.wajdeczko@intel.com> References: <20190726155805.2736-1-michal.wajdeczko@intel.com> MIME-Version: 1.0 Subject: [Intel-gfx] [PATCH 2/3] drm/i915/uc: Remove redundant ucode offset definition X-BeenThere: intel-gfx@lists.freedesktop.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: Intel graphics driver community testing & development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: intel-gfx-bounces@lists.freedesktop.org Sender: "Intel-gfx" X-Virus-Scanned: ClamAV using ClamSMTP According to Firmware layout definition, uCode is located right after CSS header, so ucode offset is always same as header size. Signed-off-by: Michal Wajdeczko Cc: Daniele Ceraolo Spurio Reviewed-by: Daniele Ceraolo Spurio --- drivers/gpu/drm/i915/gt/uc/intel_uc_fw.c | 8 +++----- drivers/gpu/drm/i915/gt/uc/intel_uc_fw.h | 1 - 2 files changed, 3 insertions(+), 6 deletions(-) diff --git a/drivers/gpu/drm/i915/gt/uc/intel_uc_fw.c b/drivers/gpu/drm/i915/gt/uc/intel_uc_fw.c index 66bda0c514a3..05079c59ae04 100644 --- a/drivers/gpu/drm/i915/gt/uc/intel_uc_fw.c +++ b/drivers/gpu/drm/i915/gt/uc/intel_uc_fw.c @@ -229,7 +229,6 @@ void intel_uc_fw_fetch(struct intel_uc_fw *uc_fw, struct drm_i915_private *i915) } /* Firmware blob always starts with the header, then uCode */ - uc_fw->ucode_offset = sizeof(struct uc_css_header); uc_fw->ucode_size = (css->size_dw - css->header_size_dw) * sizeof(u32); /* now RSA */ @@ -239,7 +238,7 @@ void intel_uc_fw_fetch(struct intel_uc_fw *uc_fw, struct drm_i915_private *i915) err = -ENOEXEC; goto fail; } - uc_fw->rsa_offset = uc_fw->ucode_offset + uc_fw->ucode_size; + uc_fw->rsa_offset = sizeof(struct uc_css_header) + uc_fw->ucode_size; uc_fw->rsa_size = css->key_size_dw * sizeof(u32); /* At least, it should have header, uCode and RSA. Size of all three. */ @@ -382,7 +381,7 @@ static int uc_fw_xfer(struct intel_uc_fw *uc_fw, struct intel_gt *gt, * via DMA, excluding any other components */ intel_uncore_write_fw(uncore, DMA_COPY_SIZE, - uc_fw->ucode_offset + uc_fw->ucode_size); + sizeof(struct uc_css_header) + uc_fw->ucode_size); /* Start the DMA */ intel_uncore_write_fw(uncore, DMA_CTRL, @@ -536,8 +535,7 @@ void intel_uc_fw_dump(const struct intel_uc_fw *uc_fw, struct drm_printer *p) drm_printf(p, "\tversion: wanted %u.%u, found %u.%u\n", uc_fw->major_ver_wanted, uc_fw->minor_ver_wanted, uc_fw->major_ver_found, uc_fw->minor_ver_found); - drm_printf(p, "\tuCode: offset %u, size %u\n", - uc_fw->ucode_offset, uc_fw->ucode_size); + drm_printf(p, "\tuCode: %u bytes\n", uc_fw->ucode_size); drm_printf(p, "\tRSA: offset %u, size %u\n", uc_fw->rsa_offset, uc_fw->rsa_size); } diff --git a/drivers/gpu/drm/i915/gt/uc/intel_uc_fw.h b/drivers/gpu/drm/i915/gt/uc/intel_uc_fw.h index a8048f91f0da..6a04bc6d419f 100644 --- a/drivers/gpu/drm/i915/gt/uc/intel_uc_fw.h +++ b/drivers/gpu/drm/i915/gt/uc/intel_uc_fw.h @@ -77,7 +77,6 @@ struct intel_uc_fw { u32 rsa_size; u32 rsa_offset; u32 ucode_size; - u32 ucode_offset; }; static inline From patchwork Fri Jul 26 15:58:05 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Michal Wajdeczko X-Patchwork-Id: 11061319 Return-Path: Received: from mail.wl.linuxfoundation.org (pdx-wl-mail.web.codeaurora.org [172.30.200.125]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id 5F40F912 for ; Fri, 26 Jul 2019 15:58:43 +0000 (UTC) Received: from mail.wl.linuxfoundation.org (localhost [127.0.0.1]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id 4FDFE2889C for ; Fri, 26 Jul 2019 15:58:43 +0000 (UTC) Received: by mail.wl.linuxfoundation.org (Postfix, from userid 486) id 442382896F; Fri, 26 Jul 2019 15:58:43 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on pdx-wl-mail.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-5.2 required=2.0 tests=BAYES_00,MAILING_LIST_MULTI, RCVD_IN_DNSWL_MED autolearn=ham version=3.3.1 Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher DHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.wl.linuxfoundation.org (Postfix) with ESMTPS id EED472889C for ; Fri, 26 Jul 2019 15:58:42 +0000 (UTC) Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id A30846EDB4; Fri, 26 Jul 2019 15:58:41 +0000 (UTC) X-Original-To: intel-gfx@lists.freedesktop.org Delivered-To: intel-gfx@lists.freedesktop.org Received: from mga14.intel.com (mga14.intel.com [192.55.52.115]) by gabe.freedesktop.org (Postfix) with ESMTPS id 51FA86EDB2 for ; Fri, 26 Jul 2019 15:58:40 +0000 (UTC) X-Amp-Result: SKIPPED(no attachment in message) X-Amp-File-Uploaded: False Received: from orsmga003.jf.intel.com ([10.7.209.27]) by fmsmga103.fm.intel.com with ESMTP/TLS/DHE-RSA-AES256-GCM-SHA384; 26 Jul 2019 08:58:39 -0700 X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.64,311,1559545200"; d="scan'208";a="173067329" Received: from irvmail001.ir.intel.com ([163.33.26.43]) by orsmga003.jf.intel.com with ESMTP; 26 Jul 2019 08:58:38 -0700 Received: from mwajdecz-MOBL1.ger.corp.intel.com (mwajdecz-mobl1.ger.corp.intel.com [172.28.174.50]) by irvmail001.ir.intel.com (8.14.3/8.13.6/MailSET/Hub) with ESMTP id x6QFwa8N030808; Fri, 26 Jul 2019 16:58:37 +0100 From: Michal Wajdeczko To: intel-gfx@lists.freedesktop.org Date: Fri, 26 Jul 2019 15:58:05 +0000 Message-Id: <20190726155805.2736-3-michal.wajdeczko@intel.com> X-Mailer: git-send-email 2.21.0.windows.1 In-Reply-To: <20190726155805.2736-1-michal.wajdeczko@intel.com> References: <20190726155805.2736-1-michal.wajdeczko@intel.com> MIME-Version: 1.0 Subject: [Intel-gfx] [PATCH 3/3] drm/i915/uc: Remove redundant RSA offset definition X-BeenThere: intel-gfx@lists.freedesktop.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: Intel graphics driver community testing & development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: intel-gfx-bounces@lists.freedesktop.org Sender: "Intel-gfx" X-Virus-Scanned: ClamAV using ClamSMTP According to Firmware layout definition, RSA signature is located after CSS header and uCode so actual RSA offset in the blob can be easily calculated when needed (and we need it only once). Signed-off-by: Michal Wajdeczko Cc: Daniele Ceraolo Spurio Reviewed-by: Daniele Ceraolo Spurio --- drivers/gpu/drm/i915/gt/uc/intel_uc_fw.c | 8 +++----- drivers/gpu/drm/i915/gt/uc/intel_uc_fw.h | 1 - 2 files changed, 3 insertions(+), 6 deletions(-) diff --git a/drivers/gpu/drm/i915/gt/uc/intel_uc_fw.c b/drivers/gpu/drm/i915/gt/uc/intel_uc_fw.c index 05079c59ae04..b0f2852dec41 100644 --- a/drivers/gpu/drm/i915/gt/uc/intel_uc_fw.c +++ b/drivers/gpu/drm/i915/gt/uc/intel_uc_fw.c @@ -238,7 +238,6 @@ void intel_uc_fw_fetch(struct intel_uc_fw *uc_fw, struct drm_i915_private *i915) err = -ENOEXEC; goto fail; } - uc_fw->rsa_offset = sizeof(struct uc_css_header) + uc_fw->ucode_size; uc_fw->rsa_size = css->key_size_dw * sizeof(u32); /* At least, it should have header, uCode and RSA. Size of all three. */ @@ -512,11 +511,11 @@ size_t intel_uc_fw_copy_rsa(struct intel_uc_fw *uc_fw, void *dst, u32 max_len) { struct sg_table *pages = uc_fw->obj->mm.pages; u32 size = min_t(u32, uc_fw->rsa_size, max_len); + u32 offset = sizeof(struct uc_css_header) + uc_fw->ucode_size; GEM_BUG_ON(!intel_uc_fw_is_available(uc_fw)); - return sg_pcopy_to_buffer(pages->sgl, pages->nents, - dst, size, uc_fw->rsa_offset); + return sg_pcopy_to_buffer(pages->sgl, pages->nents, dst, size, offset); } /** @@ -536,6 +535,5 @@ void intel_uc_fw_dump(const struct intel_uc_fw *uc_fw, struct drm_printer *p) uc_fw->major_ver_wanted, uc_fw->minor_ver_wanted, uc_fw->major_ver_found, uc_fw->minor_ver_found); drm_printf(p, "\tuCode: %u bytes\n", uc_fw->ucode_size); - drm_printf(p, "\tRSA: offset %u, size %u\n", - uc_fw->rsa_offset, uc_fw->rsa_size); + drm_printf(p, "\tRSA: %u bytes\n", uc_fw->rsa_size); } diff --git a/drivers/gpu/drm/i915/gt/uc/intel_uc_fw.h b/drivers/gpu/drm/i915/gt/uc/intel_uc_fw.h index 6a04bc6d419f..c2ab2803715d 100644 --- a/drivers/gpu/drm/i915/gt/uc/intel_uc_fw.h +++ b/drivers/gpu/drm/i915/gt/uc/intel_uc_fw.h @@ -75,7 +75,6 @@ struct intel_uc_fw { u16 minor_ver_found; u32 rsa_size; - u32 rsa_offset; u32 ucode_size; };