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26 Jul 2019 12:46:47 -0700 From: Atish Patra To: linux-kernel@vger.kernel.org Subject: [PATCH 1/4] RISC-V: Remove per cpu clocksource Date: Fri, 26 Jul 2019 12:46:35 -0700 Message-Id: <20190726194638.8068-1-atish.patra@wdc.com> X-Mailer: git-send-email 2.21.0 MIME-Version: 1.0 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20190726_124653_747027_DA69A74F X-CRM114-Status: GOOD ( 11.21 ) X-BeenThere: linux-riscv@lists.infradead.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Anup Patel , Alan Kao , Greg Kroah-Hartman , Daniel Lezcano , Johan Hovold , Atish Patra , Albert Ou , Palmer Dabbelt , Paul Walmsley , linux-riscv@lists.infradead.org, Thomas Gleixner , Allison Randal Sender: "linux-riscv" Errors-To: linux-riscv-bounces+patchwork-linux-riscv=patchwork.kernel.org@lists.infradead.org X-Virus-Scanned: ClamAV using ClamSMTP There is only one clocksource in RISC-V. The boot cpu initializes that clocksource. No need to keep a percpu data structure. Signed-off-by: Atish Patra --- drivers/clocksource/timer-riscv.c | 6 ++---- 1 file changed, 2 insertions(+), 4 deletions(-) diff --git a/drivers/clocksource/timer-riscv.c b/drivers/clocksource/timer-riscv.c index 5e6038fbf115..09e031176bc6 100644 --- a/drivers/clocksource/timer-riscv.c +++ b/drivers/clocksource/timer-riscv.c @@ -55,7 +55,7 @@ static u64 riscv_sched_clock(void) return get_cycles64(); } -static DEFINE_PER_CPU(struct clocksource, riscv_clocksource) = { +static struct clocksource riscv_clocksource = { .name = "riscv_clocksource", .rating = 300, .mask = CLOCKSOURCE_MASK(64), @@ -92,7 +92,6 @@ void riscv_timer_interrupt(void) static int __init riscv_timer_init_dt(struct device_node *n) { int cpuid, hartid, error; - struct clocksource *cs; hartid = riscv_of_processor_hartid(n); if (hartid < 0) { @@ -112,8 +111,7 @@ static int __init riscv_timer_init_dt(struct device_node *n) pr_info("%s: Registering clocksource cpuid [%d] hartid [%d]\n", __func__, cpuid, hartid); - cs = per_cpu_ptr(&riscv_clocksource, cpuid); - error = clocksource_register_hz(cs, riscv_timebase); + error = clocksource_register_hz(&riscv_clocksource, riscv_timebase); if (error) { pr_err("RISCV timer register failed [%d] for cpu = [%d]\n", error, cpuid); From patchwork Fri Jul 26 19:46:36 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Atish Patra X-Patchwork-Id: 11061785 Return-Path: Received: from mail.wl.linuxfoundation.org (pdx-wl-mail.web.codeaurora.org [172.30.200.125]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id F0ED313B1 for ; Fri, 26 Jul 2019 19:47:03 +0000 (UTC) Received: from mail.wl.linuxfoundation.org (localhost [127.0.0.1]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id E079128B3D for ; Fri, 26 Jul 2019 19:47:03 +0000 (UTC) Received: by mail.wl.linuxfoundation.org (Postfix, from userid 486) id D1F7F28B54; Fri, 26 Jul 2019 19:47:03 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on pdx-wl-mail.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-5.2 required=2.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,MAILING_LIST_MULTI,RCVD_IN_DNSWL_MED autolearn=ham version=3.3.1 Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.wl.linuxfoundation.org (Postfix) with ESMTPS id 4F5A828B3D for ; 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26 Jul 2019 12:46:47 -0700 From: Atish Patra To: linux-kernel@vger.kernel.org Subject: [PATCH 2/4] RISC-V: Add riscv_isa reprensenting ISA features common across CPUs Date: Fri, 26 Jul 2019 12:46:36 -0700 Message-Id: <20190726194638.8068-2-atish.patra@wdc.com> X-Mailer: git-send-email 2.21.0 In-Reply-To: <20190726194638.8068-1-atish.patra@wdc.com> References: <20190726194638.8068-1-atish.patra@wdc.com> MIME-Version: 1.0 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20190726_124655_202197_12B52E15 X-CRM114-Status: GOOD ( 13.66 ) X-BeenThere: linux-riscv@lists.infradead.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Albert Ou , Alan Kao , Greg Kroah-Hartman , Daniel Lezcano , Johan Hovold , Atish Patra , Anup Patel , Palmer Dabbelt , Paul Walmsley , linux-riscv@lists.infradead.org, Thomas Gleixner , Allison Randal Sender: "linux-riscv" Errors-To: linux-riscv-bounces+patchwork-linux-riscv=patchwork.kernel.org@lists.infradead.org X-Virus-Scanned: ClamAV using ClamSMTP From: Anup Patel This patch adds riscv_isa integer to represent ISA features common across all CPUs. The riscv_isa is not same as elf_hwcap because elf_hwcap will only have ISA features relevant for user-space apps whereas riscv_isa will have ISA features relevant to both kernel and user-space apps. One of the use case is KVM hypervisor where riscv_isa will be used to do following operations: 1. Check whether hypervisor extension is available 2. Find ISA features that need to be virtualized (e.g. floating point support, vector extension, etc.) Signed-off-by: Anup Patel Signed-off-by: Atish Patra --- arch/riscv/include/asm/hwcap.h | 25 ++++++++++++++++++++++ arch/riscv/kernel/cpufeature.c | 39 +++++++++++++++++++++++++++++++--- 2 files changed, 61 insertions(+), 3 deletions(-) diff --git a/arch/riscv/include/asm/hwcap.h b/arch/riscv/include/asm/hwcap.h index 7ecb7c6a57b1..e069f60ad5d2 100644 --- a/arch/riscv/include/asm/hwcap.h +++ b/arch/riscv/include/asm/hwcap.h @@ -22,5 +22,30 @@ enum { }; extern unsigned long elf_hwcap; + +#define RISCV_ISA_EXT_A (1UL << ('A' - 'A')) +#define RISCV_ISA_EXT_a RISCV_ISA_EXT_A +#define RISCV_ISA_EXT_C (1UL << ('C' - 'A')) +#define RISCV_ISA_EXT_c RISCV_ISA_EXT_C +#define RISCV_ISA_EXT_D (1UL << ('D' - 'A')) +#define RISCV_ISA_EXT_d RISCV_ISA_EXT_D +#define RISCV_ISA_EXT_F (1UL << ('F' - 'A')) +#define RISCV_ISA_EXT_f RISCV_ISA_EXT_F +#define RISCV_ISA_EXT_H (1UL << ('H' - 'A')) +#define RISCV_ISA_EXT_h RISCV_ISA_EXT_H +#define RISCV_ISA_EXT_I (1UL << ('I' - 'A')) +#define RISCV_ISA_EXT_i RISCV_ISA_EXT_I +#define RISCV_ISA_EXT_M (1UL << ('M' - 'A')) +#define RISCV_ISA_EXT_m RISCV_ISA_EXT_M +#define RISCV_ISA_EXT_S (1UL << ('S' - 'A')) +#define RISCV_ISA_EXT_s RISCV_ISA_EXT_S +#define RISCV_ISA_EXT_U (1UL << ('U' - 'A')) +#define RISCV_ISA_EXT_u RISCV_ISA_EXT_U + +extern unsigned long riscv_isa; + +#define riscv_isa_extension_available(ext_char) \ + (riscv_isa & RISCV_ISA_EXT_##ext_char) + #endif #endif diff --git a/arch/riscv/kernel/cpufeature.c b/arch/riscv/kernel/cpufeature.c index b1ade9a49347..d76c806b4fc9 100644 --- a/arch/riscv/kernel/cpufeature.c +++ b/arch/riscv/kernel/cpufeature.c @@ -12,6 +12,7 @@ #include unsigned long elf_hwcap __read_mostly; +unsigned long riscv_isa __read_mostly; #ifdef CONFIG_FPU bool has_fpu __read_mostly; #endif @@ -20,7 +21,8 @@ void riscv_fill_hwcap(void) { struct device_node *node; const char *isa; - size_t i; + char print_str[BITS_PER_LONG+1]; + size_t i, j, isa_len; static unsigned long isa2hwcap[256] = {0}; isa2hwcap['i'] = isa2hwcap['I'] = COMPAT_HWCAP_ISA_I; @@ -31,9 +33,11 @@ void riscv_fill_hwcap(void) isa2hwcap['c'] = isa2hwcap['C'] = COMPAT_HWCAP_ISA_C; elf_hwcap = 0; + riscv_isa = 0; for_each_of_cpu_node(node) { unsigned long this_hwcap = 0; + unsigned long this_isa = 0; if (riscv_of_processor_hartid(node) < 0) continue; @@ -43,8 +47,22 @@ void riscv_fill_hwcap(void) continue; } - for (i = 0; i < strlen(isa); ++i) + i = 0; + isa_len = strlen(isa); +#if defined(CONFIG_32BIT) + if (strncasecmp(isa, "rv32", 4) != 0) + i += 4; +#elif defined(CONFIG_64BIT) + if (strncasecmp(isa, "rv64", 4) != 0) + i += 4; +#endif + for (; i < isa_len; ++i) { this_hwcap |= isa2hwcap[(unsigned char)(isa[i])]; + if ('a' <= isa[i] && isa[i] <= 'z') + this_isa |= (1UL << (isa[i] - 'a')); + if ('A' <= isa[i] && isa[i] <= 'Z') + this_isa |= (1UL << (isa[i] - 'A')); + } /* * All "okay" hart should have same isa. Set HWCAP based on @@ -55,6 +73,11 @@ void riscv_fill_hwcap(void) elf_hwcap &= this_hwcap; else elf_hwcap = this_hwcap; + + if (riscv_isa) + riscv_isa &= this_isa; + else + riscv_isa = this_isa; } /* We don't support systems with F but without D, so mask those out @@ -64,7 +87,17 @@ void riscv_fill_hwcap(void) elf_hwcap &= ~COMPAT_HWCAP_ISA_F; } - pr_info("elf_hwcap is 0x%lx\n", elf_hwcap); + memset(print_str, 0, sizeof(print_str)); + for (i = 0, j = 0; i < BITS_PER_LONG; i++) + if (riscv_isa & (1UL << i)) + print_str[j++] = (char)('A' + i); + pr_info("riscv: ISA extensions %s\n", print_str); + + memset(print_str, 0, sizeof(print_str)); + for (i = 0, j = 0; i < BITS_PER_LONG; i++) + if (elf_hwcap & (1UL << i)) + print_str[j++] = (char)('A' + i); + pr_info("riscv: ELF capabilities %s\n", print_str); #ifdef CONFIG_FPU if (elf_hwcap & (COMPAT_HWCAP_ISA_F | COMPAT_HWCAP_ISA_D)) From patchwork Fri Jul 26 19:46:37 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Atish Patra X-Patchwork-Id: 11061783 Return-Path: Received: from mail.wl.linuxfoundation.org (pdx-wl-mail.web.codeaurora.org [172.30.200.125]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id F14A113B1 for ; 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26 Jul 2019 12:44:56 -0700 IronPort-SDR: wTxhkBHItRBK6MQN42Flf6IDsh0NhG04f+bcBRld7ws7XJL62cnVGK7DynbnmXlEJ2GUnFXWG0 peU7/eOrwiFPw9pbSRMd1QwreStg8598I0Tm1oqu1ia9hVcU0eFKVL/GxeBBOS++awvjNnrZ4K us0zET2Sf80U+I6/KdcnhsS+YOGXYChPOQIGCNhyMeJotR22b/t2IonRa0IKyI8xhU5mKEmJj5 4rTMHJT0NehUAirTRMneA1RTzOh30uD1OSLu0Q3X8WhW/57CSiAE9dZlVX0cuFIfe29ogq+IrQ WoE= Received: from jedi-01.sdcorp.global.sandisk.com (HELO jedi-01.int.fusionio.com) ([10.11.143.218]) by uls-op-cesaip01.wdc.com with ESMTP; 26 Jul 2019 12:46:48 -0700 From: Atish Patra To: linux-kernel@vger.kernel.org Subject: [PATCH 3/4] RISC-V: Support case insensitive ISA string parsing. Date: Fri, 26 Jul 2019 12:46:37 -0700 Message-Id: <20190726194638.8068-3-atish.patra@wdc.com> X-Mailer: git-send-email 2.21.0 In-Reply-To: <20190726194638.8068-1-atish.patra@wdc.com> References: <20190726194638.8068-1-atish.patra@wdc.com> MIME-Version: 1.0 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20190726_124655_355718_5A35D1C1 X-CRM114-Status: GOOD ( 11.76 ) X-BeenThere: linux-riscv@lists.infradead.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Anup Patel , Alan Kao , Greg Kroah-Hartman , Daniel Lezcano , Johan Hovold , Atish Patra , Albert Ou , Palmer Dabbelt , Paul Walmsley , linux-riscv@lists.infradead.org, Thomas Gleixner , Allison Randal Sender: "linux-riscv" Errors-To: linux-riscv-bounces+patchwork-linux-riscv=patchwork.kernel.org@lists.infradead.org X-Virus-Scanned: ClamAV using ClamSMTP As per riscv specification, ISA naming strings are case insensitive. However, currently only lower case strings are parsed during cpu procfs. Support parsing of upper case letters as well. Signed-off-by: Atish Patra --- arch/riscv/kernel/cpu.c | 9 +++++---- 1 file changed, 5 insertions(+), 4 deletions(-) diff --git a/arch/riscv/kernel/cpu.c b/arch/riscv/kernel/cpu.c index 7da3c6a93abd..185143478830 100644 --- a/arch/riscv/kernel/cpu.c +++ b/arch/riscv/kernel/cpu.c @@ -5,6 +5,7 @@ #include #include +#include #include #include @@ -57,10 +58,10 @@ static void print_isa(struct seq_file *f, const char *orig_isa) * kernels on harts with the same ISA that the kernel is compiled for. */ #if defined(CONFIG_32BIT) - if (strncmp(isa, "rv32i", 5) != 0) + if (strncasecmp(isa, "rv32i", 5) != 0) return; #elif defined(CONFIG_64BIT) - if (strncmp(isa, "rv64i", 5) != 0) + if (strncasecmp(isa, "rv64i", 5) != 0) return; #endif @@ -76,8 +77,8 @@ static void print_isa(struct seq_file *f, const char *orig_isa) * extension from userspace as it's not accessible from there. */ for (e = ext; *e != '\0'; ++e) { - if (isa[0] == e[0]) { - if (isa[0] != 's') + if (tolower(isa[0]) == e[0]) { + if (tolower(isa[0] != 's')) seq_write(f, isa, 1); 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26 Jul 2019 12:46:48 -0700 From: Atish Patra To: linux-kernel@vger.kernel.org Subject: [PATCH 4/4] RISC-V: Fix unsupported isa string info. Date: Fri, 26 Jul 2019 12:46:38 -0700 Message-Id: <20190726194638.8068-4-atish.patra@wdc.com> X-Mailer: git-send-email 2.21.0 In-Reply-To: <20190726194638.8068-1-atish.patra@wdc.com> References: <20190726194638.8068-1-atish.patra@wdc.com> MIME-Version: 1.0 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20190726_124656_793503_0A459C2E X-CRM114-Status: GOOD ( 19.79 ) X-BeenThere: linux-riscv@lists.infradead.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Anup Patel , Alan Kao , Greg Kroah-Hartman , Daniel Lezcano , Johan Hovold , Atish Patra , Albert Ou , Palmer Dabbelt , Paul Walmsley , linux-riscv@lists.infradead.org, Thomas Gleixner , Allison Randal Sender: "linux-riscv" Errors-To: linux-riscv-bounces+patchwork-linux-riscv=patchwork.kernel.org@lists.infradead.org X-Virus-Scanned: ClamAV using ClamSMTP Currently, kernel prints a info warning if any of the extensions from "mafdcsu" is missing in device tree. This is not entirely correct as Linux can boot with "f or d" extensions if kernel is configured accordingly. Moreover, it will continue to print the info string for future extensions such as hypervisor as well which is misleading. /proc/cpuinfo also doesn't print any other extensions except "mafdcsu". Make sure that info log is only printed only if kernel is configured to have any mandatory extensions but device tree doesn't describe it. All the extensions present in device tree and follow the order described in the RISC-V specification (except 'S') are printed via /proc/cpuinfo always. Signed-off-by: Atish Patra --- arch/riscv/kernel/cpu.c | 47 ++++++++++++++++++++++++++++++++--------- 1 file changed, 37 insertions(+), 10 deletions(-) diff --git a/arch/riscv/kernel/cpu.c b/arch/riscv/kernel/cpu.c index 185143478830..3d050440364c 100644 --- a/arch/riscv/kernel/cpu.c +++ b/arch/riscv/kernel/cpu.c @@ -8,6 +8,7 @@ #include #include #include +#include /* * Returns the hart ID of the given device tree node, or -ENODEV if the node @@ -47,11 +48,14 @@ int riscv_of_processor_hartid(struct device_node *node) #ifdef CONFIG_PROC_FS -static void print_isa(struct seq_file *f, const char *orig_isa) +static void print_isa(struct seq_file *f, const char *orig_isa, + unsigned long cpuid) { - static const char *ext = "mafdcsu"; + static const char *mandatory_ext = "mafdcsu"; const char *isa = orig_isa; const char *e; + char unsupported_isa[26] = {0}; + int index = 0; /* * Linux doesn't support rv32e or rv128i, and we only support booting @@ -71,27 +75,50 @@ static void print_isa(struct seq_file *f, const char *orig_isa) isa += 5; /* - * Check the rest of the ISA string for valid extensions, printing those - * we find. RISC-V ISA strings define an order, so we only print the + * RISC-V ISA strings define an order, so we only print all the * extension bits when they're in order. Hide the supervisor (S) * extension from userspace as it's not accessible from there. + * Throw a warning only if any mandatory extensions are not available + * and kernel is configured to have that mandatory extensions. */ - for (e = ext; *e != '\0'; ++e) { - if (tolower(isa[0]) == e[0]) { + for (e = mandatory_ext; *e != '\0'; ++e) { + if (tolower(isa[0]) != e[0]) { +#if defined(CONFIG_ISA_RISCV_C) + if (tolower(isa[0] == 'c')) + continue; +#endif +#if defined(CONFIG_FP) + if ((tolower(isa[0]) == 'f') || tolower(isa[0] == 'd')) + continue; +#endif + unsupported_isa[index] = e[0]; + index++; + } + if (isa[0] != '\0') { + /* Only write if part of isa string */ if (tolower(isa[0] != 's')) seq_write(f, isa, 1); - isa++; } } + if (isa[0] != '\0') { + /* Add remainging isa strings */ + for (e = isa; *e != '\0'; ++e) { +#if !defined(CONFIG_VIRTUALIZATION) + if ((tolower(e[0]) != 'h')) +#endif + seq_write(f, e, 1); + } + } seq_puts(f, "\n"); /* * If we were given an unsupported ISA in the device tree then print * a bit of info describing what went wrong. */ - if (isa[0] != '\0') - pr_info("unsupported ISA \"%s\" in device tree\n", orig_isa); + if (unsupported_isa[0]) + pr_info("unsupported ISA extensions \"%s\" in device tree for cpu [%ld]\n", + unsupported_isa, cpuid); } static void print_mmu(struct seq_file *f, const char *mmu_type) @@ -135,7 +162,7 @@ static int c_show(struct seq_file *m, void *v) seq_printf(m, "processor\t: %lu\n", cpu_id); seq_printf(m, "hart\t\t: %lu\n", cpuid_to_hartid_map(cpu_id)); if (!of_property_read_string(node, "riscv,isa", &isa)) - print_isa(m, isa); + print_isa(m, isa, cpu_id); if (!of_property_read_string(node, "mmu-type", &mmu)) print_mmu(m, mmu); if (!of_property_read_string(node, "compatible", &compat)