From patchwork Wed Jul 31 22:41:44 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Suman Anna X-Patchwork-Id: 11069767 Return-Path: Received: from mail.wl.linuxfoundation.org (pdx-wl-mail.web.codeaurora.org [172.30.200.125]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id 79AEE13AC for ; Wed, 31 Jul 2019 22:44:22 +0000 (UTC) Received: from mail.wl.linuxfoundation.org (localhost [127.0.0.1]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id 678D7204FA for ; Wed, 31 Jul 2019 22:44:22 +0000 (UTC) Received: by mail.wl.linuxfoundation.org (Postfix, from userid 486) id 59EBE280B0; Wed, 31 Jul 2019 22:44:22 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on pdx-wl-mail.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-5.2 required=2.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,MAILING_LIST_MULTI,RCVD_IN_DNSWL_MED autolearn=ham version=3.3.1 Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.wl.linuxfoundation.org (Postfix) with ESMTPS id B7B36204FA for ; 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Wed, 31 Jul 2019 17:42:40 -0500 Received: from fllv0039.itg.ti.com (10.64.41.19) by DLEE104.ent.ti.com (157.170.170.34) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.1713.5 via Frontend Transport; Wed, 31 Jul 2019 17:42:40 -0500 Received: from legion.dal.design.ti.com (legion.dal.design.ti.com [128.247.22.53]) by fllv0039.itg.ti.com (8.15.2/8.15.2) with ESMTP id x6VMgeVh072677; Wed, 31 Jul 2019 17:42:40 -0500 Received: from localhost (irmo.dhcp.ti.com [128.247.58.153]) by legion.dal.design.ti.com (8.11.7p1+Sun/8.11.7) with ESMTP id x6VMgeZ25759; Wed, 31 Jul 2019 17:42:40 -0500 (CDT) From: Suman Anna To: Marc Zyngier , Thomas Gleixner , Jason Cooper Subject: [PATCH v2 1/6] dt-bindings: irqchip: Add PRUSS interrupt controller bindings Date: Wed, 31 Jul 2019 17:41:44 -0500 Message-ID: <20190731224149.11153-2-s-anna@ti.com> X-Mailer: git-send-email 2.22.0 In-Reply-To: <20190731224149.11153-1-s-anna@ti.com> References: <20190731224149.11153-1-s-anna@ti.com> MIME-Version: 1.0 X-EXCLAIMER-MD-CONFIG: e1e8a2fd-e40a-4ac6-ac9b-f7e9cc9ee180 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20190731_154346_906674_755E3136 X-CRM114-Status: GOOD ( 17.74 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: devicetree@vger.kernel.org, Grygorii Strashko , David Lechner , Rob Herring , Tony Lindgren , Sekhar Nori , linux-kernel@vger.kernel.org, "Andrew F. Davis" , Lokesh Vutla , Rob Herring , Murali Karicheri , linux-omap@vger.kernel.org, linux-arm-kernel@lists.infradead.org, Roger Quadros Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+patchwork-linux-arm=patchwork.kernel.org@lists.infradead.org X-Virus-Scanned: ClamAV using ClamSMTP The Programmable Real-Time Unit Subsystem (PRUSS) contains an interrupt controller (INTC) that can handle various system input events and post interrupts back to the device-level initiators. The INTC can support upto 64 input events on most SoCs with individual control configuration and hardware prioritization. These events are mapped onto 10 output interrupt lines through two levels of many-to-one mapping support. Different interrupt lines are routed to the individual PRU cores or to the host CPU or to other PRUSS instances. The K3 AM65x and J721E SoCs have the next generation of the PRU-ICSS IP, commonly called ICSSG. The ICSSG interrupt controller on K3 SoCs provide a higher number of host interrupts (20 vs 10) and can handle an increased number of input events (160 vs 64) from various SoC interrupt sources. Add the bindings document for these interrupt controllers on all the applicable SoCs. It covers the OMAP architecture SoCs - AM33xx, AM437x and AM57xx; the Keystone 2 architecture based 66AK2G SoC; the Davinci architecture based OMAPL138 SoCs, and the K3 architecture based AM65x and J721E SoCs. Signed-off-by: Suman Anna Signed-off-by: Andrew F. Davis Signed-off-by: Roger Quadros Reviewed-by: Rob Herring --- v2: - Updated the interrupt-names from "hostX" to "host_intrX" and updated example accordingly - Updated the description for interrupts property - Used generic interrupt controller in descriptions rather than GIC - Added some clarifications about interrupt names to PRUSS INTC output interrupts - Picked up Rob's reviewed-by v1: https://patchwork.kernel.org/patch/11034567/ .../interrupt-controller/ti,pruss-intc.txt | 98 +++++++++++++++++++ 1 file changed, 98 insertions(+) create mode 100644 Documentation/devicetree/bindings/interrupt-controller/ti,pruss-intc.txt diff --git a/Documentation/devicetree/bindings/interrupt-controller/ti,pruss-intc.txt b/Documentation/devicetree/bindings/interrupt-controller/ti,pruss-intc.txt new file mode 100644 index 000000000000..17c7b49a7f2e --- /dev/null +++ b/Documentation/devicetree/bindings/interrupt-controller/ti,pruss-intc.txt @@ -0,0 +1,98 @@ +PRU ICSS INTC on TI SoCs +======================== + +Each PRUSS has a single interrupt controller instance that is common to both +the PRU cores. Most interrupt controllers can route 64 input events which are +then mapped to 10 possible output interrupts through two levels of mapping. +The input events can be triggered by either the PRUs and/or various other PRUSS +internal and external peripherals. The first 2 output interrupts (0 & 1) are +fed exclusively to the internal PRU cores, with the remaining 8 (2 through 9) +connected to external interrupt controllers including the MPU and/or other +PRUSS instances, DSPs or devices. + +The K3 family of SoCs can handle 160 input events that can be mapped to 20 +different possible output interrupts. The additional output interrupts (10 +through 19) are connected to new sub-modules within the ICSSG instances. + +This interrupt-controller node should be defined as a child node of the +corresponding PRUSS node. The node should be named "interrupt-controller". +Please see the overall PRUSS bindings document for additional details +including a complete example, + Documentation/devicetree/bindings/soc/ti/ti,pruss.txt + +Required Properties: +-------------------- +- compatible : should be one of the following, + "ti,pruss-intc" for OMAP-L13x/AM18x/DA850 SoCs, + AM335x family of SoCs, + AM437x family of SoCs, + AM57xx family of SoCs + 66AK2G family of SoCs + "ti,icssg-intc" for K3 AM65x & J721E family of SoCs +- reg : base address and size for the PRUSS INTC sub-module +- interrupts : all the interrupts generated towards the main host + processor in the SoC. The format depends on the + interrupt specifier for the particular SoC's Arm + parent interrupt controller. A shared interrupt can + be skipped if the desired destination and usage is by + a different processor/device. +- interrupt-names : should use one of the following names for each valid + host event interrupt connected to Arm interrupt + controller, the name should match the corresponding + host event interrupt number, + "host_intr0", "host_intr1", "host_intr2", + "host_intr3", "host_intr4", "host_intr5", + "host_intr6" or "host_intr7" +- interrupt-controller : mark this node as an interrupt controller +- #interrupt-cells : should be 1. Client users shall use the PRU System + event number (the interrupt source that the client + is interested in) as the value of the interrupts + property in their node + +Optional Properties: +-------------------- +The following properties are _required_ only for some SoCs. If none of the below +properties are defined, it implies that all the PRUSS INTC output interrupts 2 +through 9 (host_intr0 through host_intr7) are connected exclusively to the +Arm interrupt controller. + +- ti,irqs-reserved : an array of 8-bit elements of host interrupts between + 0 and 7 (corresponding to PRUSS INTC output interrupts + 2 through 9) that are not connected to the Arm + interrupt controller. + Eg: AM437x and 66AK2G SoCs do not have "host_intr5" + interrupt connected to MPU +- ti,irqs-shared : an array of 8-bit elements of host interrupts between + 0 and 7 (corresponding to PRUSS INTC output interrupts + 2 through 9) that are also connected to other devices + or processors in the SoC. + Eg: AM65x and J721E SoCs have "host_intr5", + "host_intr6" and "host_intr7" interrupts + connected to MPU, and other ICSSG instances + + +Example: +-------- + +1. /* AM33xx PRU-ICSS */ + pruss: pruss@0 { + compatible = "ti,am3356-pruss"; + reg = <0x0 0x80000>; + #address-cells = <1>; + #size-cells = <1>; + ranges; + ... + + pruss_intc: interrupt-controller@20000 { + compatible = "ti,pruss-intc"; + reg = <0x20000 0x2000>; + interrupts = <20 21 22 23 24 25 26 27>; + interrupt-names = "host_intr0", "host_intr1", + "host_intr2", "host_intr3", + "host_intr4", "host_intr5", + "host_intr6", "host_intr7"; + interrupt-controller; + #interrupt-cells = <1>; + ti,irqs-shared = /bits/ 8 <0 6 7>; + }; + }; From patchwork Wed Jul 31 22:41:45 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Suman Anna X-Patchwork-Id: 11069771 Return-Path: Received: from mail.wl.linuxfoundation.org (pdx-wl-mail.web.codeaurora.org [172.30.200.125]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id E7C9A13AC for ; Wed, 31 Jul 2019 22:44:46 +0000 (UTC) Received: from mail.wl.linuxfoundation.org (localhost [127.0.0.1]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id CECD727FE4 for ; Wed, 31 Jul 2019 22:44:46 +0000 (UTC) Received: by mail.wl.linuxfoundation.org (Postfix, from userid 486) id BE946280B0; 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Wed, 31 Jul 2019 17:42:41 -0500 Received: from localhost (irmo.dhcp.ti.com [128.247.58.153]) by legion.dal.design.ti.com (8.11.7p1+Sun/8.11.7) with ESMTP id x6VMgfZ25779; Wed, 31 Jul 2019 17:42:41 -0500 (CDT) From: Suman Anna To: Marc Zyngier , Thomas Gleixner , Jason Cooper Subject: [PATCH v2 2/6] irqchip/irq-pruss-intc: Add a PRUSS irqchip driver for PRUSS interrupts Date: Wed, 31 Jul 2019 17:41:45 -0500 Message-ID: <20190731224149.11153-3-s-anna@ti.com> X-Mailer: git-send-email 2.22.0 In-Reply-To: <20190731224149.11153-1-s-anna@ti.com> References: <20190731224149.11153-1-s-anna@ti.com> MIME-Version: 1.0 X-EXCLAIMER-MD-CONFIG: e1e8a2fd-e40a-4ac6-ac9b-f7e9cc9ee180 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20190731_154346_999511_1ADD4EAF X-CRM114-Status: GOOD ( 27.56 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: devicetree@vger.kernel.org, Grygorii Strashko , David Lechner , Tony Lindgren , Sekhar Nori , linux-kernel@vger.kernel.org, "Andrew F. Davis" , Lokesh Vutla , Rob Herring , Murali Karicheri , linux-omap@vger.kernel.org, linux-arm-kernel@lists.infradead.org, Roger Quadros Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+patchwork-linux-arm=patchwork.kernel.org@lists.infradead.org X-Virus-Scanned: ClamAV using ClamSMTP From: "Andrew F. Davis" The Programmable Real-Time Unit Subsystem (PRUSS) contains a local interrupt controller (INTC) that can handle various system input events and post interrupts back to the device-level initiators. The INTC can support upto 64 input events with individual control configuration and hardware prioritization. These events are mapped onto 10 output interrupt lines through two levels of many-to-one mapping support. Different interrupt lines are routed to the individual PRU cores or to the host CPU, or to other devices on the SoC. Some of these events are sourced from peripherals or other sub-modules within that PRUSS, while a few others are sourced from SoC-level peripherals/devices. The PRUSS INTC platform driver manages this PRUSS interrupt controller and implements an irqchip driver to provide a Linux standard way for the PRU client users to enable/disable/ack/re-trigger a PRUSS system event. The system events to interrupt channels and output interrupts relies on the mapping configuration provided either through the PRU firmware blob or via the PRU application's device tree node. The mappings will be programmed during the boot/shutdown of a PRU core. The PRUSS INTC module is reference counted during the interrupt setup phase through the irqchip's irq_request_resources() and irq_release_resources() ops. This restricts the module from being removed as long as there are active interrupt users. The driver currently supports and can be built for OMAP architecture based AM335x, AM437x and AM57xx SoCs; Keystone2 architecture based 66AK2G SoCs and Davinci architecture based OMAP-L13x/AM18x/DA850 SoCs. All of these SoCs support 64 system events, 10 interrupt channels and 10 output interrupt lines per PRUSS INTC with a few SoC integration differences. NOTE: Each PRU-ICSS's INTC on AM57xx SoCs is preceded by a Crossbar that enables multiple external events to be routed to a specific number of input interrupt events. Any non-default external interrupt event directed towards PRUSS needs this crossbar to be setup properly. Signed-off-by: Andrew F. Davis Signed-off-by: Suman Anna Signed-off-by: Roger Quadros --- v2: - Addressed all of David Lechner's comments - Dropped irq_retrigger callback - Updated interrupt names from "hostX" to "host_intrX" - Moved host_mask variable to patch 4 v1: https://patchwork.kernel.org/patch/11034545/ v0: https://patchwork.kernel.org/patch/10795761/ drivers/irqchip/Kconfig | 10 + drivers/irqchip/Makefile | 1 + drivers/irqchip/irq-pruss-intc.c | 338 +++++++++++++++++++++++++++++++ 3 files changed, 349 insertions(+) create mode 100644 drivers/irqchip/irq-pruss-intc.c diff --git a/drivers/irqchip/Kconfig b/drivers/irqchip/Kconfig index 80e10f4e213a..dc6b5aa77a5d 100644 --- a/drivers/irqchip/Kconfig +++ b/drivers/irqchip/Kconfig @@ -471,6 +471,16 @@ config TI_SCI_INTA_IRQCHIP If you wish to use interrupt aggregator irq resources managed by the TI System Controller, say Y here. Otherwise, say N. +config TI_PRUSS_INTC + tristate "TI PRU-ICSS Interrupt Controller" + depends on ARCH_DAVINCI || SOC_AM33XX || SOC_AM437X || SOC_DRA7XX || ARCH_KEYSTONE + select IRQ_DOMAIN + help + This enables support for the PRU-ICSS Local Interrupt Controller + present within a PRU-ICSS subsystem present on various TI SoCs. + The PRUSS INTC enables various interrupts to be routed to multiple + different processors within the SoC. + endmenu config SIFIVE_PLIC diff --git a/drivers/irqchip/Makefile b/drivers/irqchip/Makefile index 8d0fcec6ab23..a02e652ca805 100644 --- a/drivers/irqchip/Makefile +++ b/drivers/irqchip/Makefile @@ -102,3 +102,4 @@ obj-$(CONFIG_MADERA_IRQ) += irq-madera.o obj-$(CONFIG_LS1X_IRQ) += irq-ls1x.o obj-$(CONFIG_TI_SCI_INTR_IRQCHIP) += irq-ti-sci-intr.o obj-$(CONFIG_TI_SCI_INTA_IRQCHIP) += irq-ti-sci-inta.o +obj-$(CONFIG_TI_PRUSS_INTC) += irq-pruss-intc.o diff --git a/drivers/irqchip/irq-pruss-intc.c b/drivers/irqchip/irq-pruss-intc.c new file mode 100644 index 000000000000..4a9456544fd0 --- /dev/null +++ b/drivers/irqchip/irq-pruss-intc.c @@ -0,0 +1,338 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * PRU-ICSS INTC IRQChip driver for various TI SoCs + * + * Copyright (C) 2016-2019 Texas Instruments Incorporated - http://www.ti.com/ + * Andrew F. Davis + * Suman Anna + */ + +#include +#include +#include +#include +#include +#include + +/* + * Number of host interrupts reaching the main MPU sub-system. Note that this + * is not the same as the total number of host interrupts supported by the PRUSS + * INTC instance + */ +#define MAX_NUM_HOST_IRQS 8 + +/* minimum starting host interrupt number for MPU */ +#define MIN_PRU_HOST_INT 2 + +/* maximum number of system events */ +#define MAX_PRU_SYS_EVENTS 64 + +/* PRU_ICSS_INTC registers */ +#define PRU_INTC_REVID 0x0000 +#define PRU_INTC_CR 0x0004 +#define PRU_INTC_GER 0x0010 +#define PRU_INTC_GNLR 0x001c +#define PRU_INTC_SISR 0x0020 +#define PRU_INTC_SICR 0x0024 +#define PRU_INTC_EISR 0x0028 +#define PRU_INTC_EICR 0x002c +#define PRU_INTC_HIEISR 0x0034 +#define PRU_INTC_HIDISR 0x0038 +#define PRU_INTC_GPIR 0x0080 +#define PRU_INTC_SRSR0 0x0200 +#define PRU_INTC_SRSR1 0x0204 +#define PRU_INTC_SECR0 0x0280 +#define PRU_INTC_SECR1 0x0284 +#define PRU_INTC_ESR0 0x0300 +#define PRU_INTC_ESR1 0x0304 +#define PRU_INTC_ECR0 0x0380 +#define PRU_INTC_ECR1 0x0384 +#define PRU_INTC_CMR(x) (0x0400 + (x) * 4) +#define PRU_INTC_HMR(x) (0x0800 + (x) * 4) +#define PRU_INTC_HIPIR(x) (0x0900 + (x) * 4) +#define PRU_INTC_SIPR0 0x0d00 +#define PRU_INTC_SIPR1 0x0d04 +#define PRU_INTC_SITR0 0x0d80 +#define PRU_INTC_SITR1 0x0d84 +#define PRU_INTC_HINLR(x) (0x1100 + (x) * 4) +#define PRU_INTC_HIER 0x1500 + +/* HIPIR register bit-fields */ +#define INTC_HIPIR_NONE_HINT 0x80000000 + +/** + * struct pruss_intc - PRUSS interrupt controller structure + * @irqs: kernel irq numbers corresponding to PRUSS host interrupts + * @base: base virtual address of INTC register space + * @irqchip: irq chip for this interrupt controller + * @domain: irq domain for this interrupt controller + * @lock: mutex to serialize access to INTC + */ +struct pruss_intc { + unsigned int irqs[MAX_NUM_HOST_IRQS]; + void __iomem *base; + struct irq_chip *irqchip; + struct irq_domain *domain; + struct mutex lock; /* PRUSS INTC lock */ +}; + +static inline u32 pruss_intc_read_reg(struct pruss_intc *intc, unsigned int reg) +{ + return readl_relaxed(intc->base + reg); +} + +static inline void pruss_intc_write_reg(struct pruss_intc *intc, + unsigned int reg, u32 val) +{ + writel_relaxed(val, intc->base + reg); +} + +static int pruss_intc_check_write(struct pruss_intc *intc, unsigned int reg, + unsigned int sysevent) +{ + if (!intc) + return -EINVAL; + + if (sysevent >= MAX_PRU_SYS_EVENTS) + return -EINVAL; + + pruss_intc_write_reg(intc, reg, sysevent); + + return 0; +} + +static void pruss_intc_init(struct pruss_intc *intc) +{ + int i; + + /* configure polarity to active high for all system interrupts */ + pruss_intc_write_reg(intc, PRU_INTC_SIPR0, 0xffffffff); + pruss_intc_write_reg(intc, PRU_INTC_SIPR1, 0xffffffff); + + /* configure type to pulse interrupt for all system interrupts */ + pruss_intc_write_reg(intc, PRU_INTC_SITR0, 0); + pruss_intc_write_reg(intc, PRU_INTC_SITR1, 0); + + /* clear all 16 interrupt channel map registers */ + for (i = 0; i < 16; i++) + pruss_intc_write_reg(intc, PRU_INTC_CMR(i), 0); + + /* clear all 3 host interrupt map registers */ + for (i = 0; i < 3; i++) + pruss_intc_write_reg(intc, PRU_INTC_HMR(i), 0); +} + +static void pruss_intc_irq_ack(struct irq_data *data) +{ + struct pruss_intc *intc = irq_data_get_irq_chip_data(data); + unsigned int hwirq = data->hwirq; + + pruss_intc_check_write(intc, PRU_INTC_SICR, hwirq); +} + +static void pruss_intc_irq_mask(struct irq_data *data) +{ + struct pruss_intc *intc = irq_data_get_irq_chip_data(data); + unsigned int hwirq = data->hwirq; + + pruss_intc_check_write(intc, PRU_INTC_EICR, hwirq); +} + +static void pruss_intc_irq_unmask(struct irq_data *data) +{ + struct pruss_intc *intc = irq_data_get_irq_chip_data(data); + unsigned int hwirq = data->hwirq; + + pruss_intc_check_write(intc, PRU_INTC_EISR, hwirq); +} + +static int pruss_intc_irq_reqres(struct irq_data *data) +{ + if (!try_module_get(THIS_MODULE)) + return -ENODEV; + + return 0; +} + +static void pruss_intc_irq_relres(struct irq_data *data) +{ + module_put(THIS_MODULE); +} + +static int pruss_intc_irq_domain_map(struct irq_domain *d, unsigned int virq, + irq_hw_number_t hw) +{ + struct pruss_intc *intc = d->host_data; + + irq_set_chip_data(virq, intc); + irq_set_chip_and_handler(virq, intc->irqchip, handle_level_irq); + + return 0; +} + +static void pruss_intc_irq_domain_unmap(struct irq_domain *d, unsigned int virq) +{ + irq_set_chip_and_handler(virq, NULL, NULL); + irq_set_chip_data(virq, NULL); +} + +static const struct irq_domain_ops pruss_intc_irq_domain_ops = { + .xlate = irq_domain_xlate_onecell, + .map = pruss_intc_irq_domain_map, + .unmap = pruss_intc_irq_domain_unmap, +}; + +static void pruss_intc_irq_handler(struct irq_desc *desc) +{ + unsigned int irq = irq_desc_get_irq(desc); + struct irq_chip *chip = irq_desc_get_chip(desc); + struct pruss_intc *intc = irq_get_handler_data(irq); + u32 hipir; + unsigned int virq; + int i, hwirq; + + chained_irq_enter(chip, desc); + + /* find our host irq number */ + for (i = 0; i < MAX_NUM_HOST_IRQS; i++) + if (intc->irqs[i] == irq) + break; + if (i == MAX_NUM_HOST_IRQS) + goto err; + + i += MIN_PRU_HOST_INT; + + /* get highest priority pending PRUSS system event */ + hipir = pruss_intc_read_reg(intc, PRU_INTC_HIPIR(i)); + while (!(hipir & INTC_HIPIR_NONE_HINT)) { + hwirq = hipir & GENMASK(9, 0); + virq = irq_linear_revmap(intc->domain, hwirq); + + /* + * NOTE: manually ACK any system events that do not have a + * handler mapped yet + */ + if (unlikely(!virq)) + pruss_intc_check_write(intc, PRU_INTC_SICR, hwirq); + else + generic_handle_irq(virq); + + /* get next system event */ + hipir = pruss_intc_read_reg(intc, PRU_INTC_HIPIR(i)); + } +err: + chained_irq_exit(chip, desc); +} + +static int pruss_intc_probe(struct platform_device *pdev) +{ + static const char * const irq_names[] = { + "host_intr0", "host_intr1", "host_intr2", "host_intr3", + "host_intr4", "host_intr5", "host_intr6", "host_intr7", }; + struct device *dev = &pdev->dev; + struct pruss_intc *intc; + struct resource *res; + struct irq_chip *irqchip; + int i, irq; + + intc = devm_kzalloc(dev, sizeof(*intc), GFP_KERNEL); + if (!intc) + return -ENOMEM; + platform_set_drvdata(pdev, intc); + + res = platform_get_resource(pdev, IORESOURCE_MEM, 0); + intc->base = devm_ioremap_resource(dev, res); + if (IS_ERR(intc->base)) { + dev_err(dev, "failed to parse and map intc memory resource\n"); + return PTR_ERR(intc->base); + } + + dev_dbg(dev, "intc memory: pa %pa size 0x%zx va %pK\n", &res->start, + (size_t)resource_size(res), intc->base); + + mutex_init(&intc->lock); + + pruss_intc_init(intc); + + irqchip = devm_kzalloc(dev, sizeof(*irqchip), GFP_KERNEL); + if (!irqchip) + return -ENOMEM; + + irqchip->irq_ack = pruss_intc_irq_ack; + irqchip->irq_mask = pruss_intc_irq_mask; + irqchip->irq_unmask = pruss_intc_irq_unmask; + irqchip->irq_request_resources = pruss_intc_irq_reqres; + irqchip->irq_release_resources = pruss_intc_irq_relres; + irqchip->name = dev_name(dev); + intc->irqchip = irqchip; + + /* always 64 events */ + intc->domain = irq_domain_add_linear(dev->of_node, MAX_PRU_SYS_EVENTS, + &pruss_intc_irq_domain_ops, intc); + if (!intc->domain) + return -ENOMEM; + + for (i = 0; i < MAX_NUM_HOST_IRQS; i++) { + irq = platform_get_irq_byname(pdev, irq_names[i]); + if (irq < 0) { + dev_err(dev, "platform_get_irq_byname failed for %s : %d\n", + irq_names[i], irq); + goto fail_irq; + } + + intc->irqs[i] = irq; + irq_set_handler_data(irq, intc); + irq_set_chained_handler(irq, pruss_intc_irq_handler); + } + + return 0; + +fail_irq: + while (--i >= 0) { + if (intc->irqs[i]) + irq_set_chained_handler_and_data(intc->irqs[i], NULL, + NULL); + } + irq_domain_remove(intc->domain); + return irq; +} + +static int pruss_intc_remove(struct platform_device *pdev) +{ + struct pruss_intc *intc = platform_get_drvdata(pdev); + unsigned int hwirq; + int i; + + for (i = 0; i < MAX_NUM_HOST_IRQS; i++) { + if (intc->irqs[i]) + irq_set_chained_handler_and_data(intc->irqs[i], NULL, + NULL); + } + + for (hwirq = 0; hwirq < MAX_PRU_SYS_EVENTS; hwirq++) + irq_dispose_mapping(irq_find_mapping(intc->domain, hwirq)); + irq_domain_remove(intc->domain); + + return 0; +} + +static const struct of_device_id pruss_intc_of_match[] = { + { .compatible = "ti,pruss-intc", }, + { /* sentinel */ }, +}; +MODULE_DEVICE_TABLE(of, pruss_intc_of_match); + +static struct platform_driver pruss_intc_driver = { + .driver = { + .name = "pruss-intc", + .of_match_table = pruss_intc_of_match, + }, + .probe = pruss_intc_probe, + .remove = pruss_intc_remove, +}; +module_platform_driver(pruss_intc_driver); + +MODULE_AUTHOR("Andrew F. Davis "); +MODULE_AUTHOR("Suman Anna "); +MODULE_DESCRIPTION("TI PRU-ICSS INTC Driver"); +MODULE_LICENSE("GPL v2"); From patchwork Wed Jul 31 22:41:46 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Suman Anna X-Patchwork-Id: 11069757 Return-Path: Received: from mail.wl.linuxfoundation.org (pdx-wl-mail.web.codeaurora.org [172.30.200.125]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id 8F5EF13AC for ; Wed, 31 Jul 2019 22:43:56 +0000 (UTC) Received: from mail.wl.linuxfoundation.org (localhost [127.0.0.1]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id 7FD5B280B0 for ; Wed, 31 Jul 2019 22:43:56 +0000 (UTC) Received: by mail.wl.linuxfoundation.org (Postfix, from userid 486) id 7445828068; Wed, 31 Jul 2019 22:43:56 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on pdx-wl-mail.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-5.2 required=2.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,MAILING_LIST_MULTI,RCVD_IN_DNSWL_MED autolearn=ham version=3.3.1 Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.wl.linuxfoundation.org (Postfix) with ESMTPS id 7DF9F280B0 for ; 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Wed, 31 Jul 2019 17:42:42 -0500 Received: from lelv0327.itg.ti.com (10.180.67.183) by DFLE109.ent.ti.com (10.64.6.30) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.1713.5 via Frontend Transport; Wed, 31 Jul 2019 17:42:42 -0500 Received: from legion.dal.design.ti.com (legion.dal.design.ti.com [128.247.22.53]) by lelv0327.itg.ti.com (8.15.2/8.15.2) with ESMTP id x6VMggGg128520; Wed, 31 Jul 2019 17:42:42 -0500 Received: from localhost (irmo.dhcp.ti.com [128.247.58.153]) by legion.dal.design.ti.com (8.11.7p1+Sun/8.11.7) with ESMTP id x6VMggZ25783; Wed, 31 Jul 2019 17:42:42 -0500 (CDT) From: Suman Anna To: Marc Zyngier , Thomas Gleixner , Jason Cooper Subject: [PATCH v2 3/6] irqchip/irq-pruss-intc: Add support for shared and invalid interrupts Date: Wed, 31 Jul 2019 17:41:46 -0500 Message-ID: <20190731224149.11153-4-s-anna@ti.com> X-Mailer: git-send-email 2.22.0 In-Reply-To: <20190731224149.11153-1-s-anna@ti.com> References: <20190731224149.11153-1-s-anna@ti.com> MIME-Version: 1.0 X-EXCLAIMER-MD-CONFIG: e1e8a2fd-e40a-4ac6-ac9b-f7e9cc9ee180 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20190731_154346_907542_9D411F14 X-CRM114-Status: GOOD ( 21.11 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: devicetree@vger.kernel.org, Grygorii Strashko , David Lechner , Tony Lindgren , Sekhar Nori , linux-kernel@vger.kernel.org, "Andrew F. Davis" , Lokesh Vutla , Rob Herring , Murali Karicheri , linux-omap@vger.kernel.org, linux-arm-kernel@lists.infradead.org, Roger Quadros Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+patchwork-linux-arm=patchwork.kernel.org@lists.infradead.org X-Virus-Scanned: ClamAV using ClamSMTP The PRUSS INTC has a fixed number of output interrupt lines that are connected to a number of processors or other PRUSS instances or other devices (like DMA) on the SoC. The output interrupt lines 2 through 9 are usually connected to the main Arm host processor and are referred to as host interrupts 0 through 7 from ARM/MPU perspective. All of these 8 host interrupts are not always exclusively connected to the Arm interrupt controller. Some SoCs have some interrupt lines not connected to the Arm interrupt controller at all, while a few others have the interrupt lines connected to multiple processors in which they need to be partitioned as per SoC integration needs. For example, AM437x and 66AK2G SoCs have 2 PRUSS instances each and have the host interrupt 5 connected to the other PRUSS, while AM335x has host interrupt 0 shared between MPU and TSC_ADC and host interrupts 6 & 7 shared between MPU and a DMA controller. Add support to the PRUSS INTC driver to allow both these shared and invalid interrupts by not returning a failure if any of these interrupts are skipped from the corresponding INTC DT node. Signed-off-by: Suman Anna --- v2: - Fixed a typo in error message trace for ti,irqs-shared - Updated patch description to use generic "interrupt controller" instead of GIC - Revised the kerneldoc comment for invalid_intr v1: https://patchwork.kernel.org/patch/11034559/ drivers/irqchip/irq-pruss-intc.c | 44 +++++++++++++++++++++++++++++++- 1 file changed, 43 insertions(+), 1 deletion(-) diff --git a/drivers/irqchip/irq-pruss-intc.c b/drivers/irqchip/irq-pruss-intc.c index 4a9456544fd0..3a1b8a93cfad 100644 --- a/drivers/irqchip/irq-pruss-intc.c +++ b/drivers/irqchip/irq-pruss-intc.c @@ -67,6 +67,8 @@ * @irqchip: irq chip for this interrupt controller * @domain: irq domain for this interrupt controller * @lock: mutex to serialize access to INTC + * @shared_intr: bit-map denoting if the MPU host interrupt is shared + * @invalid_intr: bit-map denoting if host interrupt is not connected to MPU */ struct pruss_intc { unsigned int irqs[MAX_NUM_HOST_IRQS]; @@ -74,6 +76,8 @@ struct pruss_intc { struct irq_chip *irqchip; struct irq_domain *domain; struct mutex lock; /* PRUSS INTC lock */ + u16 shared_intr; + u16 invalid_intr; }; static inline u32 pruss_intc_read_reg(struct pruss_intc *intc, unsigned int reg) @@ -233,7 +237,8 @@ static int pruss_intc_probe(struct platform_device *pdev) struct pruss_intc *intc; struct resource *res; struct irq_chip *irqchip; - int i, irq; + int i, irq, count; + u8 temp_intr[MAX_NUM_HOST_IRQS] = { 0 }; intc = devm_kzalloc(dev, sizeof(*intc), GFP_KERNEL); if (!intc) @@ -250,6 +255,39 @@ static int pruss_intc_probe(struct platform_device *pdev) dev_dbg(dev, "intc memory: pa %pa size 0x%zx va %pK\n", &res->start, (size_t)resource_size(res), intc->base); + count = of_property_read_variable_u8_array(dev->of_node, + "ti,irqs-reserved", + temp_intr, 0, + MAX_NUM_HOST_IRQS); + if (count < 0 && count != -EINVAL) + return count; + count = (count == -EINVAL ? 0 : count); + for (i = 0; i < count; i++) { + if (temp_intr[i] < MAX_NUM_HOST_IRQS) { + intc->invalid_intr |= BIT(temp_intr[i]); + } else { + dev_warn(dev, "ignoring invalid reserved irq %d\n", + temp_intr[i]); + } + temp_intr[i] = 0; + } + + count = of_property_read_variable_u8_array(dev->of_node, + "ti,irqs-shared", + temp_intr, 0, + MAX_NUM_HOST_IRQS); + if (count < 0 && count != -EINVAL) + return count; + count = (count == -EINVAL ? 0 : count); + for (i = 0; i < count; i++) { + if (temp_intr[i] < MAX_NUM_HOST_IRQS) { + intc->shared_intr |= BIT(temp_intr[i]); + } else { + dev_warn(dev, "ignoring invalid shared irq %d\n", + temp_intr[i]); + } + } + mutex_init(&intc->lock); pruss_intc_init(intc); @@ -275,6 +313,10 @@ static int pruss_intc_probe(struct platform_device *pdev) for (i = 0; i < MAX_NUM_HOST_IRQS; i++) { irq = platform_get_irq_byname(pdev, irq_names[i]); if (irq < 0) { + if (intc->shared_intr & BIT(i) || + intc->invalid_intr & BIT(i)) + continue; + dev_err(dev, "platform_get_irq_byname failed for %s : %d\n", irq_names[i], irq); goto fail_irq; From patchwork Wed Jul 31 22:41:47 2019 Content-Type: text/plain; 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Wed, 31 Jul 2019 17:42:43 -0500 Received: from lelv0326.itg.ti.com (10.180.67.84) by DLEE114.ent.ti.com (157.170.170.25) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.1713.5 via Frontend Transport; Wed, 31 Jul 2019 17:42:43 -0500 Received: from legion.dal.design.ti.com (legion.dal.design.ti.com [128.247.22.53]) by lelv0326.itg.ti.com (8.15.2/8.15.2) with ESMTP id x6VMgh2Q074928; Wed, 31 Jul 2019 17:42:43 -0500 Received: from localhost (irmo.dhcp.ti.com [128.247.58.153]) by legion.dal.design.ti.com (8.11.7p1+Sun/8.11.7) with ESMTP id x6VMghZ25787; Wed, 31 Jul 2019 17:42:43 -0500 (CDT) From: Suman Anna To: Marc Zyngier , Thomas Gleixner , Jason Cooper Subject: [PATCH v2 4/6] irqchip/irq-pruss-intc: Add helper functions to configure internal mapping Date: Wed, 31 Jul 2019 17:41:47 -0500 Message-ID: <20190731224149.11153-5-s-anna@ti.com> X-Mailer: git-send-email 2.22.0 In-Reply-To: <20190731224149.11153-1-s-anna@ti.com> References: <20190731224149.11153-1-s-anna@ti.com> MIME-Version: 1.0 X-EXCLAIMER-MD-CONFIG: e1e8a2fd-e40a-4ac6-ac9b-f7e9cc9ee180 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20190731_154339_327697_8597EB9F X-CRM114-Status: GOOD ( 28.12 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: devicetree@vger.kernel.org, Grygorii Strashko , David Lechner , Tony Lindgren , Sekhar Nori , linux-kernel@vger.kernel.org, "Andrew F. Davis" , Lokesh Vutla , Rob Herring , Murali Karicheri , linux-omap@vger.kernel.org, linux-arm-kernel@lists.infradead.org, Roger Quadros Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+patchwork-linux-arm=patchwork.kernel.org@lists.infradead.org X-Virus-Scanned: ClamAV using ClamSMTP The PRUSS INTC receives a number of system input interrupt source events and supports individual control configuration and hardware prioritization. These input events can be mapped to some output interrupt lines through 2 levels of many-to-one mapping i.e. events to channel mapping and channels to output interrupts. This mapping information is provided through the PRU firmware that is loaded onto a PRU core/s or through the device tree node of the PRU application. The mapping is configured by the PRU remoteproc driver, and is setup before the PRU core is started and cleaned up after the PRU core is stopped. This event mapping configuration logic programs the Channel Map Registers (CMRx) and Host-Interrupt Map Registers (HMRx) only when a new program is being loaded/started and the same events and interrupt channels are reset to zero when stopping a PRU. Add two helper functions: pruss_intc_configure() & pruss_intc_unconfigure() that the PRU remoteproc driver can use to configure the PRUSS INTC. Signed-off-by: Suman Anna Signed-off-by: Andrew F. Davis Signed-off-by: Roger Quadros Signed-off-by: Suman Anna Signed-off-by: Andrew F. Davis Signed-off-by: Roger Quadros Signed-off-by: David Lechner --- v2: - Added new internal helper functions pruss_intc_update_cmr/hmr for programming CMR and HMR registers - Added unroll logic on failures in pruss_intc_configure() using the refactored functions - Updated unconfigure logic to reset the map registers and updated patch description accordingly - Renamed the FREE macro to PRU_INTC_FREE and moved it to header file v1: https://patchwork.kernel.org/patch/11034563/ drivers/irqchip/irq-pruss-intc.c | 286 ++++++++++++++++++++++++- include/linux/irqchip/irq-pruss-intc.h | 36 ++++ 2 files changed, 320 insertions(+), 2 deletions(-) create mode 100644 include/linux/irqchip/irq-pruss-intc.h diff --git a/drivers/irqchip/irq-pruss-intc.c b/drivers/irqchip/irq-pruss-intc.c index 3a1b8a93cfad..63cfc665be1e 100644 --- a/drivers/irqchip/irq-pruss-intc.c +++ b/drivers/irqchip/irq-pruss-intc.c @@ -9,6 +9,7 @@ #include #include +#include #include #include #include @@ -24,8 +25,8 @@ /* minimum starting host interrupt number for MPU */ #define MIN_PRU_HOST_INT 2 -/* maximum number of system events */ -#define MAX_PRU_SYS_EVENTS 64 +/* maximum number of host interrupts */ +#define MAX_PRU_HOST_INT 10 /* PRU_ICSS_INTC registers */ #define PRU_INTC_REVID 0x0000 @@ -57,6 +58,16 @@ #define PRU_INTC_HINLR(x) (0x1100 + (x) * 4) #define PRU_INTC_HIER 0x1500 +/* CMR register bit-field macros */ +#define CMR_EVT_MAP_MASK 0xf +#define CMR_EVT_MAP_BITS 8 +#define CMR_EVT_PER_REG 4 + +/* HMR register bit-field macros */ +#define HMR_CH_MAP_MASK 0xf +#define HMR_CH_MAP_BITS 8 +#define HMR_CH_PER_REG 4 + /* HIPIR register bit-fields */ #define INTC_HIPIR_NONE_HINT 0x80000000 @@ -66,7 +77,9 @@ * @base: base virtual address of INTC register space * @irqchip: irq chip for this interrupt controller * @domain: irq domain for this interrupt controller + * @config_map: stored INTC configuration mapping data * @lock: mutex to serialize access to INTC + * @host_mask: indicate which HOST IRQs are enabled * @shared_intr: bit-map denoting if the MPU host interrupt is shared * @invalid_intr: bit-map denoting if host interrupt is not connected to MPU */ @@ -75,7 +88,9 @@ struct pruss_intc { void __iomem *base; struct irq_chip *irqchip; struct irq_domain *domain; + struct pruss_intc_config config_map; struct mutex lock; /* PRUSS INTC lock */ + u32 host_mask; u16 shared_intr; u16 invalid_intr; }; @@ -105,6 +120,267 @@ static int pruss_intc_check_write(struct pruss_intc *intc, unsigned int reg, return 0; } +static void pruss_intc_update_cmr(struct pruss_intc *intc, int evt, s8 ch) +{ + u32 idx, val; + + idx = evt / CMR_EVT_PER_REG; + val = pruss_intc_read_reg(intc, PRU_INTC_CMR(idx)); + val &= ~(CMR_EVT_MAP_MASK << + ((evt % CMR_EVT_PER_REG) * CMR_EVT_MAP_BITS)); + val |= ch << ((evt % CMR_EVT_PER_REG) * CMR_EVT_MAP_BITS); + pruss_intc_write_reg(intc, PRU_INTC_CMR(idx), val); +} + +static void pruss_intc_update_hmr(struct pruss_intc *intc, int ch, s8 host) +{ + u32 idx, val; + + idx = ch / HMR_CH_PER_REG; + val = pruss_intc_read_reg(intc, PRU_INTC_HMR(idx)); + val &= ~(HMR_CH_MAP_MASK << + ((ch % HMR_CH_PER_REG) * HMR_CH_MAP_BITS)); + val |= host << ((ch % HMR_CH_PER_REG) * HMR_CH_MAP_BITS); + pruss_intc_write_reg(intc, PRU_INTC_HMR(idx), val); +} + +static struct pruss_intc *to_pruss_intc(struct device *pru_dev) +{ + struct device_node *np; + struct platform_device *pdev; + struct device *pruss_dev = pru_dev->parent; + struct pruss_intc *intc = ERR_PTR(-ENODEV); + + np = of_get_child_by_name(pruss_dev->of_node, "interrupt-controller"); + if (!np) { + dev_err(pruss_dev, "pruss does not have an interrupt-controller node\n"); + return intc; + } + + pdev = of_find_device_by_node(np); + if (!pdev) { + dev_err(pruss_dev, "no associated platform device\n"); + goto out; + } + + intc = platform_get_drvdata(pdev); + if (!intc) { + dev_err(pruss_dev, "pruss intc device probe failed?\n"); + intc = ERR_PTR(-EINVAL); + } + +out: + of_node_put(np); + return intc; +} + +/** + * pruss_intc_configure() - configure the PRUSS INTC + * @dev: pru device pointer + * @intc_config: PRU core-specific INTC configuration + * + * Configures the PRUSS INTC with the provided configuration from + * a PRU core. Any existing event to channel mappings or channel to + * host interrupt mappings are checked to make sure there are no + * conflicting configuration between both the PRU cores. The function + * is intended to be used only by the PRU remoteproc driver. + * + * Returns 0 on success, or a suitable error code otherwise + */ +int pruss_intc_configure(struct device *dev, + struct pruss_intc_config *intc_config) +{ + struct pruss_intc *intc; + int i, idx, ret; + s8 ch, host; + u64 sysevt_mask = 0; + u32 ch_mask = 0; + u32 host_mask = 0; + + intc = to_pruss_intc(dev); + if (IS_ERR(intc)) + return PTR_ERR(intc); + + mutex_lock(&intc->lock); + + /* + * configure channel map registers - each register holds map info + * for 4 events, with each event occupying the lower nibble in + * a register byte address in little-endian fashion + */ + for (i = 0; i < ARRAY_SIZE(intc_config->sysev_to_ch); i++) { + ch = intc_config->sysev_to_ch[i]; + if (ch < 0) + continue; + + /* check if sysevent already assigned */ + if (intc->config_map.sysev_to_ch[i] != PRU_INTC_FREE) { + dev_err(dev, "event %d (req. channel %d) already assigned to channel %d\n", + i, ch, intc->config_map.sysev_to_ch[i]); + ret = -EEXIST; + goto fail_evt; + } + + intc->config_map.sysev_to_ch[i] = ch; + pruss_intc_update_cmr(intc, i, ch); + sysevt_mask |= BIT_ULL(i); + ch_mask |= BIT(ch); + idx = i / CMR_EVT_PER_REG; + + dev_dbg(dev, "SYSEVT%d -> CH%d (CMR%d 0x%08x)\n", i, ch, idx, + pruss_intc_read_reg(intc, PRU_INTC_CMR(idx))); + } + + /* + * set host map registers - each register holds map info for + * 4 channels, with each channel occupying the lower nibble in + * a register byte address in little-endian fashion + */ + for (i = 0; i < ARRAY_SIZE(intc_config->ch_to_host); i++) { + host = intc_config->ch_to_host[i]; + if (host < 0) + continue; + + /* check if channel already assigned */ + if (intc->config_map.ch_to_host[i] != PRU_INTC_FREE) { + dev_err(dev, "channel %d (req. intr_no %d) already assigned to intr_no %d\n", + i, host, intc->config_map.ch_to_host[i]); + ret = -EEXIST; + goto fail_ch; + } + + /* check if host intr is already in use by other PRU */ + if (intc->host_mask & (1U << host)) { + dev_err(dev, "%s: host intr %d already in use\n", + __func__, host); + ret = -EEXIST; + goto fail_ch; + } + + intc->config_map.ch_to_host[i] = host; + pruss_intc_update_hmr(intc, i, host); + ch_mask |= BIT(i); + host_mask |= BIT(host); + idx = i / HMR_CH_PER_REG; + + dev_dbg(dev, "CH%d -> HOST%d (HMR%d 0x%08x)\n", i, host, idx, + pruss_intc_read_reg(intc, PRU_INTC_HMR(idx))); + } + + dev_info(dev, "configured system_events = 0x%016llx intr_channels = 0x%08x host_intr = 0x%08x\n", + sysevt_mask, ch_mask, host_mask); + + /* enable system events, writing 0 has no-effect */ + pruss_intc_write_reg(intc, PRU_INTC_ESR0, lower_32_bits(sysevt_mask)); + pruss_intc_write_reg(intc, PRU_INTC_SECR0, lower_32_bits(sysevt_mask)); + pruss_intc_write_reg(intc, PRU_INTC_ESR1, upper_32_bits(sysevt_mask)); + pruss_intc_write_reg(intc, PRU_INTC_SECR1, upper_32_bits(sysevt_mask)); + + /* enable host interrupts */ + for (i = 0; i < MAX_PRU_HOST_INT; i++) { + if (host_mask & BIT(i)) + pruss_intc_write_reg(intc, PRU_INTC_HIEISR, i); + } + + /* global interrupt enable */ + pruss_intc_write_reg(intc, PRU_INTC_GER, 1); + + intc->host_mask |= host_mask; + + mutex_unlock(&intc->lock); + return 0; + +fail_ch: + while (--i >= 0) { + if (intc_config->ch_to_host[i] >= 0) { + intc->config_map.ch_to_host[i] = PRU_INTC_FREE; + pruss_intc_update_hmr(intc, i, 0); + } + } + i = ARRAY_SIZE(intc_config->sysev_to_ch); +fail_evt: + while (--i >= 0) { + if (intc_config->sysev_to_ch[i] >= 0) { + intc->config_map.sysev_to_ch[i] = PRU_INTC_FREE; + pruss_intc_update_cmr(intc, i, 0); + } + } + mutex_unlock(&intc->lock); + return ret; +} +EXPORT_SYMBOL_GPL(pruss_intc_configure); + +/** + * pruss_intc_unconfigure() - unconfigure the PRUSS INTC + * @dev: pru device pointer + * @intc_config: PRU core specific INTC configuration + * + * Undo whatever was done in pruss_intc_configure() for a PRU core. + * It should be sufficient to just mark the resources free in the + * global map and disable the host interrupts and sysevents. + */ +int pruss_intc_unconfigure(struct device *dev, + struct pruss_intc_config *intc_config) +{ + struct pruss_intc *intc; + int i; + s8 ch, host; + u64 sysevt_mask = 0; + u32 host_mask = 0; + + intc = to_pruss_intc(dev); + if (IS_ERR(intc)) + return PTR_ERR(intc); + + mutex_lock(&intc->lock); + + for (i = 0; i < ARRAY_SIZE(intc_config->sysev_to_ch); i++) { + ch = intc_config->sysev_to_ch[i]; + if (ch < 0) + continue; + + /* mark sysevent free in global map */ + intc->config_map.sysev_to_ch[i] = PRU_INTC_FREE; + sysevt_mask |= BIT_ULL(i); + /* clear the map using reset value 0 */ + pruss_intc_update_cmr(intc, i, 0); + } + + for (i = 0; i < ARRAY_SIZE(intc_config->ch_to_host); i++) { + host = intc_config->ch_to_host[i]; + if (host < 0) + continue; + + /* mark channel free in global map */ + intc->config_map.ch_to_host[i] = PRU_INTC_FREE; + host_mask |= BIT(host); + /* clear the map using reset value 0 */ + pruss_intc_update_hmr(intc, i, 0); + } + + dev_info(dev, "unconfigured system_events = 0x%016llx host_intr = 0x%08x\n", + sysevt_mask, host_mask); + + /* disable system events, writing 0 has no-effect */ + pruss_intc_write_reg(intc, PRU_INTC_ECR0, lower_32_bits(sysevt_mask)); + pruss_intc_write_reg(intc, PRU_INTC_ECR1, upper_32_bits(sysevt_mask)); + /* clear any pending status */ + pruss_intc_write_reg(intc, PRU_INTC_SECR0, lower_32_bits(sysevt_mask)); + pruss_intc_write_reg(intc, PRU_INTC_SECR1, upper_32_bits(sysevt_mask)); + + /* disable host interrupts */ + for (i = 0; i < MAX_PRU_HOST_INT; i++) { + if (host_mask & BIT(i)) + pruss_intc_write_reg(intc, PRU_INTC_HIDISR, i); + } + + intc->host_mask &= ~host_mask; + mutex_unlock(&intc->lock); + + return 0; +} +EXPORT_SYMBOL_GPL(pruss_intc_unconfigure); + static void pruss_intc_init(struct pruss_intc *intc) { int i; @@ -290,6 +566,12 @@ static int pruss_intc_probe(struct platform_device *pdev) mutex_init(&intc->lock); + for (i = 0; i < ARRAY_SIZE(intc->config_map.sysev_to_ch); i++) + intc->config_map.sysev_to_ch[i] = PRU_INTC_FREE; + + for (i = 0; i < ARRAY_SIZE(intc->config_map.ch_to_host); i++) + intc->config_map.ch_to_host[i] = PRU_INTC_FREE; + pruss_intc_init(intc); irqchip = devm_kzalloc(dev, sizeof(*irqchip), GFP_KERNEL); diff --git a/include/linux/irqchip/irq-pruss-intc.h b/include/linux/irqchip/irq-pruss-intc.h new file mode 100644 index 000000000000..daffc048b303 --- /dev/null +++ b/include/linux/irqchip/irq-pruss-intc.h @@ -0,0 +1,36 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +/* + * PRU-ICSS sub-system private interfaces + * + * Copyright (C) 2019 Texas Instruments Incorporated - http://www.ti.com/ + * Suman Anna + */ + +#ifndef __LINUX_IRQ_PRUSS_INTC_H +#define __LINUX_IRQ_PRUSS_INTC_H + +/* maximum number of system events */ +#define MAX_PRU_SYS_EVENTS 64 + +/* maximum number of interrupt channels */ +#define MAX_PRU_CHANNELS 10 + +/* use -1 to mark unassigned events and channels */ +#define PRU_INTC_FREE -1 + +/** + * struct pruss_intc_config - INTC configuration info + * @sysev_to_ch: system events to channel mapping information + * @ch_to_host: interrupt channel to host interrupt information + */ +struct pruss_intc_config { + s8 sysev_to_ch[MAX_PRU_SYS_EVENTS]; + s8 ch_to_host[MAX_PRU_CHANNELS]; +}; + +int pruss_intc_configure(struct device *dev, + struct pruss_intc_config *intc_config); +int pruss_intc_unconfigure(struct device *dev, + struct pruss_intc_config *intc_config); + +#endif /* __LINUX_IRQ_PRUSS_INTC_H */ From patchwork Wed Jul 31 22:41:48 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Suman Anna X-Patchwork-Id: 11069769 Return-Path: Received: from mail.wl.linuxfoundation.org (pdx-wl-mail.web.codeaurora.org [172.30.200.125]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id CCB0E746 for ; Wed, 31 Jul 2019 22:44:22 +0000 (UTC) Received: from mail.wl.linuxfoundation.org (localhost [127.0.0.1]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id BBC43204FA for ; Wed, 31 Jul 2019 22:44:22 +0000 (UTC) Received: by mail.wl.linuxfoundation.org (Postfix, from userid 486) id AFEBE28068; Wed, 31 Jul 2019 22:44:22 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on pdx-wl-mail.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-5.2 required=2.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,MAILING_LIST_MULTI,RCVD_IN_DNSWL_MED autolearn=ham version=3.3.1 Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.wl.linuxfoundation.org (Postfix) with ESMTPS id 3CFF427FE4 for ; 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Wed, 31 Jul 2019 17:42:44 -0500 Received: from lelv0327.itg.ti.com (10.180.67.183) by DLEE112.ent.ti.com (157.170.170.23) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.1713.5 via Frontend Transport; Wed, 31 Jul 2019 17:42:45 -0500 Received: from legion.dal.design.ti.com (legion.dal.design.ti.com [128.247.22.53]) by lelv0327.itg.ti.com (8.15.2/8.15.2) with ESMTP id x6VMgiGE128542; Wed, 31 Jul 2019 17:42:44 -0500 Received: from localhost (irmo.dhcp.ti.com [128.247.58.153]) by legion.dal.design.ti.com (8.11.7p1+Sun/8.11.7) with ESMTP id x6VMghZ25799; Wed, 31 Jul 2019 17:42:44 -0500 (CDT) From: Suman Anna To: Marc Zyngier , Thomas Gleixner , Jason Cooper Subject: [PATCH v2 5/6] irqchip/irq-pruss-intc: Implement irq_{get, set}_irqchip_state ops Date: Wed, 31 Jul 2019 17:41:48 -0500 Message-ID: <20190731224149.11153-6-s-anna@ti.com> X-Mailer: git-send-email 2.22.0 In-Reply-To: <20190731224149.11153-1-s-anna@ti.com> References: <20190731224149.11153-1-s-anna@ti.com> MIME-Version: 1.0 X-EXCLAIMER-MD-CONFIG: e1e8a2fd-e40a-4ac6-ac9b-f7e9cc9ee180 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20190731_154347_031794_F527D956 X-CRM114-Status: GOOD ( 15.69 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: devicetree@vger.kernel.org, Grygorii Strashko , David Lechner , Tony Lindgren , Sekhar Nori , linux-kernel@vger.kernel.org, "Andrew F. Davis" , Lokesh Vutla , Rob Herring , Murali Karicheri , linux-omap@vger.kernel.org, linux-arm-kernel@lists.infradead.org, Roger Quadros Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+patchwork-linux-arm=patchwork.kernel.org@lists.infradead.org X-Virus-Scanned: ClamAV using ClamSMTP From: David Lechner This implements the irq_get_irqchip_state and irq_set_irqchip_state callbacks for the TI PRUSS INTC driver. The set callback can be used by drivers to "kick" a PRU by enabling a PRU system event. Example: irq_set_irqchip_state(irq, IRQCHIP_STATE_PENDING, true); Signed-off-by: David Lechner Signed-off-by: Suman Anna --- v2: New patch from David replacing an exported API from v1, https://patchwork.kernel.org/patch/11034565/ drivers/irqchip/irq-pruss-intc.c | 41 ++++++++++++++++++++++++++++++-- 1 file changed, 39 insertions(+), 2 deletions(-) diff --git a/drivers/irqchip/irq-pruss-intc.c b/drivers/irqchip/irq-pruss-intc.c index 63cfc665be1e..59e26dfbb179 100644 --- a/drivers/irqchip/irq-pruss-intc.c +++ b/drivers/irqchip/irq-pruss-intc.c @@ -7,6 +7,7 @@ * Suman Anna */ +#include #include #include #include @@ -40,8 +41,7 @@ #define PRU_INTC_HIEISR 0x0034 #define PRU_INTC_HIDISR 0x0038 #define PRU_INTC_GPIR 0x0080 -#define PRU_INTC_SRSR0 0x0200 -#define PRU_INTC_SRSR1 0x0204 +#define PRU_INTC_SRSR(x) (0x0200 + (x) * 4) #define PRU_INTC_SECR0 0x0280 #define PRU_INTC_SECR1 0x0284 #define PRU_INTC_ESR0 0x0300 @@ -439,6 +439,41 @@ static void pruss_intc_irq_relres(struct irq_data *data) module_put(THIS_MODULE); } +static int pruss_intc_irq_get_irqchip_state(struct irq_data *data, + enum irqchip_irq_state which, + bool *state) +{ + struct pruss_intc *intc = irq_data_get_irq_chip_data(data); + u32 reg, mask, srsr; + + if (which != IRQCHIP_STATE_PENDING) + return -EINVAL; + + reg = PRU_INTC_SRSR(data->hwirq / 32); + mask = BIT(data->hwirq % 32); + + srsr = pruss_intc_read_reg(intc, reg); + + *state = !!(srsr & mask); + + return 0; +} + +static int pruss_intc_irq_set_irqchip_state(struct irq_data *data, + enum irqchip_irq_state which, + bool state) +{ + struct pruss_intc *intc = irq_data_get_irq_chip_data(data); + + if (which != IRQCHIP_STATE_PENDING) + return -EINVAL; + + if (state) + return pruss_intc_check_write(intc, PRU_INTC_SISR, data->hwirq); + + return pruss_intc_check_write(intc, PRU_INTC_SICR, data->hwirq); +} + static int pruss_intc_irq_domain_map(struct irq_domain *d, unsigned int virq, irq_hw_number_t hw) { @@ -583,6 +618,8 @@ static int pruss_intc_probe(struct platform_device *pdev) irqchip->irq_unmask = pruss_intc_irq_unmask; irqchip->irq_request_resources = pruss_intc_irq_reqres; irqchip->irq_release_resources = pruss_intc_irq_relres; + irqchip->irq_get_irqchip_state = pruss_intc_irq_get_irqchip_state; + irqchip->irq_set_irqchip_state = pruss_intc_irq_set_irqchip_state; irqchip->name = dev_name(dev); intc->irqchip = irqchip; From patchwork Wed Jul 31 22:41:49 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Suman Anna X-Patchwork-Id: 11069773 Return-Path: Received: from mail.wl.linuxfoundation.org (pdx-wl-mail.web.codeaurora.org [172.30.200.125]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id 95638174A for ; Wed, 31 Jul 2019 22:44:47 +0000 (UTC) Received: from mail.wl.linuxfoundation.org (localhost [127.0.0.1]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id 822E1204FA for ; Wed, 31 Jul 2019 22:44:47 +0000 (UTC) Received: by mail.wl.linuxfoundation.org (Postfix, from userid 486) id 75F2128068; Wed, 31 Jul 2019 22:44:47 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on pdx-wl-mail.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-5.2 required=2.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,MAILING_LIST_MULTI,RCVD_IN_DNSWL_MED autolearn=ham version=3.3.1 Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.wl.linuxfoundation.org (Postfix) with ESMTPS id 87FE7204FA for ; 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Wed, 31 Jul 2019 17:42:46 -0500 Received: from fllv0039.itg.ti.com (10.64.41.19) by DLEE107.ent.ti.com (157.170.170.37) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.1713.5 via Frontend Transport; Wed, 31 Jul 2019 17:42:46 -0500 Received: from legion.dal.design.ti.com (legion.dal.design.ti.com [128.247.22.53]) by fllv0039.itg.ti.com (8.15.2/8.15.2) with ESMTP id x6VMgka4072719; Wed, 31 Jul 2019 17:42:46 -0500 Received: from localhost (irmo.dhcp.ti.com [128.247.58.153]) by legion.dal.design.ti.com (8.11.7p1+Sun/8.11.7) with ESMTP id x6VMgjZ25821; Wed, 31 Jul 2019 17:42:45 -0500 (CDT) From: Suman Anna To: Marc Zyngier , Thomas Gleixner , Jason Cooper Subject: [PATCH v2 6/6] irqchip/irq-pruss-intc: Add support for ICSSG INTC on K3 SoCs Date: Wed, 31 Jul 2019 17:41:49 -0500 Message-ID: <20190731224149.11153-7-s-anna@ti.com> X-Mailer: git-send-email 2.22.0 In-Reply-To: <20190731224149.11153-1-s-anna@ti.com> References: <20190731224149.11153-1-s-anna@ti.com> MIME-Version: 1.0 X-EXCLAIMER-MD-CONFIG: e1e8a2fd-e40a-4ac6-ac9b-f7e9cc9ee180 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20190731_154346_900374_A655F203 X-CRM114-Status: GOOD ( 24.82 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: devicetree@vger.kernel.org, Grygorii Strashko , David Lechner , Tony Lindgren , Sekhar Nori , linux-kernel@vger.kernel.org, "Andrew F. Davis" , Lokesh Vutla , Rob Herring , Murali Karicheri , linux-omap@vger.kernel.org, linux-arm-kernel@lists.infradead.org, Roger Quadros Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+patchwork-linux-arm=patchwork.kernel.org@lists.infradead.org X-Virus-Scanned: ClamAV using ClamSMTP The K3 AM65x and J721E SoCs have the next generation of the PRU-ICSS IP, commonly called ICSSG. The PRUSS INTC present within the ICSSG supports more System Events (160 vs 64), more Interrupt Channels and Host Interrupts (20 vs 10) compared to the previous generation PRUSS INTC instances. The first 2 and the last 10 of these host interrupt lines are used by the PRU and other auxiliary cores and sub-modules within the ICSSG, with 8 host interrupts connected to MPU. The host interrupts 5, 6, 7 are also connected to the other ICSSG instances within the SoC and can be partitioned as per system integration through the board dts files. Enhance the PRUSS INTC driver to add support for this ICSSG INTC instance. This support is added using specific compatible and match data and updating the code to use this data instead of the current hard-coded macros. The INTC config structure is updated to use the higher events and channels on all SoCs, while limiting the actual processing to only the relevant number of events/channels/interrupts. Signed-off-by: Suman Anna --- v2: - Rebased patch with indexed macros like ESRx, ECRx where x = 0,1 dropped v1: https://patchwork.kernel.org/patch/11034543/ drivers/irqchip/Kconfig | 2 +- drivers/irqchip/irq-pruss-intc.c | 181 +++++++++++++++++-------- include/linux/irqchip/irq-pruss-intc.h | 4 +- 3 files changed, 126 insertions(+), 61 deletions(-) diff --git a/drivers/irqchip/Kconfig b/drivers/irqchip/Kconfig index dc6b5aa77a5d..a98bfec6b364 100644 --- a/drivers/irqchip/Kconfig +++ b/drivers/irqchip/Kconfig @@ -473,7 +473,7 @@ config TI_SCI_INTA_IRQCHIP config TI_PRUSS_INTC tristate "TI PRU-ICSS Interrupt Controller" - depends on ARCH_DAVINCI || SOC_AM33XX || SOC_AM437X || SOC_DRA7XX || ARCH_KEYSTONE + depends on ARCH_DAVINCI || SOC_AM33XX || SOC_AM437X || SOC_DRA7XX || ARCH_KEYSTONE || ARCH_K3 select IRQ_DOMAIN help This enables support for the PRU-ICSS Local Interrupt Controller diff --git a/drivers/irqchip/irq-pruss-intc.c b/drivers/irqchip/irq-pruss-intc.c index 59e26dfbb179..891a14b6c399 100644 --- a/drivers/irqchip/irq-pruss-intc.c +++ b/drivers/irqchip/irq-pruss-intc.c @@ -7,6 +7,7 @@ * Suman Anna */ +#include #include #include #include @@ -26,9 +27,6 @@ /* minimum starting host interrupt number for MPU */ #define MIN_PRU_HOST_INT 2 -/* maximum number of host interrupts */ -#define MAX_PRU_HOST_INT 10 - /* PRU_ICSS_INTC registers */ #define PRU_INTC_REVID 0x0000 #define PRU_INTC_CR 0x0004 @@ -42,19 +40,14 @@ #define PRU_INTC_HIDISR 0x0038 #define PRU_INTC_GPIR 0x0080 #define PRU_INTC_SRSR(x) (0x0200 + (x) * 4) -#define PRU_INTC_SECR0 0x0280 -#define PRU_INTC_SECR1 0x0284 -#define PRU_INTC_ESR0 0x0300 -#define PRU_INTC_ESR1 0x0304 -#define PRU_INTC_ECR0 0x0380 -#define PRU_INTC_ECR1 0x0384 +#define PRU_INTC_SECR(x) (0x0280 + (x) * 4) +#define PRU_INTC_ESR(x) (0x0300 + (x) * 4) +#define PRU_INTC_ECR(x) (0x0380 + (x) * 4) #define PRU_INTC_CMR(x) (0x0400 + (x) * 4) #define PRU_INTC_HMR(x) (0x0800 + (x) * 4) #define PRU_INTC_HIPIR(x) (0x0900 + (x) * 4) -#define PRU_INTC_SIPR0 0x0d00 -#define PRU_INTC_SIPR1 0x0d04 -#define PRU_INTC_SITR0 0x0d80 -#define PRU_INTC_SITR1 0x0d84 +#define PRU_INTC_SIPR(x) (0x0d00 + (x) * 4) +#define PRU_INTC_SITR(x) (0x0d80 + (x) * 4) #define PRU_INTC_HINLR(x) (0x1100 + (x) * 4) #define PRU_INTC_HIER 0x1500 @@ -71,12 +64,23 @@ /* HIPIR register bit-fields */ #define INTC_HIPIR_NONE_HINT 0x80000000 +/** + * struct pruss_intc_match_data - match data to handle SoC variations + * @num_system_events: number of input system events handled by the PRUSS INTC + * @num_host_intrs: number of host interrupts supported by the PRUSS INTC + */ +struct pruss_intc_match_data { + u8 num_system_events; + u8 num_host_intrs; +}; + /** * struct pruss_intc - PRUSS interrupt controller structure * @irqs: kernel irq numbers corresponding to PRUSS host interrupts * @base: base virtual address of INTC register space * @irqchip: irq chip for this interrupt controller * @domain: irq domain for this interrupt controller + * @data: cached PRUSS INTC IP configuration data * @config_map: stored INTC configuration mapping data * @lock: mutex to serialize access to INTC * @host_mask: indicate which HOST IRQs are enabled @@ -88,6 +92,7 @@ struct pruss_intc { void __iomem *base; struct irq_chip *irqchip; struct irq_domain *domain; + const struct pruss_intc_match_data *data; struct pruss_intc_config config_map; struct mutex lock; /* PRUSS INTC lock */ u32 host_mask; @@ -112,7 +117,7 @@ static int pruss_intc_check_write(struct pruss_intc *intc, unsigned int reg, if (!intc) return -EINVAL; - if (sysevent >= MAX_PRU_SYS_EVENTS) + if (sysevent >= intc->data->num_system_events) return -EINVAL; pruss_intc_write_reg(intc, reg, sysevent); @@ -191,16 +196,28 @@ int pruss_intc_configure(struct device *dev, struct pruss_intc_config *intc_config) { struct pruss_intc *intc; - int i, idx, ret; + int i, idx; s8 ch, host; - u64 sysevt_mask = 0; + u32 num_events, num_intrs, num_regs; + unsigned long *sysevt_bitmap; + u32 *sysevts; u32 ch_mask = 0; u32 host_mask = 0; + int ret = 0; intc = to_pruss_intc(dev); if (IS_ERR(intc)) return PTR_ERR(intc); + num_events = intc->data->num_system_events; + num_intrs = intc->data->num_host_intrs; + num_regs = DIV_ROUND_UP(num_events, 32); + + sysevt_bitmap = bitmap_zalloc(num_events, GFP_KERNEL); + if (!sysevt_bitmap) + return -ENOMEM; + sysevts = (u32 *)sysevt_bitmap; + mutex_lock(&intc->lock); /* @@ -208,7 +225,7 @@ int pruss_intc_configure(struct device *dev, * for 4 events, with each event occupying the lower nibble in * a register byte address in little-endian fashion */ - for (i = 0; i < ARRAY_SIZE(intc_config->sysev_to_ch); i++) { + for (i = 0; i < num_events; i++) { ch = intc_config->sysev_to_ch[i]; if (ch < 0) continue; @@ -223,7 +240,7 @@ int pruss_intc_configure(struct device *dev, intc->config_map.sysev_to_ch[i] = ch; pruss_intc_update_cmr(intc, i, ch); - sysevt_mask |= BIT_ULL(i); + bitmap_set(sysevt_bitmap, i, 1); ch_mask |= BIT(ch); idx = i / CMR_EVT_PER_REG; @@ -236,7 +253,7 @@ int pruss_intc_configure(struct device *dev, * 4 channels, with each channel occupying the lower nibble in * a register byte address in little-endian fashion */ - for (i = 0; i < ARRAY_SIZE(intc_config->ch_to_host); i++) { + for (i = 0; i < num_intrs; i++) { host = intc_config->ch_to_host[i]; if (host < 0) continue; @@ -267,17 +284,19 @@ int pruss_intc_configure(struct device *dev, pruss_intc_read_reg(intc, PRU_INTC_HMR(idx))); } - dev_info(dev, "configured system_events = 0x%016llx intr_channels = 0x%08x host_intr = 0x%08x\n", - sysevt_mask, ch_mask, host_mask); + dev_info(dev, "configured system_events[%d-0] = %*pb\n", + num_events - 1, num_events, sysevt_bitmap); + dev_info(dev, "configured intr_channels = 0x%08x host_intr = 0x%08x\n", + ch_mask, host_mask); /* enable system events, writing 0 has no-effect */ - pruss_intc_write_reg(intc, PRU_INTC_ESR0, lower_32_bits(sysevt_mask)); - pruss_intc_write_reg(intc, PRU_INTC_SECR0, lower_32_bits(sysevt_mask)); - pruss_intc_write_reg(intc, PRU_INTC_ESR1, upper_32_bits(sysevt_mask)); - pruss_intc_write_reg(intc, PRU_INTC_SECR1, upper_32_bits(sysevt_mask)); + for (i = 0; i < num_regs; i++) { + pruss_intc_write_reg(intc, PRU_INTC_ESR(i), sysevts[i]); + pruss_intc_write_reg(intc, PRU_INTC_SECR(i), sysevts[i]); + } /* enable host interrupts */ - for (i = 0; i < MAX_PRU_HOST_INT; i++) { + for (i = 0; i < num_intrs; i++) { if (host_mask & BIT(i)) pruss_intc_write_reg(intc, PRU_INTC_HIEISR, i); } @@ -286,9 +305,7 @@ int pruss_intc_configure(struct device *dev, pruss_intc_write_reg(intc, PRU_INTC_GER, 1); intc->host_mask |= host_mask; - - mutex_unlock(&intc->lock); - return 0; + goto out; fail_ch: while (--i >= 0) { @@ -297,7 +314,7 @@ int pruss_intc_configure(struct device *dev, pruss_intc_update_hmr(intc, i, 0); } } - i = ARRAY_SIZE(intc_config->sysev_to_ch); + i = num_events; fail_evt: while (--i >= 0) { if (intc_config->sysev_to_ch[i] >= 0) { @@ -305,7 +322,9 @@ int pruss_intc_configure(struct device *dev, pruss_intc_update_cmr(intc, i, 0); } } +out: mutex_unlock(&intc->lock); + bitmap_free(sysevt_bitmap); return ret; } EXPORT_SYMBOL_GPL(pruss_intc_configure); @@ -325,28 +344,39 @@ int pruss_intc_unconfigure(struct device *dev, struct pruss_intc *intc; int i; s8 ch, host; - u64 sysevt_mask = 0; + u32 num_events, num_intrs, num_regs; + unsigned long *sysevt_bitmap; + u32 *sysevts; u32 host_mask = 0; intc = to_pruss_intc(dev); if (IS_ERR(intc)) return PTR_ERR(intc); + num_events = intc->data->num_system_events; + num_intrs = intc->data->num_host_intrs; + num_regs = DIV_ROUND_UP(num_events, 32); + + sysevt_bitmap = bitmap_zalloc(num_events, GFP_KERNEL); + if (!sysevt_bitmap) + return -ENOMEM; + sysevts = (u32 *)sysevt_bitmap; + mutex_lock(&intc->lock); - for (i = 0; i < ARRAY_SIZE(intc_config->sysev_to_ch); i++) { + for (i = 0; i < num_events; i++) { ch = intc_config->sysev_to_ch[i]; if (ch < 0) continue; /* mark sysevent free in global map */ intc->config_map.sysev_to_ch[i] = PRU_INTC_FREE; - sysevt_mask |= BIT_ULL(i); + bitmap_set(sysevt_bitmap, i, 1); /* clear the map using reset value 0 */ pruss_intc_update_cmr(intc, i, 0); } - for (i = 0; i < ARRAY_SIZE(intc_config->ch_to_host); i++) { + for (i = 0; i < num_intrs; i++) { host = intc_config->ch_to_host[i]; if (host < 0) continue; @@ -358,24 +388,26 @@ int pruss_intc_unconfigure(struct device *dev, pruss_intc_update_hmr(intc, i, 0); } - dev_info(dev, "unconfigured system_events = 0x%016llx host_intr = 0x%08x\n", - sysevt_mask, host_mask); + dev_info(dev, "unconfigured system_events[%d-0] = %*pb\n", + num_events - 1, num_events, sysevt_bitmap); + dev_info(dev, "unconfigured host_intr = 0x%08x\n", host_mask); - /* disable system events, writing 0 has no-effect */ - pruss_intc_write_reg(intc, PRU_INTC_ECR0, lower_32_bits(sysevt_mask)); - pruss_intc_write_reg(intc, PRU_INTC_ECR1, upper_32_bits(sysevt_mask)); - /* clear any pending status */ - pruss_intc_write_reg(intc, PRU_INTC_SECR0, lower_32_bits(sysevt_mask)); - pruss_intc_write_reg(intc, PRU_INTC_SECR1, upper_32_bits(sysevt_mask)); + for (i = 0; i < num_regs; i++) { + /* disable system events, writing 0 has no-effect */ + pruss_intc_write_reg(intc, PRU_INTC_ECR(i), sysevts[i]); + /* clear any pending status */ + pruss_intc_write_reg(intc, PRU_INTC_SECR(i), sysevts[i]); + } /* disable host interrupts */ - for (i = 0; i < MAX_PRU_HOST_INT; i++) { + for (i = 0; i < num_intrs; i++) { if (host_mask & BIT(i)) pruss_intc_write_reg(intc, PRU_INTC_HIDISR, i); } intc->host_mask &= ~host_mask; mutex_unlock(&intc->lock); + bitmap_free(sysevt_bitmap); return 0; } @@ -384,21 +416,28 @@ EXPORT_SYMBOL_GPL(pruss_intc_unconfigure); static void pruss_intc_init(struct pruss_intc *intc) { int i; + int num_chnl_map_regs = DIV_ROUND_UP(intc->data->num_system_events, + CMR_EVT_PER_REG); + int num_host_intr_regs = DIV_ROUND_UP(intc->data->num_host_intrs, + HMR_CH_PER_REG); + int num_event_type_regs = + DIV_ROUND_UP(intc->data->num_system_events, 32); - /* configure polarity to active high for all system interrupts */ - pruss_intc_write_reg(intc, PRU_INTC_SIPR0, 0xffffffff); - pruss_intc_write_reg(intc, PRU_INTC_SIPR1, 0xffffffff); - - /* configure type to pulse interrupt for all system interrupts */ - pruss_intc_write_reg(intc, PRU_INTC_SITR0, 0); - pruss_intc_write_reg(intc, PRU_INTC_SITR1, 0); + /* + * configure polarity (SIPR register) to active high and + * type (SITR register) to pulse interrupt for all system events + */ + for (i = 0; i < num_event_type_regs; i++) { + pruss_intc_write_reg(intc, PRU_INTC_SIPR(i), 0xffffffff); + pruss_intc_write_reg(intc, PRU_INTC_SITR(i), 0); + } - /* clear all 16 interrupt channel map registers */ - for (i = 0; i < 16; i++) + /* clear all interrupt channel map registers, 4 events per register */ + for (i = 0; i < num_chnl_map_regs; i++) pruss_intc_write_reg(intc, PRU_INTC_CMR(i), 0); - /* clear all 3 host interrupt map registers */ - for (i = 0; i < 3; i++) + /* clear all host interrupt map registers, 4 channels per register */ + for (i = 0; i < num_host_intr_regs; i++) pruss_intc_write_reg(intc, PRU_INTC_HMR(i), 0); } @@ -549,11 +588,20 @@ static int pruss_intc_probe(struct platform_device *pdev) struct resource *res; struct irq_chip *irqchip; int i, irq, count; + const struct pruss_intc_match_data *data; u8 temp_intr[MAX_NUM_HOST_IRQS] = { 0 }; + u8 max_system_events; + + data = of_device_get_match_data(dev); + if (!data) + return -ENODEV; + + max_system_events = data->num_system_events; intc = devm_kzalloc(dev, sizeof(*intc), GFP_KERNEL); if (!intc) return -ENOMEM; + intc->data = data; platform_set_drvdata(pdev, intc); res = platform_get_resource(pdev, IORESOURCE_MEM, 0); @@ -623,8 +671,7 @@ static int pruss_intc_probe(struct platform_device *pdev) irqchip->name = dev_name(dev); intc->irqchip = irqchip; - /* always 64 events */ - intc->domain = irq_domain_add_linear(dev->of_node, MAX_PRU_SYS_EVENTS, + intc->domain = irq_domain_add_linear(dev->of_node, max_system_events, &pruss_intc_irq_domain_ops, intc); if (!intc->domain) return -ENOMEM; @@ -661,6 +708,7 @@ static int pruss_intc_probe(struct platform_device *pdev) static int pruss_intc_remove(struct platform_device *pdev) { struct pruss_intc *intc = platform_get_drvdata(pdev); + u8 max_system_events = intc->data->num_system_events; unsigned int hwirq; int i; @@ -670,15 +718,32 @@ static int pruss_intc_remove(struct platform_device *pdev) NULL); } - for (hwirq = 0; hwirq < MAX_PRU_SYS_EVENTS; hwirq++) + for (hwirq = 0; hwirq < max_system_events; hwirq++) irq_dispose_mapping(irq_find_mapping(intc->domain, hwirq)); irq_domain_remove(intc->domain); return 0; } +static const struct pruss_intc_match_data pruss_intc_data = { + .num_system_events = 64, + .num_host_intrs = 10, +}; + +static const struct pruss_intc_match_data icssg_intc_data = { + .num_system_events = 160, + .num_host_intrs = 20, +}; + static const struct of_device_id pruss_intc_of_match[] = { - { .compatible = "ti,pruss-intc", }, + { + .compatible = "ti,pruss-intc", + .data = &pruss_intc_data, + }, + { + .compatible = "ti,icssg-intc", + .data = &icssg_intc_data, + }, { /* sentinel */ }, }; MODULE_DEVICE_TABLE(of, pruss_intc_of_match); diff --git a/include/linux/irqchip/irq-pruss-intc.h b/include/linux/irqchip/irq-pruss-intc.h index daffc048b303..cc6f9190b04f 100644 --- a/include/linux/irqchip/irq-pruss-intc.h +++ b/include/linux/irqchip/irq-pruss-intc.h @@ -10,10 +10,10 @@ #define __LINUX_IRQ_PRUSS_INTC_H /* maximum number of system events */ -#define MAX_PRU_SYS_EVENTS 64 +#define MAX_PRU_SYS_EVENTS 160 /* maximum number of interrupt channels */ -#define MAX_PRU_CHANNELS 10 +#define MAX_PRU_CHANNELS 20 /* use -1 to mark unassigned events and channels */ #define PRU_INTC_FREE -1