From patchwork Mon Aug 5 10:03:03 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Miquel Raynal X-Patchwork-Id: 11076437 Return-Path: Received: from mail.wl.linuxfoundation.org (pdx-wl-mail.web.codeaurora.org [172.30.200.125]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id 5D26B14E5 for ; Mon, 5 Aug 2019 10:03:18 +0000 (UTC) Received: from mail.wl.linuxfoundation.org (localhost [127.0.0.1]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id 4AC7428372 for ; Mon, 5 Aug 2019 10:03:18 +0000 (UTC) Received: by mail.wl.linuxfoundation.org (Postfix, from userid 486) id 3EC6328861; Mon, 5 Aug 2019 10:03:18 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on pdx-wl-mail.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-7.9 required=2.0 tests=BAYES_00,MAILING_LIST_MULTI, RCVD_IN_DNSWL_HI autolearn=ham version=3.3.1 Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id D99AA28372 for ; Mon, 5 Aug 2019 10:03:17 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1727349AbfHEKDR (ORCPT ); Mon, 5 Aug 2019 06:03:17 -0400 Received: from relay3-d.mail.gandi.net ([217.70.183.195]:50945 "EHLO relay3-d.mail.gandi.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1727230AbfHEKDR (ORCPT ); Mon, 5 Aug 2019 06:03:17 -0400 X-Originating-IP: 86.250.200.211 Received: from localhost.localdomain (lfbn-1-17395-211.w86-250.abo.wanadoo.fr [86.250.200.211]) (Authenticated sender: miquel.raynal@bootlin.com) by relay3-d.mail.gandi.net (Postfix) with ESMTPSA id 0DAF86000C; Mon, 5 Aug 2019 10:03:14 +0000 (UTC) From: Miquel Raynal To: Rob Herring , Mark Rutland , Michael Turquette , Stephen Boyd Cc: , linux-clk@vger.kernel.org, Thomas Petazzoni , Gregory Clement , Antoine Tenart , Maxime Chevallier , Nadav Haklai , Grzegorz Jaszczyk , Marcin Wojtas , Stefan Chulski , Yan Markman , Miquel Raynal Subject: [PATCH 1/8] dt-bindings: ap80x: Document AP807 CPU clock compatible Date: Mon, 5 Aug 2019 12:03:03 +0200 Message-Id: <20190805100310.29048-2-miquel.raynal@bootlin.com> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20190805100310.29048-1-miquel.raynal@bootlin.com> References: <20190805100310.29048-1-miquel.raynal@bootlin.com> MIME-Version: 1.0 Sender: linux-clk-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-clk@vger.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP Add AP807 CPU clock compatible to the bindings. Signed-off-by: Miquel Raynal Reviewed-by: Rob Herring --- .../bindings/arm/marvell/ap806-system-controller.txt | 9 ++++++--- 1 file changed, 6 insertions(+), 3 deletions(-) diff --git a/Documentation/devicetree/bindings/arm/marvell/ap806-system-controller.txt b/Documentation/devicetree/bindings/arm/marvell/ap806-system-controller.txt index 4f21c1024073..59b6b992fbc9 100644 --- a/Documentation/devicetree/bindings/arm/marvell/ap806-system-controller.txt +++ b/Documentation/devicetree/bindings/arm/marvell/ap806-system-controller.txt @@ -147,11 +147,14 @@ ap_syscon1: system-controller@6f8000 { Cluster clocks: --------------- -Device Tree Clock bindings for cluster clock of AP806 Marvell. Each -cluster contain up to 2 CPUs running at the same frequency. +Device Tree Clock bindings for cluster clock of Marvell +AP806/AP807. Each cluster contain up to 2 CPUs running at the same +frequency. Required properties: -- compatible: must be "marvell,ap806-cpu-clock"; + - compatible: must be one of: + * "marvell,ap806-cpu-clock" + * "marvell,ap807-cpu-clock" - #clock-cells : should be set to 1. - clocks : shall be the input parent clock(s) phandle for the clock From patchwork Mon Aug 5 10:03:04 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Miquel Raynal X-Patchwork-Id: 11076439 Return-Path: Received: from mail.wl.linuxfoundation.org (pdx-wl-mail.web.codeaurora.org [172.30.200.125]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id 10E9814E5 for ; Mon, 5 Aug 2019 10:03:20 +0000 (UTC) Received: from mail.wl.linuxfoundation.org (localhost [127.0.0.1]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id F1F6A28372 for ; Mon, 5 Aug 2019 10:03:19 +0000 (UTC) Received: by mail.wl.linuxfoundation.org (Postfix, from userid 486) id E626028861; Mon, 5 Aug 2019 10:03:19 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on pdx-wl-mail.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-7.9 required=2.0 tests=BAYES_00,MAILING_LIST_MULTI, RCVD_IN_DNSWL_HI autolearn=ham version=3.3.1 Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id 905F62883D for ; Mon, 5 Aug 2019 10:03:19 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1727928AbfHEKDT (ORCPT ); Mon, 5 Aug 2019 06:03:19 -0400 Received: from relay3-d.mail.gandi.net ([217.70.183.195]:57665 "EHLO relay3-d.mail.gandi.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1727230AbfHEKDT (ORCPT ); Mon, 5 Aug 2019 06:03:19 -0400 X-Originating-IP: 86.250.200.211 Received: from localhost.localdomain (lfbn-1-17395-211.w86-250.abo.wanadoo.fr [86.250.200.211]) (Authenticated sender: miquel.raynal@bootlin.com) by relay3-d.mail.gandi.net (Postfix) with ESMTPSA id 6072C60005; Mon, 5 Aug 2019 10:03:16 +0000 (UTC) From: Miquel Raynal To: Rob Herring , Mark Rutland , Michael Turquette , Stephen Boyd Cc: , linux-clk@vger.kernel.org, Thomas Petazzoni , Gregory Clement , Antoine Tenart , Maxime Chevallier , Nadav Haklai , Grzegorz Jaszczyk , Marcin Wojtas , Stefan Chulski , Yan Markman , Miquel Raynal Subject: [PATCH 2/8] dt-bindings: ap806: Document AP807 clock compatible Date: Mon, 5 Aug 2019 12:03:04 +0200 Message-Id: <20190805100310.29048-3-miquel.raynal@bootlin.com> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20190805100310.29048-1-miquel.raynal@bootlin.com> References: <20190805100310.29048-1-miquel.raynal@bootlin.com> MIME-Version: 1.0 Sender: linux-clk-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-clk@vger.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP Add AP807 clock compatible to the bindings. Signed-off-by: Miquel Raynal Reviewed-by: Rob Herring --- .../bindings/arm/marvell/ap806-system-controller.txt | 8 +++++--- 1 file changed, 5 insertions(+), 3 deletions(-) diff --git a/Documentation/devicetree/bindings/arm/marvell/ap806-system-controller.txt b/Documentation/devicetree/bindings/arm/marvell/ap806-system-controller.txt index 59b6b992fbc9..26410fbb85be 100644 --- a/Documentation/devicetree/bindings/arm/marvell/ap806-system-controller.txt +++ b/Documentation/devicetree/bindings/arm/marvell/ap806-system-controller.txt @@ -18,8 +18,8 @@ Clocks: ------- -The Device Tree node representing the AP806 system controller provides -a number of clocks: +The Device Tree node representing the AP806/AP807 system controller +provides a number of clocks: - 0: reference clock of CPU cluster 0 - 1: reference clock of CPU cluster 1 @@ -28,7 +28,9 @@ a number of clocks: Required properties: - - compatible: must be: "marvell,ap806-clock" + - compatible: must be one of: + * "marvell,ap806-clock" + * "marvell,ap807-clock" - #clock-cells: must be set to 1 Pinctrl: From patchwork Mon Aug 5 10:03:05 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Miquel Raynal X-Patchwork-Id: 11076443 Return-Path: Received: from mail.wl.linuxfoundation.org (pdx-wl-mail.web.codeaurora.org [172.30.200.125]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id 0A36015AC for ; Mon, 5 Aug 2019 10:03:25 +0000 (UTC) Received: from mail.wl.linuxfoundation.org (localhost [127.0.0.1]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id E90A528372 for ; Mon, 5 Aug 2019 10:03:24 +0000 (UTC) Received: by mail.wl.linuxfoundation.org (Postfix, from userid 486) id DD0EE2883D; Mon, 5 Aug 2019 10:03:24 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on pdx-wl-mail.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-7.9 required=2.0 tests=BAYES_00,MAILING_LIST_MULTI, RCVD_IN_DNSWL_HI autolearn=ham version=3.3.1 Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id 1659428861 for ; Mon, 5 Aug 2019 10:03:24 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1728220AbfHEKDW (ORCPT ); Mon, 5 Aug 2019 06:03:22 -0400 Received: from relay3-d.mail.gandi.net ([217.70.183.195]:55735 "EHLO relay3-d.mail.gandi.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1728148AbfHEKDW (ORCPT ); Mon, 5 Aug 2019 06:03:22 -0400 X-Originating-IP: 86.250.200.211 Received: from localhost.localdomain (lfbn-1-17395-211.w86-250.abo.wanadoo.fr [86.250.200.211]) (Authenticated sender: miquel.raynal@bootlin.com) by relay3-d.mail.gandi.net (Postfix) with ESMTPSA id CE71C60008; Mon, 5 Aug 2019 10:03:17 +0000 (UTC) From: Miquel Raynal To: Rob Herring , Mark Rutland , Michael Turquette , Stephen Boyd Cc: , linux-clk@vger.kernel.org, Thomas Petazzoni , Gregory Clement , Antoine Tenart , Maxime Chevallier , Nadav Haklai , Grzegorz Jaszczyk , Marcin Wojtas , Stefan Chulski , Yan Markman , Christine Gharzuzi , Miquel Raynal Subject: [PATCH 3/8] clk: mvebu: ap806-cpu: prepare mapping of AP807 CPU clock Date: Mon, 5 Aug 2019 12:03:05 +0200 Message-Id: <20190805100310.29048-4-miquel.raynal@bootlin.com> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20190805100310.29048-1-miquel.raynal@bootlin.com> References: <20190805100310.29048-1-miquel.raynal@bootlin.com> MIME-Version: 1.0 Sender: linux-clk-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-clk@vger.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP From: Christine Gharzuzi This patch allows same flow to be executed on chips with different register mappings like AP806 and, in the future, AP807. Note: this patch has no functional effect, and only prepares the driver for additional chips to be supported by retrieving the right device data depenging on the compatible property. Signed-off-by: Christine Gharzuzi Signed-off-by: Miquel Raynal --- drivers/clk/mvebu/ap-cpu-clk.c | 82 +++++++++++++++++++++++++--------- 1 file changed, 62 insertions(+), 20 deletions(-) diff --git a/drivers/clk/mvebu/ap-cpu-clk.c b/drivers/clk/mvebu/ap-cpu-clk.c index e4cecb456884..784104f6793b 100644 --- a/drivers/clk/mvebu/ap-cpu-clk.c +++ b/drivers/clk/mvebu/ap-cpu-clk.c @@ -15,6 +15,7 @@ #include #include #include +#include #include #include #include "armada_ap_cp_helper.h" @@ -29,6 +30,26 @@ #define APN806_MAX_DIVIDER 32 +/** + * struct cpu_dfs_regs: CPU DFS register mapping + * @divider_reg: full integer ratio from PLL frequency to CPU clock frequency + * @force_reg: request to force new ratio regardless of relation to other clocks + * @ratio_reg: central request to switch ratios + */ +struct cpu_dfs_regs { + unsigned int divider_reg; + unsigned int force_reg; + unsigned int ratio_reg; + unsigned int ratio_state_reg; + unsigned int divider_mask; + unsigned int cluster_offset; + unsigned int force_mask; + int divider_offset; + int ratio_offset; + int ratio_state_offset; + int ratio_state_cluster_offset; +}; + /* AP806 CPU DFS register mapping*/ #define AP806_CA72MP2_0_PLL_CR_0_REG_OFFSET 0x278 #define AP806_CA72MP2_0_PLL_CR_1_REG_OFFSET 0x280 @@ -43,6 +64,7 @@ #define AP806_PLL_CR_0_CPU_CLK_RELOAD_FORCE_MASK \ (0x1 << AP806_PLL_CR_0_CPU_CLK_RELOAD_FORCE_OFFSET) #define AP806_PLL_CR_0_CPU_CLK_RELOAD_RATIO_OFFSET 16 +#define AP806_CA72MP2_0_PLL_RATIO_STABLE_OFFSET 0 #define AP806_CA72MP2_0_PLL_RATIO_STATE 11 #define STATUS_POLL_PERIOD_US 1 @@ -50,6 +72,20 @@ #define to_ap_cpu_clk(_hw) container_of(_hw, struct ap_cpu_clk, hw) +static const struct cpu_dfs_regs ap806_dfs_regs = { + .divider_reg = AP806_CA72MP2_0_PLL_CR_0_REG_OFFSET, + .force_reg = AP806_CA72MP2_0_PLL_CR_1_REG_OFFSET, + .ratio_reg = AP806_CA72MP2_0_PLL_CR_2_REG_OFFSET, + .ratio_state_reg = AP806_CA72MP2_0_PLL_SR_REG_OFFSET, + .divider_mask = AP806_PLL_CR_0_CPU_CLK_DIV_RATIO_MASK, + .cluster_offset = AP806_CA72MP2_0_PLL_CR_CLUSTER_OFFSET, + .force_mask = AP806_PLL_CR_0_CPU_CLK_RELOAD_FORCE_MASK, + .divider_offset = AP806_PLL_CR_0_CPU_CLK_DIV_RATIO_OFFSET, + .ratio_offset = AP806_PLL_CR_0_CPU_CLK_RELOAD_RATIO_OFFSET, + .ratio_state_offset = AP806_CA72MP2_0_PLL_RATIO_STABLE_OFFSET, + .ratio_state_cluster_offset = AP806_CA72MP2_0_PLL_RATIO_STABLE_OFFSET, +}; + /* * struct ap806_clk: CPU cluster clock controller instance * @cluster: Cluster clock controller index @@ -64,6 +100,7 @@ struct ap_cpu_clk { struct device *dev; struct clk_hw hw; struct regmap *pll_cr_base; + const struct cpu_dfs_regs *pll_regs; }; static unsigned long ap_cpu_clk_recalc_rate(struct clk_hw *hw, @@ -73,11 +110,11 @@ static unsigned long ap_cpu_clk_recalc_rate(struct clk_hw *hw, unsigned int cpu_clkdiv_reg; int cpu_clkdiv_ratio; - cpu_clkdiv_reg = AP806_CA72MP2_0_PLL_CR_0_REG_OFFSET + - (clk->cluster * AP806_CA72MP2_0_PLL_CR_CLUSTER_OFFSET); + cpu_clkdiv_reg = clk->pll_regs->divider_reg + + (clk->cluster * clk->pll_regs->cluster_offset); regmap_read(clk->pll_cr_base, cpu_clkdiv_reg, &cpu_clkdiv_ratio); - cpu_clkdiv_ratio &= AP806_PLL_CR_0_CPU_CLK_DIV_RATIO_MASK; - cpu_clkdiv_ratio >>= AP806_PLL_CR_0_CPU_CLK_DIV_RATIO_OFFSET; + cpu_clkdiv_ratio &= clk->pll_regs->divider_mask; + cpu_clkdiv_ratio >>= clk->pll_regs->divider_offset; return parent_rate / cpu_clkdiv_ratio; } @@ -89,35 +126,36 @@ static int ap_cpu_clk_set_rate(struct clk_hw *hw, unsigned long rate, int ret, reg, divider = parent_rate / rate; unsigned int cpu_clkdiv_reg, cpu_force_reg, cpu_ratio_reg, stable_bit; - cpu_clkdiv_reg = AP806_CA72MP2_0_PLL_CR_0_REG_OFFSET + - (clk->cluster * AP806_CA72MP2_0_PLL_CR_CLUSTER_OFFSET); - cpu_force_reg = AP806_CA72MP2_0_PLL_CR_1_REG_OFFSET + - (clk->cluster * AP806_CA72MP2_0_PLL_CR_CLUSTER_OFFSET); - cpu_ratio_reg = AP806_CA72MP2_0_PLL_CR_2_REG_OFFSET + - (clk->cluster * AP806_CA72MP2_0_PLL_CR_CLUSTER_OFFSET); + cpu_clkdiv_reg = clk->pll_regs->divider_reg + + (clk->cluster * clk->pll_regs->cluster_offset); + cpu_force_reg = clk->pll_regs->force_reg + + (clk->cluster * clk->pll_regs->cluster_offset); + cpu_ratio_reg = clk->pll_regs->ratio_reg + + (clk->cluster * clk->pll_regs->cluster_offset); regmap_update_bits(clk->pll_cr_base, cpu_clkdiv_reg, - AP806_PLL_CR_0_CPU_CLK_DIV_RATIO_MASK, divider); + clk->pll_regs->divider_mask, divider); regmap_update_bits(clk->pll_cr_base, cpu_force_reg, - AP806_PLL_CR_0_CPU_CLK_RELOAD_FORCE_MASK, - AP806_PLL_CR_0_CPU_CLK_RELOAD_FORCE_MASK); + clk->pll_regs->force_mask, + clk->pll_regs->force_mask); regmap_update_bits(clk->pll_cr_base, cpu_ratio_reg, - BIT(AP806_PLL_CR_0_CPU_CLK_RELOAD_RATIO_OFFSET), - BIT(AP806_PLL_CR_0_CPU_CLK_RELOAD_RATIO_OFFSET)); - - stable_bit = BIT(clk->cluster * AP806_CA72MP2_0_PLL_RATIO_STATE), + BIT(clk->pll_regs->ratio_offset), + BIT(clk->pll_regs->ratio_offset)); + stable_bit = BIT(clk->pll_regs->ratio_state_offset + + clk->cluster * + clk->pll_regs->ratio_state_cluster_offset), ret = regmap_read_poll_timeout(clk->pll_cr_base, - AP806_CA72MP2_0_PLL_SR_REG_OFFSET, reg, + clk->pll_regs->ratio_state_reg, reg, reg & stable_bit, STATUS_POLL_PERIOD_US, STATUS_POLL_TIMEOUT_US); if (ret) return ret; regmap_update_bits(clk->pll_cr_base, cpu_ratio_reg, - BIT(AP806_PLL_CR_0_CPU_CLK_RELOAD_RATIO_OFFSET), 0); + BIT(clk->pll_regs->ratio_offset), 0); return 0; } @@ -222,6 +260,7 @@ static int ap_cpu_clock_probe(struct platform_device *pdev) ap_cpu_clk[cluster_index].pll_cr_base = regmap; ap_cpu_clk[cluster_index].hw.init = &init; ap_cpu_clk[cluster_index].dev = dev; + ap_cpu_clk[cluster_index].pll_regs = of_device_get_match_data(&pdev->dev); init.name = ap_cpu_clk[cluster_index].clk_name; init.ops = &ap_cpu_clk_ops; @@ -244,7 +283,10 @@ static int ap_cpu_clock_probe(struct platform_device *pdev) } static const struct of_device_id ap_cpu_clock_of_match[] = { - { .compatible = "marvell,ap806-cpu-clock", }, + { + .compatible = "marvell,ap806-cpu-clock", + .data = &ap806_dfs_regs, + }, { } }; From patchwork Mon Aug 5 10:03:06 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Miquel Raynal X-Patchwork-Id: 11076441 Return-Path: Received: from mail.wl.linuxfoundation.org (pdx-wl-mail.web.codeaurora.org [172.30.200.125]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id 8F4081850 for ; Mon, 5 Aug 2019 10:03:24 +0000 (UTC) Received: from mail.wl.linuxfoundation.org (localhost [127.0.0.1]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id 7CA0428372 for ; Mon, 5 Aug 2019 10:03:24 +0000 (UTC) Received: by mail.wl.linuxfoundation.org (Postfix, from userid 486) id 70C92288A9; Mon, 5 Aug 2019 10:03:24 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on pdx-wl-mail.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-7.9 required=2.0 tests=BAYES_00,MAILING_LIST_MULTI, RCVD_IN_DNSWL_HI autolearn=ham version=3.3.1 Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id EA1EA28372 for ; Mon, 5 Aug 2019 10:03:23 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1728148AbfHEKDX (ORCPT ); Mon, 5 Aug 2019 06:03:23 -0400 Received: from relay3-d.mail.gandi.net ([217.70.183.195]:43611 "EHLO relay3-d.mail.gandi.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1727830AbfHEKDW (ORCPT ); Mon, 5 Aug 2019 06:03:22 -0400 X-Originating-IP: 86.250.200.211 Received: from localhost.localdomain (lfbn-1-17395-211.w86-250.abo.wanadoo.fr [86.250.200.211]) (Authenticated sender: miquel.raynal@bootlin.com) by relay3-d.mail.gandi.net (Postfix) with ESMTPSA id 9B5DF60015; Mon, 5 Aug 2019 10:03:19 +0000 (UTC) From: Miquel Raynal To: Rob Herring , Mark Rutland , Michael Turquette , Stephen Boyd Cc: , linux-clk@vger.kernel.org, Thomas Petazzoni , Gregory Clement , Antoine Tenart , Maxime Chevallier , Nadav Haklai , Grzegorz Jaszczyk , Marcin Wojtas , Stefan Chulski , Yan Markman , Ben Peled , Miquel Raynal Subject: [PATCH 4/8] clk: mvebu: ap80x-cpu: add AP807 CPU clock support Date: Mon, 5 Aug 2019 12:03:06 +0200 Message-Id: <20190805100310.29048-5-miquel.raynal@bootlin.com> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20190805100310.29048-1-miquel.raynal@bootlin.com> References: <20190805100310.29048-1-miquel.raynal@bootlin.com> MIME-Version: 1.0 Sender: linux-clk-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-clk@vger.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP From: Ben Peled Enhance the ap-cpu-clk driver to support both AP806 and AP807 CPU clocks. Signed-off-by: Ben Peled [: use device data instead of conditions on the compatible] Signed-off-by: Miquel Raynal --- drivers/clk/mvebu/ap-cpu-clk.c | 59 ++++++++++++++++++++++++++++++++-- 1 file changed, 57 insertions(+), 2 deletions(-) diff --git a/drivers/clk/mvebu/ap-cpu-clk.c b/drivers/clk/mvebu/ap-cpu-clk.c index 784104f6793b..af5e5acad370 100644 --- a/drivers/clk/mvebu/ap-cpu-clk.c +++ b/drivers/clk/mvebu/ap-cpu-clk.c @@ -45,6 +45,7 @@ struct cpu_dfs_regs { unsigned int cluster_offset; unsigned int force_mask; int divider_offset; + int divider_ratio; int ratio_offset; int ratio_state_offset; int ratio_state_cluster_offset; @@ -58,6 +59,7 @@ struct cpu_dfs_regs { #define AP806_CA72MP2_0_PLL_CR_CLUSTER_OFFSET 0x14 #define AP806_PLL_CR_0_CPU_CLK_DIV_RATIO_OFFSET 0 +#define AP806_PLL_CR_CPU_CLK_DIV_RATIO 0 #define AP806_PLL_CR_0_CPU_CLK_DIV_RATIO_MASK \ (0x3f << AP806_PLL_CR_0_CPU_CLK_DIV_RATIO_OFFSET) #define AP806_PLL_CR_0_CPU_CLK_RELOAD_FORCE_OFFSET 24 @@ -81,11 +83,47 @@ static const struct cpu_dfs_regs ap806_dfs_regs = { .cluster_offset = AP806_CA72MP2_0_PLL_CR_CLUSTER_OFFSET, .force_mask = AP806_PLL_CR_0_CPU_CLK_RELOAD_FORCE_MASK, .divider_offset = AP806_PLL_CR_0_CPU_CLK_DIV_RATIO_OFFSET, + .divider_ratio = AP806_PLL_CR_CPU_CLK_DIV_RATIO, .ratio_offset = AP806_PLL_CR_0_CPU_CLK_RELOAD_RATIO_OFFSET, .ratio_state_offset = AP806_CA72MP2_0_PLL_RATIO_STABLE_OFFSET, .ratio_state_cluster_offset = AP806_CA72MP2_0_PLL_RATIO_STABLE_OFFSET, }; +/* AP807 CPU DFS register mapping */ +#define AP807_DEVICE_GENERAL_CONTROL_10_REG_OFFSET 0x278 +#define AP807_DEVICE_GENERAL_CONTROL_11_REG_OFFSET 0x27c +#define AP807_DEVICE_GENERAL_STATUS_6_REG_OFFSET 0xc98 +#define AP807_CA72MP2_0_PLL_CR_CLUSTER_OFFSET 0x8 +#define AP807_PLL_CR_0_CPU_CLK_DIV_RATIO_OFFSET 18 +#define AP807_PLL_CR_0_CPU_CLK_DIV_RATIO_MASK \ + (0x3f << AP807_PLL_CR_0_CPU_CLK_DIV_RATIO_OFFSET) +#define AP807_PLL_CR_1_CPU_CLK_DIV_RATIO_OFFSET 12 +#define AP807_PLL_CR_1_CPU_CLK_DIV_RATIO_MASK \ + (0x3f << AP807_PLL_CR_1_CPU_CLK_DIV_RATIO_OFFSET) +#define AP807_PLL_CR_CPU_CLK_DIV_RATIO 3 +#define AP807_PLL_CR_0_CPU_CLK_RELOAD_FORCE_OFFSET 0 +#define AP807_PLL_CR_0_CPU_CLK_RELOAD_FORCE_MASK \ + (0x3 << AP807_PLL_CR_0_CPU_CLK_RELOAD_FORCE_OFFSET) +#define AP807_PLL_CR_0_CPU_CLK_RELOAD_RATIO_OFFSET 6 +#define AP807_CA72MP2_0_PLL_CLKDIV_RATIO_STABLE_OFFSET 20 +#define AP807_CA72MP2_0_PLL_CLKDIV_RATIO_STABLE_CLUSTER_OFFSET 3 + +static const struct cpu_dfs_regs ap807_dfs_regs = { + .divider_reg = AP807_DEVICE_GENERAL_CONTROL_10_REG_OFFSET, + .force_reg = AP807_DEVICE_GENERAL_CONTROL_11_REG_OFFSET, + .ratio_reg = AP807_DEVICE_GENERAL_CONTROL_11_REG_OFFSET, + .ratio_state_reg = AP807_DEVICE_GENERAL_STATUS_6_REG_OFFSET, + .divider_mask = AP807_PLL_CR_0_CPU_CLK_DIV_RATIO_MASK, + .cluster_offset = AP807_CA72MP2_0_PLL_CR_CLUSTER_OFFSET, + .force_mask = AP807_PLL_CR_0_CPU_CLK_RELOAD_FORCE_MASK, + .divider_offset = AP807_PLL_CR_0_CPU_CLK_DIV_RATIO_OFFSET, + .divider_ratio = AP807_PLL_CR_CPU_CLK_DIV_RATIO, + .ratio_offset = AP807_PLL_CR_0_CPU_CLK_RELOAD_RATIO_OFFSET, + .ratio_state_offset = AP807_CA72MP2_0_PLL_CLKDIV_RATIO_STABLE_OFFSET, + .ratio_state_cluster_offset = + AP807_CA72MP2_0_PLL_CLKDIV_RATIO_STABLE_CLUSTER_OFFSET +}; + /* * struct ap806_clk: CPU cluster clock controller instance * @cluster: Cluster clock controller index @@ -133,8 +171,21 @@ static int ap_cpu_clk_set_rate(struct clk_hw *hw, unsigned long rate, cpu_ratio_reg = clk->pll_regs->ratio_reg + (clk->cluster * clk->pll_regs->cluster_offset); - regmap_update_bits(clk->pll_cr_base, cpu_clkdiv_reg, - clk->pll_regs->divider_mask, divider); + regmap_read(clk->pll_cr_base, cpu_clkdiv_reg, ®); + reg &= ~(clk->pll_regs->divider_mask); + reg |= (divider << clk->pll_regs->divider_offset); + + /* + * AP807 CPU divider has two channels with ratio 1:3 and divider_ratio + * is 1. Otherwise, in the case of the AP806, divider_ratio is 0. + */ + if (clk->pll_regs->divider_ratio) { + reg &= ~(AP807_PLL_CR_1_CPU_CLK_DIV_RATIO_MASK); + reg |= ((divider * clk->pll_regs->divider_ratio) << + AP807_PLL_CR_1_CPU_CLK_DIV_RATIO_OFFSET); + } + regmap_write(clk->pll_cr_base, cpu_clkdiv_reg, reg); + regmap_update_bits(clk->pll_cr_base, cpu_force_reg, clk->pll_regs->force_mask, @@ -287,6 +338,10 @@ static const struct of_device_id ap_cpu_clock_of_match[] = { .compatible = "marvell,ap806-cpu-clock", .data = &ap806_dfs_regs, }, + { + .compatible = "marvell,ap807-cpu-clock", + .data = &ap807_dfs_regs, + }, { } }; From patchwork Mon Aug 5 10:03:07 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Miquel Raynal X-Patchwork-Id: 11076445 Return-Path: Received: from mail.wl.linuxfoundation.org (pdx-wl-mail.web.codeaurora.org [172.30.200.125]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id B01E713B1 for ; Mon, 5 Aug 2019 10:03:26 +0000 (UTC) Received: from mail.wl.linuxfoundation.org (localhost [127.0.0.1]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id 9D7C128372 for ; Mon, 5 Aug 2019 10:03:26 +0000 (UTC) Received: by mail.wl.linuxfoundation.org (Postfix, from userid 486) id 9118628861; Mon, 5 Aug 2019 10:03:26 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on pdx-wl-mail.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-7.9 required=2.0 tests=BAYES_00,MAILING_LIST_MULTI, RCVD_IN_DNSWL_HI autolearn=ham version=3.3.1 Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id 3DF9D28372 for ; Mon, 5 Aug 2019 10:03:26 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1728237AbfHEKDY (ORCPT ); Mon, 5 Aug 2019 06:03:24 -0400 Received: from relay3-d.mail.gandi.net ([217.70.183.195]:38079 "EHLO relay3-d.mail.gandi.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1728232AbfHEKDY (ORCPT ); Mon, 5 Aug 2019 06:03:24 -0400 X-Originating-IP: 86.250.200.211 Received: from localhost.localdomain (lfbn-1-17395-211.w86-250.abo.wanadoo.fr [86.250.200.211]) (Authenticated sender: miquel.raynal@bootlin.com) by relay3-d.mail.gandi.net (Postfix) with ESMTPSA id 268EB60011; Mon, 5 Aug 2019 10:03:21 +0000 (UTC) From: Miquel Raynal To: Rob Herring , Mark Rutland , Michael Turquette , Stephen Boyd Cc: , linux-clk@vger.kernel.org, Thomas Petazzoni , Gregory Clement , Antoine Tenart , Maxime Chevallier , Nadav Haklai , Grzegorz Jaszczyk , Marcin Wojtas , Stefan Chulski , Yan Markman , Miquel Raynal Subject: [PATCH 5/8] clk: mvebu: ap806: be more explicit on what SaR is Date: Mon, 5 Aug 2019 12:03:07 +0200 Message-Id: <20190805100310.29048-6-miquel.raynal@bootlin.com> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20190805100310.29048-1-miquel.raynal@bootlin.com> References: <20190805100310.29048-1-miquel.raynal@bootlin.com> MIME-Version: 1.0 Sender: linux-clk-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-clk@vger.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP "SaR" means Sample at Reset. DIP switches can be changed on the board, their states at reset time is available through a register read. Signed-off-by: Miquel Raynal --- drivers/clk/mvebu/ap806-system-controller.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/clk/mvebu/ap806-system-controller.c b/drivers/clk/mvebu/ap806-system-controller.c index 73ba8fd7860f..2cf874f01394 100644 --- a/drivers/clk/mvebu/ap806-system-controller.c +++ b/drivers/clk/mvebu/ap806-system-controller.c @@ -89,7 +89,7 @@ static int ap806_syscon_common_probe(struct platform_device *pdev, cpuclk_freq = 600; break; default: - dev_err(dev, "invalid SAR value\n"); + dev_err(dev, "invalid Sample at Reset value\n"); return -EINVAL; } From patchwork Mon Aug 5 10:03:08 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Miquel Raynal X-Patchwork-Id: 11076447 Return-Path: Received: from mail.wl.linuxfoundation.org (pdx-wl-mail.web.codeaurora.org [172.30.200.125]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id DC69314E5 for ; Mon, 5 Aug 2019 10:03:27 +0000 (UTC) Received: from mail.wl.linuxfoundation.org (localhost [127.0.0.1]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id C9EF128372 for ; Mon, 5 Aug 2019 10:03:27 +0000 (UTC) Received: by mail.wl.linuxfoundation.org (Postfix, from userid 486) id BDCD228861; Mon, 5 Aug 2019 10:03:27 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on pdx-wl-mail.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-7.9 required=2.0 tests=BAYES_00,MAILING_LIST_MULTI, RCVD_IN_DNSWL_HI autolearn=ham version=3.3.1 Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id 56B6728372 for ; Mon, 5 Aug 2019 10:03:27 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1728240AbfHEKD0 (ORCPT ); Mon, 5 Aug 2019 06:03:26 -0400 Received: from relay3-d.mail.gandi.net ([217.70.183.195]:52765 "EHLO relay3-d.mail.gandi.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1727830AbfHEKD0 (ORCPT ); Mon, 5 Aug 2019 06:03:26 -0400 X-Originating-IP: 86.250.200.211 Received: from localhost.localdomain (lfbn-1-17395-211.w86-250.abo.wanadoo.fr [86.250.200.211]) (Authenticated sender: miquel.raynal@bootlin.com) by relay3-d.mail.gandi.net (Postfix) with ESMTPSA id CD5B860008; Mon, 5 Aug 2019 10:03:22 +0000 (UTC) From: Miquel Raynal To: Rob Herring , Mark Rutland , Michael Turquette , Stephen Boyd Cc: , linux-clk@vger.kernel.org, Thomas Petazzoni , Gregory Clement , Antoine Tenart , Maxime Chevallier , Nadav Haklai , Grzegorz Jaszczyk , Marcin Wojtas , Stefan Chulski , Yan Markman , Omri Itach , Miquel Raynal Subject: [PATCH 6/8] clk: mvebu: ap806: add AP-DCLK (hclk) to system controller driver Date: Mon, 5 Aug 2019 12:03:08 +0200 Message-Id: <20190805100310.29048-7-miquel.raynal@bootlin.com> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20190805100310.29048-1-miquel.raynal@bootlin.com> References: <20190805100310.29048-1-miquel.raynal@bootlin.com> MIME-Version: 1.0 Sender: linux-clk-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-clk@vger.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP From: Omri Itach Add dynamic AP-DCLK clock (hclk) to system controller driver. AP-DCLK is half the rate of DDR clock, so its derrived from Sample At Reset configuration. The clock frequency is required for AP806 AXI monitor profiling feature. Signed-off-by: Omri Itach Signed-off-by: Miquel Raynal --- drivers/clk/mvebu/ap806-system-controller.c | 48 ++++++++++++++++++++- 1 file changed, 46 insertions(+), 2 deletions(-) diff --git a/drivers/clk/mvebu/ap806-system-controller.c b/drivers/clk/mvebu/ap806-system-controller.c index 2cf874f01394..bc43adff02e0 100644 --- a/drivers/clk/mvebu/ap806-system-controller.c +++ b/drivers/clk/mvebu/ap806-system-controller.c @@ -21,7 +21,7 @@ #define AP806_SAR_REG 0x400 #define AP806_SAR_CLKFREQ_MODE_MASK 0x1f -#define AP806_CLK_NUM 5 +#define AP806_CLK_NUM 6 static struct clk *ap806_clks[AP806_CLK_NUM]; @@ -33,7 +33,7 @@ static struct clk_onecell_data ap806_clk_data = { static int ap806_syscon_common_probe(struct platform_device *pdev, struct device_node *syscon_node) { - unsigned int freq_mode, cpuclk_freq; + unsigned int freq_mode, cpuclk_freq, dclk_freq; const char *name, *fixedclk_name; struct device *dev = &pdev->dev; struct device_node *np = dev->of_node; @@ -93,8 +93,42 @@ static int ap806_syscon_common_probe(struct platform_device *pdev, return -EINVAL; } + /* Get DCLK frequency (DCLK = DDR_CLK / 2) */ + switch (freq_mode) { + case 0x0: + case 0x6: + /* DDR_CLK = 1200Mhz */ + dclk_freq = 600; + break; + case 0x1: + case 0x7: + case 0xD: + /* DDR_CLK = 1050Mhz */ + dclk_freq = 525; + break; + case 0x13: + case 0x17: + /* DDR_CLK = 650Mhz */ + dclk_freq = 325; + break; + case 0x4: + case 0x14: + case 0x19: + case 0x1A: + case 0x1B: + case 0x1C: + case 0x1D: + /* DDR_CLK = 800Mhz */ + dclk_freq = 400; + break; + default: + dclk_freq = 0; + dev_err(dev, "invalid Sample at Reset value\n"); + } + /* Convert to hertz */ cpuclk_freq *= 1000 * 1000; + dclk_freq *= 1000 * 1000; /* CPU clocks depend on the Sample At Reset configuration */ name = ap_cp_unique_name(dev, syscon_node, "pll-cluster-0"); @@ -141,6 +175,14 @@ static int ap806_syscon_common_probe(struct platform_device *pdev, goto fail4; } + /* AP-DCLK(HCLK) Clock is DDR clock divided by 2 */ + name = ap_cp_unique_name(dev, syscon_node, "ap-dclk"); + ap806_clks[5] = clk_register_fixed_rate(dev, name, NULL, 0, dclk_freq); + if (IS_ERR(ap806_clks[5])) { + ret = PTR_ERR(ap806_clks[5]); + goto fail5; + } + ret = of_clk_add_provider(np, of_clk_src_onecell_get, &ap806_clk_data); if (ret) goto fail_clk_add; @@ -148,6 +190,8 @@ static int ap806_syscon_common_probe(struct platform_device *pdev, return 0; fail_clk_add: + clk_unregister_fixed_factor(ap806_clks[5]); +fail5: clk_unregister_fixed_factor(ap806_clks[4]); fail4: clk_unregister_fixed_factor(ap806_clks[3]); From patchwork Mon Aug 5 10:03:09 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Miquel Raynal X-Patchwork-Id: 11076449 Return-Path: Received: from mail.wl.linuxfoundation.org (pdx-wl-mail.web.codeaurora.org [172.30.200.125]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id DC39D14E5 for ; Mon, 5 Aug 2019 10:03:29 +0000 (UTC) Received: from mail.wl.linuxfoundation.org (localhost [127.0.0.1]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id C91CC28372 for ; Mon, 5 Aug 2019 10:03:29 +0000 (UTC) Received: by mail.wl.linuxfoundation.org (Postfix, from userid 486) id BD78328861; Mon, 5 Aug 2019 10:03:29 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on pdx-wl-mail.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-7.9 required=2.0 tests=BAYES_00,MAILING_LIST_MULTI, RCVD_IN_DNSWL_HI autolearn=ham version=3.3.1 Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id 43E7A28372 for ; Mon, 5 Aug 2019 10:03:29 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1727830AbfHEKD3 (ORCPT ); Mon, 5 Aug 2019 06:03:29 -0400 Received: from relay3-d.mail.gandi.net ([217.70.183.195]:37909 "EHLO relay3-d.mail.gandi.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1728244AbfHEKD2 (ORCPT ); Mon, 5 Aug 2019 06:03:28 -0400 X-Originating-IP: 86.250.200.211 Received: from localhost.localdomain (lfbn-1-17395-211.w86-250.abo.wanadoo.fr [86.250.200.211]) (Authenticated sender: miquel.raynal@bootlin.com) by relay3-d.mail.gandi.net (Postfix) with ESMTPSA id 38FD360019; Mon, 5 Aug 2019 10:03:25 +0000 (UTC) From: Miquel Raynal To: Rob Herring , Mark Rutland , Michael Turquette , Stephen Boyd Cc: , linux-clk@vger.kernel.org, Thomas Petazzoni , Gregory Clement , Antoine Tenart , Maxime Chevallier , Nadav Haklai , Grzegorz Jaszczyk , Marcin Wojtas , Stefan Chulski , Yan Markman , Ben Peled , Miquel Raynal Subject: [PATCH 7/8] clk: mvebu: ap806: Prepare the introduction of AP807 clock support Date: Mon, 5 Aug 2019 12:03:09 +0200 Message-Id: <20190805100310.29048-8-miquel.raynal@bootlin.com> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20190805100310.29048-1-miquel.raynal@bootlin.com> References: <20190805100310.29048-1-miquel.raynal@bootlin.com> MIME-Version: 1.0 Sender: linux-clk-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-clk@vger.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP From: Ben Peled Factor out the code that is only useful to AP806 so it will be easier to support AP807. No functional changes. Signed-off-by: Ben Peled Signed-off-by: Miquel Raynal --- drivers/clk/mvebu/ap806-system-controller.c | 146 +++++++++++--------- 1 file changed, 80 insertions(+), 66 deletions(-) diff --git a/drivers/clk/mvebu/ap806-system-controller.c b/drivers/clk/mvebu/ap806-system-controller.c index bc43adff02e0..c64e2cc4a3ba 100644 --- a/drivers/clk/mvebu/ap806-system-controller.c +++ b/drivers/clk/mvebu/ap806-system-controller.c @@ -30,6 +30,78 @@ static struct clk_onecell_data ap806_clk_data = { .clk_num = AP806_CLK_NUM, }; +static int ap806_get_sar_clocks(unsigned int freq_mode, + unsigned int *cpuclk_freq, + unsigned int *dclk_freq) +{ + switch (freq_mode) { + case 0x0: + *cpuclk_freq = 2000; + *dclk_freq = 600; + break; + case 0x1: + *cpuclk_freq = 2000; + *dclk_freq = 525; + break; + case 0x6: + *cpuclk_freq = 1800; + *dclk_freq = 600; + break; + case 0x7: + *cpuclk_freq = 1800; + *dclk_freq = 525; + break; + case 0x4: + *cpuclk_freq = 1600; + *dclk_freq = 400; + break; + case 0xB: + *cpuclk_freq = 1600; + *dclk_freq = 450; + break; + case 0xD: + *cpuclk_freq = 1600; + *dclk_freq = 525; + break; + case 0x1a: + *cpuclk_freq = 1400; + *dclk_freq = 400; + break; + case 0x14: + *cpuclk_freq = 1300; + *dclk_freq = 400; + break; + case 0x17: + *cpuclk_freq = 1300; + *dclk_freq = 325; + break; + case 0x19: + *cpuclk_freq = 1200; + *dclk_freq = 400; + break; + case 0x13: + *cpuclk_freq = 1000; + *dclk_freq = 325; + break; + case 0x1d: + *cpuclk_freq = 1000; + *dclk_freq = 400; + break; + case 0x1c: + *cpuclk_freq = 800; + *dclk_freq = 400; + break; + case 0x1b: + *cpuclk_freq = 600; + *dclk_freq = 400; + break; + default: + return -EINVAL; + } + + return 0; +} + static int ap806_syscon_common_probe(struct platform_device *pdev, struct device_node *syscon_node) { @@ -54,76 +126,18 @@ static int ap806_syscon_common_probe(struct platform_device *pdev, } freq_mode = reg & AP806_SAR_CLKFREQ_MODE_MASK; - switch (freq_mode) { - case 0x0: - case 0x1: - cpuclk_freq = 2000; - break; - case 0x6: - case 0x7: - cpuclk_freq = 1800; - break; - case 0x4: - case 0xB: - case 0xD: - cpuclk_freq = 1600; - break; - case 0x1a: - cpuclk_freq = 1400; - break; - case 0x14: - case 0x17: - cpuclk_freq = 1300; - break; - case 0x19: - cpuclk_freq = 1200; - break; - case 0x13: - case 0x1d: - cpuclk_freq = 1000; - break; - case 0x1c: - cpuclk_freq = 800; - break; - case 0x1b: - cpuclk_freq = 600; - break; - default: - dev_err(dev, "invalid Sample at Reset value\n"); + + if (of_device_is_compatible(pdev->dev.of_node, + "marvell,ap806-clock")) { + ret = ap806_get_sar_clocks(freq_mode, &cpuclk_freq, &dclk_freq); + } else { + dev_err(dev, "compatible not supported\n"); return -EINVAL; } - /* Get DCLK frequency (DCLK = DDR_CLK / 2) */ - switch (freq_mode) { - case 0x0: - case 0x6: - /* DDR_CLK = 1200Mhz */ - dclk_freq = 600; - break; - case 0x1: - case 0x7: - case 0xD: - /* DDR_CLK = 1050Mhz */ - dclk_freq = 525; - break; - case 0x13: - case 0x17: - /* DDR_CLK = 650Mhz */ - dclk_freq = 325; - break; - case 0x4: - case 0x14: - case 0x19: - case 0x1A: - case 0x1B: - case 0x1C: - case 0x1D: - /* DDR_CLK = 800Mhz */ - dclk_freq = 400; - break; - default: - dclk_freq = 0; + if (ret) { dev_err(dev, "invalid Sample at Reset value\n"); + return ret; } /* Convert to hertz */ From patchwork Mon Aug 5 10:03:10 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Miquel Raynal X-Patchwork-Id: 11076451 Return-Path: Received: from mail.wl.linuxfoundation.org (pdx-wl-mail.web.codeaurora.org [172.30.200.125]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id 056F413B1 for ; Mon, 5 Aug 2019 10:03:31 +0000 (UTC) Received: from mail.wl.linuxfoundation.org (localhost [127.0.0.1]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id E5FFD28372 for ; Mon, 5 Aug 2019 10:03:30 +0000 (UTC) Received: by mail.wl.linuxfoundation.org (Postfix, from userid 486) id D991B28861; Mon, 5 Aug 2019 10:03:30 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on pdx-wl-mail.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-7.9 required=2.0 tests=BAYES_00,MAILING_LIST_MULTI, RCVD_IN_DNSWL_HI autolearn=ham version=3.3.1 Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id 7F39528372 for ; Mon, 5 Aug 2019 10:03:30 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1728244AbfHEKDa (ORCPT ); Mon, 5 Aug 2019 06:03:30 -0400 Received: from relay3-d.mail.gandi.net ([217.70.183.195]:44065 "EHLO relay3-d.mail.gandi.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1728232AbfHEKD3 (ORCPT ); Mon, 5 Aug 2019 06:03:29 -0400 X-Originating-IP: 86.250.200.211 Received: from localhost.localdomain (lfbn-1-17395-211.w86-250.abo.wanadoo.fr [86.250.200.211]) (Authenticated sender: miquel.raynal@bootlin.com) by relay3-d.mail.gandi.net (Postfix) with ESMTPSA id BBCC36000C; Mon, 5 Aug 2019 10:03:26 +0000 (UTC) From: Miquel Raynal To: Rob Herring , Mark Rutland , Michael Turquette , Stephen Boyd Cc: , linux-clk@vger.kernel.org, Thomas Petazzoni , Gregory Clement , Antoine Tenart , Maxime Chevallier , Nadav Haklai , Grzegorz Jaszczyk , Marcin Wojtas , Stefan Chulski , Yan Markman , Ben Peled , Miquel Raynal Subject: [PATCH 8/8] clk: mvebu: ap80x: add AP807 clock support Date: Mon, 5 Aug 2019 12:03:10 +0200 Message-Id: <20190805100310.29048-9-miquel.raynal@bootlin.com> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20190805100310.29048-1-miquel.raynal@bootlin.com> References: <20190805100310.29048-1-miquel.raynal@bootlin.com> MIME-Version: 1.0 Sender: linux-clk-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-clk@vger.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP From: Ben Peled Add driver support for AP807 clock. Signed-off-by: Ben Peled Signed-off-by: Miquel Raynal --- drivers/clk/mvebu/ap806-system-controller.c | 28 +++++++++++++++++++++ 1 file changed, 28 insertions(+) diff --git a/drivers/clk/mvebu/ap806-system-controller.c b/drivers/clk/mvebu/ap806-system-controller.c index c64e2cc4a3ba..948bd1e71aea 100644 --- a/drivers/clk/mvebu/ap806-system-controller.c +++ b/drivers/clk/mvebu/ap806-system-controller.c @@ -102,6 +102,30 @@ static int ap806_get_sar_clocks(unsigned int freq_mode, return 0; } +static int ap807_get_sar_clocks(unsigned int freq_mode, + unsigned int *cpuclk_freq, + unsigned int *dclk_freq) +{ + switch (freq_mode) { + case 0x0: + *cpuclk_freq = 2000; + *dclk_freq = 1200; + break; + case 0x6: + *cpuclk_freq = 2200; + *dclk_freq = 1200; + break; + case 0xD: + *cpuclk_freq = 1600; + *dclk_freq = 1200; + break; + default: + return -EINVAL; + } + + return 0; +} + static int ap806_syscon_common_probe(struct platform_device *pdev, struct device_node *syscon_node) { @@ -130,6 +154,9 @@ static int ap806_syscon_common_probe(struct platform_device *pdev, if (of_device_is_compatible(pdev->dev.of_node, "marvell,ap806-clock")) { ret = ap806_get_sar_clocks(freq_mode, &cpuclk_freq, &dclk_freq); + } else if (of_device_is_compatible(pdev->dev.of_node, + "marvell,ap807-clock")) { + ret = ap807_get_sar_clocks(freq_mode, &cpuclk_freq, &dclk_freq); } else { dev_err(dev, "compatible not supported\n"); return -EINVAL; @@ -252,6 +279,7 @@ builtin_platform_driver(ap806_syscon_legacy_driver); static const struct of_device_id ap806_clock_of_match[] = { { .compatible = "marvell,ap806-clock", }, + { .compatible = "marvell,ap807-clock", }, { } };