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Wed, 7 Aug 2019 16:25:10 +0000 (GMT) From: Sylwester Nawrocki To: sboyd@kernel.org, mturquette@baylibre.com Cc: linux@armlinux.org.uk, linux-clk@vger.kernel.org, linux-kernel@vger.kernel.org, linux-samsung-soc@vger.kernel.org, krzk@kernel.org, cw00.choi@samsung.com, m.szyprowski@samsung.com, b.zolnierkie@samsung.com, Sylwester Nawrocki Subject: [PATCH 1/2] clk: samsung: Change signature of exynos5_subcmus_init() function Date: Wed, 7 Aug 2019 18:24:55 +0200 Message-Id: <20190807162456.28694-1-s.nawrocki@samsung.com> X-Mailer: git-send-email 2.17.1 X-Brightmail-Tracker: H4sIAAAAAAAAA0WSfSzUcRzHfe93vwenaz8/Nh+S6pY2laey+ZUerdbxRw9/ZdlNJ785xdH9 UMqW9UTC1DQ0K7HINfOQJGJ26DaNIyVc4Q/FPNdda7mQ8zv13/vh9d7n+8eXwpjruBsVo07k NGplrIyQiOvf/jZ4qyyhCr/Zlw5sTUEVzn4yj+OswVBNst+zhnG2r7GIYAsMLSJW96AZsZXt X0i2t/Mo2zadjrNL/TXiQw7yvv5eTD43cIuU12rvEPKcOi2Sm2o9TuJnJPuiuNiYZE7je+Cs RFVoNJIJHbsvd33F09D0jkxkTwEdAMVZFeJMJKEY+hkCXeWizZgRDFb1EIIxIaj4/BRfm3wY LbFR5Qja5rqJf5Pa1sFViqD9IbsjB1m1M+0N6WUtqxBG3xTBR3MJZi2c6DCo6ZoSZSKKEtOe 8Kgr0hpL6SCwZAsI0JvgeXUrZt0C/YsA43idSCiOwNLUBCloJ5jU19m0Oyy/fiwSBjcQZDUZ ScHkIhjRFyOBCoI2fS9uvYzRXlDV6CvEh2Fo0UBYY6DXw8CMozXGVuT9+nxMiKWQcZsR6K1g 0ebbnuMGd8eWxYKWw2jnt1XN0ApYaJgQ5SKPh/9vFSOkRS5cEh8XzfG71NwlH14Zxyepo33O xcfVopWf8W5Jb25AjX8idYimkGyd1K4nVMHgymQ+JU6HgMJkztLh5BAFI41SplzhNPERmqRY jtehDZRY5iK9ajcaztDRykTuAsclcJq1VkTZu6UhV6aUActGPSpKSgjIk2O4M0lPBlZiDuGZ O/uxsu4np8Z+DtyL8PEd8fa6Jjn/Y78MQhrny4NfnZDP20e4huryLvYEn9YHppKOQzOmaUnq VJq5+SCxd/Z9iLublmuK9NxyrDTj+B6Jd3vom22by1UtCzEVYQYRIXthLDT5mWViXqX0345p eOVfPV+QkhUDAAA= X-Brightmail-Tracker: H4sIAAAAAAAAA+NgFrrGLMWRmVeSWpSXmKPExsVy+t/xe7rpv71iDbr3s1hsnLGe1eL6l+es FufPb2C3+Nhzj9Xi8q45bBYzzu9jsjg0dS+jxdojd9ktLp5ytTj8pp3V4t+1jSwO3B6Xr11k 9nh/o5XdY9OqTjaPvi2rGD0+b5ILYI3SsynKLy1JVcjILy6xVYo2tDDSM7S00DMysdQzNDaP tTIyVdK3s0lJzcksSy3St0vQy5h5+zZ7wVHjirNPWRsY32h3MXJySAiYSFx5sIili5GLQ0hg KaPEzFmrmLoYOYASUhLzW5QgaoQl/lzrYoOo+cQo8fP4dVaQBJuAoUTv0T5GEFtEQF9ictsG sEHMAn1MEnduXQErEhYIk3h7YRkLyFAWAVWJeWeTQMK8AtYSv3sXMUMskJdYveEA8wRGngWM DKsYRVJLi3PTc4uN9IoTc4tL89L1kvNzNzECw3TbsZ9bdjB2vQs+xCjAwajEw8twwStWiDWx rLgy9xCjBAezkgjvvTLPWCHelMTKqtSi/Pii0pzU4kOMpkC7JzJLiSbnA2MoryTe0NTQ3MLS 0NzY3NjMQkmct0PgYIyQQHpiSWp2ampBahFMHxMHp1QD4/lZP1TnHvYtnfnKavEPQb8bt2Yc 3XZtvoDIypsmk/grEnNfm02NP8exJjyHT3uvcFtwiSRn8r/wF5XvztW9esF59trBY30qi+z/ 7ufRDr9zh6dbkf/dMW5+ldnl167YLgjWuWr9aWns6R8epodnMhTPaxW643SakTnu0QvlY+fj X11craqzab0SS3FGoqEWc1FxIgCQFVLFaQIAAA== X-CMS-MailID: 20190807162511eucas1p2eedb33bdee87f80528b59bb4e869daf1 X-Msg-Generator: CA X-RootMTR: 20190807162511eucas1p2eedb33bdee87f80528b59bb4e869daf1 X-EPHeader: CA CMS-TYPE: 201P X-CMS-RootMailID: 20190807162511eucas1p2eedb33bdee87f80528b59bb4e869daf1 References: Sender: linux-clk-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-clk@vger.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP In order to make it easier in subsequent patch to create different subcmu lists for exynos5420 and exynos5800 SoCs the code is rewritten so we pass an array of pointers to the subcmus initialization function. Signed-off-by: Sylwester Nawrocki Tested-by: Jaafar Ali Reviewed-by: Marek Szyprowski --- drivers/clk/samsung/clk-exynos5-subcmu.c | 16 +++---- drivers/clk/samsung/clk-exynos5-subcmu.h | 2 +- drivers/clk/samsung/clk-exynos5250.c | 7 ++- drivers/clk/samsung/clk-exynos5420.c | 60 ++++++++++++++---------- 4 files changed, 49 insertions(+), 36 deletions(-) diff --git a/drivers/clk/samsung/clk-exynos5-subcmu.c b/drivers/clk/samsung/clk-exynos5-subcmu.c index 91db7894125d..65c82d922b05 100644 --- a/drivers/clk/samsung/clk-exynos5-subcmu.c +++ b/drivers/clk/samsung/clk-exynos5-subcmu.c @@ -14,7 +14,7 @@ #include "clk-exynos5-subcmu.h" static struct samsung_clk_provider *ctx; -static const struct exynos5_subcmu_info *cmu; +static const struct exynos5_subcmu_info **cmu; static int nr_cmus; static void exynos5_subcmu_clk_save(void __iomem *base, @@ -56,17 +56,17 @@ static void exynos5_subcmu_defer_gate(struct samsung_clk_provider *ctx, * when OF-core populates all device-tree nodes. */ void exynos5_subcmus_init(struct samsung_clk_provider *_ctx, int _nr_cmus, - const struct exynos5_subcmu_info *_cmu) + const struct exynos5_subcmu_info **_cmu) { ctx = _ctx; cmu = _cmu; nr_cmus = _nr_cmus; for (; _nr_cmus--; _cmu++) { - exynos5_subcmu_defer_gate(ctx, _cmu->gate_clks, - _cmu->nr_gate_clks); - exynos5_subcmu_clk_save(ctx->reg_base, _cmu->suspend_regs, - _cmu->nr_suspend_regs); + exynos5_subcmu_defer_gate(ctx, (*_cmu)->gate_clks, + (*_cmu)->nr_gate_clks); + exynos5_subcmu_clk_save(ctx->reg_base, (*_cmu)->suspend_regs, + (*_cmu)->nr_suspend_regs); } } @@ -163,9 +163,9 @@ static int __init exynos5_clk_probe(struct platform_device *pdev) if (of_property_read_string(np, "label", &name) < 0) continue; for (i = 0; i < nr_cmus; i++) - if (strcmp(cmu[i].pd_name, name) == 0) + if (strcmp(cmu[i]->pd_name, name) == 0) exynos5_clk_register_subcmu(&pdev->dev, - &cmu[i], np); + cmu[i], np); } return 0; } diff --git a/drivers/clk/samsung/clk-exynos5-subcmu.h b/drivers/clk/samsung/clk-exynos5-subcmu.h index 755ee8aaa3de..9ae5356f25aa 100644 --- a/drivers/clk/samsung/clk-exynos5-subcmu.h +++ b/drivers/clk/samsung/clk-exynos5-subcmu.h @@ -21,6 +21,6 @@ struct exynos5_subcmu_info { }; void exynos5_subcmus_init(struct samsung_clk_provider *ctx, int nr_cmus, - const struct exynos5_subcmu_info *cmu); + const struct exynos5_subcmu_info **cmu); #endif diff --git a/drivers/clk/samsung/clk-exynos5250.c b/drivers/clk/samsung/clk-exynos5250.c index f2b896881768..931c70a4da19 100644 --- a/drivers/clk/samsung/clk-exynos5250.c +++ b/drivers/clk/samsung/clk-exynos5250.c @@ -681,6 +681,10 @@ static const struct exynos5_subcmu_info exynos5250_disp_subcmu = { .pd_name = "DISP1", }; +static const struct exynos5_subcmu_info *exynos5250_subcmus[] = { + &exynos5250_disp_subcmu, +}; + static const struct samsung_pll_rate_table vpll_24mhz_tbl[] __initconst = { /* sorted in descending order */ /* PLL_36XX_RATE(rate, m, p, s, k) */ @@ -843,7 +847,8 @@ static void __init exynos5250_clk_init(struct device_node *np) samsung_clk_sleep_init(reg_base, exynos5250_clk_regs, ARRAY_SIZE(exynos5250_clk_regs)); - exynos5_subcmus_init(ctx, 1, &exynos5250_disp_subcmu); + exynos5_subcmus_init(ctx, ARRAY_SIZE(exynos5250_subcmus), + exynos5250_subcmus); samsung_clk_of_add_provider(np, ctx); diff --git a/drivers/clk/samsung/clk-exynos5420.c b/drivers/clk/samsung/clk-exynos5420.c index 01bca5a498b2..fdb17c799aa5 100644 --- a/drivers/clk/samsung/clk-exynos5420.c +++ b/drivers/clk/samsung/clk-exynos5420.c @@ -1281,32 +1281,40 @@ static struct exynos5_subcmu_reg_dump exynos5x_mfc_suspend_regs[] = { { DIV4_RATIO, 0, 0x3 }, /* DIV dout_mfc_blk */ }; -static const struct exynos5_subcmu_info exynos5x_subcmus[] = { - { - .div_clks = exynos5x_disp_div_clks, - .nr_div_clks = ARRAY_SIZE(exynos5x_disp_div_clks), - .gate_clks = exynos5x_disp_gate_clks, - .nr_gate_clks = ARRAY_SIZE(exynos5x_disp_gate_clks), - .suspend_regs = exynos5x_disp_suspend_regs, - .nr_suspend_regs = ARRAY_SIZE(exynos5x_disp_suspend_regs), - .pd_name = "DISP", - }, { - .div_clks = exynos5x_gsc_div_clks, - .nr_div_clks = ARRAY_SIZE(exynos5x_gsc_div_clks), - .gate_clks = exynos5x_gsc_gate_clks, - .nr_gate_clks = ARRAY_SIZE(exynos5x_gsc_gate_clks), - .suspend_regs = exynos5x_gsc_suspend_regs, - .nr_suspend_regs = ARRAY_SIZE(exynos5x_gsc_suspend_regs), - .pd_name = "GSC", - }, { - .div_clks = exynos5x_mfc_div_clks, - .nr_div_clks = ARRAY_SIZE(exynos5x_mfc_div_clks), - .gate_clks = exynos5x_mfc_gate_clks, - .nr_gate_clks = ARRAY_SIZE(exynos5x_mfc_gate_clks), - .suspend_regs = exynos5x_mfc_suspend_regs, - .nr_suspend_regs = ARRAY_SIZE(exynos5x_mfc_suspend_regs), - .pd_name = "MFC", - }, +static const struct exynos5_subcmu_info exynos5x_disp_subcmu = { + .div_clks = exynos5x_disp_div_clks, + .nr_div_clks = ARRAY_SIZE(exynos5x_disp_div_clks), + .gate_clks = exynos5x_disp_gate_clks, + .nr_gate_clks = ARRAY_SIZE(exynos5x_disp_gate_clks), + .suspend_regs = exynos5x_disp_suspend_regs, + .nr_suspend_regs = ARRAY_SIZE(exynos5x_disp_suspend_regs), + .pd_name = "DISP", +}; + +static const struct exynos5_subcmu_info exynos5x_gsc_subcmu = { + .div_clks = exynos5x_gsc_div_clks, + .nr_div_clks = ARRAY_SIZE(exynos5x_gsc_div_clks), + .gate_clks = exynos5x_gsc_gate_clks, + .nr_gate_clks = ARRAY_SIZE(exynos5x_gsc_gate_clks), + .suspend_regs = exynos5x_gsc_suspend_regs, + .nr_suspend_regs = ARRAY_SIZE(exynos5x_gsc_suspend_regs), + .pd_name = "GSC", +}; + +static const struct exynos5_subcmu_info exynos5x_mfc_subcmu = { + .div_clks = exynos5x_mfc_div_clks, + .nr_div_clks = ARRAY_SIZE(exynos5x_mfc_div_clks), + .gate_clks = exynos5x_mfc_gate_clks, + .nr_gate_clks = ARRAY_SIZE(exynos5x_mfc_gate_clks), + .suspend_regs = exynos5x_mfc_suspend_regs, + .nr_suspend_regs = ARRAY_SIZE(exynos5x_mfc_suspend_regs), + .pd_name = "MFC", +}; + +static const struct exynos5_subcmu_info *exynos5x_subcmus[] = { + &exynos5x_disp_subcmu, + &exynos5x_gsc_subcmu, + &exynos5x_mfc_subcmu, }; static const struct samsung_pll_rate_table exynos5420_pll2550x_24mhz_tbl[] __initconst = { From patchwork Wed Aug 7 16:24:56 2019 Content-Type: text/plain; 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Wed, 7 Aug 2019 16:25:18 +0000 (GMT) From: Sylwester Nawrocki To: sboyd@kernel.org, mturquette@baylibre.com Cc: linux@armlinux.org.uk, linux-clk@vger.kernel.org, linux-kernel@vger.kernel.org, linux-samsung-soc@vger.kernel.org, krzk@kernel.org, cw00.choi@samsung.com, m.szyprowski@samsung.com, b.zolnierkie@samsung.com, Sylwester Nawrocki Subject: [PATCH 2/2] clk: samsung: exynos5800: Move MAU subsystem clocks to MAU sub-CMU Date: Wed, 7 Aug 2019 18:24:56 +0200 Message-Id: <20190807162456.28694-2-s.nawrocki@samsung.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20190807162456.28694-1-s.nawrocki@samsung.com> X-Brightmail-Tracker: H4sIAAAAAAAAA+NgFuplleLIzCtJLcpLzFFi42LZduzned38316xBjO2KVlsnLGe1eL6l+es FufPb2C3+Nhzj9Xi8q45bBYzzu9jsjg0dS+jxdojd9ktLp5ytTj8pp3V4t+1jSwO3B6Xr11k 9nh/o5XdY9OqTjaPvi2rGD0+b5ILYI3isklJzcksSy3St0vgypjZMJupYKlOxZ+P/g2MZ1S7 GDk5JARMJD7sPMfexcjFISSwglHi1up/zBDOF0aJjvaTTBDOZ0aJg/MXMMO03Li8jgnEFhJY zijxtk0YruPBxl/sIAk2AUOJ3qN9jCC2iICuRPuyfWwgRcwCLUwSV78sApskLBApcfzHKrAi FgFViV+LfoDFeQWsJS7taWWF2CYvsXrDAaA4BwengI3Ey5ehIHMkBPrZJd5/2M8EUeMisfHW NhYIW1ji1fEt7BC2jMT/nfOZIBqaGSV6dt9mh3AmMErcP76AEaLKWuLw8YusIBuYBTQl1u/S hwg7SjzvAinhALL5JG68FQQJMwOZk7ZNZ4YI80p0tAlBVKtI/F41HeocKYnuJ/+hzvGQ+LD4 AhsksPoZJU5OZ5zAKD8LYdcCRsZVjOKppcW56anFhnmp5XrFibnFpXnpesn5uZsYgYnk9L/j n3Ywfr2UdIhRgINRiYeX4YJXrBBrYllxZe4hRgkOZiUR3ntlnrFCvCmJlVWpRfnxRaU5qcWH GKU5WJTEeasZHkQLCaQnlqRmp6YWpBbBZJk4OKUaGCeH7Z0Y2Xjpz/Q+ZrHOJZuFZa4b3vYq F8y6fvzV/IkNZ6J2/Sgxin+vxv+fIerCxWxWsQdaZotD27S4F8wrnRnlfPXlo6c2XSq7637p T43eN+0kW7Xk3J0v+hZ1XPx45ff9z4t+P1B7M88n5rTxCktFycCnnxxnrchryVGJP5arLjY7 /Te3taESS3FGoqEWc1FxIgDJL9ekIAMAAA== X-Brightmail-Tracker: H4sIAAAAAAAAA+NgFnrHLMWRmVeSWpSXmKPExsVy+t/xe7p5v71iDdY+0LfYOGM9q8X1L89Z Lc6f38Bu8bHnHqvF5V1z2CxmnN/HZHFo6l5Gi7VH7rJbXDzlanH4TTurxb9rG1kcuD0uX7vI 7PH+Riu7x6ZVnWwefVtWMXp83iQXwBqlZ1OUX1qSqpCRX1xiqxRtaGGkZ2hpoWdkYqlnaGwe a2VkqqRvZ5OSmpNZllqkb5eglzGzYTZTwVKdij8f/RsYz6h2MXJySAiYSNy4vI6pi5GLQ0hg KaPEzBfvWbsYOYASUhLzW5QgaoQl/lzrYoOo+cQo8WLSERaQBJuAoUTv0T5GEFtEQF9ictsG FpAiZoE+Jok7t66wgiSEBcIlns5/AWazCKhK/Fr0gxnE5hWwlri0p5UVYoO8xOoNB5hBFnMK 2Ei8fBkKEhYCKpn29grrBEa+BYwMqxhFUkuLc9Nzi430ihNzi0vz0vWS83M3MQLDetuxn1t2 MHa9Cz7EKMDBqMTDy3DBK1aINbGsuDL3EKMEB7OSCO+9Ms9YId6UxMqq1KL8+KLSnNTiQ4ym QDdNZJYSTc4HxlxeSbyhqaG5haWhubG5sZmFkjhvh8DBGCGB9MSS1OzU1ILUIpg+Jg5OqQbG 6RNMObaEm/7zP3PveXWylUruhDWzTz9isXtUz3HkYcN8ZkHLTV/2Nu5ZX695p8h02g9mo7wL 5+/5qH+oj/b6/zl/7VXzOezSdgGCm04+aQh0zJ7FOjM/ovDRnYMGaSvVGTYt1lRU1ZA/cGqT 08xkIV6R0/E1a9Xz+sS/FL6U3TJZt/4Nx1deJZbijERDLeai4kQAlNvfjoECAAA= X-CMS-MailID: 20190807162519eucas1p2b9dd9f31cc6e60e0bc935e9a6ceef908 X-Msg-Generator: CA X-RootMTR: 20190807162519eucas1p2b9dd9f31cc6e60e0bc935e9a6ceef908 X-EPHeader: CA CMS-TYPE: 201P X-CMS-RootMailID: 20190807162519eucas1p2b9dd9f31cc6e60e0bc935e9a6ceef908 References: <20190807162456.28694-1-s.nawrocki@samsung.com> Sender: linux-clk-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-clk@vger.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP This patch fixes broken sound on Exynos5422/5800 platforms after system/suspend resume cycle in cases where the audio root clock is derived from MAU_EPLL_CLK. In order to preserve state of the USER_MUX_MAU_EPLL_CLK clock mux during system suspend/resume cycle for Exynos5800 we group the MAU block input clocks in "MAU" sub-CMU and add the clock mux control bit to .suspend_regs. This ensures that user configuration of the mux is not lost after the PMU block changes the mux setting to OSC_DIV when switching off the MAU power domain. Adding the SRC_TOP9 register to exynos5800_clk_regs[] array is not sufficient as at the time of the syscore_ops suspend call MAU power domain is already turned off and we already save and subsequently restore an incorrect register's value. Fixes: b06a532bf1fa ("clk: samsung: Add Exynos5 sub-CMU clock driver") Reported-by: Jaafar Ali Suggested-by: Marek Szyprowski Signed-off-by: Sylwester Nawrocki Tested-by: Jaafar Ali --- drivers/clk/samsung/clk-exynos5420.c | 54 ++++++++++++++++++++++------ 1 file changed, 43 insertions(+), 11 deletions(-) diff --git a/drivers/clk/samsung/clk-exynos5420.c b/drivers/clk/samsung/clk-exynos5420.c index fdb17c799aa5..b52daf5aa755 100644 --- a/drivers/clk/samsung/clk-exynos5420.c +++ b/drivers/clk/samsung/clk-exynos5420.c @@ -534,8 +534,6 @@ static const struct samsung_gate_clock exynos5800_gate_clks[] __initconst = { GATE_BUS_TOP, 24, 0, 0), GATE(CLK_ACLK432_SCALER, "aclk432_scaler", "mout_user_aclk432_scaler", GATE_BUS_TOP, 27, CLK_IS_CRITICAL, 0), - GATE(CLK_MAU_EPLL, "mau_epll", "mout_user_mau_epll", - SRC_MASK_TOP7, 20, CLK_SET_RATE_PARENT, 0), }; static const struct samsung_mux_clock exynos5420_mux_clks[] __initconst = { @@ -577,8 +575,13 @@ static const struct samsung_div_clock exynos5420_div_clks[] __initconst = { static const struct samsung_gate_clock exynos5420_gate_clks[] __initconst = { GATE(CLK_SECKEY, "seckey", "aclk66_psgen", GATE_BUS_PERIS1, 1, 0, 0), + /* Maudio Block */ GATE(CLK_MAU_EPLL, "mau_epll", "mout_mau_epll_clk", SRC_MASK_TOP7, 20, CLK_SET_RATE_PARENT, 0), + GATE(CLK_SCLK_MAUDIO0, "sclk_maudio0", "dout_maudio0", + GATE_TOP_SCLK_MAU, 0, CLK_SET_RATE_PARENT, 0), + GATE(CLK_SCLK_MAUPCM0, "sclk_maupcm0", "dout_maupcm0", + GATE_TOP_SCLK_MAU, 1, CLK_SET_RATE_PARENT, 0), }; static const struct samsung_mux_clock exynos5x_mux_clks[] __initconst = { @@ -1017,12 +1020,6 @@ static const struct samsung_gate_clock exynos5x_gate_clks[] __initconst = { GATE(CLK_SCLK_DP1, "sclk_dp1", "dout_dp1", GATE_TOP_SCLK_DISP1, 20, CLK_SET_RATE_PARENT, 0), - /* Maudio Block */ - GATE(CLK_SCLK_MAUDIO0, "sclk_maudio0", "dout_maudio0", - GATE_TOP_SCLK_MAU, 0, CLK_SET_RATE_PARENT, 0), - GATE(CLK_SCLK_MAUPCM0, "sclk_maupcm0", "dout_maupcm0", - GATE_TOP_SCLK_MAU, 1, CLK_SET_RATE_PARENT, 0), - /* FSYS Block */ GATE(CLK_TSI, "tsi", "aclk200_fsys", GATE_BUS_FSYS0, 0, 0, 0), GATE(CLK_PDMA0, "pdma0", "aclk200_fsys", GATE_BUS_FSYS0, 1, 0, 0), @@ -1281,6 +1278,20 @@ static struct exynos5_subcmu_reg_dump exynos5x_mfc_suspend_regs[] = { { DIV4_RATIO, 0, 0x3 }, /* DIV dout_mfc_blk */ }; + +static const struct samsung_gate_clock exynos5800_mau_gate_clks[] __initconst = { + GATE(CLK_MAU_EPLL, "mau_epll", "mout_user_mau_epll", + SRC_MASK_TOP7, 20, CLK_SET_RATE_PARENT, 0), + GATE(CLK_SCLK_MAUDIO0, "sclk_maudio0", "dout_maudio0", + GATE_TOP_SCLK_MAU, 0, CLK_SET_RATE_PARENT, 0), + GATE(CLK_SCLK_MAUPCM0, "sclk_maupcm0", "dout_maupcm0", + GATE_TOP_SCLK_MAU, 1, CLK_SET_RATE_PARENT, 0), +}; + +static struct exynos5_subcmu_reg_dump exynos5800_mau_suspend_regs[] = { + { SRC_TOP9, 0, BIT(8) }, +}; + static const struct exynos5_subcmu_info exynos5x_disp_subcmu = { .div_clks = exynos5x_disp_div_clks, .nr_div_clks = ARRAY_SIZE(exynos5x_disp_div_clks), @@ -1311,12 +1322,27 @@ static const struct exynos5_subcmu_info exynos5x_mfc_subcmu = { .pd_name = "MFC", }; +static const struct exynos5_subcmu_info exynos5800_mau_subcmu = { + .gate_clks = exynos5800_mau_gate_clks, + .nr_gate_clks = ARRAY_SIZE(exynos5800_mau_gate_clks), + .suspend_regs = exynos5800_mau_suspend_regs, + .nr_suspend_regs = ARRAY_SIZE(exynos5800_mau_suspend_regs), + .pd_name = "MAU", +}; + static const struct exynos5_subcmu_info *exynos5x_subcmus[] = { &exynos5x_disp_subcmu, &exynos5x_gsc_subcmu, &exynos5x_mfc_subcmu, }; +static const struct exynos5_subcmu_info *exynos5800_subcmus[] = { + &exynos5x_disp_subcmu, + &exynos5x_gsc_subcmu, + &exynos5x_mfc_subcmu, + &exynos5800_mau_subcmu, +}; + static const struct samsung_pll_rate_table exynos5420_pll2550x_24mhz_tbl[] __initconst = { PLL_35XX_RATE(24 * MHZ, 2000000000, 250, 3, 0), PLL_35XX_RATE(24 * MHZ, 1900000000, 475, 6, 0), @@ -1547,11 +1573,17 @@ static void __init exynos5x_clk_init(struct device_node *np, samsung_clk_extended_sleep_init(reg_base, exynos5x_clk_regs, ARRAY_SIZE(exynos5x_clk_regs), exynos5420_set_clksrc, ARRAY_SIZE(exynos5420_set_clksrc)); - if (soc == EXYNOS5800) + + if (soc == EXYNOS5800) { samsung_clk_sleep_init(reg_base, exynos5800_clk_regs, ARRAY_SIZE(exynos5800_clk_regs)); - exynos5_subcmus_init(ctx, ARRAY_SIZE(exynos5x_subcmus), - exynos5x_subcmus); + + exynos5_subcmus_init(ctx, ARRAY_SIZE(exynos5800_subcmus), + exynos5800_subcmus); + } else { + exynos5_subcmus_init(ctx, ARRAY_SIZE(exynos5x_subcmus), + exynos5x_subcmus); + } samsung_clk_of_add_provider(np, ctx); }