From patchwork Thu Aug 8 01:44:21 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Daniele Ceraolo Spurio X-Patchwork-Id: 11083067 Return-Path: Received: from mail.wl.linuxfoundation.org (pdx-wl-mail.web.codeaurora.org [172.30.200.125]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id 0991F912 for ; Thu, 8 Aug 2019 01:44:47 +0000 (UTC) Received: from mail.wl.linuxfoundation.org (localhost [127.0.0.1]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id EC99028694 for ; Thu, 8 Aug 2019 01:44:46 +0000 (UTC) Received: by mail.wl.linuxfoundation.org (Postfix, from userid 486) id E06B828AE0; Thu, 8 Aug 2019 01:44:46 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on pdx-wl-mail.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-5.2 required=2.0 tests=BAYES_00,MAILING_LIST_MULTI, RCVD_IN_DNSWL_MED autolearn=ham version=3.3.1 Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher DHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.wl.linuxfoundation.org (Postfix) with ESMTPS id 41BF328694 for ; Thu, 8 Aug 2019 01:44:46 +0000 (UTC) Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id 604E46E77F; Thu, 8 Aug 2019 01:44:45 +0000 (UTC) X-Original-To: intel-gfx@lists.freedesktop.org Delivered-To: intel-gfx@lists.freedesktop.org Received: from mga06.intel.com (mga06.intel.com [134.134.136.31]) by gabe.freedesktop.org (Postfix) with ESMTPS id 47F966E0A2 for ; Thu, 8 Aug 2019 01:44:43 +0000 (UTC) X-Amp-Result: SKIPPED(no attachment in message) X-Amp-File-Uploaded: False Received: from orsmga007.jf.intel.com ([10.7.209.58]) by orsmga104.jf.intel.com with ESMTP/TLS/DHE-RSA-AES256-GCM-SHA384; 07 Aug 2019 18:44:43 -0700 X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.64,358,1559545200"; d="scan'208";a="165538120" Received: from dceraolo-linux.fm.intel.com ([10.1.27.145]) by orsmga007.jf.intel.com with ESMTP; 07 Aug 2019 18:44:43 -0700 From: Daniele Ceraolo Spurio To: intel-gfx@lists.freedesktop.org Date: Wed, 7 Aug 2019 18:44:21 -0700 Message-Id: <20190808014423.20377-2-daniele.ceraolospurio@intel.com> X-Mailer: git-send-email 2.22.0 In-Reply-To: <20190808014423.20377-1-daniele.ceraolospurio@intel.com> References: <20190808014423.20377-1-daniele.ceraolospurio@intel.com> MIME-Version: 1.0 Subject: [Intel-gfx] [RFC 1/3] drm/i915: split out uncore_mmio_debug X-BeenThere: intel-gfx@lists.freedesktop.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: Intel graphics driver community testing & development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: intel-gfx-bounces@lists.freedesktop.org Sender: "Intel-gfx" X-Virus-Scanned: ClamAV using ClamSMTP Multiple uncore structures will share the debug infrastructure, so move it to a common place and add extra locking around it. Also, since we now have a separate object, it is cleaner to have dedicated functions working on the object to stop and restart the mmio debug. Apart from the cosmetic changes, this patch introduces 2 functional updates: - All calls to check_for_unclaimed_mmio will now return false when the debug is suspended, not just the ones that are active only when i915_modparams.mmio_debug is set. If we don't trust the result of the check while a user is doing mmio access then we shouldn't attempt the check anywhere. - i915_modparams.mmio_debug is not save/restored anymore around user access. The value is now never touched by the kernel while debug is disabled so no need for save/restore. v2: squash mmio_debug patches, restrict mmio_debug lock usage (Chris) Signed-off-by: Daniele Ceraolo Spurio Cc: Chris Wilson Reviewed-by: Chris Wilson --- drivers/gpu/drm/i915/i915_debugfs.c | 2 +- drivers/gpu/drm/i915/i915_drv.c | 3 +- drivers/gpu/drm/i915/i915_drv.h | 1 + drivers/gpu/drm/i915/intel_uncore.c | 91 ++++++++++++++++++++--------- drivers/gpu/drm/i915/intel_uncore.h | 18 +++--- 5 files changed, 79 insertions(+), 36 deletions(-) diff --git a/drivers/gpu/drm/i915/i915_debugfs.c b/drivers/gpu/drm/i915/i915_debugfs.c index 3b15266c54fd..2310512111ab 100644 --- a/drivers/gpu/drm/i915/i915_debugfs.c +++ b/drivers/gpu/drm/i915/i915_debugfs.c @@ -1129,7 +1129,7 @@ static int i915_forcewake_domains(struct seq_file *m, void *data) unsigned int tmp; seq_printf(m, "user.bypass_count = %u\n", - uncore->user_forcewake.count); + uncore->user_forcewake_count); for_each_fw_domain(fw_domain, uncore, tmp) seq_printf(m, "%s.wake_count = %u\n", diff --git a/drivers/gpu/drm/i915/i915_drv.c b/drivers/gpu/drm/i915/i915_drv.c index 3480db36b63f..fbbff4a133ba 100644 --- a/drivers/gpu/drm/i915/i915_drv.c +++ b/drivers/gpu/drm/i915/i915_drv.c @@ -744,6 +744,7 @@ static int i915_driver_early_probe(struct drm_i915_private *dev_priv) intel_device_info_subplatform_init(dev_priv); + intel_uncore_mmio_debug_init_early(&dev_priv->mmio_debug); intel_uncore_init_early(&dev_priv->uncore, dev_priv); spin_lock_init(&dev_priv->irq_lock); @@ -2044,7 +2045,7 @@ static int i915_drm_suspend_late(struct drm_device *dev, bool hibernation) out: enable_rpm_wakeref_asserts(rpm); - if (!dev_priv->uncore.user_forcewake.count) + if (!dev_priv->uncore.user_forcewake_count) intel_runtime_pm_driver_release(rpm); return ret; diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h index c9476f24f5c1..13c27a75dca8 100644 --- a/drivers/gpu/drm/i915/i915_drv.h +++ b/drivers/gpu/drm/i915/i915_drv.h @@ -1346,6 +1346,7 @@ struct drm_i915_private { resource_size_t stolen_usable_size; /* Total size minus reserved ranges */ struct intel_uncore uncore; + struct intel_uncore_mmio_debug mmio_debug; struct i915_virtual_gpu vgpu; diff --git a/drivers/gpu/drm/i915/intel_uncore.c b/drivers/gpu/drm/i915/intel_uncore.c index 39e8710afdd9..9e583f13a9e4 100644 --- a/drivers/gpu/drm/i915/intel_uncore.c +++ b/drivers/gpu/drm/i915/intel_uncore.c @@ -34,6 +34,32 @@ #define __raw_posting_read(...) ((void)__raw_uncore_read32(__VA_ARGS__)) +void +intel_uncore_mmio_debug_init_early(struct intel_uncore_mmio_debug *mmio_debug) +{ + spin_lock_init(&mmio_debug->lock); + mmio_debug->unclaimed_mmio_check = 1; +} + +static void mmio_debug_suspend(struct intel_uncore_mmio_debug *mmio_debug) +{ + lockdep_assert_held(&mmio_debug->lock); + + /* Save and disable mmio debugging for the user bypass */ + if (!mmio_debug->suspend_count++) { + mmio_debug->saved_mmio_check = mmio_debug->unclaimed_mmio_check; + mmio_debug->unclaimed_mmio_check = 0; + } +} + +static void mmio_debug_resume(struct intel_uncore_mmio_debug *mmio_debug) +{ + lockdep_assert_held(&mmio_debug->lock); + + if (!--mmio_debug->suspend_count) + mmio_debug->unclaimed_mmio_check = mmio_debug->saved_mmio_check; +} + static const char * const forcewake_domain_names[] = { "render", "blitter", @@ -476,6 +502,11 @@ check_for_unclaimed_mmio(struct intel_uncore *uncore) { bool ret = false; + lockdep_assert_held(&uncore->debug->lock); + + if (uncore->debug->suspend_count) + return false; + if (intel_uncore_has_fpga_dbg_unclaimed(uncore)) ret |= fpga_check_for_unclaimed_mmio(uncore); @@ -608,17 +639,11 @@ void intel_uncore_forcewake_get(struct intel_uncore *uncore, void intel_uncore_forcewake_user_get(struct intel_uncore *uncore) { spin_lock_irq(&uncore->lock); - if (!uncore->user_forcewake.count++) { + if (!uncore->user_forcewake_count++) { intel_uncore_forcewake_get__locked(uncore, FORCEWAKE_ALL); - - /* Save and disable mmio debugging for the user bypass */ - uncore->user_forcewake.saved_mmio_check = - uncore->unclaimed_mmio_check; - uncore->user_forcewake.saved_mmio_debug = - i915_modparams.mmio_debug; - - uncore->unclaimed_mmio_check = 0; - i915_modparams.mmio_debug = 0; + spin_lock(&uncore->debug->lock); + mmio_debug_suspend(uncore->debug); + spin_unlock(&uncore->debug->lock); } spin_unlock_irq(&uncore->lock); } @@ -633,15 +658,14 @@ void intel_uncore_forcewake_user_get(struct intel_uncore *uncore) void intel_uncore_forcewake_user_put(struct intel_uncore *uncore) { spin_lock_irq(&uncore->lock); - if (!--uncore->user_forcewake.count) { - if (intel_uncore_unclaimed_mmio(uncore)) + if (!--uncore->user_forcewake_count) { + spin_lock(&uncore->debug->lock); + mmio_debug_resume(uncore->debug); + + if (check_for_unclaimed_mmio(uncore)) dev_info(uncore->i915->drm.dev, "Invalid mmio detected during user access\n"); - - uncore->unclaimed_mmio_check = - uncore->user_forcewake.saved_mmio_check; - i915_modparams.mmio_debug = - uncore->user_forcewake.saved_mmio_debug; + spin_unlock(&uncore->debug->lock); intel_uncore_forcewake_put__locked(uncore, FORCEWAKE_ALL); } @@ -1088,7 +1112,16 @@ unclaimed_reg_debug(struct intel_uncore *uncore, if (likely(!i915_modparams.mmio_debug)) return; + /* interrupts are disabled and re-enabled around uncore->lock usage */ + lockdep_assert_held(&uncore->lock); + + if (before) + spin_lock(&uncore->debug->lock); + __unclaimed_reg_debug(uncore, reg, read, before); + + if (!before) + spin_unlock(&uncore->debug->lock); } #define GEN2_READ_HEADER(x) \ @@ -1607,6 +1640,7 @@ void intel_uncore_init_early(struct intel_uncore *uncore, spin_lock_init(&uncore->lock); uncore->i915 = i915; uncore->rpm = &i915->runtime_pm; + uncore->debug = &i915->mmio_debug; } static void uncore_raw_init(struct intel_uncore *uncore) @@ -1632,7 +1666,6 @@ static int uncore_forcewake_init(struct intel_uncore *uncore) ret = intel_uncore_fw_domains_init(uncore); if (ret) return ret; - forcewake_early_sanitize(uncore, 0); if (IS_GEN_RANGE(i915, 6, 7)) { @@ -1681,8 +1714,6 @@ int intel_uncore_init_mmio(struct intel_uncore *uncore) if (INTEL_GEN(i915) > 5 && !intel_vgpu_active(i915)) uncore->flags |= UNCORE_HAS_FORCEWAKE; - uncore->unclaimed_mmio_check = 1; - if (!intel_uncore_has_forcewake(uncore)) { uncore_raw_init(uncore); } else { @@ -1707,7 +1738,7 @@ int intel_uncore_init_mmio(struct intel_uncore *uncore) uncore->flags |= UNCORE_HAS_FIFO; /* clear out unclaimed reg detection bit */ - if (check_for_unclaimed_mmio(uncore)) + if (intel_uncore_unclaimed_mmio(uncore)) DRM_DEBUG("unclaimed mmio detected on uncore init, clearing\n"); return 0; @@ -1952,7 +1983,13 @@ int __intel_wait_for_register(struct intel_uncore *uncore, bool intel_uncore_unclaimed_mmio(struct intel_uncore *uncore) { - return check_for_unclaimed_mmio(uncore); + bool ret; + + spin_lock_irq(&uncore->debug->lock); + ret = check_for_unclaimed_mmio(uncore); + spin_unlock_irq(&uncore->debug->lock); + + return ret; } bool @@ -1960,24 +1997,24 @@ intel_uncore_arm_unclaimed_mmio_detection(struct intel_uncore *uncore) { bool ret = false; - spin_lock_irq(&uncore->lock); + spin_lock_irq(&uncore->debug->lock); - if (unlikely(uncore->unclaimed_mmio_check <= 0)) + if (unlikely(uncore->debug->unclaimed_mmio_check <= 0)) goto out; - if (unlikely(intel_uncore_unclaimed_mmio(uncore))) { + if (unlikely(check_for_unclaimed_mmio(uncore))) { if (!i915_modparams.mmio_debug) { DRM_DEBUG("Unclaimed register detected, " "enabling oneshot unclaimed register reporting. " "Please use i915.mmio_debug=N for more information.\n"); i915_modparams.mmio_debug++; } - uncore->unclaimed_mmio_check--; + uncore->debug->unclaimed_mmio_check--; ret = true; } out: - spin_unlock_irq(&uncore->lock); + spin_unlock_irq(&uncore->debug->lock); return ret; } diff --git a/drivers/gpu/drm/i915/intel_uncore.h b/drivers/gpu/drm/i915/intel_uncore.h index e603d210a34d..414fc2cb0459 100644 --- a/drivers/gpu/drm/i915/intel_uncore.h +++ b/drivers/gpu/drm/i915/intel_uncore.h @@ -36,6 +36,13 @@ struct drm_i915_private; struct intel_runtime_pm; struct intel_uncore; +struct intel_uncore_mmio_debug { + spinlock_t lock; /** lock is also taken in irq contexts. */ + int unclaimed_mmio_check; + int saved_mmio_check; + u32 suspend_count; +}; + enum forcewake_domain_id { FW_DOMAIN_ID_RENDER = 0, FW_DOMAIN_ID_BLITTER, @@ -137,14 +144,9 @@ struct intel_uncore { u32 __iomem *reg_ack; } *fw_domain[FW_DOMAIN_ID_COUNT]; - struct { - unsigned int count; - - int saved_mmio_check; - int saved_mmio_debug; - } user_forcewake; + unsigned int user_forcewake_count; - int unclaimed_mmio_check; + struct intel_uncore_mmio_debug *debug; }; /* Iterate over initialised fw domains */ @@ -179,6 +181,8 @@ intel_uncore_has_fifo(const struct intel_uncore *uncore) return uncore->flags & UNCORE_HAS_FIFO; } +void +intel_uncore_mmio_debug_init_early(struct intel_uncore_mmio_debug *mmio_debug); void intel_uncore_init_early(struct intel_uncore *uncore, struct drm_i915_private *i915); int intel_uncore_init_mmio(struct intel_uncore *uncore); From patchwork Thu Aug 8 01:44:22 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Daniele Ceraolo Spurio X-Patchwork-Id: 11083069 Return-Path: Received: from mail.wl.linuxfoundation.org (pdx-wl-mail.web.codeaurora.org [172.30.200.125]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id 7E998912 for ; Thu, 8 Aug 2019 01:44:48 +0000 (UTC) Received: from mail.wl.linuxfoundation.org (localhost [127.0.0.1]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id 6EE4A28694 for ; Thu, 8 Aug 2019 01:44:48 +0000 (UTC) Received: by mail.wl.linuxfoundation.org (Postfix, from userid 486) id 631B128AE0; Thu, 8 Aug 2019 01:44:48 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on pdx-wl-mail.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-5.2 required=2.0 tests=BAYES_00,MAILING_LIST_MULTI, RCVD_IN_DNSWL_MED autolearn=ham version=3.3.1 Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher DHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.wl.linuxfoundation.org (Postfix) with ESMTPS id D65A728694 for ; Thu, 8 Aug 2019 01:44:47 +0000 (UTC) Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id 58A566E781; Thu, 8 Aug 2019 01:44:47 +0000 (UTC) X-Original-To: intel-gfx@lists.freedesktop.org Delivered-To: intel-gfx@lists.freedesktop.org Received: from mga06.intel.com (mga06.intel.com [134.134.136.31]) by gabe.freedesktop.org (Postfix) with ESMTPS id 38ACB6E784 for ; Thu, 8 Aug 2019 01:44:44 +0000 (UTC) X-Amp-Result: SKIPPED(no attachment in message) X-Amp-File-Uploaded: False Received: from orsmga007.jf.intel.com ([10.7.209.58]) by orsmga104.jf.intel.com with ESMTP/TLS/DHE-RSA-AES256-GCM-SHA384; 07 Aug 2019 18:44:44 -0700 X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.64,358,1559545200"; d="scan'208";a="165538123" Received: from dceraolo-linux.fm.intel.com ([10.1.27.145]) by orsmga007.jf.intel.com with ESMTP; 07 Aug 2019 18:44:44 -0700 From: Daniele Ceraolo Spurio To: intel-gfx@lists.freedesktop.org Date: Wed, 7 Aug 2019 18:44:22 -0700 Message-Id: <20190808014423.20377-3-daniele.ceraolospurio@intel.com> X-Mailer: git-send-email 2.22.0 In-Reply-To: <20190808014423.20377-1-daniele.ceraolospurio@intel.com> References: <20190808014423.20377-1-daniele.ceraolospurio@intel.com> MIME-Version: 1.0 Subject: [Intel-gfx] [RFC 2/3] drm/i915: introduce display_uncore X-BeenThere: intel-gfx@lists.freedesktop.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: Intel graphics driver community testing & development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: intel-gfx-bounces@lists.freedesktop.org Sender: "Intel-gfx" X-Virus-Scanned: ClamAV using ClamSMTP A forcewake-less uncore to be used to decouple GT accesses from display ones to avoid serializing them when there is no need. New accessors that implicitly use the new uncore have also been added. To avoid accessing the same register from 2 different uncores (which could cause hard hangs), the new accessors expect registers to be defined with the new _DE_MMIO macro. Signed-off-by: Daniele Ceraolo Spurio Cc: Ville Syrjälä --- .../gpu/drm/i915/display/intel_display_reg.h | 22 +++++++++++++ drivers/gpu/drm/i915/i915_drv.c | 17 ++++++++-- drivers/gpu/drm/i915/i915_drv.h | 31 +++++++++++++++++++ drivers/gpu/drm/i915/intel_uncore.c | 9 +++++- 4 files changed, 76 insertions(+), 3 deletions(-) create mode 100644 drivers/gpu/drm/i915/display/intel_display_reg.h diff --git a/drivers/gpu/drm/i915/display/intel_display_reg.h b/drivers/gpu/drm/i915/display/intel_display_reg.h new file mode 100644 index 000000000000..ac0c6975271d --- /dev/null +++ b/drivers/gpu/drm/i915/display/intel_display_reg.h @@ -0,0 +1,22 @@ +/* SPDX-License-Identifier: MIT */ +/* + * Copyright © 2019 Intel Corporation + */ + +#ifndef _INTEL_DISPLAY_REG_H_ +#define _INTEL_DISPLAY_REG_H_ + +#include "i915_reg.h" + +typedef struct { + const i915_reg_t reg; +} intel_de_reg_t; + +#define _DE_MMIO(r) ((const intel_de_reg_t){ .reg = _MMIO(r) }) + +static inline i915_reg_t intel_de_reg_to_mmio(intel_de_reg_t reg) +{ + return reg.reg; +} + +#endif diff --git a/drivers/gpu/drm/i915/i915_drv.c b/drivers/gpu/drm/i915/i915_drv.c index fbbff4a133ba..af015ecf3dcc 100644 --- a/drivers/gpu/drm/i915/i915_drv.c +++ b/drivers/gpu/drm/i915/i915_drv.c @@ -746,6 +746,7 @@ static int i915_driver_early_probe(struct drm_i915_private *dev_priv) intel_uncore_mmio_debug_init_early(&dev_priv->mmio_debug); intel_uncore_init_early(&dev_priv->uncore, dev_priv); + intel_uncore_init_early(&dev_priv->de_uncore, dev_priv); spin_lock_init(&dev_priv->irq_lock); spin_lock_init(&dev_priv->gpu_error.lock); @@ -841,6 +842,10 @@ static int i915_driver_mmio_probe(struct drm_i915_private *dev_priv) if (ret < 0) goto err_bridge; + ret = intel_uncore_init_mmio(&dev_priv->de_uncore); + if (ret < 0) + goto err_uncore; + /* Try to make sure MCHBAR is enabled before poking at it */ intel_setup_mchbar(dev_priv); @@ -852,14 +857,16 @@ static int i915_driver_mmio_probe(struct drm_i915_private *dev_priv) ret = intel_engines_init_mmio(dev_priv); if (ret) - goto err_uncore; + goto err_mchbar; i915_gem_init_mmio(dev_priv); return 0; -err_uncore: +err_mchbar: intel_teardown_mchbar(dev_priv); + intel_uncore_fini_mmio(&dev_priv->de_uncore); +err_uncore: intel_uncore_fini_mmio(&dev_priv->uncore); err_bridge: pci_dev_put(dev_priv->bridge_dev); @@ -875,6 +882,7 @@ static void i915_driver_mmio_release(struct drm_i915_private *dev_priv) { intel_engines_cleanup(dev_priv); intel_teardown_mchbar(dev_priv); + intel_uncore_fini_mmio(&dev_priv->de_uncore); intel_uncore_fini_mmio(&dev_priv->uncore); pci_dev_put(dev_priv->bridge_dev); } @@ -2010,6 +2018,7 @@ static int i915_drm_suspend_late(struct drm_device *dev, bool hibernation) i915_gem_suspend_late(dev_priv); + intel_uncore_suspend(&dev_priv->de_uncore); intel_uncore_suspend(&dev_priv->uncore); intel_power_domains_suspend(dev_priv, @@ -2199,6 +2208,7 @@ static int i915_drm_resume_early(struct drm_device *dev) ret); intel_uncore_resume_early(&dev_priv->uncore); + intel_uncore_resume_early(&dev_priv->de_uncore); intel_gt_check_and_clear_faults(&dev_priv->gt); @@ -2764,6 +2774,7 @@ static int intel_runtime_suspend(struct device *kdev) intel_runtime_pm_disable_interrupts(dev_priv); + intel_uncore_suspend(&dev_priv->de_uncore); intel_uncore_suspend(&dev_priv->uncore); intel_display_power_suspend(dev_priv); @@ -2774,6 +2785,7 @@ static int intel_runtime_suspend(struct device *kdev) if (ret) { DRM_ERROR("Runtime suspend failed, disabling it (%d)\n", ret); intel_uncore_runtime_resume(&dev_priv->uncore); + intel_uncore_runtime_resume(&dev_priv->de_uncore); intel_runtime_pm_enable_interrupts(dev_priv); @@ -2851,6 +2863,7 @@ static int intel_runtime_resume(struct device *kdev) ret = vlv_resume_prepare(dev_priv, true); intel_uncore_runtime_resume(&dev_priv->uncore); + intel_uncore_runtime_resume(&dev_priv->de_uncore); intel_runtime_pm_enable_interrupts(dev_priv); diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h index 13c27a75dca8..015b490c14d6 100644 --- a/drivers/gpu/drm/i915/i915_drv.h +++ b/drivers/gpu/drm/i915/i915_drv.h @@ -66,6 +66,7 @@ #include "display/intel_bios.h" #include "display/intel_display.h" #include "display/intel_display_power.h" +#include "display/intel_display_reg.h" #include "display/intel_dpll_mgr.h" #include "display/intel_frontbuffer.h" #include "display/intel_opregion.h" @@ -1346,6 +1347,7 @@ struct drm_i915_private { resource_size_t stolen_usable_size; /* Total size minus reserved ranges */ struct intel_uncore uncore; + struct intel_uncore de_uncore; struct intel_uncore_mmio_debug mmio_debug; struct i915_virtual_gpu vgpu; @@ -2687,6 +2689,35 @@ int i915_reg_read_ioctl(struct drm_device *dev, void *data, #define I915_READ_FW(reg__) __I915_REG_OP(read_fw, dev_priv, (reg__)) #define I915_WRITE_FW(reg__, val__) __I915_REG_OP(write_fw, dev_priv, (reg__), (val__)) +/* + * The following are mmio-accessors that use an independent lock and skip all + * the forcewake logic, to be used to access display registers, which are + * outside the GT forcewake wells. + */ +static inline u32 +intel_de_read(struct drm_i915_private *i915, intel_de_reg_t reg) +{ + return intel_uncore_read(&i915->de_uncore, intel_de_reg_to_mmio(reg)); +} + +static inline void +intel_de_posting_read(struct drm_i915_private *i915, intel_de_reg_t reg) +{ + intel_uncore_posting_read(&i915->de_uncore, intel_de_reg_to_mmio(reg)); +} + +static inline void +intel_de_write(struct drm_i915_private *i915, intel_de_reg_t reg, u32 val) +{ + intel_uncore_write(&i915->de_uncore, intel_de_reg_to_mmio(reg), val); +} + +static inline void +intel_de_rmw(struct drm_i915_private *i915, intel_de_reg_t reg, u32 clear, u32 set) +{ + intel_uncore_rmw(&i915->de_uncore, intel_de_reg_to_mmio(reg), clear, set); +} + void i915_memcpy_init_early(struct drm_i915_private *dev_priv); bool i915_memcpy_from_wc(void *dst, const void *src, unsigned long len); diff --git a/drivers/gpu/drm/i915/intel_uncore.c b/drivers/gpu/drm/i915/intel_uncore.c index 9e583f13a9e4..fba5e2a63888 100644 --- a/drivers/gpu/drm/i915/intel_uncore.c +++ b/drivers/gpu/drm/i915/intel_uncore.c @@ -1702,6 +1702,12 @@ static int uncore_forcewake_init(struct intel_uncore *uncore) return 0; } +static bool +intel_uncore_is_display(const struct intel_uncore *uncore) +{ + return uncore == &uncore->i915->de_uncore; +} + int intel_uncore_init_mmio(struct intel_uncore *uncore) { struct drm_i915_private *i915 = uncore->i915; @@ -1711,7 +1717,8 @@ int intel_uncore_init_mmio(struct intel_uncore *uncore) if (ret) return ret; - if (INTEL_GEN(i915) > 5 && !intel_vgpu_active(i915)) + if (INTEL_GEN(i915) > 5 && !intel_vgpu_active(i915) && + !intel_uncore_is_display(uncore)) uncore->flags |= UNCORE_HAS_FORCEWAKE; if (!intel_uncore_has_forcewake(uncore)) { From patchwork Thu Aug 8 01:44:23 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Daniele Ceraolo Spurio X-Patchwork-Id: 11083071 Return-Path: Received: from mail.wl.linuxfoundation.org (pdx-wl-mail.web.codeaurora.org [172.30.200.125]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id B780F112C for ; Thu, 8 Aug 2019 01:44:49 +0000 (UTC) Received: from mail.wl.linuxfoundation.org (localhost [127.0.0.1]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id A490E28694 for ; Thu, 8 Aug 2019 01:44:49 +0000 (UTC) Received: by mail.wl.linuxfoundation.org (Postfix, from userid 486) id 991B628AE0; Thu, 8 Aug 2019 01:44:49 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on pdx-wl-mail.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-5.2 required=2.0 tests=BAYES_00,MAILING_LIST_MULTI, RCVD_IN_DNSWL_MED autolearn=ham version=3.3.1 Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher DHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.wl.linuxfoundation.org (Postfix) with ESMTPS id 10FEE28694 for ; Thu, 8 Aug 2019 01:44:49 +0000 (UTC) Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id 4466B6E784; Thu, 8 Aug 2019 01:44:48 +0000 (UTC) X-Original-To: intel-gfx@lists.freedesktop.org Delivered-To: intel-gfx@lists.freedesktop.org Received: from mga06.intel.com (mga06.intel.com [134.134.136.31]) by gabe.freedesktop.org (Postfix) with ESMTPS id 224FF6E784 for ; Thu, 8 Aug 2019 01:44:46 +0000 (UTC) X-Amp-Result: SKIPPED(no attachment in message) X-Amp-File-Uploaded: False Received: from orsmga007.jf.intel.com ([10.7.209.58]) by orsmga104.jf.intel.com with ESMTP/TLS/DHE-RSA-AES256-GCM-SHA384; 07 Aug 2019 18:44:46 -0700 X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.64,358,1559545200"; d="scan'208";a="165538127" Received: from dceraolo-linux.fm.intel.com ([10.1.27.145]) by orsmga007.jf.intel.com with ESMTP; 07 Aug 2019 18:44:45 -0700 From: Daniele Ceraolo Spurio To: intel-gfx@lists.freedesktop.org Date: Wed, 7 Aug 2019 18:44:23 -0700 Message-Id: <20190808014423.20377-4-daniele.ceraolospurio@intel.com> X-Mailer: git-send-email 2.22.0 In-Reply-To: <20190808014423.20377-1-daniele.ceraolospurio@intel.com> References: <20190808014423.20377-1-daniele.ceraolospurio@intel.com> MIME-Version: 1.0 Subject: [Intel-gfx] [RFC 3/3] drm/i915: convert a couple of registers to _DE_MMIO X-BeenThere: intel-gfx@lists.freedesktop.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: Intel graphics driver community testing & development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: intel-gfx-bounces@lists.freedesktop.org Sender: "Intel-gfx" X-Virus-Scanned: ClamAV using ClamSMTP As an example of usage of the new accessors Signed-off-by: Daniele Ceraolo Spurio --- .../gpu/drm/i915/display/intel_display_reg.h | 44 +++++++++++++++++++ drivers/gpu/drm/i915/display/intel_hdmi.c | 32 +++++++------- drivers/gpu/drm/i915/i915_reg.h | 44 ------------------- 3 files changed, 60 insertions(+), 60 deletions(-) diff --git a/drivers/gpu/drm/i915/display/intel_display_reg.h b/drivers/gpu/drm/i915/display/intel_display_reg.h index ac0c6975271d..2b61d4fd12e3 100644 --- a/drivers/gpu/drm/i915/display/intel_display_reg.h +++ b/drivers/gpu/drm/i915/display/intel_display_reg.h @@ -19,4 +19,48 @@ static inline i915_reg_t intel_de_reg_to_mmio(intel_de_reg_t reg) return reg.reg; } +/* Video Data Island Packet control */ +#define VIDEO_DIP_DATA _DE_MMIO(0x61178) +/* Read the description of VIDEO_DIP_DATA (before Haswell) or VIDEO_DIP_ECC + * (Haswell and newer) to see which VIDEO_DIP_DATA byte corresponds to each byte + * of the infoframe structure specified by CEA-861. */ +#define VIDEO_DIP_DATA_SIZE 32 +#define VIDEO_DIP_VSC_DATA_SIZE 36 +#define VIDEO_DIP_PPS_DATA_SIZE 132 +#define VIDEO_DIP_CTL _DE_MMIO(0x61170) +/* Pre HSW: */ +#define VIDEO_DIP_ENABLE (1 << 31) +#define VIDEO_DIP_PORT(port) ((port) << 29) +#define VIDEO_DIP_PORT_MASK (3 << 29) +#define VIDEO_DIP_ENABLE_GCP (1 << 25) /* ilk+ */ +#define VIDEO_DIP_ENABLE_AVI (1 << 21) +#define VIDEO_DIP_ENABLE_VENDOR (2 << 21) +#define VIDEO_DIP_ENABLE_GAMUT (4 << 21) /* ilk+ */ +#define VIDEO_DIP_ENABLE_SPD (8 << 21) +#define VIDEO_DIP_SELECT_AVI (0 << 19) +#define VIDEO_DIP_SELECT_VENDOR (1 << 19) +#define VIDEO_DIP_SELECT_GAMUT (2 << 19) +#define VIDEO_DIP_SELECT_SPD (3 << 19) +#define VIDEO_DIP_SELECT_MASK (3 << 19) +#define VIDEO_DIP_FREQ_ONCE (0 << 16) +#define VIDEO_DIP_FREQ_VSYNC (1 << 16) +#define VIDEO_DIP_FREQ_2VSYNC (2 << 16) +#define VIDEO_DIP_FREQ_MASK (3 << 16) +/* HSW and later: */ +#define VIDEO_DIP_ENABLE_DRM_GLK (1 << 28) +#define PSR_VSC_BIT_7_SET (1 << 27) +#define VSC_SELECT_MASK (0x3 << 25) +#define VSC_SELECT_SHIFT 25 +#define VSC_DIP_HW_HEA_DATA (0 << 25) +#define VSC_DIP_HW_HEA_SW_DATA (1 << 25) +#define VSC_DIP_HW_DATA_SW_HEA (2 << 25) +#define VSC_DIP_SW_HEA_DATA (3 << 25) +#define VDIP_ENABLE_PPS (1 << 24) +#define VIDEO_DIP_ENABLE_VSC_HSW (1 << 20) +#define VIDEO_DIP_ENABLE_GCP_HSW (1 << 16) +#define VIDEO_DIP_ENABLE_AVI_HSW (1 << 12) +#define VIDEO_DIP_ENABLE_VS_HSW (1 << 8) +#define VIDEO_DIP_ENABLE_GMP_HSW (1 << 4) +#define VIDEO_DIP_ENABLE_SPD_HSW (1 << 0) + #endif diff --git a/drivers/gpu/drm/i915/display/intel_hdmi.c b/drivers/gpu/drm/i915/display/intel_hdmi.c index b1ca8e5bdb56..64666d9dfb49 100644 --- a/drivers/gpu/drm/i915/display/intel_hdmi.c +++ b/drivers/gpu/drm/i915/display/intel_hdmi.c @@ -208,7 +208,7 @@ static void g4x_write_infoframe(struct intel_encoder *encoder, { const u32 *data = frame; struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); - u32 val = I915_READ(VIDEO_DIP_CTL); + u32 val = intel_de_read(dev_priv, VIDEO_DIP_CTL); int i; WARN(!(val & VIDEO_DIP_ENABLE), "Writing DIP with CTL reg disabled\n"); @@ -218,22 +218,22 @@ static void g4x_write_infoframe(struct intel_encoder *encoder, val &= ~g4x_infoframe_enable(type); - I915_WRITE(VIDEO_DIP_CTL, val); + intel_de_write(dev_priv, VIDEO_DIP_CTL, val); for (i = 0; i < len; i += 4) { - I915_WRITE(VIDEO_DIP_DATA, *data); + intel_de_write(dev_priv, VIDEO_DIP_DATA, *data); data++; } /* Write every possible data byte to force correct ECC calculation. */ for (; i < VIDEO_DIP_DATA_SIZE; i += 4) - I915_WRITE(VIDEO_DIP_DATA, 0); + intel_de_write(dev_priv, VIDEO_DIP_DATA, 0); val |= g4x_infoframe_enable(type); val &= ~VIDEO_DIP_FREQ_MASK; val |= VIDEO_DIP_FREQ_VSYNC; - I915_WRITE(VIDEO_DIP_CTL, val); - POSTING_READ(VIDEO_DIP_CTL); + intel_de_write(dev_priv, VIDEO_DIP_CTL, val); + intel_de_posting_read(dev_priv, VIDEO_DIP_CTL); } static void g4x_read_infoframe(struct intel_encoder *encoder, @@ -245,22 +245,22 @@ static void g4x_read_infoframe(struct intel_encoder *encoder, u32 val, *data = frame; int i; - val = I915_READ(VIDEO_DIP_CTL); + val = intel_de_read(dev_priv, VIDEO_DIP_CTL); val &= ~(VIDEO_DIP_SELECT_MASK | 0xf); /* clear DIP data offset */ val |= g4x_infoframe_index(type); - I915_WRITE(VIDEO_DIP_CTL, val); + intel_de_write(dev_priv, VIDEO_DIP_CTL, val); for (i = 0; i < len; i += 4) - *data++ = I915_READ(VIDEO_DIP_DATA); + *data++ = intel_de_read(dev_priv, VIDEO_DIP_DATA); } static u32 g4x_infoframes_enabled(struct intel_encoder *encoder, const struct intel_crtc_state *pipe_config) { struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); - u32 val = I915_READ(VIDEO_DIP_CTL); + u32 val = intel_de_read(dev_priv, VIDEO_DIP_CTL); if ((val & VIDEO_DIP_ENABLE) == 0) return 0; @@ -840,8 +840,8 @@ static void g4x_set_infoframes(struct intel_encoder *encoder, struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); struct intel_digital_port *intel_dig_port = enc_to_dig_port(&encoder->base); struct intel_hdmi *intel_hdmi = &intel_dig_port->hdmi; - i915_reg_t reg = VIDEO_DIP_CTL; - u32 val = I915_READ(reg); + intel_de_reg_t reg = VIDEO_DIP_CTL; + u32 val = intel_de_read(dev_priv, reg); u32 port = VIDEO_DIP_PORT(encoder->port); assert_hdmi_port_disabled(intel_hdmi); @@ -867,8 +867,8 @@ static void g4x_set_infoframes(struct intel_encoder *encoder, } val &= ~(VIDEO_DIP_ENABLE | VIDEO_DIP_ENABLE_AVI | VIDEO_DIP_ENABLE_VENDOR | VIDEO_DIP_ENABLE_SPD); - I915_WRITE(reg, val); - POSTING_READ(reg); + intel_de_write(dev_priv, reg, val); + intel_de_posting_read(dev_priv, reg); return; } @@ -886,8 +886,8 @@ static void g4x_set_infoframes(struct intel_encoder *encoder, val &= ~(VIDEO_DIP_ENABLE_AVI | VIDEO_DIP_ENABLE_VENDOR | VIDEO_DIP_ENABLE_SPD); - I915_WRITE(reg, val); - POSTING_READ(reg); + intel_de_write(dev_priv, reg, val); + intel_de_posting_read(dev_priv, reg); intel_write_infoframe(encoder, crtc_state, HDMI_INFOFRAME_TYPE_AVI, diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h index d760830cfd7b..66f9a4e9c869 100644 --- a/drivers/gpu/drm/i915/i915_reg.h +++ b/drivers/gpu/drm/i915/i915_reg.h @@ -4703,50 +4703,6 @@ enum { #define LVDS_B0B3_POWER_DOWN (0 << 2) #define LVDS_B0B3_POWER_UP (3 << 2) -/* Video Data Island Packet control */ -#define VIDEO_DIP_DATA _MMIO(0x61178) -/* Read the description of VIDEO_DIP_DATA (before Haswell) or VIDEO_DIP_ECC - * (Haswell and newer) to see which VIDEO_DIP_DATA byte corresponds to each byte - * of the infoframe structure specified by CEA-861. */ -#define VIDEO_DIP_DATA_SIZE 32 -#define VIDEO_DIP_VSC_DATA_SIZE 36 -#define VIDEO_DIP_PPS_DATA_SIZE 132 -#define VIDEO_DIP_CTL _MMIO(0x61170) -/* Pre HSW: */ -#define VIDEO_DIP_ENABLE (1 << 31) -#define VIDEO_DIP_PORT(port) ((port) << 29) -#define VIDEO_DIP_PORT_MASK (3 << 29) -#define VIDEO_DIP_ENABLE_GCP (1 << 25) /* ilk+ */ -#define VIDEO_DIP_ENABLE_AVI (1 << 21) -#define VIDEO_DIP_ENABLE_VENDOR (2 << 21) -#define VIDEO_DIP_ENABLE_GAMUT (4 << 21) /* ilk+ */ -#define VIDEO_DIP_ENABLE_SPD (8 << 21) -#define VIDEO_DIP_SELECT_AVI (0 << 19) -#define VIDEO_DIP_SELECT_VENDOR (1 << 19) -#define VIDEO_DIP_SELECT_GAMUT (2 << 19) -#define VIDEO_DIP_SELECT_SPD (3 << 19) -#define VIDEO_DIP_SELECT_MASK (3 << 19) -#define VIDEO_DIP_FREQ_ONCE (0 << 16) -#define VIDEO_DIP_FREQ_VSYNC (1 << 16) -#define VIDEO_DIP_FREQ_2VSYNC (2 << 16) -#define VIDEO_DIP_FREQ_MASK (3 << 16) -/* HSW and later: */ -#define VIDEO_DIP_ENABLE_DRM_GLK (1 << 28) -#define PSR_VSC_BIT_7_SET (1 << 27) -#define VSC_SELECT_MASK (0x3 << 25) -#define VSC_SELECT_SHIFT 25 -#define VSC_DIP_HW_HEA_DATA (0 << 25) -#define VSC_DIP_HW_HEA_SW_DATA (1 << 25) -#define VSC_DIP_HW_DATA_SW_HEA (2 << 25) -#define VSC_DIP_SW_HEA_DATA (3 << 25) -#define VDIP_ENABLE_PPS (1 << 24) -#define VIDEO_DIP_ENABLE_VSC_HSW (1 << 20) -#define VIDEO_DIP_ENABLE_GCP_HSW (1 << 16) -#define VIDEO_DIP_ENABLE_AVI_HSW (1 << 12) -#define VIDEO_DIP_ENABLE_VS_HSW (1 << 8) -#define VIDEO_DIP_ENABLE_GMP_HSW (1 << 4) -#define VIDEO_DIP_ENABLE_SPD_HSW (1 << 0) - /* Panel power sequencing */ #define PPS_BASE 0x61200 #define VLV_PPS_BASE (VLV_DISPLAY_BASE + PPS_BASE)