From patchwork Fri Aug 16 02:35:23 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "Zhang, Tina" X-Patchwork-Id: 11096705 Return-Path: Received: from mail.wl.linuxfoundation.org (pdx-wl-mail.web.codeaurora.org [172.30.200.125]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id EA1BB112C for ; Fri, 16 Aug 2019 02:36:34 +0000 (UTC) Received: from mail.wl.linuxfoundation.org (localhost [127.0.0.1]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id D9378289CD for ; Fri, 16 Aug 2019 02:36:34 +0000 (UTC) Received: by mail.wl.linuxfoundation.org (Postfix, from userid 486) id CB31E289D0; Fri, 16 Aug 2019 02:36:34 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on pdx-wl-mail.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-7.9 required=2.0 tests=BAYES_00,MAILING_LIST_MULTI, RCVD_IN_DNSWL_HI autolearn=ham version=3.3.1 Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id 7C2F0289CD for ; Fri, 16 Aug 2019 02:36:34 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1726880AbfHPCga (ORCPT ); Thu, 15 Aug 2019 22:36:30 -0400 Received: from mga07.intel.com ([134.134.136.100]:39512 "EHLO mga07.intel.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1726427AbfHPCgB (ORCPT ); Thu, 15 Aug 2019 22:36:01 -0400 X-Amp-Result: SKIPPED(no attachment in message) X-Amp-File-Uploaded: False Received: from fmsmga001.fm.intel.com ([10.253.24.23]) by orsmga105.jf.intel.com with ESMTP/TLS/DHE-RSA-AES256-GCM-SHA384; 15 Aug 2019 19:35:46 -0700 X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.64,391,1559545200"; d="scan'208";a="194894834" Received: from gvt.bj.intel.com ([10.238.158.180]) by fmsmga001.fm.intel.com with ESMTP; 15 Aug 2019 19:35:45 -0700 From: Tina Zhang To: intel-gvt-dev@lists.freedesktop.org Cc: Tina Zhang , kraxel@redhat.com, alex.williamson@redhat.com, kvm@vger.kernel.org, linux-kernel@vger.kernel.org, hang.yuan@intel.com, zhiyuan.lv@intel.com, Eric Auger Subject: [PATCH v5 1/6] vfio: Define device specific irq type capability Date: Fri, 16 Aug 2019 10:35:23 +0800 Message-Id: <20190816023528.30210-2-tina.zhang@intel.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20190816023528.30210-1-tina.zhang@intel.com> References: <20190816023528.30210-1-tina.zhang@intel.com> Sender: kvm-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: kvm@vger.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP Cap the number of irqs with fixed indexes and use capability chains to chain device specific irqs. Signed-off-by: Tina Zhang Signed-off-by: Eric Auger --- include/uapi/linux/vfio.h | 19 ++++++++++++++++++- 1 file changed, 18 insertions(+), 1 deletion(-) diff --git a/include/uapi/linux/vfio.h b/include/uapi/linux/vfio.h index 02bb7ad6e986..d83c9f136a5b 100644 --- a/include/uapi/linux/vfio.h +++ b/include/uapi/linux/vfio.h @@ -444,11 +444,27 @@ struct vfio_irq_info { #define VFIO_IRQ_INFO_MASKABLE (1 << 1) #define VFIO_IRQ_INFO_AUTOMASKED (1 << 2) #define VFIO_IRQ_INFO_NORESIZE (1 << 3) +#define VFIO_IRQ_INFO_FLAG_CAPS (1 << 4) /* Info supports caps */ __u32 index; /* IRQ index */ __u32 count; /* Number of IRQs within this index */ + __u32 cap_offset; /* Offset within info struct of first cap */ }; #define VFIO_DEVICE_GET_IRQ_INFO _IO(VFIO_TYPE, VFIO_BASE + 9) +/* + * The irq type capability allows irqs unique to a specific device or + * class of devices to be exposed. + * + * The structures below define version 1 of this capability. + */ +#define VFIO_IRQ_INFO_CAP_TYPE 3 + +struct vfio_irq_info_cap_type { + struct vfio_info_cap_header header; + __u32 type; /* global per bus driver */ + __u32 subtype; /* type specific */ +}; + /** * VFIO_DEVICE_SET_IRQS - _IOW(VFIO_TYPE, VFIO_BASE + 10, struct vfio_irq_set) * @@ -550,7 +566,8 @@ enum { VFIO_PCI_MSIX_IRQ_INDEX, VFIO_PCI_ERR_IRQ_INDEX, VFIO_PCI_REQ_IRQ_INDEX, - VFIO_PCI_NUM_IRQS + VFIO_PCI_NUM_IRQS = 5 /* Fixed user ABI, IRQ indexes >=5 use */ + /* device specific cap to define content */ }; /* From patchwork Fri Aug 16 02:35:24 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "Zhang, Tina" X-Patchwork-Id: 11096695 Return-Path: Received: from mail.wl.linuxfoundation.org (pdx-wl-mail.web.codeaurora.org [172.30.200.125]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id 7DEA6112C for ; Fri, 16 Aug 2019 02:36:07 +0000 (UTC) Received: from mail.wl.linuxfoundation.org (localhost [127.0.0.1]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id 655CB289BA for ; Fri, 16 Aug 2019 02:36:07 +0000 (UTC) Received: by mail.wl.linuxfoundation.org (Postfix, from userid 486) id 535BC289CF; Fri, 16 Aug 2019 02:36:07 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on pdx-wl-mail.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-7.9 required=2.0 tests=BAYES_00,MAILING_LIST_MULTI, RCVD_IN_DNSWL_HI autolearn=ham version=3.3.1 Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id 2B117289BA for ; Fri, 16 Aug 2019 02:36:05 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1726668AbfHPCgE (ORCPT ); Thu, 15 Aug 2019 22:36:04 -0400 Received: from mga07.intel.com ([134.134.136.100]:39512 "EHLO mga07.intel.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1726414AbfHPCgC (ORCPT ); Thu, 15 Aug 2019 22:36:02 -0400 X-Amp-Result: SKIPPED(no attachment in message) X-Amp-File-Uploaded: False Received: from fmsmga001.fm.intel.com ([10.253.24.23]) by orsmga105.jf.intel.com with ESMTP/TLS/DHE-RSA-AES256-GCM-SHA384; 15 Aug 2019 19:35:48 -0700 X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.64,391,1559545200"; d="scan'208";a="194894840" Received: from gvt.bj.intel.com ([10.238.158.180]) by fmsmga001.fm.intel.com with ESMTP; 15 Aug 2019 19:35:47 -0700 From: Tina Zhang To: intel-gvt-dev@lists.freedesktop.org Cc: Tina Zhang , kraxel@redhat.com, alex.williamson@redhat.com, kvm@vger.kernel.org, linux-kernel@vger.kernel.org, hang.yuan@intel.com, zhiyuan.lv@intel.com Subject: [PATCH v5 2/6] vfio: Introduce vGPU display irq type Date: Fri, 16 Aug 2019 10:35:24 +0800 Message-Id: <20190816023528.30210-3-tina.zhang@intel.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20190816023528.30210-1-tina.zhang@intel.com> References: <20190816023528.30210-1-tina.zhang@intel.com> Sender: kvm-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: kvm@vger.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP Introduce vGPU specific irq type VFIO_IRQ_TYPE_GFX, and VFIO_IRQ_SUBTYPE_GFX_DISPLAY_IRQ as the subtype for vGPU display. Introduce vfio_irq_info_cap_display_plane_events capability to notify user space with the vGPU's plane update events v2: - Add VFIO_IRQ_SUBTYPE_GFX_DISPLAY_IRQ description. (Alex & Kechen) - Introduce vfio_irq_info_cap_display_plane_events. (Gerd & Alex) Signed-off-by: Tina Zhang --- include/uapi/linux/vfio.h | 21 +++++++++++++++++++++ 1 file changed, 21 insertions(+) diff --git a/include/uapi/linux/vfio.h b/include/uapi/linux/vfio.h index d83c9f136a5b..21ac69f0e1a9 100644 --- a/include/uapi/linux/vfio.h +++ b/include/uapi/linux/vfio.h @@ -465,6 +465,27 @@ struct vfio_irq_info_cap_type { __u32 subtype; /* type specific */ }; +#define VFIO_IRQ_TYPE_GFX (1) +/* + * vGPU vendor sub-type + * vGPU device display related interrupts e.g. vblank/pageflip + */ +#define VFIO_IRQ_SUBTYPE_GFX_DISPLAY_IRQ (1) + +/* + * Display capability of using one eventfd to notify user space with the + * vGPU's plane update events. + * cur_event_val: eventfd value stands for cursor plane change event. + * pri_event_val: eventfd value stands for primary plane change event. + */ +#define VFIO_IRQ_INFO_CAP_DISPLAY 4 + +struct vfio_irq_info_cap_display_plane_events { + struct vfio_info_cap_header header; + __u64 cur_event_val; + __u64 pri_event_val; +}; + /** * VFIO_DEVICE_SET_IRQS - _IOW(VFIO_TYPE, VFIO_BASE + 10, struct vfio_irq_set) * From patchwork Fri Aug 16 02:35:25 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "Zhang, Tina" X-Patchwork-Id: 11096701 Return-Path: Received: from mail.wl.linuxfoundation.org (pdx-wl-mail.web.codeaurora.org [172.30.200.125]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id 2487E14DB for ; Fri, 16 Aug 2019 02:36:28 +0000 (UTC) Received: from mail.wl.linuxfoundation.org (localhost [127.0.0.1]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id 13E62289CD for ; Fri, 16 Aug 2019 02:36:28 +0000 (UTC) Received: by mail.wl.linuxfoundation.org (Postfix, from userid 486) id 04E54289D0; Fri, 16 Aug 2019 02:36:28 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on pdx-wl-mail.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-7.9 required=2.0 tests=BAYES_00,MAILING_LIST_MULTI, RCVD_IN_DNSWL_HI autolearn=ham version=3.3.1 Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id 3DFAC289CD for ; Fri, 16 Aug 2019 02:36:27 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1726801AbfHPCgT (ORCPT ); Thu, 15 Aug 2019 22:36:19 -0400 Received: from mga07.intel.com ([134.134.136.100]:39512 "EHLO mga07.intel.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1726619AbfHPCgD (ORCPT ); Thu, 15 Aug 2019 22:36:03 -0400 X-Amp-Result: SKIPPED(no attachment in message) X-Amp-File-Uploaded: False Received: from fmsmga001.fm.intel.com ([10.253.24.23]) by orsmga105.jf.intel.com with ESMTP/TLS/DHE-RSA-AES256-GCM-SHA384; 15 Aug 2019 19:35:50 -0700 X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.64,391,1559545200"; d="scan'208";a="194894847" Received: from gvt.bj.intel.com ([10.238.158.180]) by fmsmga001.fm.intel.com with ESMTP; 15 Aug 2019 19:35:48 -0700 From: Tina Zhang To: intel-gvt-dev@lists.freedesktop.org Cc: Tina Zhang , kraxel@redhat.com, alex.williamson@redhat.com, kvm@vger.kernel.org, linux-kernel@vger.kernel.org, hang.yuan@intel.com, zhiyuan.lv@intel.com Subject: [PATCH v5 3/6] drm/i915/gvt: Register vGPU display event irq Date: Fri, 16 Aug 2019 10:35:25 +0800 Message-Id: <20190816023528.30210-4-tina.zhang@intel.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20190816023528.30210-1-tina.zhang@intel.com> References: <20190816023528.30210-1-tina.zhang@intel.com> Sender: kvm-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: kvm@vger.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP Gvt-g emulates and injects the vGPU's display interrupts in kernel space. However the dma-buf based framebuffer consumer in the user land (e.g. Qemu vfio/display) may also need to be notified by this event. Register the display irq as VFIO_IRQ_SUBTYPE_GFX_DISPLAY_IRQ to each vGPU, so that the display interrupt event can be delivered to userspace through eventfd. Signed-off-by: Tina Zhang --- drivers/gpu/drm/i915/gvt/display.c | 10 +++- drivers/gpu/drm/i915/gvt/display.h | 3 ++ drivers/gpu/drm/i915/gvt/gvt.h | 2 + drivers/gpu/drm/i915/gvt/hypercall.h | 1 + drivers/gpu/drm/i915/gvt/kvmgt.c | 71 ++++++++++++++++++++++++++++ drivers/gpu/drm/i915/gvt/mpt.h | 17 +++++++ 6 files changed, 102 insertions(+), 2 deletions(-) diff --git a/drivers/gpu/drm/i915/gvt/display.c b/drivers/gpu/drm/i915/gvt/display.c index e1c313da6c00..1a0a4ae4826e 100644 --- a/drivers/gpu/drm/i915/gvt/display.c +++ b/drivers/gpu/drm/i915/gvt/display.c @@ -506,16 +506,22 @@ void intel_vgpu_clean_display(struct intel_vgpu *vgpu) int intel_vgpu_init_display(struct intel_vgpu *vgpu, u64 resolution) { struct drm_i915_private *dev_priv = vgpu->gvt->dev_priv; + int ret; intel_vgpu_init_i2c_edid(vgpu); if (IS_SKYLAKE(dev_priv) || IS_KABYLAKE(dev_priv) || IS_COFFEELAKE(dev_priv)) - return setup_virtual_dp_monitor(vgpu, PORT_D, GVT_DP_D, + ret = setup_virtual_dp_monitor(vgpu, PORT_D, GVT_DP_D, resolution); else - return setup_virtual_dp_monitor(vgpu, PORT_B, GVT_DP_B, + ret = setup_virtual_dp_monitor(vgpu, PORT_B, GVT_DP_B, resolution); + + if (ret == 0) + intel_gvt_hypervisor_register_display_irq(vgpu); + + return ret; } /** diff --git a/drivers/gpu/drm/i915/gvt/display.h b/drivers/gpu/drm/i915/gvt/display.h index a87f33e6a23c..ba07fbef9194 100644 --- a/drivers/gpu/drm/i915/gvt/display.h +++ b/drivers/gpu/drm/i915/gvt/display.h @@ -112,6 +112,9 @@ #define SBI_ADDR_OFFSET_SHIFT 16 #define SBI_ADDR_OFFSET_MASK (0xffff << SBI_ADDR_OFFSET_SHIFT) +#define DISPLAY_PRI_REFRESH_EVENT_VAL (1UL << 56) +#define DISPLAY_CUR_REFRESH_EVENT_VAL (1UL << 48) + struct intel_vgpu_sbi_register { unsigned int offset; u32 value; diff --git a/drivers/gpu/drm/i915/gvt/gvt.h b/drivers/gpu/drm/i915/gvt/gvt.h index f5a328b5290a..cd29ea28d7ed 100644 --- a/drivers/gpu/drm/i915/gvt/gvt.h +++ b/drivers/gpu/drm/i915/gvt/gvt.h @@ -201,6 +201,8 @@ struct intel_vgpu { struct mdev_device *mdev; struct vfio_region *region; int num_regions; + struct vfio_irq *irq; + int num_irqs; struct eventfd_ctx *intx_trigger; struct eventfd_ctx *msi_trigger; diff --git a/drivers/gpu/drm/i915/gvt/hypercall.h b/drivers/gpu/drm/i915/gvt/hypercall.h index 4862fb12778e..be33f20f3bc1 100644 --- a/drivers/gpu/drm/i915/gvt/hypercall.h +++ b/drivers/gpu/drm/i915/gvt/hypercall.h @@ -68,6 +68,7 @@ struct intel_gvt_mpt { bool map); int (*set_opregion)(void *vgpu); int (*set_edid)(void *vgpu, int port_num); + int (*register_display_irq)(void *vgpu); int (*get_vfio_device)(void *vgpu); void (*put_vfio_device)(void *vgpu); bool (*is_valid_gfn)(unsigned long handle, unsigned long gfn); diff --git a/drivers/gpu/drm/i915/gvt/kvmgt.c b/drivers/gpu/drm/i915/gvt/kvmgt.c index a68addf95c23..fd1633342e53 100644 --- a/drivers/gpu/drm/i915/gvt/kvmgt.c +++ b/drivers/gpu/drm/i915/gvt/kvmgt.c @@ -78,6 +78,19 @@ struct vfio_region { void *data; }; +struct intel_vgpu_irqops { + int (*add_capability)(struct intel_vgpu *vgpu, + struct vfio_info_cap *caps); +}; + +struct vfio_irq { + u32 type; + u32 subtype; + u32 flags; + u32 count; + const struct intel_vgpu_irqops *ops; +}; + struct vfio_edid_region { struct vfio_region_gfx_edid vfio_edid_regs; void *edid_blob; @@ -635,6 +648,59 @@ static int kvmgt_set_edid(void *p_vgpu, int port_num) return ret; } +static int add_display_irq_capability(struct intel_vgpu *vgpu, + struct vfio_info_cap *caps) +{ + struct vfio_irq_info_cap_display_plane_events cap = { + .header.id = VFIO_IRQ_INFO_CAP_DISPLAY, + .header.version = 1, + .cur_event_val = DISPLAY_CUR_REFRESH_EVENT_VAL, + .pri_event_val = DISPLAY_PRI_REFRESH_EVENT_VAL, + }; + + return vfio_info_add_capability(caps, &cap.header, sizeof(cap)); +} + + +static const struct intel_vgpu_irqops intel_vgpu_irqops_display = { + .add_capability = add_display_irq_capability, +}; + +static int intel_vgpu_register_irq(struct intel_vgpu *vgpu, + unsigned int type, unsigned int subtype, + u32 count, u32 flags, + const struct intel_vgpu_irqops *ops) +{ + struct vfio_irq *irq; + + irq = krealloc(vgpu->vdev.irq, + (vgpu->vdev.num_irqs + 1) * sizeof(*irq), + GFP_KERNEL); + if (!irq) + return -ENOMEM; + + vgpu->vdev.irq = irq; + vgpu->vdev.irq[vgpu->vdev.num_irqs].type = type; + vgpu->vdev.irq[vgpu->vdev.num_irqs].subtype = subtype; + vgpu->vdev.irq[vgpu->vdev.num_irqs].count = count; + vgpu->vdev.irq[vgpu->vdev.num_irqs].flags = flags; + vgpu->vdev.irq[vgpu->vdev.num_irqs].ops = ops; + vgpu->vdev.num_irqs++; + return 0; +} + +static int kvmgt_register_display_irq(void *p_vgpu) +{ + struct intel_vgpu *vgpu = (struct intel_vgpu *)p_vgpu; + + intel_vgpu_register_irq(vgpu, VFIO_IRQ_TYPE_GFX, + VFIO_IRQ_SUBTYPE_GFX_DISPLAY_IRQ, + 1, + VFIO_IRQ_INFO_MASKABLE | VFIO_IRQ_INFO_EVENTFD, + &intel_vgpu_irqops_display); + return 0; +} + static void kvmgt_put_vfio_device(void *vgpu) { if (WARN_ON(!((struct intel_vgpu *)vgpu)->vdev.vfio_device)) @@ -1838,6 +1904,10 @@ static void kvmgt_detach_vgpu(void *p_vgpu) vgpu->vdev.num_regions = 0; kfree(vgpu->vdev.region); vgpu->vdev.region = NULL; + + vgpu->vdev.num_irqs = 0; + kfree(vgpu->vdev.irq); + vgpu->vdev.irq = NULL; } static int kvmgt_inject_msi(unsigned long handle, u32 addr, u16 data) @@ -2039,6 +2109,7 @@ static struct intel_gvt_mpt kvmgt_mpt = { .dma_unmap_guest_page = kvmgt_dma_unmap_guest_page, .set_opregion = kvmgt_set_opregion, .set_edid = kvmgt_set_edid, + .register_display_irq = kvmgt_register_display_irq, .get_vfio_device = kvmgt_get_vfio_device, .put_vfio_device = kvmgt_put_vfio_device, .is_valid_gfn = kvmgt_is_valid_gfn, diff --git a/drivers/gpu/drm/i915/gvt/mpt.h b/drivers/gpu/drm/i915/gvt/mpt.h index 0f9440128123..abf4a69920d3 100644 --- a/drivers/gpu/drm/i915/gvt/mpt.h +++ b/drivers/gpu/drm/i915/gvt/mpt.h @@ -330,6 +330,23 @@ static inline int intel_gvt_hypervisor_set_edid(struct intel_vgpu *vgpu, return intel_gvt_host.mpt->set_edid(vgpu, port_num); } +/** + * intel_gvt_hypervisor_set_irq - register vgpu specific irq + * @vgpu: a vGPU + * @port_num: display port number + * + * Returns: + * Zero on success, negative error code if failed. + */ +static inline int intel_gvt_hypervisor_register_display_irq( + struct intel_vgpu *vgpu) +{ + if (!intel_gvt_host.mpt->register_display_irq) + return 0; + + return intel_gvt_host.mpt->register_display_irq(vgpu); +} + /** * intel_gvt_hypervisor_get_vfio_device - increase vfio device ref count * @vgpu: a vGPU From patchwork Fri Aug 16 02:35:26 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "Zhang, Tina" X-Patchwork-Id: 11096703 Return-Path: Received: from mail.wl.linuxfoundation.org (pdx-wl-mail.web.codeaurora.org [172.30.200.125]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id AA28614DB for ; Fri, 16 Aug 2019 02:36:29 +0000 (UTC) Received: from mail.wl.linuxfoundation.org (localhost [127.0.0.1]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id 9A4B1289CD for ; Fri, 16 Aug 2019 02:36:29 +0000 (UTC) Received: by mail.wl.linuxfoundation.org (Postfix, from userid 486) id 8E5FE289D0; Fri, 16 Aug 2019 02:36:29 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on pdx-wl-mail.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-7.9 required=2.0 tests=BAYES_00,MAILING_LIST_MULTI, RCVD_IN_DNSWL_HI autolearn=ham version=3.3.1 Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id BCA84289CD for ; Fri, 16 Aug 2019 02:36:28 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1726781AbfHPCgT (ORCPT ); Thu, 15 Aug 2019 22:36:19 -0400 Received: from mga07.intel.com ([134.134.136.100]:39514 "EHLO mga07.intel.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1726622AbfHPCgD (ORCPT ); Thu, 15 Aug 2019 22:36:03 -0400 X-Amp-Result: SKIPPED(no attachment in message) X-Amp-File-Uploaded: False Received: from fmsmga001.fm.intel.com ([10.253.24.23]) by orsmga105.jf.intel.com with ESMTP/TLS/DHE-RSA-AES256-GCM-SHA384; 15 Aug 2019 19:35:52 -0700 X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.64,391,1559545200"; d="scan'208";a="194894854" Received: from gvt.bj.intel.com ([10.238.158.180]) by fmsmga001.fm.intel.com with ESMTP; 15 Aug 2019 19:35:50 -0700 From: Tina Zhang To: intel-gvt-dev@lists.freedesktop.org Cc: Tina Zhang , kraxel@redhat.com, alex.williamson@redhat.com, kvm@vger.kernel.org, linux-kernel@vger.kernel.org, hang.yuan@intel.com, zhiyuan.lv@intel.com, Kechen Lu Subject: [PATCH v5 4/6] drm/i915/gvt: Deliver vGPU refresh event to userspace Date: Fri, 16 Aug 2019 10:35:26 +0800 Message-Id: <20190816023528.30210-5-tina.zhang@intel.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20190816023528.30210-1-tina.zhang@intel.com> References: <20190816023528.30210-1-tina.zhang@intel.com> Sender: kvm-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: kvm@vger.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP Deliver the display refresh events to the user land. Userspace can use the irq mask/unmask mechanism to disable or enable the event delivery. As we know, delivering refresh event at each vblank safely avoids tearing and unexpected event overwhelming, but there are still spaces to optimize. For handling the normal case, deliver the page flip refresh event at each vblank, in other words, bounded by vblanks. Skipping some events bring performance enhancement while not hurting user experience. For single framebuffer case, deliver the refresh events to userspace at all vblanks. This heuristic at each vblank leverages pageflip_count incresements to determine if there is no page flip happens after a certain period and so that the case is regarded as single framebuffer one. Although this heuristic makes incorrect decision sometimes and it depends on guest behavior, for example, when no cursor movements happen, the user experience does not harm and front buffer is still correctly acquired. Meanwhile, in actual single framebuffer case, the user experience is enhanced compared with page flip events only. Addtionally, to mitigate the events delivering footprints, one eventfd and 8 byte eventfd counter partition are leveraged. v2: - Support vfio_irq_info_cap_display_plane_events. (Tina) Signed-off-by: Tina Zhang Signed-off-by: Kechen Lu --- drivers/gpu/drm/i915/gvt/display.c | 22 ++++ drivers/gpu/drm/i915/gvt/gvt.h | 2 + drivers/gpu/drm/i915/gvt/kvmgt.c | 159 +++++++++++++++++++++++++++-- 3 files changed, 174 insertions(+), 9 deletions(-) diff --git a/drivers/gpu/drm/i915/gvt/display.c b/drivers/gpu/drm/i915/gvt/display.c index 1a0a4ae4826e..616285e4a014 100644 --- a/drivers/gpu/drm/i915/gvt/display.c +++ b/drivers/gpu/drm/i915/gvt/display.c @@ -34,6 +34,8 @@ #include "i915_drv.h" #include "gvt.h" +#include +#include static int get_edp_pipe(struct intel_vgpu *vgpu) { @@ -387,6 +389,8 @@ void intel_gvt_check_vblank_emulation(struct intel_gvt *gvt) mutex_unlock(&gvt->lock); } +#define PAGEFLIP_DELAY_THR 10 + static void emulate_vblank_on_pipe(struct intel_vgpu *vgpu, int pipe) { struct drm_i915_private *dev_priv = vgpu->gvt->dev_priv; @@ -396,7 +400,10 @@ static void emulate_vblank_on_pipe(struct intel_vgpu *vgpu, int pipe) [PIPE_B] = PIPE_B_VBLANK, [PIPE_C] = PIPE_C_VBLANK, }; + int pri_flip_event = SKL_FLIP_EVENT(pipe, PLANE_PRIMARY); int event; + u64 eventfd_signal_val = 0; + static int no_pageflip_count; if (pipe < PIPE_A || pipe > PIPE_C) return; @@ -407,11 +414,26 @@ static void emulate_vblank_on_pipe(struct intel_vgpu *vgpu, int pipe) if (!pipe_is_enabled(vgpu, pipe)) continue; + if (event == pri_flip_event) + eventfd_signal_val |= DISPLAY_PRI_REFRESH_EVENT_VAL; + intel_vgpu_trigger_virtual_event(vgpu, event); } + if (eventfd_signal_val) + no_pageflip_count = 0; + else if (!eventfd_signal_val && no_pageflip_count > PAGEFLIP_DELAY_THR) + eventfd_signal_val |= DISPLAY_PRI_REFRESH_EVENT_VAL; + else + no_pageflip_count++; + + if (vgpu->vdev.vblank_trigger && !vgpu->vdev.display_event_mask && + eventfd_signal_val) + eventfd_signal(vgpu->vdev.vblank_trigger, eventfd_signal_val); + if (pipe_is_enabled(vgpu, pipe)) { vgpu_vreg_t(vgpu, PIPE_FRMCOUNT_G4X(pipe))++; + intel_vgpu_trigger_virtual_event(vgpu, vblank_event[pipe]); } } diff --git a/drivers/gpu/drm/i915/gvt/gvt.h b/drivers/gpu/drm/i915/gvt/gvt.h index cd29ea28d7ed..6c8ed030c30b 100644 --- a/drivers/gpu/drm/i915/gvt/gvt.h +++ b/drivers/gpu/drm/i915/gvt/gvt.h @@ -205,6 +205,8 @@ struct intel_vgpu { int num_irqs; struct eventfd_ctx *intx_trigger; struct eventfd_ctx *msi_trigger; + struct eventfd_ctx *vblank_trigger; + u32 display_event_mask; /* * Two caches are used to avoid mapping duplicated pages (eg. diff --git a/drivers/gpu/drm/i915/gvt/kvmgt.c b/drivers/gpu/drm/i915/gvt/kvmgt.c index fd1633342e53..9ace1f4ff9eb 100644 --- a/drivers/gpu/drm/i915/gvt/kvmgt.c +++ b/drivers/gpu/drm/i915/gvt/kvmgt.c @@ -1250,6 +1250,8 @@ static int intel_vgpu_get_irq_count(struct intel_vgpu *vgpu, int type) { if (type == VFIO_PCI_INTX_IRQ_INDEX || type == VFIO_PCI_MSI_IRQ_INDEX) return 1; + else if (type < VFIO_PCI_NUM_IRQS + vgpu->vdev.num_irqs) + return vgpu->vdev.irq[type - VFIO_PCI_NUM_IRQS].count; return 0; } @@ -1297,7 +1299,60 @@ static int intel_vgpu_set_msi_trigger(struct intel_vgpu *vgpu, return 0; } -static int intel_vgpu_set_irqs(struct intel_vgpu *vgpu, u32 flags, +static int intel_vgu_set_display_irq_mask(struct intel_vgpu *vgpu, + unsigned int index, unsigned int start, unsigned int count, + u32 flags, void *data) +{ + if (start != 0 || count > 2) + return -EINVAL; + + if (flags & VFIO_IRQ_SET_DATA_NONE) + vgpu->vdev.display_event_mask |= 1; + + return 0; +} + +static int intel_vgu_set_display_irq_unmask(struct intel_vgpu *vgpu, + unsigned int index, unsigned int start, unsigned int count, + u32 flags, void *data) +{ + if (start != 0 || count > 2) + return -EINVAL; + + if (flags & VFIO_IRQ_SET_DATA_NONE) + vgpu->vdev.display_event_mask &= 0; + + return 0; +} + +static int intel_vgpu_set_display_event_trigger(struct intel_vgpu *vgpu, + unsigned int index, unsigned int start, unsigned int count, + u32 flags, void *data) +{ + struct eventfd_ctx *trigger; + + if (flags & VFIO_IRQ_SET_DATA_EVENTFD) { + int fd = *(int *)data; + + trigger = eventfd_ctx_fdget(fd); + if (IS_ERR(trigger)) { + gvt_vgpu_err("eventfd_ctx_fdget failed\n"); + return PTR_ERR(trigger); + } + vgpu->vdev.vblank_trigger = trigger; + vgpu->vdev.display_event_mask = 0; + } else if ((flags & VFIO_IRQ_SET_DATA_NONE) && !count) { + trigger = vgpu->vdev.vblank_trigger; + if (trigger) { + eventfd_ctx_put(trigger); + vgpu->vdev.vblank_trigger = NULL; + } + } + + return 0; +} + +int intel_vgpu_set_irqs(struct intel_vgpu *vgpu, u32 flags, unsigned int index, unsigned int start, unsigned int count, void *data) { @@ -1330,6 +1385,35 @@ static int intel_vgpu_set_irqs(struct intel_vgpu *vgpu, u32 flags, break; } break; + default: + { + int i; + + if (index >= VFIO_PCI_NUM_IRQS + + vgpu->vdev.num_irqs) + return -EINVAL; + index = + array_index_nospec(index, + VFIO_PCI_NUM_IRQS + + vgpu->vdev.num_irqs); + + i = index - VFIO_PCI_NUM_IRQS; + if (vgpu->vdev.irq[i].type == VFIO_IRQ_TYPE_GFX && + vgpu->vdev.irq[i].subtype == + VFIO_IRQ_SUBTYPE_GFX_DISPLAY_IRQ) { + switch (flags & VFIO_IRQ_SET_ACTION_TYPE_MASK) { + case VFIO_IRQ_SET_ACTION_MASK: + func = intel_vgu_set_display_irq_mask; + break; + case VFIO_IRQ_SET_ACTION_UNMASK: + func = intel_vgu_set_display_irq_unmask; + break; + case VFIO_IRQ_SET_ACTION_TRIGGER: + func = intel_vgpu_set_display_event_trigger; + break; + } + } + } } if (!func) @@ -1361,7 +1445,7 @@ static long intel_vgpu_ioctl(struct mdev_device *mdev, unsigned int cmd, info.flags |= VFIO_DEVICE_FLAGS_RESET; info.num_regions = VFIO_PCI_NUM_REGIONS + vgpu->vdev.num_regions; - info.num_irqs = VFIO_PCI_NUM_IRQS; + info.num_irqs = VFIO_PCI_NUM_IRQS + vgpu->vdev.num_irqs; return copy_to_user((void __user *)arg, &info, minsz) ? -EFAULT : 0; @@ -1521,32 +1605,88 @@ static long intel_vgpu_ioctl(struct mdev_device *mdev, unsigned int cmd, -EFAULT : 0; } else if (cmd == VFIO_DEVICE_GET_IRQ_INFO) { struct vfio_irq_info info; + struct vfio_info_cap caps = { .buf = NULL, .size = 0 }; + unsigned int i; + int ret; minsz = offsetofend(struct vfio_irq_info, count); if (copy_from_user(&info, (void __user *)arg, minsz)) return -EFAULT; - if (info.argsz < minsz || info.index >= VFIO_PCI_NUM_IRQS) + if (info.argsz < minsz) return -EINVAL; switch (info.index) { case VFIO_PCI_INTX_IRQ_INDEX: case VFIO_PCI_MSI_IRQ_INDEX: + info.flags = VFIO_IRQ_INFO_EVENTFD; break; - default: + case VFIO_PCI_MSIX_IRQ_INDEX: + case VFIO_PCI_ERR_IRQ_INDEX: + case VFIO_PCI_REQ_IRQ_INDEX: return -EINVAL; - } + default: + { + struct vfio_irq_info_cap_type cap_type = { + .header.id = VFIO_IRQ_INFO_CAP_TYPE, + .header.version = 1 }; - info.flags = VFIO_IRQ_INFO_EVENTFD; + if (info.index >= VFIO_PCI_NUM_IRQS + + vgpu->vdev.num_irqs) + return -EINVAL; + info.index = + array_index_nospec(info.index, + VFIO_PCI_NUM_IRQS + + vgpu->vdev.num_irqs); + + i = info.index - VFIO_PCI_NUM_IRQS; + + info.flags = vgpu->vdev.irq[i].flags; + cap_type.type = vgpu->vdev.irq[i].type; + cap_type.subtype = vgpu->vdev.irq[i].subtype; + + ret = vfio_info_add_capability(&caps, + &cap_type.header, + sizeof(cap_type)); + if (ret) + return ret; + + if (vgpu->vdev.irq[i].ops->add_capability) { + ret = vgpu->vdev.irq[i].ops->add_capability(vgpu, + &caps); + if (ret) + return ret; + } + } + } info.count = intel_vgpu_get_irq_count(vgpu, info.index); if (info.index == VFIO_PCI_INTX_IRQ_INDEX) info.flags |= (VFIO_IRQ_INFO_MASKABLE | VFIO_IRQ_INFO_AUTOMASKED); - else - info.flags |= VFIO_IRQ_INFO_NORESIZE; + + if (caps.size) { + info.flags |= VFIO_IRQ_INFO_FLAG_CAPS; + if (info.argsz < sizeof(info) + caps.size) { + info.argsz = sizeof(info) + caps.size; + info.cap_offset = 0; + } else { + vfio_info_cap_shift(&caps, sizeof(info)); + if (copy_to_user((void __user *)arg + + sizeof(info), caps.buf, + caps.size)) { + kfree(caps.buf); + return -EFAULT; + } + info.cap_offset = sizeof(info); + if (offsetofend(struct vfio_irq_info, cap_offset) > minsz) + minsz = offsetofend(struct vfio_irq_info, cap_offset); + } + + kfree(caps.buf); + } return copy_to_user((void __user *)arg, &info, minsz) ? -EFAULT : 0; @@ -1565,7 +1705,8 @@ static long intel_vgpu_ioctl(struct mdev_device *mdev, unsigned int cmd, int max = intel_vgpu_get_irq_count(vgpu, hdr.index); ret = vfio_set_irqs_validate_and_prepare(&hdr, max, - VFIO_PCI_NUM_IRQS, &data_size); + VFIO_PCI_NUM_IRQS + vgpu->vdev.num_irqs, + &data_size); if (ret) { gvt_vgpu_err("intel:vfio_set_irqs_validate_and_prepare failed\n"); return -EINVAL; From patchwork Fri Aug 16 02:35:27 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "Zhang, Tina" X-Patchwork-Id: 11096699 Return-Path: Received: from mail.wl.linuxfoundation.org (pdx-wl-mail.web.codeaurora.org [172.30.200.125]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id A0B8C112C for ; Fri, 16 Aug 2019 02:36:17 +0000 (UTC) Received: from mail.wl.linuxfoundation.org (localhost [127.0.0.1]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id 90CD7289CD for ; Fri, 16 Aug 2019 02:36:17 +0000 (UTC) Received: by mail.wl.linuxfoundation.org (Postfix, from userid 486) id 84DEE289D0; Fri, 16 Aug 2019 02:36:17 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on pdx-wl-mail.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-7.9 required=2.0 tests=BAYES_00,MAILING_LIST_MULTI, RCVD_IN_DNSWL_HI autolearn=ham version=3.3.1 Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id 224C7289CD for ; Fri, 16 Aug 2019 02:36:17 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1726710AbfHPCgN (ORCPT ); Thu, 15 Aug 2019 22:36:13 -0400 Received: from mga07.intel.com ([134.134.136.100]:39512 "EHLO mga07.intel.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1726656AbfHPCgD (ORCPT ); Thu, 15 Aug 2019 22:36:03 -0400 X-Amp-Result: SKIPPED(no attachment in message) X-Amp-File-Uploaded: False Received: from fmsmga001.fm.intel.com ([10.253.24.23]) by orsmga105.jf.intel.com with ESMTP/TLS/DHE-RSA-AES256-GCM-SHA384; 15 Aug 2019 19:35:54 -0700 X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.64,391,1559545200"; d="scan'208";a="194894858" Received: from gvt.bj.intel.com ([10.238.158.180]) by fmsmga001.fm.intel.com with ESMTP; 15 Aug 2019 19:35:52 -0700 From: Tina Zhang To: intel-gvt-dev@lists.freedesktop.org Cc: Kechen Lu , kraxel@redhat.com, alex.williamson@redhat.com, kvm@vger.kernel.org, linux-kernel@vger.kernel.org, hang.yuan@intel.com, zhiyuan.lv@intel.com, Tina Zhang Subject: [PATCH v5 5/6] drm/i915/gvt: Deliver async primary plane page flip events at vblank Date: Fri, 16 Aug 2019 10:35:27 +0800 Message-Id: <20190816023528.30210-6-tina.zhang@intel.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20190816023528.30210-1-tina.zhang@intel.com> References: <20190816023528.30210-1-tina.zhang@intel.com> Sender: kvm-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: kvm@vger.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP From: Kechen Lu Only sync primary plane page flip events are checked and delivered as the display refresh events before, this patch tries to deliver async primary page flip events bounded by vblanks. To deliver correct async page flip, the new async flip bitmap is introduced and in vblank emulation handler to check bitset. Signed-off-by: Kechen Lu Signed-off-by: Tina Zhang --- drivers/gpu/drm/i915/gvt/cmd_parser.c | 6 ++++-- drivers/gpu/drm/i915/gvt/display.c | 10 ++++++++++ drivers/gpu/drm/i915/gvt/gvt.h | 2 ++ drivers/gpu/drm/i915/gvt/handlers.c | 5 +++-- 4 files changed, 19 insertions(+), 4 deletions(-) diff --git a/drivers/gpu/drm/i915/gvt/cmd_parser.c b/drivers/gpu/drm/i915/gvt/cmd_parser.c index ab002cfd3cab..51c3a1b10a54 100644 --- a/drivers/gpu/drm/i915/gvt/cmd_parser.c +++ b/drivers/gpu/drm/i915/gvt/cmd_parser.c @@ -1330,9 +1330,11 @@ static int gen8_update_plane_mmio_from_mi_display_flip( if (info->plane == PLANE_PRIMARY) vgpu_vreg_t(vgpu, PIPE_FLIPCOUNT_G4X(info->pipe))++; - if (info->async_flip) + if (info->async_flip) { intel_vgpu_trigger_virtual_event(vgpu, info->event); - else + set_bit(info->plane, + vgpu->display.async_flip_event[info->pipe]); + } else set_bit(info->event, vgpu->irq.flip_done_event[info->pipe]); return 0; diff --git a/drivers/gpu/drm/i915/gvt/display.c b/drivers/gpu/drm/i915/gvt/display.c index 616285e4a014..35436e845227 100644 --- a/drivers/gpu/drm/i915/gvt/display.c +++ b/drivers/gpu/drm/i915/gvt/display.c @@ -420,6 +420,16 @@ static void emulate_vblank_on_pipe(struct intel_vgpu *vgpu, int pipe) intel_vgpu_trigger_virtual_event(vgpu, event); } + for_each_set_bit(event, vgpu->display.async_flip_event[pipe], + I915_MAX_PLANES) { + clear_bit(event, vgpu->display.async_flip_event[pipe]); + if (!pipe_is_enabled(vgpu, pipe)) + continue; + + if (event == PLANE_PRIMARY) + eventfd_signal_val |= DISPLAY_PRI_REFRESH_EVENT_VAL; + } + if (eventfd_signal_val) no_pageflip_count = 0; else if (!eventfd_signal_val && no_pageflip_count > PAGEFLIP_DELAY_THR) diff --git a/drivers/gpu/drm/i915/gvt/gvt.h b/drivers/gpu/drm/i915/gvt/gvt.h index 6c8ed030c30b..90e35e436666 100644 --- a/drivers/gpu/drm/i915/gvt/gvt.h +++ b/drivers/gpu/drm/i915/gvt/gvt.h @@ -128,6 +128,8 @@ struct intel_vgpu_display { struct intel_vgpu_i2c_edid i2c_edid; struct intel_vgpu_port ports[I915_MAX_PORTS]; struct intel_vgpu_sbi sbi; + DECLARE_BITMAP(async_flip_event[I915_MAX_PIPES], + I915_MAX_PLANES); }; struct vgpu_sched_ctl { diff --git a/drivers/gpu/drm/i915/gvt/handlers.c b/drivers/gpu/drm/i915/gvt/handlers.c index 18f01eeb2510..92ff037996a2 100644 --- a/drivers/gpu/drm/i915/gvt/handlers.c +++ b/drivers/gpu/drm/i915/gvt/handlers.c @@ -758,9 +758,10 @@ static int pri_surf_mmio_write(struct intel_vgpu *vgpu, unsigned int offset, vgpu_vreg_t(vgpu, PIPE_FLIPCOUNT_G4X(pipe))++; - if (vgpu_vreg_t(vgpu, DSPCNTR(pipe)) & PLANE_CTL_ASYNC_FLIP) + if (vgpu_vreg_t(vgpu, DSPCNTR(pipe)) & PLANE_CTL_ASYNC_FLIP) { intel_vgpu_trigger_virtual_event(vgpu, event); - else + set_bit(PLANE_PRIMARY, vgpu->display.async_flip_event[pipe]); + } else set_bit(event, vgpu->irq.flip_done_event[pipe]); return 0; From patchwork Fri Aug 16 02:35:28 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "Zhang, Tina" X-Patchwork-Id: 11096697 Return-Path: Received: from mail.wl.linuxfoundation.org (pdx-wl-mail.web.codeaurora.org [172.30.200.125]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id B816B112C for ; Fri, 16 Aug 2019 02:36:11 +0000 (UTC) Received: from mail.wl.linuxfoundation.org (localhost [127.0.0.1]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id A83AB289CD for ; Fri, 16 Aug 2019 02:36:11 +0000 (UTC) Received: by mail.wl.linuxfoundation.org (Postfix, from userid 486) id 9C033289D0; Fri, 16 Aug 2019 02:36:11 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on pdx-wl-mail.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-7.9 required=2.0 tests=BAYES_00,MAILING_LIST_MULTI, RCVD_IN_DNSWL_HI autolearn=ham version=3.3.1 Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id 12742289CD for ; Fri, 16 Aug 2019 02:36:11 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1726699AbfHPCgE (ORCPT ); Thu, 15 Aug 2019 22:36:04 -0400 Received: from mga07.intel.com ([134.134.136.100]:39514 "EHLO mga07.intel.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1726649AbfHPCgD (ORCPT ); Thu, 15 Aug 2019 22:36:03 -0400 X-Amp-Result: SKIPPED(no attachment in message) X-Amp-File-Uploaded: False Received: from fmsmga001.fm.intel.com ([10.253.24.23]) by orsmga105.jf.intel.com with ESMTP/TLS/DHE-RSA-AES256-GCM-SHA384; 15 Aug 2019 19:35:55 -0700 X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.64,391,1559545200"; d="scan'208";a="194894864" Received: from gvt.bj.intel.com ([10.238.158.180]) by fmsmga001.fm.intel.com with ESMTP; 15 Aug 2019 19:35:54 -0700 From: Tina Zhang To: intel-gvt-dev@lists.freedesktop.org Cc: Kechen Lu , kraxel@redhat.com, alex.williamson@redhat.com, kvm@vger.kernel.org, linux-kernel@vger.kernel.org, hang.yuan@intel.com, zhiyuan.lv@intel.com, Tina Zhang Subject: [PATCH v5 6/6] drm/i915/gvt: Add cursor plane reg update trap emulation handler Date: Fri, 16 Aug 2019 10:35:28 +0800 Message-Id: <20190816023528.30210-7-tina.zhang@intel.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20190816023528.30210-1-tina.zhang@intel.com> References: <20190816023528.30210-1-tina.zhang@intel.com> Sender: kvm-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: kvm@vger.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP From: Kechen Lu This patch adds the cursor plane CURBASE reg update trap handler in order to: - Deliver the cursor refresh event at each vblank emulation, the flip_done_event bit check is supposed to do here. If cursor plane updates happen, deliver the cursor refresh events. - Support the sync and async cursor plane updates and corresponding cursor plane flip interrupts reporting. v2: - As the suggestion from Zhenyu, the experiments show that Windows driver programs the CURBASE and CURPOS at one time as well as the Linux i915 driver. So only track the CURBASE is enough. Signed-off-by: Kechen Lu Signed-off-by: Tina Zhang --- drivers/gpu/drm/i915/gvt/display.c | 7 +++++++ drivers/gpu/drm/i915/gvt/handlers.c | 27 ++++++++++++++++++++++++--- drivers/gpu/drm/i915/gvt/interrupt.c | 7 +++++++ drivers/gpu/drm/i915/gvt/interrupt.h | 3 +++ 4 files changed, 41 insertions(+), 3 deletions(-) diff --git a/drivers/gpu/drm/i915/gvt/display.c b/drivers/gpu/drm/i915/gvt/display.c index 35436e845227..78d43a81bbeb 100644 --- a/drivers/gpu/drm/i915/gvt/display.c +++ b/drivers/gpu/drm/i915/gvt/display.c @@ -401,6 +401,7 @@ static void emulate_vblank_on_pipe(struct intel_vgpu *vgpu, int pipe) [PIPE_C] = PIPE_C_VBLANK, }; int pri_flip_event = SKL_FLIP_EVENT(pipe, PLANE_PRIMARY); + int cur_flip_event = CURSOR_A_FLIP_DONE + pipe; int event; u64 eventfd_signal_val = 0; static int no_pageflip_count; @@ -417,6 +418,9 @@ static void emulate_vblank_on_pipe(struct intel_vgpu *vgpu, int pipe) if (event == pri_flip_event) eventfd_signal_val |= DISPLAY_PRI_REFRESH_EVENT_VAL; + if (event == cur_flip_event) + eventfd_signal_val |= DISPLAY_CUR_REFRESH_EVENT_VAL; + intel_vgpu_trigger_virtual_event(vgpu, event); } @@ -428,6 +432,9 @@ static void emulate_vblank_on_pipe(struct intel_vgpu *vgpu, int pipe) if (event == PLANE_PRIMARY) eventfd_signal_val |= DISPLAY_PRI_REFRESH_EVENT_VAL; + + if (event == PLANE_CURSOR) + eventfd_signal_val |= DISPLAY_CUR_REFRESH_EVENT_VAL; } if (eventfd_signal_val) diff --git a/drivers/gpu/drm/i915/gvt/handlers.c b/drivers/gpu/drm/i915/gvt/handlers.c index 92ff037996a2..53ef96562d48 100644 --- a/drivers/gpu/drm/i915/gvt/handlers.c +++ b/drivers/gpu/drm/i915/gvt/handlers.c @@ -767,6 +767,27 @@ static int pri_surf_mmio_write(struct intel_vgpu *vgpu, unsigned int offset, return 0; } +#define CURBASE_TO_PIPE(offset) \ + calc_index(offset, _CURABASE, _CURBBASE, 0, CURBASE(PIPE_C)) + +static int cur_surf_mmio_write(struct intel_vgpu *vgpu, unsigned int offset, + void *p_data, unsigned int bytes) +{ + struct drm_i915_private *dev_priv = vgpu->gvt->dev_priv; + u32 pipe = CURBASE_TO_PIPE(offset); + int event = CURSOR_A_FLIP_DONE + pipe; + + write_vreg(vgpu, offset, p_data, bytes); + + if (vgpu_vreg_t(vgpu, CURCNTR(pipe)) & PLANE_CTL_ASYNC_FLIP) { + intel_vgpu_trigger_virtual_event(vgpu, event); + set_bit(PLANE_CURSOR, vgpu->display.async_flip_event[pipe]); + } else + set_bit(event, vgpu->irq.flip_done_event[pipe]); + + return 0; +} + #define SPRSURF_TO_PIPE(offset) \ calc_index(offset, _SPRA_SURF, _SPRB_SURF, 0, SPRSURF(PIPE_C)) @@ -1970,9 +1991,9 @@ static int init_generic_mmio_info(struct intel_gvt *gvt) MMIO_D(CURPOS(PIPE_B), D_ALL); MMIO_D(CURPOS(PIPE_C), D_ALL); - MMIO_D(CURBASE(PIPE_A), D_ALL); - MMIO_D(CURBASE(PIPE_B), D_ALL); - MMIO_D(CURBASE(PIPE_C), D_ALL); + MMIO_DH(CURBASE(PIPE_A), D_ALL, NULL, cur_surf_mmio_write); + MMIO_DH(CURBASE(PIPE_B), D_ALL, NULL, cur_surf_mmio_write); + MMIO_DH(CURBASE(PIPE_C), D_ALL, NULL, cur_surf_mmio_write); MMIO_D(CUR_FBC_CTL(PIPE_A), D_ALL); MMIO_D(CUR_FBC_CTL(PIPE_B), D_ALL); diff --git a/drivers/gpu/drm/i915/gvt/interrupt.c b/drivers/gpu/drm/i915/gvt/interrupt.c index 951681813230..9c2b9d2e1529 100644 --- a/drivers/gpu/drm/i915/gvt/interrupt.c +++ b/drivers/gpu/drm/i915/gvt/interrupt.c @@ -113,6 +113,9 @@ static const char * const irq_name[INTEL_GVT_EVENT_MAX] = { [SPRITE_A_FLIP_DONE] = "Sprite Plane A flip done", [SPRITE_B_FLIP_DONE] = "Sprite Plane B flip done", [SPRITE_C_FLIP_DONE] = "Sprite Plane C flip done", + [CURSOR_A_FLIP_DONE] = "Cursor Plane A flip done", + [CURSOR_B_FLIP_DONE] = "Cursor Plane B flip done", + [CURSOR_C_FLIP_DONE] = "Cursor Plane C flip done", [PCU_THERMAL] = "PCU Thermal Event", [PCU_PCODE2DRIVER_MAILBOX] = "PCU pcode2driver mailbox event", @@ -593,6 +596,10 @@ static void gen8_init_irq( SET_BIT_INFO(irq, 4, SPRITE_A_FLIP_DONE, INTEL_GVT_IRQ_INFO_DE_PIPE_A); SET_BIT_INFO(irq, 4, SPRITE_B_FLIP_DONE, INTEL_GVT_IRQ_INFO_DE_PIPE_B); SET_BIT_INFO(irq, 4, SPRITE_C_FLIP_DONE, INTEL_GVT_IRQ_INFO_DE_PIPE_C); + + SET_BIT_INFO(irq, 6, CURSOR_A_FLIP_DONE, INTEL_GVT_IRQ_INFO_DE_PIPE_A); + SET_BIT_INFO(irq, 6, CURSOR_B_FLIP_DONE, INTEL_GVT_IRQ_INFO_DE_PIPE_B); + SET_BIT_INFO(irq, 6, CURSOR_C_FLIP_DONE, INTEL_GVT_IRQ_INFO_DE_PIPE_C); } /* GEN8 interrupt PCU events */ diff --git a/drivers/gpu/drm/i915/gvt/interrupt.h b/drivers/gpu/drm/i915/gvt/interrupt.h index 5313fb1b33e1..158f1c7a23f2 100644 --- a/drivers/gpu/drm/i915/gvt/interrupt.h +++ b/drivers/gpu/drm/i915/gvt/interrupt.h @@ -92,6 +92,9 @@ enum intel_gvt_event_type { SPRITE_A_FLIP_DONE, SPRITE_B_FLIP_DONE, SPRITE_C_FLIP_DONE, + CURSOR_A_FLIP_DONE, + CURSOR_B_FLIP_DONE, + CURSOR_C_FLIP_DONE, PCU_THERMAL, PCU_PCODE2DRIVER_MAILBOX,