From patchwork Sun Aug 18 16:23:41 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Stefan Wahren X-Patchwork-Id: 11099671 Return-Path: Received: from mail.wl.linuxfoundation.org (pdx-wl-mail.web.codeaurora.org [172.30.200.125]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id 360C318EC for ; Sun, 18 Aug 2019 16:24:24 +0000 (UTC) Received: from mail.wl.linuxfoundation.org (localhost [127.0.0.1]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id 251F5286B3 for ; Sun, 18 Aug 2019 16:24:24 +0000 (UTC) Received: by mail.wl.linuxfoundation.org (Postfix, from userid 486) id 18FE5286B8; Sun, 18 Aug 2019 16:24:24 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on pdx-wl-mail.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-8.0 required=2.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,FREEMAIL_FROM,MAILING_LIST_MULTI,RCVD_IN_DNSWL_HI autolearn=ham version=3.3.1 Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id BCC4C286D0 for ; Sun, 18 Aug 2019 16:24:23 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1726097AbfHRQYX (ORCPT ); Sun, 18 Aug 2019 12:24:23 -0400 Received: from mout.gmx.net ([212.227.15.19]:44627 "EHLO mout.gmx.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1726270AbfHRQYX (ORCPT ); Sun, 18 Aug 2019 12:24:23 -0400 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=gmx.net; s=badeba3b8450; t=1566145452; bh=UFpVfFUO4Wlq/HWE/2I9HA5xmIrtUaebTGvddy1P0q8=; h=X-UI-Sender-Class:From:To:Cc:Subject:Date:In-Reply-To:References; b=Y8k0y5+eI+7SjTRo+iO37aYwPmSlfwXlL1VtQOhwZf6FuSKqH2uciByxECOCbUVS6 +2iUaYAro4pqs6aantmc1UTe8OlyNDtr8XcsI2c3AhneKtdaR4o0qB2foMAqflf/hW 1+8WsmUrQ3560u2HhPPOv1FqdAPr2hfrM56JRn/o= X-UI-Sender-Class: 01bb95c1-4bf8-414a-932a-4f6e2808ef9c Received: from localhost.localdomain ([37.4.249.106]) by mail.gmx.com (mrgmx003 [212.227.17.190]) with ESMTPSA (Nemesis) id 0MEWkb-1i1FW10jlZ-00Fixn; Sun, 18 Aug 2019 18:24:12 +0200 From: Stefan Wahren To: Eric Anholt , Florian Fainelli , Ray Jui , Scott Branden , Rob Herring , Mark Rutland , Michael Turquette , Stephen Boyd Cc: linux-clk@vger.kernel.org, Stefan Wahren Subject: [PATCH 1/4] dt-bindings: bcm2835-cprman: Add bcm2711 support Date: Sun, 18 Aug 2019 18:23:41 +0200 Message-Id: <1566145424-3186-2-git-send-email-wahrenst@gmx.net> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1566145424-3186-1-git-send-email-wahrenst@gmx.net> References: <1566145424-3186-1-git-send-email-wahrenst@gmx.net> X-Provags-ID: V03:K1:gnkiswwseTiTeANk59dd9ZoAA9yGcxHHPjQPV7dmNUTqLgCPnA/ QjEzwwdun1wm7VT6Ep6sk+5uw0Pg1HnX4FSpK8bHOIP1X2PbOa8bpi4zUdMeXlGGe271Qhi rk8I9F34lhmw6LQV7clwqk9tpA9bHYoT2cX7GQqseWWK0HKRz7FdGkRvzv6P2OTMMnpGpWD r1/IzZi8AvkeHaEgVWiOw== X-UI-Out-Filterresults: notjunk:1;V03:K0:UijD47CAtM8=:C7qltEQQx2JJ4xyKn6Iuyi ieYvc7wo7Cwf7D07w/SEkVvM8VxI18JQiBnjpgHXPr7KL9/+jf/6m/QqP16PSq0PVV2myVKrI yO4pAGF77wkoh5yZNUDiJyXqndRYv1OloGnowOXe1KPeo810YhvyqF7YNVXMRi3SlJaxLxMo3 gjPCIQuejcEZkVvu5L+kcCpp0DbZsWy/toNRwN1eOKYLYoTbHmDw5zkcYUjS+6cRzISRWQ0So PAVZZ2DhvwLJd0w0ZKnL6RPe0VoiYZKFEZQUXu/mT3/v2f2QrC83oyh0/fwktxBEV+AMWrw4c Q2g0mV5HUHBO60Cc7WFvEVNjTuEL1BMhFcSdbMwy8sKSQdguH2iE6d03Hq79JbEcT6qwUgYtx eFNMahycGlrnZVFMZqLjInLUyFHT/im5XSYvdaTrD1Z2Ao39MxbqvFbnYoAcGyrFtP5JVwbBW 9gDgi36pf+PDZDZ8GdRoYgUY0TQPj1uuSmKMF2r8T9xcMnAJ494mGWZ4Q94CURAYWK3zA3vQR ZyJs89P/JRCMGA0XLCpNOeMA8Qgv8uxJFVRGLzMhY4Ne02HP8HQC98aQStYL+jwWOyPaA/kKa HH6KfhYMXV6BcCc1wEKMbCzg+Wo6au2mtqSN6szicJ8OiGG62GmNbeicCKlCJAKJ4XI1PU2Bt Esz8Y7R9Rj2o0QoKZKblf0DZIO0x9GMTkYDSD0qpbzfLvk5An0XxPrl8V4BDJd/EqbwgBY/Fp tRAn6G4Gjf1zWaNJkWv4JaRAyHwaKMoE3QEblHBCEGMdE5bfbkLiiY5igERFy4vCA709DHOHe svMycUTR6ZfQVyQqpidkrwEHF+sYQHHxIpuIF+g4WLxYIjZ6VM3RXVaqBL7PUiqznqrkfF8xH ikR+/yD9w1/PmGzR1zx80aaxG56mu6BVycVKKG3bXqpMopo2dZKOP8uAcuzsO7bpw0BIslGSJ Gee4gXeAciGUchA8SG4fWSzJQnGiXyHWozO9AD7LCexjy8AwKgrfg/R7mqa55pFtcGEcSzbED XA02wTqTMZ4gzDK5WvmMa4srTe6phxuT8zExWRkU0wrlmNisCC+SGIB21UqlODnh+4qkTvvJ0 K/RMIdpbmzLEXr0v/Bej445ca1GNEMfvQp/8sjk1VtCrhkJT/nH/PsIbg== Sender: linux-clk-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-clk@vger.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP The new BCM2711 supports an additional clock for the emmc2 block. So we need an additional compatible. Signed-off-by: Stefan Wahren Acked-by: Eric Anholt Reviewed-by: Eric Anholt --- Documentation/devicetree/bindings/clock/brcm,bcm2835-cprman.txt | 4 +++- include/dt-bindings/clock/bcm2835.h | 2 ++ 2 files changed, 5 insertions(+), 1 deletion(-) -- 2.7.4 diff --git a/Documentation/devicetree/bindings/clock/brcm,bcm2835-cprman.txt b/Documentation/devicetree/bindings/clock/brcm,bcm2835-cprman.txt index dd906db..9e0b03a 100644 --- a/Documentation/devicetree/bindings/clock/brcm,bcm2835-cprman.txt +++ b/Documentation/devicetree/bindings/clock/brcm,bcm2835-cprman.txt @@ -12,7 +12,9 @@ clock generators, but a few (like the ARM or HDMI) will source from the PLL dividers directly. Required properties: -- compatible: Should be "brcm,bcm2835-cprman" +- compatible: should be one of the following, + "brcm,bcm2711-cprman" + "brcm,bcm2835-cprman" - #clock-cells: Should be <1>. The permitted clock-specifier values can be found in include/dt-bindings/clock/bcm2835.h - reg: Specifies base physical address and size of the registers diff --git a/include/dt-bindings/clock/bcm2835.h b/include/dt-bindings/clock/bcm2835.h index 2cec01f..b60c0343 100644 --- a/include/dt-bindings/clock/bcm2835.h +++ b/include/dt-bindings/clock/bcm2835.h @@ -58,3 +58,5 @@ #define BCM2835_CLOCK_DSI1E 48 #define BCM2835_CLOCK_DSI0P 49 #define BCM2835_CLOCK_DSI1P 50 + +#define BCM2711_CLOCK_EMMC2 51 From patchwork Sun Aug 18 16:23:42 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Stefan Wahren X-Patchwork-Id: 11099675 Return-Path: Received: from mail.wl.linuxfoundation.org (pdx-wl-mail.web.codeaurora.org [172.30.200.125]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id EF3001399 for ; Sun, 18 Aug 2019 16:24:26 +0000 (UTC) Received: from mail.wl.linuxfoundation.org (localhost [127.0.0.1]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id DE2D428455 for ; Sun, 18 Aug 2019 16:24:26 +0000 (UTC) Received: by mail.wl.linuxfoundation.org (Postfix, from userid 486) id D1D70286B8; Sun, 18 Aug 2019 16:24:26 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on pdx-wl-mail.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-8.0 required=2.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,FREEMAIL_FROM,MAILING_LIST_MULTI,RCVD_IN_DNSWL_HI autolearn=ham version=3.3.1 Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id 9E53628455 for ; Sun, 18 Aug 2019 16:24:25 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1726261AbfHRQYZ (ORCPT ); Sun, 18 Aug 2019 12:24:25 -0400 Received: from mout.gmx.net ([212.227.15.18]:50827 "EHLO mout.gmx.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1726247AbfHRQYZ (ORCPT ); Sun, 18 Aug 2019 12:24:25 -0400 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=gmx.net; s=badeba3b8450; t=1566145452; bh=2EQQbD1OW5Bat6jRODQb5wvrchX/224QkLBdZwcOXzg=; h=X-UI-Sender-Class:From:To:Cc:Subject:Date:In-Reply-To:References; b=VdXh5FGDMapgTSr12/QmTtV/UlGS8CuQjDa2sK0Niv+b1O4Yfc5dgOq58N6RXfXec c8YR4ZM843RkL+KEA0XGrg/1HOF37XlTkia74NzpI8M+rd+reYxD5H5uxJSL1PhsNk YvyAawFNzF4ZHjcKwLjjCQPnKt0/oVenlgMCVh0c= X-UI-Sender-Class: 01bb95c1-4bf8-414a-932a-4f6e2808ef9c Received: from localhost.localdomain ([37.4.249.106]) by mail.gmx.com (mrgmx003 [212.227.17.190]) with ESMTPSA (Nemesis) id 0MGSgq-1i3jYa2Jay-00DEvS; Sun, 18 Aug 2019 18:24:12 +0200 From: Stefan Wahren To: Eric Anholt , Florian Fainelli , Ray Jui , Scott Branden , Rob Herring , Mark Rutland , Michael Turquette , Stephen Boyd Cc: linux-clk@vger.kernel.org, Stefan Wahren Subject: [PATCH 2/4] clk: bcm2835: Introduce SoC specific clock registration Date: Sun, 18 Aug 2019 18:23:42 +0200 Message-Id: <1566145424-3186-3-git-send-email-wahrenst@gmx.net> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1566145424-3186-1-git-send-email-wahrenst@gmx.net> References: <1566145424-3186-1-git-send-email-wahrenst@gmx.net> X-Provags-ID: V03:K1:3+OL5bhxKNbr6IFtcjyo9FSr2ymBIiDKeonKZfyvq8Cau5Cj9lp mAepi+FeNDU80vobYer0HxKU98DzzIfjiuyHM3oJHK99FpxqXN07wS7pyo9KFZ8QQyxGg7w c/MLdAHVAuIgXn9OwfKvfS5pI7QvyhkZEuWGfiX2lMgrAotYnaJfH7gVBYcT0mizKAsFx/P qiviF+vIDtrdmtROE+FqQ== X-UI-Out-Filterresults: notjunk:1;V03:K0:wnYFS8Kxe9k=:L8xS8SfUMwrvKcHDsW9HX8 LiNv2UPjodY8Z8rChhHVToQnqAO+cwnbLe88sDa3o+SGePTNZ2kiVetLnc3EeLKufYX0M+ow5 B8kcUM21u+uBy8SKuSyu2+thZds+vmFTYQZBrNAZpGn6rG7fxso3My+ihf8AZ9PSBVSGsIuMp 7nIlrt4JCmmkATprBwU8IiWW6CaP/egqCxbIFbtduiy3Obl1gzCBD8VRHyD2QCmB1sSIm6pMY dsV4rgJ+FknzgR4aIW8TV1g3hC8YsxBeEWwR650W38yFN7Wcfnal6A1JJnMf1va84nd5NLHkJ XxoUHIOOEG9nCXePJN3tw8i8fmAW/7B42EG86G61w6miF6WLSif+vgqWBUY9pyk/cmkY40X4L WlVmIqMG97n0tRDDz/Ph8lp4x6zRFo17fvtMNxGhb57Ei5XJzpRfViy+aLXSpJBADgKRUfe4Q ibLeEfYKGcxPFibrsO6u48jCvUCuoWCkB70I6v1ZhQR7Tcv7uD+7IcxGj7PJcI1RUy2acJGQR Qv3r0HjeXgFc5kmRyhfClo20jtBub+/qo/mKYWb97j7CmS7gfWSgT9e6ROJtck79OzT06/hXp qxz6oLVjD6Et291ePU/YKDQrsc5WCxEmqUxw4YHRYEPoF15UXQoONAvNoeEgDDauRT2I6YeBA ZNlMO1xooObMDpXaC8d6Hn21iiIQ+MTiq2qTZK8iFd/rv5LVzJjOcFPFCcZ081zwRt6NNYklI EASX2MH8/YBsl5nuZjIw3ofX+C77FNvFE6imop0hKwgWGTYkHzvPE+Rbepie141VuL6WhhA4Z 639/XiFa3Nud93xTdbQFv/3gWkRPP+SD83Ge900tVz0BSN6jRAkUy66AJOUVi0SlE+MYjG2ZM LFqTnvBYsZ0eIcuNb5Syv9X4fl4HGOvDBgfgwVVGChsud1KAQkoCJW233Ks41tje5dLqLc3bM qOVNubYrHHRGrpNvlwHEu6hVppZAdbSExQc+OBx+KSwbusBZ8u4pc8Nph2SobEUNl3YDg9tf8 YK70ZQzq77akPGegm4Ecb0I/u5rCgIUXWyqmEHryCIHo13QaBtWjDug+PYtvotYhyW6xfuF7p hma6mkWfYFoWUZ7U951MKyR7LCNkI8D6wdpEJBr8ySFq0Bkx0T41yvKp4nWwPWXh22idwEciZ RkLjkh3VYoASapliZI1dwr2a6B1yyr1ApPljMXsIPTTCdkzg== Sender: linux-clk-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-clk@vger.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP In order to support SoC specific clocks (e.g. emmc2 for BCM2711), we extend the description with a SoC support flag. This approach avoids long and mostly redundant lists of clock IDs. Since PLLH is specific to BCM2835, we register only rest of the clocks as common to all SoC. Suggested-by: Florian Fainelli Signed-off-by: Stefan Wahren Reviewed-by: Matthias Brugger Acked-by: Eric Anholt Reviewed-by: Eric Anholt --- drivers/clk/bcm/clk-bcm2835.c | 113 +++++++++++++++++++++++++++++++++++------- 1 file changed, 96 insertions(+), 17 deletions(-) -- 2.7.4 diff --git a/drivers/clk/bcm/clk-bcm2835.c b/drivers/clk/bcm/clk-bcm2835.c index 867ae3c..21cd952 100644 --- a/drivers/clk/bcm/clk-bcm2835.c +++ b/drivers/clk/bcm/clk-bcm2835.c @@ -31,7 +31,7 @@ #include #include #include -#include +#include #include #include #include @@ -289,6 +289,9 @@ #define LOCK_TIMEOUT_NS 100000000 #define BCM2835_MAX_FB_RATE 1750000000u +#define SOC_BCM2835 BIT(0) +#define SOC_ALL (SOC_BCM2835) + /* * Names of clocks used within the driver that need to be replaced * with an external parent's name. This array is in the order that @@ -320,6 +323,10 @@ struct bcm2835_cprman { struct clk_hw_onecell_data onecell; }; +struct cprman_plat_data { + unsigned int soc; +}; + static inline void cprman_write(struct bcm2835_cprman *cprman, u32 reg, u32 val) { writel(CM_PASSWORD | val, cprman->regs + reg); @@ -1451,22 +1458,28 @@ typedef struct clk_hw *(*bcm2835_clk_register)(struct bcm2835_cprman *cprman, const void *data); struct bcm2835_clk_desc { bcm2835_clk_register clk_register; + unsigned int supported; const void *data; }; /* assignment helper macros for different clock types */ -#define _REGISTER(f, ...) { .clk_register = (bcm2835_clk_register)f, \ - .data = __VA_ARGS__ } -#define REGISTER_PLL(...) _REGISTER(&bcm2835_register_pll, \ +#define _REGISTER(f, s, ...) { .clk_register = (bcm2835_clk_register)f, \ + .supported = s, \ + .data = __VA_ARGS__ } +#define REGISTER_PLL(s, ...) _REGISTER(&bcm2835_register_pll, \ + s, \ &(struct bcm2835_pll_data) \ {__VA_ARGS__}) -#define REGISTER_PLL_DIV(...) _REGISTER(&bcm2835_register_pll_divider, \ - &(struct bcm2835_pll_divider_data) \ - {__VA_ARGS__}) -#define REGISTER_CLK(...) _REGISTER(&bcm2835_register_clock, \ +#define REGISTER_PLL_DIV(s, ...) _REGISTER(&bcm2835_register_pll_divider, \ + s, \ + &(struct bcm2835_pll_divider_data) \ + {__VA_ARGS__}) +#define REGISTER_CLK(s, ...) _REGISTER(&bcm2835_register_clock, \ + s, \ &(struct bcm2835_clock_data) \ {__VA_ARGS__}) -#define REGISTER_GATE(...) _REGISTER(&bcm2835_register_gate, \ +#define REGISTER_GATE(s, ...) _REGISTER(&bcm2835_register_gate, \ + s, \ &(struct bcm2835_gate_data) \ {__VA_ARGS__}) @@ -1480,7 +1493,8 @@ static const char *const bcm2835_clock_osc_parents[] = { "testdebug1" }; -#define REGISTER_OSC_CLK(...) REGISTER_CLK( \ +#define REGISTER_OSC_CLK(s, ...) REGISTER_CLK( \ + s, \ .num_mux_parents = ARRAY_SIZE(bcm2835_clock_osc_parents), \ .parents = bcm2835_clock_osc_parents, \ __VA_ARGS__) @@ -1497,7 +1511,8 @@ static const char *const bcm2835_clock_per_parents[] = { "pllh_aux", }; -#define REGISTER_PER_CLK(...) REGISTER_CLK( \ +#define REGISTER_PER_CLK(s, ...) REGISTER_CLK( \ + s, \ .num_mux_parents = ARRAY_SIZE(bcm2835_clock_per_parents), \ .parents = bcm2835_clock_per_parents, \ __VA_ARGS__) @@ -1522,7 +1537,8 @@ static const char *const bcm2835_pcm_per_parents[] = { "-", }; -#define REGISTER_PCM_CLK(...) REGISTER_CLK( \ +#define REGISTER_PCM_CLK(s, ...) REGISTER_CLK( \ + s, \ .num_mux_parents = ARRAY_SIZE(bcm2835_pcm_per_parents), \ .parents = bcm2835_pcm_per_parents, \ __VA_ARGS__) @@ -1541,7 +1557,8 @@ static const char *const bcm2835_clock_vpu_parents[] = { "pllc_core2", }; -#define REGISTER_VPU_CLK(...) REGISTER_CLK( \ +#define REGISTER_VPU_CLK(s, ...) REGISTER_CLK( \ + s, \ .num_mux_parents = ARRAY_SIZE(bcm2835_clock_vpu_parents), \ .parents = bcm2835_clock_vpu_parents, \ __VA_ARGS__) @@ -1577,12 +1594,14 @@ static const char *const bcm2835_clock_dsi1_parents[] = { "dsi1_byte_inv", }; -#define REGISTER_DSI0_CLK(...) REGISTER_CLK( \ +#define REGISTER_DSI0_CLK(s, ...) REGISTER_CLK( \ + s, \ .num_mux_parents = ARRAY_SIZE(bcm2835_clock_dsi0_parents), \ .parents = bcm2835_clock_dsi0_parents, \ __VA_ARGS__) -#define REGISTER_DSI1_CLK(...) REGISTER_CLK( \ +#define REGISTER_DSI1_CLK(s, ...) REGISTER_CLK( \ + s, \ .num_mux_parents = ARRAY_SIZE(bcm2835_clock_dsi1_parents), \ .parents = bcm2835_clock_dsi1_parents, \ __VA_ARGS__) @@ -1602,6 +1621,7 @@ static const struct bcm2835_clk_desc clk_desc_array[] = { * AUDIO domain is on. */ [BCM2835_PLLA] = REGISTER_PLL( + SOC_ALL, .name = "plla", .cm_ctrl_reg = CM_PLLA, .a2w_ctrl_reg = A2W_PLLA_CTRL, @@ -1616,6 +1636,7 @@ static const struct bcm2835_clk_desc clk_desc_array[] = { .max_rate = 2400000000u, .max_fb_rate = BCM2835_MAX_FB_RATE), [BCM2835_PLLA_CORE] = REGISTER_PLL_DIV( + SOC_ALL, .name = "plla_core", .source_pll = "plla", .cm_reg = CM_PLLA, @@ -1625,6 +1646,7 @@ static const struct bcm2835_clk_desc clk_desc_array[] = { .fixed_divider = 1, .flags = CLK_SET_RATE_PARENT), [BCM2835_PLLA_PER] = REGISTER_PLL_DIV( + SOC_ALL, .name = "plla_per", .source_pll = "plla", .cm_reg = CM_PLLA, @@ -1634,6 +1656,7 @@ static const struct bcm2835_clk_desc clk_desc_array[] = { .fixed_divider = 1, .flags = CLK_SET_RATE_PARENT), [BCM2835_PLLA_DSI0] = REGISTER_PLL_DIV( + SOC_ALL, .name = "plla_dsi0", .source_pll = "plla", .cm_reg = CM_PLLA, @@ -1642,6 +1665,7 @@ static const struct bcm2835_clk_desc clk_desc_array[] = { .hold_mask = CM_PLLA_HOLDDSI0, .fixed_divider = 1), [BCM2835_PLLA_CCP2] = REGISTER_PLL_DIV( + SOC_ALL, .name = "plla_ccp2", .source_pll = "plla", .cm_reg = CM_PLLA, @@ -1663,6 +1687,7 @@ static const struct bcm2835_clk_desc clk_desc_array[] = { * AUDIO domain is on. */ [BCM2835_PLLC] = REGISTER_PLL( + SOC_ALL, .name = "pllc", .cm_ctrl_reg = CM_PLLC, .a2w_ctrl_reg = A2W_PLLC_CTRL, @@ -1677,6 +1702,7 @@ static const struct bcm2835_clk_desc clk_desc_array[] = { .max_rate = 3000000000u, .max_fb_rate = BCM2835_MAX_FB_RATE), [BCM2835_PLLC_CORE0] = REGISTER_PLL_DIV( + SOC_ALL, .name = "pllc_core0", .source_pll = "pllc", .cm_reg = CM_PLLC, @@ -1686,6 +1712,7 @@ static const struct bcm2835_clk_desc clk_desc_array[] = { .fixed_divider = 1, .flags = CLK_SET_RATE_PARENT), [BCM2835_PLLC_CORE1] = REGISTER_PLL_DIV( + SOC_ALL, .name = "pllc_core1", .source_pll = "pllc", .cm_reg = CM_PLLC, @@ -1695,6 +1722,7 @@ static const struct bcm2835_clk_desc clk_desc_array[] = { .fixed_divider = 1, .flags = CLK_SET_RATE_PARENT), [BCM2835_PLLC_CORE2] = REGISTER_PLL_DIV( + SOC_ALL, .name = "pllc_core2", .source_pll = "pllc", .cm_reg = CM_PLLC, @@ -1704,6 +1732,7 @@ static const struct bcm2835_clk_desc clk_desc_array[] = { .fixed_divider = 1, .flags = CLK_SET_RATE_PARENT), [BCM2835_PLLC_PER] = REGISTER_PLL_DIV( + SOC_ALL, .name = "pllc_per", .source_pll = "pllc", .cm_reg = CM_PLLC, @@ -1720,6 +1749,7 @@ static const struct bcm2835_clk_desc clk_desc_array[] = { * AUDIO domain is on. */ [BCM2835_PLLD] = REGISTER_PLL( + SOC_ALL, .name = "plld", .cm_ctrl_reg = CM_PLLD, .a2w_ctrl_reg = A2W_PLLD_CTRL, @@ -1734,6 +1764,7 @@ static const struct bcm2835_clk_desc clk_desc_array[] = { .max_rate = 2400000000u, .max_fb_rate = BCM2835_MAX_FB_RATE), [BCM2835_PLLD_CORE] = REGISTER_PLL_DIV( + SOC_ALL, .name = "plld_core", .source_pll = "plld", .cm_reg = CM_PLLD, @@ -1743,6 +1774,7 @@ static const struct bcm2835_clk_desc clk_desc_array[] = { .fixed_divider = 1, .flags = CLK_SET_RATE_PARENT), [BCM2835_PLLD_PER] = REGISTER_PLL_DIV( + SOC_ALL, .name = "plld_per", .source_pll = "plld", .cm_reg = CM_PLLD, @@ -1752,6 +1784,7 @@ static const struct bcm2835_clk_desc clk_desc_array[] = { .fixed_divider = 1, .flags = CLK_SET_RATE_PARENT), [BCM2835_PLLD_DSI0] = REGISTER_PLL_DIV( + SOC_ALL, .name = "plld_dsi0", .source_pll = "plld", .cm_reg = CM_PLLD, @@ -1760,6 +1793,7 @@ static const struct bcm2835_clk_desc clk_desc_array[] = { .hold_mask = CM_PLLD_HOLDDSI0, .fixed_divider = 1), [BCM2835_PLLD_DSI1] = REGISTER_PLL_DIV( + SOC_ALL, .name = "plld_dsi1", .source_pll = "plld", .cm_reg = CM_PLLD, @@ -1775,6 +1809,7 @@ static const struct bcm2835_clk_desc clk_desc_array[] = { * It is in the HDMI power domain. */ [BCM2835_PLLH] = REGISTER_PLL( + SOC_BCM2835, "pllh", .cm_ctrl_reg = CM_PLLH, .a2w_ctrl_reg = A2W_PLLH_CTRL, @@ -1789,6 +1824,7 @@ static const struct bcm2835_clk_desc clk_desc_array[] = { .max_rate = 3000000000u, .max_fb_rate = BCM2835_MAX_FB_RATE), [BCM2835_PLLH_RCAL] = REGISTER_PLL_DIV( + SOC_BCM2835, .name = "pllh_rcal", .source_pll = "pllh", .cm_reg = CM_PLLH, @@ -1798,6 +1834,7 @@ static const struct bcm2835_clk_desc clk_desc_array[] = { .fixed_divider = 10, .flags = CLK_SET_RATE_PARENT), [BCM2835_PLLH_AUX] = REGISTER_PLL_DIV( + SOC_BCM2835, .name = "pllh_aux", .source_pll = "pllh", .cm_reg = CM_PLLH, @@ -1807,6 +1844,7 @@ static const struct bcm2835_clk_desc clk_desc_array[] = { .fixed_divider = 1, .flags = CLK_SET_RATE_PARENT), [BCM2835_PLLH_PIX] = REGISTER_PLL_DIV( + SOC_BCM2835, .name = "pllh_pix", .source_pll = "pllh", .cm_reg = CM_PLLH, @@ -1822,6 +1860,7 @@ static const struct bcm2835_clk_desc clk_desc_array[] = { /* One Time Programmable Memory clock. Maximum 10Mhz. */ [BCM2835_CLOCK_OTP] = REGISTER_OSC_CLK( + SOC_ALL, .name = "otp", .ctl_reg = CM_OTPCTL, .div_reg = CM_OTPDIV, @@ -1833,6 +1872,7 @@ static const struct bcm2835_clk_desc clk_desc_array[] = { * bythe watchdog timer and the camera pulse generator. */ [BCM2835_CLOCK_TIMER] = REGISTER_OSC_CLK( + SOC_ALL, .name = "timer", .ctl_reg = CM_TIMERCTL, .div_reg = CM_TIMERDIV, @@ -1843,12 +1883,14 @@ static const struct bcm2835_clk_desc clk_desc_array[] = { * Generally run at 2Mhz, max 5Mhz. */ [BCM2835_CLOCK_TSENS] = REGISTER_OSC_CLK( + SOC_ALL, .name = "tsens", .ctl_reg = CM_TSENSCTL, .div_reg = CM_TSENSDIV, .int_bits = 5, .frac_bits = 0), [BCM2835_CLOCK_TEC] = REGISTER_OSC_CLK( + SOC_ALL, .name = "tec", .ctl_reg = CM_TECCTL, .div_reg = CM_TECDIV, @@ -1857,6 +1899,7 @@ static const struct bcm2835_clk_desc clk_desc_array[] = { /* clocks with vpu parent mux */ [BCM2835_CLOCK_H264] = REGISTER_VPU_CLK( + SOC_ALL, .name = "h264", .ctl_reg = CM_H264CTL, .div_reg = CM_H264DIV, @@ -1864,6 +1907,7 @@ static const struct bcm2835_clk_desc clk_desc_array[] = { .frac_bits = 8, .tcnt_mux = 1), [BCM2835_CLOCK_ISP] = REGISTER_VPU_CLK( + SOC_ALL, .name = "isp", .ctl_reg = CM_ISPCTL, .div_reg = CM_ISPDIV, @@ -1876,6 +1920,7 @@ static const struct bcm2835_clk_desc clk_desc_array[] = { * in the SDRAM controller can't be used. */ [BCM2835_CLOCK_SDRAM] = REGISTER_VPU_CLK( + SOC_ALL, .name = "sdram", .ctl_reg = CM_SDCCTL, .div_reg = CM_SDCDIV, @@ -1883,6 +1928,7 @@ static const struct bcm2835_clk_desc clk_desc_array[] = { .frac_bits = 0, .tcnt_mux = 3), [BCM2835_CLOCK_V3D] = REGISTER_VPU_CLK( + SOC_ALL, .name = "v3d", .ctl_reg = CM_V3DCTL, .div_reg = CM_V3DDIV, @@ -1896,6 +1942,7 @@ static const struct bcm2835_clk_desc clk_desc_array[] = { * in various hardware documentation. */ [BCM2835_CLOCK_VPU] = REGISTER_VPU_CLK( + SOC_ALL, .name = "vpu", .ctl_reg = CM_VPUCTL, .div_reg = CM_VPUDIV, @@ -1907,6 +1954,7 @@ static const struct bcm2835_clk_desc clk_desc_array[] = { /* clocks with per parent mux */ [BCM2835_CLOCK_AVEO] = REGISTER_PER_CLK( + SOC_ALL, .name = "aveo", .ctl_reg = CM_AVEOCTL, .div_reg = CM_AVEODIV, @@ -1914,6 +1962,7 @@ static const struct bcm2835_clk_desc clk_desc_array[] = { .frac_bits = 0, .tcnt_mux = 38), [BCM2835_CLOCK_CAM0] = REGISTER_PER_CLK( + SOC_ALL, .name = "cam0", .ctl_reg = CM_CAM0CTL, .div_reg = CM_CAM0DIV, @@ -1921,6 +1970,7 @@ static const struct bcm2835_clk_desc clk_desc_array[] = { .frac_bits = 8, .tcnt_mux = 14), [BCM2835_CLOCK_CAM1] = REGISTER_PER_CLK( + SOC_ALL, .name = "cam1", .ctl_reg = CM_CAM1CTL, .div_reg = CM_CAM1DIV, @@ -1928,12 +1978,14 @@ static const struct bcm2835_clk_desc clk_desc_array[] = { .frac_bits = 8, .tcnt_mux = 15), [BCM2835_CLOCK_DFT] = REGISTER_PER_CLK( + SOC_ALL, .name = "dft", .ctl_reg = CM_DFTCTL, .div_reg = CM_DFTDIV, .int_bits = 5, .frac_bits = 0), [BCM2835_CLOCK_DPI] = REGISTER_PER_CLK( + SOC_ALL, .name = "dpi", .ctl_reg = CM_DPICTL, .div_reg = CM_DPIDIV, @@ -1943,6 +1995,7 @@ static const struct bcm2835_clk_desc clk_desc_array[] = { /* Arasan EMMC clock */ [BCM2835_CLOCK_EMMC] = REGISTER_PER_CLK( + SOC_ALL, .name = "emmc", .ctl_reg = CM_EMMCCTL, .div_reg = CM_EMMCDIV, @@ -1952,6 +2005,7 @@ static const struct bcm2835_clk_desc clk_desc_array[] = { /* General purpose (GPIO) clocks */ [BCM2835_CLOCK_GP0] = REGISTER_PER_CLK( + SOC_ALL, .name = "gp0", .ctl_reg = CM_GP0CTL, .div_reg = CM_GP0DIV, @@ -1960,6 +2014,7 @@ static const struct bcm2835_clk_desc clk_desc_array[] = { .is_mash_clock = true, .tcnt_mux = 20), [BCM2835_CLOCK_GP1] = REGISTER_PER_CLK( + SOC_ALL, .name = "gp1", .ctl_reg = CM_GP1CTL, .div_reg = CM_GP1DIV, @@ -1969,6 +2024,7 @@ static const struct bcm2835_clk_desc clk_desc_array[] = { .is_mash_clock = true, .tcnt_mux = 21), [BCM2835_CLOCK_GP2] = REGISTER_PER_CLK( + SOC_ALL, .name = "gp2", .ctl_reg = CM_GP2CTL, .div_reg = CM_GP2DIV, @@ -1978,6 +2034,7 @@ static const struct bcm2835_clk_desc clk_desc_array[] = { /* HDMI state machine */ [BCM2835_CLOCK_HSM] = REGISTER_PER_CLK( + SOC_ALL, .name = "hsm", .ctl_reg = CM_HSMCTL, .div_reg = CM_HSMDIV, @@ -1985,6 +2042,7 @@ static const struct bcm2835_clk_desc clk_desc_array[] = { .frac_bits = 8, .tcnt_mux = 22), [BCM2835_CLOCK_PCM] = REGISTER_PCM_CLK( + SOC_ALL, .name = "pcm", .ctl_reg = CM_PCMCTL, .div_reg = CM_PCMDIV, @@ -1994,6 +2052,7 @@ static const struct bcm2835_clk_desc clk_desc_array[] = { .low_jitter = true, .tcnt_mux = 23), [BCM2835_CLOCK_PWM] = REGISTER_PER_CLK( + SOC_ALL, .name = "pwm", .ctl_reg = CM_PWMCTL, .div_reg = CM_PWMDIV, @@ -2002,6 +2061,7 @@ static const struct bcm2835_clk_desc clk_desc_array[] = { .is_mash_clock = true, .tcnt_mux = 24), [BCM2835_CLOCK_SLIM] = REGISTER_PER_CLK( + SOC_ALL, .name = "slim", .ctl_reg = CM_SLIMCTL, .div_reg = CM_SLIMDIV, @@ -2010,6 +2070,7 @@ static const struct bcm2835_clk_desc clk_desc_array[] = { .is_mash_clock = true, .tcnt_mux = 25), [BCM2835_CLOCK_SMI] = REGISTER_PER_CLK( + SOC_ALL, .name = "smi", .ctl_reg = CM_SMICTL, .div_reg = CM_SMIDIV, @@ -2017,6 +2078,7 @@ static const struct bcm2835_clk_desc clk_desc_array[] = { .frac_bits = 8, .tcnt_mux = 27), [BCM2835_CLOCK_UART] = REGISTER_PER_CLK( + SOC_ALL, .name = "uart", .ctl_reg = CM_UARTCTL, .div_reg = CM_UARTDIV, @@ -2026,6 +2088,7 @@ static const struct bcm2835_clk_desc clk_desc_array[] = { /* TV encoder clock. Only operating frequency is 108Mhz. */ [BCM2835_CLOCK_VEC] = REGISTER_PER_CLK( + SOC_ALL, .name = "vec", .ctl_reg = CM_VECCTL, .div_reg = CM_VECDIV, @@ -2040,6 +2103,7 @@ static const struct bcm2835_clk_desc clk_desc_array[] = { /* dsi clocks */ [BCM2835_CLOCK_DSI0E] = REGISTER_PER_CLK( + SOC_ALL, .name = "dsi0e", .ctl_reg = CM_DSI0ECTL, .div_reg = CM_DSI0EDIV, @@ -2047,6 +2111,7 @@ static const struct bcm2835_clk_desc clk_desc_array[] = { .frac_bits = 8, .tcnt_mux = 18), [BCM2835_CLOCK_DSI1E] = REGISTER_PER_CLK( + SOC_ALL, .name = "dsi1e", .ctl_reg = CM_DSI1ECTL, .div_reg = CM_DSI1EDIV, @@ -2054,6 +2119,7 @@ static const struct bcm2835_clk_desc clk_desc_array[] = { .frac_bits = 8, .tcnt_mux = 19), [BCM2835_CLOCK_DSI0P] = REGISTER_DSI0_CLK( + SOC_ALL, .name = "dsi0p", .ctl_reg = CM_DSI0PCTL, .div_reg = CM_DSI0PDIV, @@ -2061,6 +2127,7 @@ static const struct bcm2835_clk_desc clk_desc_array[] = { .frac_bits = 0, .tcnt_mux = 12), [BCM2835_CLOCK_DSI1P] = REGISTER_DSI1_CLK( + SOC_ALL, .name = "dsi1p", .ctl_reg = CM_DSI1PCTL, .div_reg = CM_DSI1PDIV, @@ -2077,6 +2144,7 @@ static const struct bcm2835_clk_desc clk_desc_array[] = { * non-stop vpu clock. */ [BCM2835_CLOCK_PERI_IMAGE] = REGISTER_GATE( + SOC_ALL, .name = "peri_image", .parent = "vpu", .ctl_reg = CM_PERIICTL), @@ -2109,9 +2177,14 @@ static int bcm2835_clk_probe(struct platform_device *pdev) struct resource *res; const struct bcm2835_clk_desc *desc; const size_t asize = ARRAY_SIZE(clk_desc_array); + const struct cprman_plat_data *pdata; size_t i; int ret; + pdata = of_device_get_match_data(&pdev->dev); + if (!pdata) + return -ENODEV; + cprman = devm_kzalloc(dev, struct_size(cprman, onecell.hws, asize), GFP_KERNEL); @@ -2147,8 +2220,10 @@ static int bcm2835_clk_probe(struct platform_device *pdev) for (i = 0; i < asize; i++) { desc = &clk_desc_array[i]; - if (desc->clk_register && desc->data) + if (desc->clk_register && desc->data && + (desc->supported & pdata->soc)) { hws[i] = desc->clk_register(cprman, desc->data); + } } ret = bcm2835_mark_sdc_parent_critical(hws[BCM2835_CLOCK_SDRAM]->clk); @@ -2159,8 +2234,12 @@ static int bcm2835_clk_probe(struct platform_device *pdev) &cprman->onecell); } +static const struct cprman_plat_data cprman_bcm2835_plat_data = { + .soc = SOC_BCM2835, +}; + static const struct of_device_id bcm2835_clk_of_match[] = { - { .compatible = "brcm,bcm2835-cprman", }, + { .compatible = "brcm,bcm2835-cprman", .data = &cprman_bcm2835_plat_data }, {} }; MODULE_DEVICE_TABLE(of, bcm2835_clk_of_match); From patchwork Sun Aug 18 16:23:43 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Stefan Wahren X-Patchwork-Id: 11099669 Return-Path: Received: from mail.wl.linuxfoundation.org (pdx-wl-mail.web.codeaurora.org [172.30.200.125]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id CEAC818A6 for ; Sun, 18 Aug 2019 16:24:23 +0000 (UTC) Received: from mail.wl.linuxfoundation.org (localhost [127.0.0.1]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id BA0DC28455 for ; Sun, 18 Aug 2019 16:24:23 +0000 (UTC) Received: by mail.wl.linuxfoundation.org (Postfix, from userid 486) id ADAD0286B8; Sun, 18 Aug 2019 16:24:23 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on pdx-wl-mail.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-8.0 required=2.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,FREEMAIL_FROM,MAILING_LIST_MULTI,RCVD_IN_DNSWL_HI autolearn=ham version=3.3.1 Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id 2956E286B3 for ; Sun, 18 Aug 2019 16:24:23 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1726089AbfHRQYW (ORCPT ); Sun, 18 Aug 2019 12:24:22 -0400 Received: from mout.gmx.net ([212.227.15.18]:52027 "EHLO mout.gmx.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1726097AbfHRQYW (ORCPT ); Sun, 18 Aug 2019 12:24:22 -0400 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=gmx.net; s=badeba3b8450; t=1566145453; bh=IM5UxVrBLP5hF/1d1ZFHRD2GqKmi/z5awy9hXKawSn0=; h=X-UI-Sender-Class:From:To:Cc:Subject:Date:In-Reply-To:References; b=VJQRqdVGHgbBsll1Q6/ZxhVx4LMhKHwxogARlRTqPT6fvTAQNtl9wsNYetEmiH/rP P7i0TWzXvcbhTSA6O4JRjfY3w0i6OIddUJ0hs3jwU3P2XW9g1Nm1EFD+t2e9lBCMSu K7FTt0AS+IR514jkzbxSDcpyfK+09lPuIqIjZ/TQ= X-UI-Sender-Class: 01bb95c1-4bf8-414a-932a-4f6e2808ef9c Received: from localhost.localdomain ([37.4.249.106]) by mail.gmx.com (mrgmx003 [212.227.17.190]) with ESMTPSA (Nemesis) id 0LiDrv-1idL9r45ul-00nOkz; Sun, 18 Aug 2019 18:24:13 +0200 From: Stefan Wahren To: Eric Anholt , Florian Fainelli , Ray Jui , Scott Branden , Rob Herring , Mark Rutland , Michael Turquette , Stephen Boyd Cc: linux-clk@vger.kernel.org, Stefan Wahren Subject: [PATCH 3/4] clk: bcm2835: Add BCM2711_CLOCK_EMMC2 support Date: Sun, 18 Aug 2019 18:23:43 +0200 Message-Id: <1566145424-3186-4-git-send-email-wahrenst@gmx.net> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1566145424-3186-1-git-send-email-wahrenst@gmx.net> References: <1566145424-3186-1-git-send-email-wahrenst@gmx.net> X-Provags-ID: V03:K1:3ix2WU/9XnteCrpqo9GRNBYCbCi4Wfo4+blR26+ik5fMozdrR6M IghvLQO/EwpzWfdg9kKXg2hsd3BK+ZoToDC0ZpJYldJ/xLjeZ8BJSK/nK+oDAJHpWo56YW9 RyrSQLY7JZsEIzW6TnBFCZ+ZUbiYE8Iqdzd2YiiagIiwCRWHF1k/yYMT7X6bcjZ9Cs0Xapz yjF5mlpWix3xuvMimQqhw== X-UI-Out-Filterresults: notjunk:1;V03:K0:7CXaunGzrZ4=:Egj7MudH8uxFdxWABY4fA7 AhhP/oquYGzDWVx+MzIW4sjt96cAt6IvJ3v4lge5brB2XY7Ongklh7dktv1BuA/wu6Q4Yex2u 5Clq1mLb5PgyEsltJsKbHG95mPSrYsJ/RJ4q6wJnQbkFuTC4Dk6z7VHrxwWxgQe2eNTKBCDGQ 1/znipapwh8wa1Y7xV8Lzj7AlEff5F5ppEenvc2wBQrVu7xu/DT4x/xIlD5RSJIa4BbMPRKFG Kj8svd7XsWFuN07ec3HTjJdHS7L0ujKbaBiJjGPFXeB2nzU3ezLDxpUrYeUNyJ6etLiPxN0gH 8dUwxwSFh7V0DmX5VImGLn/jpg6+YlJuLxbvXf08ibSykNOAFGeiQ14SPup58kMmJUZzuCnlh W/aJgX9sCa00zFf0Y94rC2I52A5werh6PA27/uaYv4t3X6yoa1wERQvMT/6BGCX6x5v0AEB/q DCKr0GSzdK1eGx0m5W+/3fJDGdd9jTGZetIN1QZ21qIlglk3/DWuMKVU6KoVi5v2bYy6u5uCm uimyNWu4oWYmzDOwvVcWKMkE+I7OTpmQ4rVdSks/7ZWbTpzHNxtFbF+ykBl3jafWOMxyGIZd+ sAJiVT/SJFlnVbp/prsxSCyVzoKBptsf7sEhMuAdGdK15+VynrayO2ECwMNxJwyxNbFQQDmki EuiNKmZb3SgOsEYKOgW6SUK/AUScx3m01PPOeOu0AXDUXJpNS1cYDBM5YkB2extJVjvdIwIJv qukGm+WDAuEpg0KKhzJMOHDDiyhDwmRhQMrujiRAmCWsjcmqH7L9wD32riu+36gicJhl8pq7B 50py9QA+fCH1LJ3i0t1frOtfxP/iyxU6kXxA1MxGk0llcpvIf8RF+9FdzLcwr0tifXyIaXauw l1WwUFsmsoOLfboAc4A7Bp9ngxMr2rINpcmOBwHWd0sI6k5s4YhxT2xpaqAAPIDsr3uHSDOLD MUjasn8zBVqjG8CQEtZL4IsT8WtpLOfw0Nu2lVNP4tfioL1v3QcnUKxFJuyGj9OtTXsAh4Qec ausLzF9H5JHYpmXeA0hRST2CW8roj2efbega2zkd/AN4QbMN0vSxdPIZCjb8F9IYGS3tljA9m s/nuGA0lXG5Sw+MEc2zHRo5VFJtYdt6kgnL0Ep9sFPrFxt22Q/kSzx6BmwgbL9yTr3nMFDOtz aeqxQNKqE742PAxTNWkJo49/geXMtnJ1UlIQxykMOYbPNNOQ== Sender: linux-clk-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-clk@vger.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP The new BCM2711 supports an additional clock for the emmc2 block. So add a new compatible and register this clock only for BCM2711. Signed-off-by: Stefan Wahren Reviewed-by: Matthias Brugger Acked-by: Eric Anholt Reviewed-by: Eric Anholt --- drivers/clk/bcm/clk-bcm2835.c | 20 +++++++++++++++++++- 1 file changed, 19 insertions(+), 1 deletion(-) -- 2.7.4 diff --git a/drivers/clk/bcm/clk-bcm2835.c b/drivers/clk/bcm/clk-bcm2835.c index 21cd952..fdf672a 100644 --- a/drivers/clk/bcm/clk-bcm2835.c +++ b/drivers/clk/bcm/clk-bcm2835.c @@ -114,6 +114,8 @@ #define CM_AVEODIV 0x1bc #define CM_EMMCCTL 0x1c0 #define CM_EMMCDIV 0x1c4 +#define CM_EMMC2CTL 0x1d0 +#define CM_EMMC2DIV 0x1d4 /* General bits for the CM_*CTL regs */ # define CM_ENABLE BIT(4) @@ -290,7 +292,8 @@ #define BCM2835_MAX_FB_RATE 1750000000u #define SOC_BCM2835 BIT(0) -#define SOC_ALL (SOC_BCM2835) +#define SOC_BCM2711 BIT(1) +#define SOC_ALL (SOC_BCM2835 | SOC_BCM2711) /* * Names of clocks used within the driver that need to be replaced @@ -2003,6 +2006,16 @@ static const struct bcm2835_clk_desc clk_desc_array[] = { .frac_bits = 8, .tcnt_mux = 39), + /* EMMC2 clock (only available for BCM2711) */ + [BCM2711_CLOCK_EMMC2] = REGISTER_PER_CLK( + SOC_BCM2711, + .name = "emmc2", + .ctl_reg = CM_EMMC2CTL, + .div_reg = CM_EMMC2DIV, + .int_bits = 4, + .frac_bits = 8, + .tcnt_mux = 42), + /* General purpose (GPIO) clocks */ [BCM2835_CLOCK_GP0] = REGISTER_PER_CLK( SOC_ALL, @@ -2238,8 +2251,13 @@ static const struct cprman_plat_data cprman_bcm2835_plat_data = { .soc = SOC_BCM2835, }; +static const struct cprman_plat_data cprman_bcm2711_plat_data = { + .soc = SOC_BCM2711, +}; + static const struct of_device_id bcm2835_clk_of_match[] = { { .compatible = "brcm,bcm2835-cprman", .data = &cprman_bcm2835_plat_data }, + { .compatible = "brcm,bcm2711-cprman", .data = &cprman_bcm2711_plat_data }, {} }; MODULE_DEVICE_TABLE(of, bcm2835_clk_of_match); From patchwork Sun Aug 18 16:23:44 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Stefan Wahren X-Patchwork-Id: 11099667 Return-Path: Received: from mail.wl.linuxfoundation.org (pdx-wl-mail.web.codeaurora.org [172.30.200.125]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id A194D112C for ; Sun, 18 Aug 2019 16:24:23 +0000 (UTC) Received: from mail.wl.linuxfoundation.org (localhost [127.0.0.1]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id 7887228455 for ; Sun, 18 Aug 2019 16:24:23 +0000 (UTC) Received: by mail.wl.linuxfoundation.org (Postfix, from userid 486) id 674B3286B9; Sun, 18 Aug 2019 16:24:23 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on pdx-wl-mail.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-8.0 required=2.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,FREEMAIL_FROM,MAILING_LIST_MULTI,RCVD_IN_DNSWL_HI autolearn=ham version=3.3.1 Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id 0982728455 for ; Sun, 18 Aug 2019 16:24:23 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1726742AbfHRQYW (ORCPT ); Sun, 18 Aug 2019 12:24:22 -0400 Received: from mout.gmx.net ([212.227.15.18]:57915 "EHLO mout.gmx.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1726089AbfHRQYW (ORCPT ); Sun, 18 Aug 2019 12:24:22 -0400 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=gmx.net; s=badeba3b8450; t=1566145453; bh=CzdbVQq8IrILnm9Q22KWEYU789AoTBUeM4pr8EHs4B0=; h=X-UI-Sender-Class:From:To:Cc:Subject:Date:In-Reply-To:References; b=BE9iF8C9awFP40knspDwDKei8JkqD7bb9v5Gi76ncS8K5jBzRguKhTSnq8tlqV+/x MwuCbxOZ47MpMMglpq9dybmhqtl4OZ86/UsZGS+/ZUpghSjnA3/r6lF2PwWD+EQRfA JpCiMyy6mD80XCggcJmH/vNZ4CR9MgEBRPC7W1U8= X-UI-Sender-Class: 01bb95c1-4bf8-414a-932a-4f6e2808ef9c Received: from localhost.localdomain ([37.4.249.106]) by mail.gmx.com (mrgmx003 [212.227.17.190]) with ESMTPSA (Nemesis) id 0LikE1-1iXL961U8j-00cwDf; Sun, 18 Aug 2019 18:24:13 +0200 From: Stefan Wahren To: Eric Anholt , Florian Fainelli , Ray Jui , Scott Branden , Rob Herring , Mark Rutland , Michael Turquette , Stephen Boyd Cc: linux-clk@vger.kernel.org, Stefan Wahren Subject: [PATCH 4/4] clk: bcm2835: Mark PLLD_PER as CRITICAL Date: Sun, 18 Aug 2019 18:23:44 +0200 Message-Id: <1566145424-3186-5-git-send-email-wahrenst@gmx.net> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1566145424-3186-1-git-send-email-wahrenst@gmx.net> References: <1566145424-3186-1-git-send-email-wahrenst@gmx.net> X-Provags-ID: V03:K1:Y5KnN3P4dN6rJKtSRnxV6bmbDrsIR6RJHsGa2SS5ZGPEIdDjLld m9M0ggJUPJlABn8hfTzpFBgFqiYKPW5JlB5RGi+IvwChqvpw7psC09DRv2MM+TDMNATZCE3 G4l1+YDGPkAM574T8IeaN/7Vdauxv9c2tqnK5l0dpWv3V8n2W2AV4q4FoKZvvePl5g6afXY itREXpAZkk6eV5xJwAMpw== X-UI-Out-Filterresults: notjunk:1;V03:K0:6nY4L7DJmR8=:qhqpx98PZ0Yv7ARb0iDSAf h2jl3qUYO/BYr+H/YYgmWcwtz1Iz6YTHj0jSXT4ri44f5vZsuYU5nCMsgzxakTYnSUnOCayXi 3jghAzsIWTwYXFfFmv+KKDhQMlTkBL0dleN9e5c34P4eVhPMNdtmfzZgjpQjPuj6O37VWU9Hl 8om56VkzvFVkHwRuugO/4+roZQLgg9QGexvtS7xsBcbm7MpltLKKqJ8KaVCNHFYAPSPWAt9Bk UxdjgujtrotUVTeWuKcKzSpwf9dVde15sXHtUKoHvBKWwLSypkxsKXU503ykjrD2peGxhWXz4 tVH6Dslruvn59VAL6MycATISgVL8EeMM/gERlOOh9MfF/yapVaUMXE14oxixsE4VrooWeOo/z 6fTILJZC9dssUEU8SzbvlH93OlGAjnePFjk+B2CJ7RSHX8NiJbWbOlFhEA7FU4RVL3eJZw6zY 5EQxckN9iUNzqv3Is1zhKJSWpQU951FYleYSo9KcB9jo6ZgXeHuGCEwIXCTsRdHZokZQ36dBZ DeAHtkuGuWNPhFiDn9bgNllVmoW6IyOI5TeIpPgcloH9aqsBJzn6F1i6U1cjRsiw6ba19FN8z AuJ9LWblHpgFsVZzY/1nDUloY6BUNlkYunlUHOf7sjP1PyDUMO7dNvW7+I6D6UgaGvV3RWfvy 74zmGfI780eyqA1BxJlcxkoWv6slxYY12jDw+85ItsYkf3CMo6J9seVW5Ge9em1Jy6FeQdNix 8zrITqCH+HiADIMXbpFoi70etb9NwIQ+z+t+ykhfBsi7eQV+B6uRdpOQl1Xfrd7jdo7tagYgK sJRGuyvumkKICNyaLyKC8h2SSbUdbyfaTDUE9x4qTYGDKU9n3WMyBusU0ekXAAjtGIXVEDJKl sgb5yn2VmWSd1dskSnkynpVsZQLu4rYs+Y2ntcByXXamfzfrTT3wpHL7Pi/rcI2dZOMXhXbG4 wSIl5eRxC42HjYGdgaQuKW1Im6z+T7JJaAKffe+varrIARFWFURLxj67BdT0Swiz28P0kmriK Ugte/8SCJsdJzDsvIPmhrLnHWQVHOcrrbXzi1CpF9xqZNQ8XxbtH6vhEJeCBJoHw5kqcsFVCm Ddp+Cw6a5hIaMTqsZpo1VXc2xV+pE+ryXSCqVf8J1NQNtTXbNySvuJB4X3bYGpnoBLaqbzyfC O0zwjoIsF8nN/La0J/60/xCWk455dDKt9r2EjdfFCO25se2g== Sender: linux-clk-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-clk@vger.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP The VPU firmware assume that the PLLD_PER isn't modified by the ARM core. Otherwise this could cause firmware lookups. So mark the clock as critical to avoid this. Signed-off-by: Stefan Wahren Reviewed-by: Eric Anholt --- drivers/clk/bcm/clk-bcm2835.c | 7 ++++++- 1 file changed, 6 insertions(+), 1 deletion(-) -- 2.7.4 diff --git a/drivers/clk/bcm/clk-bcm2835.c b/drivers/clk/bcm/clk-bcm2835.c index fdf672a..802e488 100644 --- a/drivers/clk/bcm/clk-bcm2835.c +++ b/drivers/clk/bcm/clk-bcm2835.c @@ -1776,6 +1776,11 @@ static const struct bcm2835_clk_desc clk_desc_array[] = { .hold_mask = CM_PLLD_HOLDCORE, .fixed_divider = 1, .flags = CLK_SET_RATE_PARENT), + /* + * VPU firmware assumes that PLLD_PER isn't disabled by the ARM core. + * Otherwise this could cause firmware lookups. That's why we mark + * it as critical. + */ [BCM2835_PLLD_PER] = REGISTER_PLL_DIV( SOC_ALL, .name = "plld_per", @@ -1785,7 +1790,7 @@ static const struct bcm2835_clk_desc clk_desc_array[] = { .load_mask = CM_PLLD_LOADPER, .hold_mask = CM_PLLD_HOLDPER, .fixed_divider = 1, - .flags = CLK_SET_RATE_PARENT), + .flags = CLK_IS_CRITICAL | CLK_SET_RATE_PARENT), [BCM2835_PLLD_DSI0] = REGISTER_PLL_DIV( SOC_ALL, .name = "plld_dsi0",