From patchwork Mon Aug 19 18:08:22 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Matt Roper X-Patchwork-Id: 11101609 Return-Path: Received: from mail.kernel.org (pdx-korg-mail-1.web.codeaurora.org [172.30.200.123]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id DBEA01813 for ; Mon, 19 Aug 2019 18:08:45 +0000 (UTC) Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id C6B7F22CF4 for ; Mon, 19 Aug 2019 18:08:45 +0000 (UTC) DMARC-Filter: OpenDMARC Filter v1.3.2 mail.kernel.org C6B7F22CF4 Authentication-Results: mail.kernel.org; dmarc=fail (p=none dis=none) header.from=intel.com Authentication-Results: mail.kernel.org; spf=none smtp.mailfrom=intel-gfx-bounces@lists.freedesktop.org Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id 3E0356E260; Mon, 19 Aug 2019 18:08:45 +0000 (UTC) X-Original-To: intel-gfx@lists.freedesktop.org Delivered-To: intel-gfx@lists.freedesktop.org Received: from mga01.intel.com (mga01.intel.com [192.55.52.88]) by gabe.freedesktop.org (Postfix) with ESMTPS id 4228B6E260 for ; Mon, 19 Aug 2019 18:08:44 +0000 (UTC) X-Amp-Result: SKIPPED(no attachment in message) X-Amp-File-Uploaded: False Received: from orsmga007.jf.intel.com ([10.7.209.58]) by fmsmga101.fm.intel.com with ESMTP/TLS/DHE-RSA-AES256-GCM-SHA384; 19 Aug 2019 11:08:43 -0700 X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.64,405,1559545200"; d="scan'208,223";a="168828723" Received: from mdroper-desk.fm.intel.com ([10.105.128.126]) by orsmga007.jf.intel.com with ESMTP; 19 Aug 2019 11:08:43 -0700 From: Matt Roper To: intel-gfx@lists.freedesktop.org Date: Mon, 19 Aug 2019 11:08:22 -0700 Message-Id: <20190819180822.15665-1-matthew.d.roper@intel.com> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20190819164606.GF27240@mdroper-desk.amr.corp.intel.com> References: <20190819164606.GF27240@mdroper-desk.amr.corp.intel.com> MIME-Version: 1.0 Subject: [Intel-gfx] [PATCH v2] drm/i915/gen11: Add Wa_1604278689:icl,ehl X-BeenThere: intel-gfx@lists.freedesktop.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: Intel graphics driver community testing & development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: intel-gfx-bounces@lists.freedesktop.org Sender: "Intel-gfx" From the bspec: "SW must always program the FBC_RT_BASE_ADDR_REGISTER_* register in Render Engine to a reserved value (0xFFFF_FFFF) such that the programmed value doesn’t match the render target surface address programmed. This would disable render engine from generating modify messages to FBC unit in display." This workaround seems a bit questionable as written since using all 1's to the RT_BASE register implies setting bit 0, which is a flag to indicate whether the address is valid. Indeed, we start seeing CI failures when we follow the directions here literally. Let's slightly deviate from the workaround instructions and set all bits _except_ for bit 0 of FBC_RT_BASE_ADDR_REGISTER. v2: - Mask off the RT_VALID bit. Experimentation with CI trybot indicates that this is necessary to avoid reset failures on BCS. Bspec: 11388 Bspec: 33451 Cc: José Roberto de Souza Cc: Chris Wilson Cc: Ville Syrjälä Signed-off-by: Matt Roper --- drivers/gpu/drm/i915/gt/intel_workarounds.c | 6 ++++++ drivers/gpu/drm/i915/i915_reg.h | 1 + 2 files changed, 7 insertions(+) diff --git a/drivers/gpu/drm/i915/gt/intel_workarounds.c b/drivers/gpu/drm/i915/gt/intel_workarounds.c index 704ace01e7f5..f70b7a95bc23 100644 --- a/drivers/gpu/drm/i915/gt/intel_workarounds.c +++ b/drivers/gpu/drm/i915/gt/intel_workarounds.c @@ -567,6 +567,12 @@ static void icl_ctx_workarounds_init(struct intel_engine_cs *engine, /* allow headerless messages for preemptible GPGPU context */ WA_SET_BIT_MASKED(GEN10_SAMPLER_MODE, GEN11_SAMPLER_ENABLE_HEADLESS_MSG); + + /* Wa_1604278689:icl,ehl */ + wa_write_masked_or(wal, IVB_FBC_RT_BASE_UPPER, + 0, /* write-only register; skip validation */ + 0xFFFFFFFF); + wa_write(wal, IVB_FBC_RT_BASE, 0xFFFFFFFF & ~ILK_FBC_RT_VALID); } static void diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h index ea2f0fa2402d..bce7326329db 100644 --- a/drivers/gpu/drm/i915/i915_reg.h +++ b/drivers/gpu/drm/i915/i915_reg.h @@ -3170,6 +3170,7 @@ static inline bool i915_mmio_reg_valid(i915_reg_t reg) /* Framebuffer compression for Ivybridge */ #define IVB_FBC_RT_BASE _MMIO(0x7020) +#define IVB_FBC_RT_BASE_UPPER _MMIO(0x7024) #define IPS_CTL _MMIO(0x43408) #define IPS_ENABLE (1 << 31)