From patchwork Mon Aug 19 20:57:13 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Mike Leach X-Patchwork-Id: 11101929 Return-Path: Received: from mail.kernel.org (pdx-korg-mail-1.web.codeaurora.org [172.30.200.123]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id 310D2912 for ; Mon, 19 Aug 2019 20:58:31 +0000 (UTC) Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id 10A9F2087E for ; Mon, 19 Aug 2019 20:58:31 +0000 (UTC) Authentication-Results: mail.kernel.org; dkim=pass (2048-bit key) header.d=lists.infradead.org header.i=@lists.infradead.org header.b="bKg1dcc+"; dkim=fail reason="signature verification failed" (2048-bit key) header.d=linaro.org header.i=@linaro.org header.b="AfPBwxMS" DMARC-Filter: OpenDMARC Filter v1.3.2 mail.kernel.org 10A9F2087E Authentication-Results: mail.kernel.org; dmarc=fail (p=none dis=none) header.from=linaro.org Authentication-Results: mail.kernel.org; spf=none smtp.mailfrom=linux-arm-kernel-bounces+patchwork-linux-arm=patchwork.kernel.org@lists.infradead.org DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=bombadil.20170209; h=Sender: Content-Transfer-Encoding:Content-Type:MIME-Version:Cc:List-Subscribe: List-Help:List-Post:List-Archive:List-Unsubscribe:List-Id:References: In-Reply-To:Message-Id:Date:Subject:To:From:Reply-To:Content-ID: Content-Description:Resent-Date:Resent-From:Resent-Sender:Resent-To:Resent-Cc :Resent-Message-ID:List-Owner; bh=fgLx9jf6ZIgG4RH25Sv38ZqmrnVdkQx2Vk1mvJog+g8=; b=bKg1dcc+LMqGSWQ/qnky3mr9yi MpHYpBkVX9cudK8U2Dhi0Ak5NbMy3hBF/duvrzz/Yxjn6NKVHERx1Qe1ieeb1+8VDjoxo1bssbQf+ eRgKVZFeDMqMf3AY+tq4lFCo6QY9T386lLvgAARhTeCk9LuKn1NRhh9rYRpISHhT1kyO5djBBiAYN 5RzkgiZmEFK/FosC7UYOt1SMV45HUvnWEsEeTXdOTAMBH/xaWbY9n2lx8qNQR+/w1UyTSyFx4tGnT EV6KemXunV41OAAAN2X5wtQ0UfVIBC2oNuXOoWaen+31h+eKl04UXQsm7kq2pb4dcE3XtRntfj7LF TJtGazSQ==; Received: from localhost ([127.0.0.1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.92 #3 (Red Hat Linux)) id 1hzojW-00065K-Jc; Mon, 19 Aug 2019 20:58:30 +0000 Received: from mail-wr1-x441.google.com ([2a00:1450:4864:20::441]) by bombadil.infradead.org with esmtps (Exim 4.92 #3 (Red Hat Linux)) id 1hzoij-0005Gm-9G for linux-arm-kernel@lists.infradead.org; Mon, 19 Aug 2019 20:57:44 +0000 Received: by mail-wr1-x441.google.com with SMTP id b16so10108393wrq.9 for ; Mon, 19 Aug 2019 13:57:40 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=KrxSG+qaFTGAM+LupS+n0Ni/hovDe7so4u3P1kbutKI=; b=AfPBwxMSQ1ba+LbK5pefijL5w5t3/iBSgyl/j8kX8ULPMvEuUXMrhx3iDjh/+RMF8G 3LsfElfVH0jnz/kaHrd23SxJLApk09QQn96C1lgYL5BDEmtPwh1R2jbgT8UbZI6bRFJT tbgpYLOHScQGqusRR8EyAyqjDhKBdCXOLNFuiIkZeE9a4csdHylQk0U7CbH1KbqDfG+B kM8i+JfWenNpabGIA/DbV6aCoYOvaSdXNfQ2wfQ27vZk1Ub6x042lzjPyQUIlBkIfE1V jr29vcFjzH0wiNgucKH22so6Eoo7T54Sr3+72LL0ICuaHSZgu6fhJX0PtPDd2qRb+/31 eS+g== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=KrxSG+qaFTGAM+LupS+n0Ni/hovDe7so4u3P1kbutKI=; b=Ho0taze1fGRUUXY4cgJA+w00WE5P4CUjmR0QgtCNsvqcaFESNlfSvnCCsrOlpteN45 Hi1xSvG36vMGpLt3iri8DO47bNMH2X0Vtg+0o+DN8JKNr1blIC98dYLVPqVuv1mvUwOI vDVzJvPqya5DmNfDmN/H/JiQK6eDkHTJmECG5hFRnKAsE0ojmN2IBGIjdefa0BJms1sh R6j8iLro61Ro+Az5ZFKd8Ip7D6h9OQdnlIYWrjE1gM3uWR5rWcbKYFww4icGhB7byhHM dpo36vAsEBS2LbUg8ZZHfSqnfA61Fg+VvBVJV+ZotVqV7NXie0BLajJ9U4NStM88ahV3 m5fw== X-Gm-Message-State: APjAAAVt56Onk3ZY+TuGJKFf8asHp1jCvL1VtfWfsUorPE7LfympB6e3 335fP/zNdUp5IaY+lukxrmIQxw== X-Google-Smtp-Source: APXvYqxlFWi/L+H9lIWtV9v/12HM4on9h/0D3aTLDCei8QnCdb6P8Wso0jnA4Np1LEXGgJ6Asqj9tQ== X-Received: by 2002:adf:ffc2:: with SMTP id x2mr25728010wrs.338.1566248258951; Mon, 19 Aug 2019 13:57:38 -0700 (PDT) Received: from linaro.org ([2a00:23c5:6815:3901:247e:6e55:2413:b21c]) by smtp.gmail.com with ESMTPSA id n9sm6698423wrx.76.2019.08.19.13.57.38 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 19 Aug 2019 13:57:38 -0700 (PDT) From: Mike Leach To: mathieu.poirier@linaro.org, linux-arm-kernel@lists.infradead.org, coresight@lists.linaro.org Subject: [PATCH 1/8] coresight: etm4x: Fixes for ETM v4.4 architecture updates. Date: Mon, 19 Aug 2019 21:57:13 +0100 Message-Id: <20190819205720.24457-2-mike.leach@linaro.org> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20190819205720.24457-1-mike.leach@linaro.org> References: <20190819205720.24457-1-mike.leach@linaro.org> X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20190819_135741_347870_E755EB9E X-CRM114-Status: GOOD ( 13.48 ) X-Spam-Score: -0.2 (/) X-Spam-Report: SpamAssassin version 3.4.2 on bombadil.infradead.org summary: Content analysis details: (-0.2 points) pts rule name description ---- ---------------------- -------------------------------------------------- -0.0 RCVD_IN_DNSWL_NONE RBL: Sender listed at https://www.dnswl.org/, no trust [2a00:1450:4864:20:0:0:0:441 listed in] [list.dnswl.org] -0.0 SPF_PASS SPF: sender matches SPF record 0.0 SPF_HELO_NONE SPF: HELO does not publish an SPF Record -0.1 DKIM_VALID_EF Message has a valid DKIM or DK signature from envelope-from domain -0.1 DKIM_VALID Message has at least one valid DKIM or DK signature -0.1 DKIM_VALID_AU Message has a valid DKIM or DK signature from author's domain 0.1 DKIM_SIGNED Message has a DKIM or DK signature, not necessarily valid X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: suzuki.poulose@arm.com, mike.leach@linaro.org MIME-Version: 1.0 Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+patchwork-linux-arm=patchwork.kernel.org@lists.infradead.org ETMv4.4 adds in support for tracing secure EL2 (per arch 8.x updates). Patch accounts for this new capability. Signed-off-by: Mike Leach Reviewed-by: Leo Yan --- .../hwtracing/coresight/coresight-etm4x-sysfs.c | 12 ++++++------ drivers/hwtracing/coresight/coresight-etm4x.c | 5 ++++- drivers/hwtracing/coresight/coresight-etm4x.h | 15 +++++++++++---- 3 files changed, 21 insertions(+), 11 deletions(-) diff --git a/drivers/hwtracing/coresight/coresight-etm4x-sysfs.c b/drivers/hwtracing/coresight/coresight-etm4x-sysfs.c index 219c10eb752c..b6984be0c515 100644 --- a/drivers/hwtracing/coresight/coresight-etm4x-sysfs.c +++ b/drivers/hwtracing/coresight/coresight-etm4x-sysfs.c @@ -738,7 +738,7 @@ static ssize_t s_exlevel_vinst_show(struct device *dev, struct etmv4_drvdata *drvdata = dev_get_drvdata(dev->parent); struct etmv4_config *config = &drvdata->config; - val = BMVAL(config->vinst_ctrl, 16, 19); + val = (config->vinst_ctrl & ETM_EXLEVEL_S_VICTLR_MASK) >> 16; return scnprintf(buf, PAGE_SIZE, "%#lx\n", val); } @@ -754,8 +754,8 @@ static ssize_t s_exlevel_vinst_store(struct device *dev, return -EINVAL; spin_lock(&drvdata->spinlock); - /* clear all EXLEVEL_S bits (bit[18] is never implemented) */ - config->vinst_ctrl &= ~(BIT(16) | BIT(17) | BIT(19)); + /* clear all EXLEVEL_S bits */ + config->vinst_ctrl &= ~(ETM_EXLEVEL_S_VICTLR_MASK); /* enable instruction tracing for corresponding exception level */ val &= drvdata->s_ex_level; config->vinst_ctrl |= (val << 16); @@ -773,7 +773,7 @@ static ssize_t ns_exlevel_vinst_show(struct device *dev, struct etmv4_config *config = &drvdata->config; /* EXLEVEL_NS, bits[23:20] */ - val = BMVAL(config->vinst_ctrl, 20, 23); + val = (config->vinst_ctrl & ETM_EXLEVEL_NS_VICTLR_MASK) >> 20; return scnprintf(buf, PAGE_SIZE, "%#lx\n", val); } @@ -789,8 +789,8 @@ static ssize_t ns_exlevel_vinst_store(struct device *dev, return -EINVAL; spin_lock(&drvdata->spinlock); - /* clear EXLEVEL_NS bits (bit[23] is never implemented */ - config->vinst_ctrl &= ~(BIT(20) | BIT(21) | BIT(22)); + /* clear EXLEVEL_NS bits */ + config->vinst_ctrl &= ~(ETM_EXLEVEL_NS_VICTLR_MASK); /* enable instruction tracing for corresponding exception level */ val &= drvdata->ns_ex_level; config->vinst_ctrl |= (val << 20); diff --git a/drivers/hwtracing/coresight/coresight-etm4x.c b/drivers/hwtracing/coresight/coresight-etm4x.c index a128b5063f46..52b8876de157 100644 --- a/drivers/hwtracing/coresight/coresight-etm4x.c +++ b/drivers/hwtracing/coresight/coresight-etm4x.c @@ -629,6 +629,7 @@ static void etm4_init_arch_data(void *info) * TRCARCHMAJ, bits[11:8] architecture major versin number */ drvdata->arch = BMVAL(etmidr1, 4, 11); + drvdata->config.arch = drvdata->arch; /* maximum size of resources */ etmidr2 = readl_relaxed(drvdata->base + TRCIDR2); @@ -780,6 +781,7 @@ static u64 etm4_get_ns_access_type(struct etmv4_config *config) static u64 etm4_get_access_type(struct etmv4_config *config) { u64 access_type = etm4_get_ns_access_type(config); + u64 s_hyp = (config->arch & 0x0f) >= 0x4 ? ETM_EXLEVEL_S_HYP : 0; /* * EXLEVEL_S, bits[11:8], don't trace anything happening @@ -787,7 +789,8 @@ static u64 etm4_get_access_type(struct etmv4_config *config) */ access_type |= (ETM_EXLEVEL_S_APP | ETM_EXLEVEL_S_OS | - ETM_EXLEVEL_S_HYP); + s_hyp | + ETM_EXLEVEL_S_MON); return access_type; } diff --git a/drivers/hwtracing/coresight/coresight-etm4x.h b/drivers/hwtracing/coresight/coresight-etm4x.h index 4523f10ddd0f..60bc2fb5159b 100644 --- a/drivers/hwtracing/coresight/coresight-etm4x.h +++ b/drivers/hwtracing/coresight/coresight-etm4x.h @@ -180,17 +180,22 @@ /* PowerDown Control Register bits */ #define TRCPDCR_PU BIT(3) -/* secure state access levels */ +/* secure state access levels - TRCACATRn */ #define ETM_EXLEVEL_S_APP BIT(8) #define ETM_EXLEVEL_S_OS BIT(9) -#define ETM_EXLEVEL_S_NA BIT(10) -#define ETM_EXLEVEL_S_HYP BIT(11) -/* non-secure state access levels */ +#define ETM_EXLEVEL_S_HYP BIT(10) +#define ETM_EXLEVEL_S_MON BIT(11) +/* non-secure state access levels - TRCACATRn */ #define ETM_EXLEVEL_NS_APP BIT(12) #define ETM_EXLEVEL_NS_OS BIT(13) #define ETM_EXLEVEL_NS_HYP BIT(14) #define ETM_EXLEVEL_NS_NA BIT(15) +/* secure / non secure masks - TRCVICTLR, IDR3 */ +#define ETM_EXLEVEL_S_VICTLR_MASK GENMASK(19, 16) +/* NS MON (EL3) mode never implemented */ +#define ETM_EXLEVEL_NS_VICTLR_MASK GENMASK(22, 20) + /** * struct etmv4_config - configuration information related to an ETMv4 * @mode: Controls various modes supported by this ETM. @@ -237,6 +242,7 @@ * @vmid_mask0: VM ID comparator mask for comparator 0-3. * @vmid_mask1: VM ID comparator mask for comparator 4-7. * @ext_inp: External input selection. + * @arch: ETM architecture version (for arch dependent config). */ struct etmv4_config { u32 mode; @@ -279,6 +285,7 @@ struct etmv4_config { u32 vmid_mask0; u32 vmid_mask1; u32 ext_inp; + u8 arch; }; /** From patchwork Mon Aug 19 20:57:14 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Mike Leach X-Patchwork-Id: 11101933 Return-Path: Received: from mail.kernel.org (pdx-korg-mail-1.web.codeaurora.org [172.30.200.123]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id 46C991813 for ; Mon, 19 Aug 2019 20:59:04 +0000 (UTC) Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id 248AC2087E for ; Mon, 19 Aug 2019 20:59:04 +0000 (UTC) Authentication-Results: mail.kernel.org; dkim=pass (2048-bit key) header.d=lists.infradead.org header.i=@lists.infradead.org header.b="rvSid4gO"; dkim=fail reason="signature verification failed" (2048-bit key) header.d=linaro.org header.i=@linaro.org header.b="NTnzk+XX" DMARC-Filter: OpenDMARC Filter v1.3.2 mail.kernel.org 248AC2087E Authentication-Results: mail.kernel.org; dmarc=fail (p=none dis=none) header.from=linaro.org Authentication-Results: mail.kernel.org; spf=none smtp.mailfrom=linux-arm-kernel-bounces+patchwork-linux-arm=patchwork.kernel.org@lists.infradead.org DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=bombadil.20170209; h=Sender: Content-Transfer-Encoding:Content-Type:MIME-Version:Cc:List-Subscribe: List-Help:List-Post:List-Archive:List-Unsubscribe:List-Id:References: In-Reply-To:Message-Id:Date:Subject:To:From:Reply-To:Content-ID: Content-Description:Resent-Date:Resent-From:Resent-Sender:Resent-To:Resent-Cc :Resent-Message-ID:List-Owner; bh=IEpWMhoB3jcCt9THCkMADVTaGT9TJByRGuTSCwvCQHo=; b=rvSid4gOYK1EbzhCZOxekhA8OH 9iXoQwFnHi1+9Blc6+ROLeDsmmR51/khTtAl99mZdQ4WSHClJAGISo0IWnpDlhRuRBpAYTSEdeu+d k2qDaRLugPMECSAjIgDApCnpCWBDPGy0G6QMKk+7myNvUmIhOlt3keO5U12yVDl4r9Leg3lJTq9d/ kDbzQ3PV1siMtRJoe51Qx2XtgUjdkUkTv23zEFTs5HTIWEI6xbbn5BfFTL2ruvTSXVeBCh6clKXpJ RzLN5g1kIPJajosY+4wJJFa2FLJcLdw8jKbCnkxIfiuqMCk6NYSg/e/8myHnMAQdfZsa1f8yHgFNp Gax+aQpA==; Received: from localhost ([127.0.0.1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.92 #3 (Red Hat Linux)) id 1hzok3-0006dS-Ec; Mon, 19 Aug 2019 20:59:03 +0000 Received: from mail-wr1-x442.google.com ([2a00:1450:4864:20::442]) by bombadil.infradead.org with esmtps (Exim 4.92 #3 (Red Hat Linux)) id 1hzoij-0005Ha-7r for linux-arm-kernel@lists.infradead.org; Mon, 19 Aug 2019 20:57:46 +0000 Received: by mail-wr1-x442.google.com with SMTP id b16so10108435wrq.9 for ; Mon, 19 Aug 2019 13:57:40 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=INjabaSGZPkEn9B72o9FQotjLSWcPzG5kAFJlXBsUZU=; b=NTnzk+XXQyrdoLxrX3R9G318V3+Ap1olLPhWzT7nI0eO0YsYm32Z7T0zozWyDEYTVY Se+k5u4miJRD/TpkPVoPm+WK9ZpTTzLD2Z5qjngL3N2cUmX8azhkoGw/yqkbtIZiqv9K wmxvxvFUB+2UbZb5chFPgq/mq9DzC1UyTp31Kn/sqWrnWIa0nZHPFma1STJgJYGcFfzO /tW/8knnx64D88kHlthu5mo2txvcSBatkUf5Wm9n3kItr9pjwplNLAarHiIbufSvVcXW ZXMD6O+jIvUYhJ9W5k34gqoRNoCHwH6O4Mt6cK3LuNLO9DXAvI7490HFRkOTeEoGiZ6R MNcw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=INjabaSGZPkEn9B72o9FQotjLSWcPzG5kAFJlXBsUZU=; b=j1H8/PvzDDB9KhxYP4vFexhrkXW0Ug3fIwdSbm4lkbA7LkLgWxkkAj9Gj22RH3YG+i KrXbMaDZ6U1VVkNqc6iDHg2qg5H+y4g+X3jrTnp5YqzBYSIzNRNTzmBBZ9rfOSK/Glr8 xn+EbKb8rYSPKsNUvKzzIWv2deQ86AAjw7qtxfvB8V758bdNoidz93TgmLKi49djQ1lD mHIjmwZI/weNvC22gBkcZ7QCb/7rboEraztGxrT2A0pw3CCu2WKl6/MOC7LIzG1wjdc3 6jduWRsGe+T2Ra5UWp12z8X0yc6vgeqdjztQPdwmpDSUIyOSvHU+h7AtM28uQMhq0bgb 4TOQ== X-Gm-Message-State: APjAAAWT7LbFxfxYh56Mu0smRx4Y0Uvxi4S3qZ1ygGBlzuIu50xNCuiv GKOBzJO8MjsHlEyH19H/m1bOiA== X-Google-Smtp-Source: APXvYqyTtzqQbxNT/ix949eUwDwuswz2kLB5wjP//FLB2p4tGFjCXKMJjPgl8U3kGvtn6p5Ch6x3iw== X-Received: by 2002:adf:fdcc:: with SMTP id i12mr30804331wrs.88.1566248259774; Mon, 19 Aug 2019 13:57:39 -0700 (PDT) Received: from linaro.org ([2a00:23c5:6815:3901:247e:6e55:2413:b21c]) by smtp.gmail.com with ESMTPSA id n9sm6698423wrx.76.2019.08.19.13.57.38 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 19 Aug 2019 13:57:39 -0700 (PDT) From: Mike Leach To: mathieu.poirier@linaro.org, linux-arm-kernel@lists.infradead.org, coresight@lists.linaro.org Subject: [PATCH 2/8] coresight: etm4x: Fix input validation for sysfs. Date: Mon, 19 Aug 2019 21:57:14 +0100 Message-Id: <20190819205720.24457-3-mike.leach@linaro.org> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20190819205720.24457-1-mike.leach@linaro.org> References: <20190819205720.24457-1-mike.leach@linaro.org> X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20190819_135741_358991_B98E927B X-CRM114-Status: GOOD ( 12.40 ) X-Spam-Score: -0.2 (/) X-Spam-Report: SpamAssassin version 3.4.2 on bombadil.infradead.org summary: Content analysis details: (-0.2 points) pts rule name description ---- ---------------------- -------------------------------------------------- -0.0 RCVD_IN_DNSWL_NONE RBL: Sender listed at https://www.dnswl.org/, no trust [2a00:1450:4864:20:0:0:0:442 listed in] [list.dnswl.org] -0.0 SPF_PASS SPF: sender matches SPF record 0.0 SPF_HELO_NONE SPF: HELO does not publish an SPF Record -0.1 DKIM_VALID_EF Message has a valid DKIM or DK signature from envelope-from domain -0.1 DKIM_VALID Message has at least one valid DKIM or DK signature -0.1 DKIM_VALID_AU Message has a valid DKIM or DK signature from author's domain 0.1 DKIM_SIGNED Message has a DKIM or DK signature, not necessarily valid X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: suzuki.poulose@arm.com, mike.leach@linaro.org MIME-Version: 1.0 Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+patchwork-linux-arm=patchwork.kernel.org@lists.infradead.org A number of issues are fixed relating to sysfs input validation:- 1) bb_ctrl_store() - incorrect compare of bit select field to absolute value. Reworked per ETMv4 specification. 2) seq_event_store() - incorrect mask value - register has two event values. 3) cyc_threshold_store() - must mask with max before checking min otherwise wrapped values can set illegal value below min. 4) res_ctrl_store() - update to mask off all res0 bits. Signed-off-by: Mike Leach Reviewed-by: Mathieu Poirier Reviewed-by: Leo Yan --- .../coresight/coresight-etm4x-sysfs.c | 21 ++++++++++++------- 1 file changed, 13 insertions(+), 8 deletions(-) diff --git a/drivers/hwtracing/coresight/coresight-etm4x-sysfs.c b/drivers/hwtracing/coresight/coresight-etm4x-sysfs.c index b6984be0c515..fa1d6a938f6c 100644 --- a/drivers/hwtracing/coresight/coresight-etm4x-sysfs.c +++ b/drivers/hwtracing/coresight/coresight-etm4x-sysfs.c @@ -652,10 +652,13 @@ static ssize_t cyc_threshold_store(struct device *dev, if (kstrtoul(buf, 16, &val)) return -EINVAL; + + /* mask off max threshold before checking min value */ + val &= ETM_CYC_THRESHOLD_MASK; if (val < drvdata->ccitmin) return -EINVAL; - config->ccctlr = val & ETM_CYC_THRESHOLD_MASK; + config->ccctlr = val; return size; } static DEVICE_ATTR_RW(cyc_threshold); @@ -686,14 +689,16 @@ static ssize_t bb_ctrl_store(struct device *dev, return -EINVAL; if (!drvdata->nr_addr_cmp) return -EINVAL; + /* - * Bit[7:0] selects which address range comparator is used for - * branch broadcast control. + * Bit[8] controls include(1) / exclude(0), bits[0-7] select + * individual range comparators. If include then at least 1 + * range must be selected. */ - if (BMVAL(val, 0, 7) > drvdata->nr_addr_cmp) + if ((val & BIT(8)) && (BMVAL(val, 0, 7) == 0)) return -EINVAL; - config->bb_ctrl = val; + config->bb_ctrl = val & GENMASK(8, 0); return size; } static DEVICE_ATTR_RW(bb_ctrl); @@ -1324,8 +1329,8 @@ static ssize_t seq_event_store(struct device *dev, spin_lock(&drvdata->spinlock); idx = config->seq_idx; - /* RST, bits[7:0] */ - config->seq_ctrl[idx] = val & 0xFF; + /* Seq control has two masks B[15:5] F[7:0] */ + config->seq_ctrl[idx] = val & 0xFFFF; spin_unlock(&drvdata->spinlock); return size; } @@ -1580,7 +1585,7 @@ static ssize_t res_ctrl_store(struct device *dev, if (idx % 2 != 0) /* PAIRINV, bit[21] */ val &= ~BIT(21); - config->res_ctrl[idx] = val; + config->res_ctrl[idx] = val & GENMASK(21, 0); spin_unlock(&drvdata->spinlock); return size; } From patchwork Mon Aug 19 20:57:15 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Mike Leach X-Patchwork-Id: 11101939 Return-Path: Received: from mail.kernel.org (pdx-korg-mail-1.web.codeaurora.org [172.30.200.123]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id 779211398 for ; Mon, 19 Aug 2019 20:59:49 +0000 (UTC) Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id 4757522CEC for ; Mon, 19 Aug 2019 20:59:49 +0000 (UTC) Authentication-Results: mail.kernel.org; dkim=pass (2048-bit key) header.d=lists.infradead.org header.i=@lists.infradead.org header.b="C+ipRTx8"; dkim=fail reason="signature verification failed" (2048-bit key) header.d=linaro.org header.i=@linaro.org header.b="rEAy1qMI" DMARC-Filter: OpenDMARC Filter v1.3.2 mail.kernel.org 4757522CEC Authentication-Results: mail.kernel.org; dmarc=fail (p=none dis=none) header.from=linaro.org Authentication-Results: mail.kernel.org; spf=none smtp.mailfrom=linux-arm-kernel-bounces+patchwork-linux-arm=patchwork.kernel.org@lists.infradead.org DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=bombadil.20170209; h=Sender: Content-Transfer-Encoding:Content-Type:MIME-Version:Cc:List-Subscribe: List-Help:List-Post:List-Archive:List-Unsubscribe:List-Id:References: In-Reply-To:Message-Id:Date:Subject:To:From:Reply-To:Content-ID: Content-Description:Resent-Date:Resent-From:Resent-Sender:Resent-To:Resent-Cc :Resent-Message-ID:List-Owner; bh=uLgFVwZHQk2IOTXT0FWlc933SycsiI3wekmnZRd8JXU=; b=C+ipRTx81fQfZvwgXtRrrLC90T X91ArbYrRTjaWv+KGhCvyp2+6tzxrvkHRMUHfM4nPWGW0wRKQxudxsTeXBgHJQcRqiNz5bA/jpMkA jA8NeQ+r1pnDpPkGjDjlu+ztl3RAD7OxLHwA9F/OtGVvqQzTNkhj/8WR+9DQU9W4lGtA8gjsj+T// jcN9gxMYonlA97nYSOj3l8497pccIzB6JDE+zdbICgboMNkFjRKwy/LObXgFbnJmMLOrdjn7MRgkL 0NUju1gspMm/mJ5rHunrJEffIJBoNIlnZ2djESKRn16awr5P22nJENDB4ORMvE5JDOUc7eiCdmJDj JbCYv3HA==; Received: from localhost ([127.0.0.1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.92 #3 (Red Hat Linux)) id 1hzokm-0007Zh-Ly; Mon, 19 Aug 2019 20:59:48 +0000 Received: from mail-wr1-x443.google.com ([2a00:1450:4864:20::443]) by bombadil.infradead.org with esmtps (Exim 4.92 #3 (Red Hat Linux)) id 1hzoim-0005IF-Nf for linux-arm-kernel@lists.infradead.org; Mon, 19 Aug 2019 20:57:48 +0000 Received: by mail-wr1-x443.google.com with SMTP id z11so10116559wrt.4 for ; Mon, 19 Aug 2019 13:57:41 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=tZjDuINKZVADY8hFckbdEg/JuW5ruTkY0MkR12ux+y8=; b=rEAy1qMIvoJ+nkeHLNwmZcxzPiNOKTgM2UYbLYy+E83UyTvNCacwhQPL05uJKsOS9H 5kiv2cSx5N8tPsyS0WdQIueq9P1OjNLEzRSGQNI+iQZzrwWOpB6ROn67gVyoxZMkdvkC 54gaOjqBiXp5JQIco/z1t0WKBPeCLPp3cvn3Qym/KcS3D7dae1rcNJO2/hynCFDH0am1 pDglPhSF50jMv+voW4BKRD2yoM8sA07EJSM7dcnOlItD273ZlPUpgHOAZii+kWa4Kwxb BtQzd5LkUiiF+LgaHyPjUtNncuvzW3ZWJSkXqeQHdeaBXB8nFmR7un6DT3yJWYuxnify MCCA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=tZjDuINKZVADY8hFckbdEg/JuW5ruTkY0MkR12ux+y8=; b=QLCro4Tmlr9OonrZBTV98hA/4DTYSAWSHQDAoMMzLAGxV8DJnEIRP87PeCNfj4InCb uIQhGvYXIvw1SEQShGjuZopPB2g0jNI22Q9S556IBEUCFxMdjaYu7bERVkxiiQ/M16OU VkpYg7yl2ZjwpCrxuLBKxSYhRckcU4l40tuJruzICEuylqtbP5Yr1SPcCnm76hbSp9R/ iXBgW9ja4A9XdXQHfZbkDiaKqBZgf8ytyGSbnMXdzuQKWl/MAWg/wejhuUsrrCIojPBF quMVlFdR5ks6n7tFWpB3WVHhlvTl+BQRJkcc5APl1B23vRbpflKZ06aRgs4EFV4dEaLp TSoQ== X-Gm-Message-State: APjAAAXfckf0R1ZbdXAF02VpF4BJiGp5ieTdRjawU6oJzwtRzCMICT2L PsENm889DzfNAK/uk/VhvoTgrQ== X-Google-Smtp-Source: APXvYqyga+92Y/kSuU5nRch9r2MUMH7THNMXRYEAuo/i+1tIU6nw75rqqn1zGTpKQNCR6eMHrvyx3w== X-Received: by 2002:adf:a348:: with SMTP id d8mr30703662wrb.235.1566248260540; Mon, 19 Aug 2019 13:57:40 -0700 (PDT) Received: from linaro.org ([2a00:23c5:6815:3901:247e:6e55:2413:b21c]) by smtp.gmail.com with ESMTPSA id n9sm6698423wrx.76.2019.08.19.13.57.39 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 19 Aug 2019 13:57:40 -0700 (PDT) From: Mike Leach To: mathieu.poirier@linaro.org, linux-arm-kernel@lists.infradead.org, coresight@lists.linaro.org Subject: [PATCH 3/8] coresight: etm4x: Add missing API to set EL match on address filters Date: Mon, 19 Aug 2019 21:57:15 +0100 Message-Id: <20190819205720.24457-4-mike.leach@linaro.org> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20190819205720.24457-1-mike.leach@linaro.org> References: <20190819205720.24457-1-mike.leach@linaro.org> X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20190819_135744_867608_B5F8F05F X-CRM114-Status: GOOD ( 11.00 ) X-Spam-Score: -0.2 (/) X-Spam-Report: SpamAssassin version 3.4.2 on bombadil.infradead.org summary: Content analysis details: (-0.2 points) pts rule name description ---- ---------------------- -------------------------------------------------- -0.0 RCVD_IN_DNSWL_NONE RBL: Sender listed at https://www.dnswl.org/, no trust [2a00:1450:4864:20:0:0:0:443 listed in] [list.dnswl.org] -0.0 SPF_PASS SPF: sender matches SPF record 0.0 SPF_HELO_NONE SPF: HELO does not publish an SPF Record -0.1 DKIM_VALID_EF Message has a valid DKIM or DK signature from envelope-from domain -0.1 DKIM_VALID Message has at least one valid DKIM or DK signature -0.1 DKIM_VALID_AU Message has a valid DKIM or DK signature from author's domain 0.1 DKIM_SIGNED Message has a DKIM or DK signature, not necessarily valid X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: suzuki.poulose@arm.com, mike.leach@linaro.org MIME-Version: 1.0 Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+patchwork-linux-arm=patchwork.kernel.org@lists.infradead.org TRCACATRn registers have match bits for secure and non-secure exception levels which are not accessible by the sysfs API. This adds a new sysfs parameter to enable this - addr_exlevel_s_ns. Signed-off-by: Mike Leach --- .../coresight/coresight-etm4x-sysfs.c | 39 +++++++++++++++++++ 1 file changed, 39 insertions(+) diff --git a/drivers/hwtracing/coresight/coresight-etm4x-sysfs.c b/drivers/hwtracing/coresight/coresight-etm4x-sysfs.c index fa1d6a938f6c..7eab5d7d0b62 100644 --- a/drivers/hwtracing/coresight/coresight-etm4x-sysfs.c +++ b/drivers/hwtracing/coresight/coresight-etm4x-sysfs.c @@ -1233,6 +1233,44 @@ static ssize_t addr_context_store(struct device *dev, } static DEVICE_ATTR_RW(addr_context); +static ssize_t addr_exlevel_s_ns_show(struct device *dev, + struct device_attribute *attr, + char *buf) +{ + u8 idx; + unsigned long val; + struct etmv4_drvdata *drvdata = dev_get_drvdata(dev->parent); + struct etmv4_config *config = &drvdata->config; + + spin_lock(&drvdata->spinlock); + idx = config->addr_idx; + val = BMVAL(config->addr_acc[idx], 14, 8); + spin_unlock(&drvdata->spinlock); + return scnprintf(buf, PAGE_SIZE, "%#lx\n", val); +} + +static ssize_t addr_exlevel_s_ns_store(struct device *dev, + struct device_attribute *attr, + const char *buf, size_t size) +{ + u8 idx; + unsigned long val; + struct etmv4_drvdata *drvdata = dev_get_drvdata(dev->parent); + struct etmv4_config *config = &drvdata->config; + + if (kstrtoul(buf, 16, &val)) + return -EINVAL; + + spin_lock(&drvdata->spinlock); + idx = config->addr_idx; + /* clear Exlevel_ns & Exlevel_s bits[14:12, 11:8] */ + config->addr_acc[idx] &= ~(GENMASK(14, 8)); + config->addr_acc[idx] |= (val << 8); + spin_unlock(&drvdata->spinlock); + return size; +} +static DEVICE_ATTR_RW(addr_exlevel_s_ns); + static ssize_t seq_idx_show(struct device *dev, struct device_attribute *attr, char *buf) @@ -2038,6 +2076,7 @@ static struct attribute *coresight_etmv4_attrs[] = { &dev_attr_addr_stop.attr, &dev_attr_addr_ctxtype.attr, &dev_attr_addr_context.attr, + &dev_attr_addr_exlevel_s_ns.attr, &dev_attr_seq_idx.attr, &dev_attr_seq_state.attr, &dev_attr_seq_event.attr, From patchwork Mon Aug 19 20:57:16 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Mike Leach X-Patchwork-Id: 11101931 Return-Path: Received: from mail.kernel.org (pdx-korg-mail-1.web.codeaurora.org [172.30.200.123]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id 76D2C912 for ; Mon, 19 Aug 2019 20:58:48 +0000 (UTC) Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id 555D12087E for ; Mon, 19 Aug 2019 20:58:48 +0000 (UTC) Authentication-Results: mail.kernel.org; dkim=pass (2048-bit key) header.d=lists.infradead.org header.i=@lists.infradead.org header.b="fl7EyFjd"; dkim=fail reason="signature verification failed" (2048-bit key) header.d=linaro.org header.i=@linaro.org header.b="XPrCyM8w" DMARC-Filter: OpenDMARC Filter v1.3.2 mail.kernel.org 555D12087E Authentication-Results: mail.kernel.org; dmarc=fail (p=none dis=none) header.from=linaro.org Authentication-Results: mail.kernel.org; spf=none smtp.mailfrom=linux-arm-kernel-bounces+patchwork-linux-arm=patchwork.kernel.org@lists.infradead.org DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=bombadil.20170209; h=Sender: Content-Transfer-Encoding:Content-Type:MIME-Version:Cc:List-Subscribe: List-Help:List-Post:List-Archive:List-Unsubscribe:List-Id:References: In-Reply-To:Message-Id:Date:Subject:To:From:Reply-To:Content-ID: Content-Description:Resent-Date:Resent-From:Resent-Sender:Resent-To:Resent-Cc :Resent-Message-ID:List-Owner; bh=+uv1KJREAelw9J2bZpxTWP61C4inb5CLvzQAZf73GnA=; b=fl7EyFjdadVK1OFA8GRL8+ugBd sSPDjS29sqBq8AP/8zP913xFsdXHZjjNd9y7GpZrPyVgo0aRFTaMurmwJgkXLhQYDKLVY7hw03LFg SBx7+r9YrTvvd8AhLJ9/cdBl5CFUbHj8qe89peAd7t2UvyRjJI+by013g1vUo7r/MDvzov3dJ6rqQ 1dHX0lYlJdvLOYftWfIl1CnN3ucV7X2Y2ZPbbV+ioUi9JsV4Gbmow2PA03fdH0/uJ3K15+bLZTyOg ffsooCKsrfKu8gKaVwR33jWhxVblAvQsFRFB9vq/mjSQQ5So87X3AMKENLtzk90XcJZcekOEhY5+j rdE7sPZg==; Received: from localhost ([127.0.0.1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.92 #3 (Red Hat Linux)) id 1hzojn-0006JM-K7; Mon, 19 Aug 2019 20:58:47 +0000 Received: from mail-wr1-x442.google.com ([2a00:1450:4864:20::442]) by bombadil.infradead.org with esmtps (Exim 4.92 #3 (Red Hat Linux)) id 1hzoik-0005Jg-NA for linux-arm-kernel@lists.infradead.org; Mon, 19 Aug 2019 20:57:46 +0000 Received: by mail-wr1-x442.google.com with SMTP id j16so10104025wrr.8 for ; Mon, 19 Aug 2019 13:57:42 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=HETJqMmXH/Vh/v0MKmFkWUVEJbYhaPbpt5CvCKS+cYY=; b=XPrCyM8wjGvuKRTCe+5cGMRhhPNWj1huHLUdq0lIo2XnG0Rr/82xNRGXEi2fMywDa5 lw4IqDMBGPBW9BLM2pSujVIVmMpNbn/47ZcarrdRj8qXwjRx+TttF94RoeJWpxvdzcSO zWG+E0ljBe2SqwuSBtX0NyZE4vNBNbSNZ05BU7iySkCtpnm25hHwdBkmlpyE6eKKMG0l u5vlBCuryKqyzygKWQUwVuOBw3nJVVkVOC52S3H+IS+eq4vp7K6axQetqdWHTU9ANYG0 eCjg75E+P9QFhfbQwbeTxuAR203/mfG13OcjmHN2uWGYZsrNXbWxAHMT76ems50+odMO 2CwA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=HETJqMmXH/Vh/v0MKmFkWUVEJbYhaPbpt5CvCKS+cYY=; b=UahJDun/3O8lp5+WY0PwDMiB8h9hW54cJzdNtHx7kYqh+BtZ2QN72E3TR4xW2wCTP3 R+p3IQIDYrHy/y59OF3YZ627BnQviEfHbRMOGWFs5CRJtnKAoJ9Kao9JB91GQpPM3aQW Q+mDloPP0B2aqQl3S8UbLIusSBB/xtUgG3+a/3siVf77+x7d3KwIEdlSokCkpRGkH+n0 D/8nyjnFV9aZSqngXWSvWm5Ct9dYjGB8axZjyyv858Ob06eZ8OqhbLaA/A5ExidFMeG4 K0nU7pdr204dM0sN2nX9d2Li1+HzBa884ZTxIZxIcnUCrAFtW4Pdz2hKaBeT161ET8tT 1htg== X-Gm-Message-State: APjAAAWGlg+mlG6j86uKsqENg1wRO1xoKxnzXntJxaedkT0eQ9wPz0yL EXEBrm4PgbgBdvpbgDZVNwR0Ng== X-Google-Smtp-Source: APXvYqxnNSfp/w/bnJEd/xhsB8E+zCWpUdGWXIrxmQ5D56UB6C+2oQ5KrtbAb1oXZCXiahXq+ID4OA== X-Received: by 2002:adf:8541:: with SMTP id 59mr29456251wrh.298.1566248261435; Mon, 19 Aug 2019 13:57:41 -0700 (PDT) Received: from linaro.org ([2a00:23c5:6815:3901:247e:6e55:2413:b21c]) by smtp.gmail.com with ESMTPSA id n9sm6698423wrx.76.2019.08.19.13.57.40 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 19 Aug 2019 13:57:40 -0700 (PDT) From: Mike Leach To: mathieu.poirier@linaro.org, linux-arm-kernel@lists.infradead.org, coresight@lists.linaro.org Subject: [PATCH 4/8] coresight: etm4x: Fix issues with start-stop logic. Date: Mon, 19 Aug 2019 21:57:16 +0100 Message-Id: <20190819205720.24457-5-mike.leach@linaro.org> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20190819205720.24457-1-mike.leach@linaro.org> References: <20190819205720.24457-1-mike.leach@linaro.org> X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20190819_135742_934271_E714C9A1 X-CRM114-Status: GOOD ( 15.38 ) X-Spam-Score: -0.2 (/) X-Spam-Report: SpamAssassin version 3.4.2 on bombadil.infradead.org summary: Content analysis details: (-0.2 points) pts rule name description ---- ---------------------- -------------------------------------------------- -0.0 RCVD_IN_DNSWL_NONE RBL: Sender listed at https://www.dnswl.org/, no trust [2a00:1450:4864:20:0:0:0:442 listed in] [list.dnswl.org] -0.0 SPF_PASS SPF: sender matches SPF record 0.0 SPF_HELO_NONE SPF: HELO does not publish an SPF Record -0.1 DKIM_VALID_EF Message has a valid DKIM or DK signature from envelope-from domain -0.1 DKIM_VALID Message has at least one valid DKIM or DK signature -0.1 DKIM_VALID_AU Message has a valid DKIM or DK signature from author's domain 0.1 DKIM_SIGNED Message has a DKIM or DK signature, not necessarily valid X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: suzuki.poulose@arm.com, mike.leach@linaro.org MIME-Version: 1.0 Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+patchwork-linux-arm=patchwork.kernel.org@lists.infradead.org Fixes the following issues when using the ETMv4 start-stop logic. 1) Setting a start or a stop address should not automatically set the start-stop status to 'on'. The value set by the user in 'mode' must be respected or start instances could be missed. 2) Missing API for controlling TRCVIPCSSCTLR - start stop control by PE comparators. 3) Default ETM configuration sets a trace all range, and correctly sets the start-stop status bit. This was not being correctly reflected in the 'mode' parameter. Signed-off-by: Mike Leach --- .../coresight/coresight-etm4x-sysfs.c | 39 +++++++++++++++++-- drivers/hwtracing/coresight/coresight-etm4x.c | 1 + 2 files changed, 36 insertions(+), 4 deletions(-) diff --git a/drivers/hwtracing/coresight/coresight-etm4x-sysfs.c b/drivers/hwtracing/coresight/coresight-etm4x-sysfs.c index 7eab5d7d0b62..3bcc260c9e55 100644 --- a/drivers/hwtracing/coresight/coresight-etm4x-sysfs.c +++ b/drivers/hwtracing/coresight/coresight-etm4x-sysfs.c @@ -217,6 +217,7 @@ static ssize_t reset_store(struct device *dev, /* No start-stop filtering for ViewInst */ config->vissctlr = 0x0; + config->vipcssctlr = 0x0; /* Disable seq events */ for (i = 0; i < drvdata->nrseqstate-1; i++) @@ -1059,8 +1060,6 @@ static ssize_t addr_start_store(struct device *dev, config->addr_val[idx] = (u64)val; config->addr_type[idx] = ETM_ADDR_TYPE_START; config->vissctlr |= BIT(idx); - /* SSSTATUS, bit[9] - turn on start/stop logic */ - config->vinst_ctrl |= BIT(9); spin_unlock(&drvdata->spinlock); return size; } @@ -1116,8 +1115,6 @@ static ssize_t addr_stop_store(struct device *dev, config->addr_val[idx] = (u64)val; config->addr_type[idx] = ETM_ADDR_TYPE_STOP; config->vissctlr |= BIT(idx + 16); - /* SSSTATUS, bit[9] - turn on start/stop logic */ - config->vinst_ctrl |= BIT(9); spin_unlock(&drvdata->spinlock); return size; } @@ -1271,6 +1268,39 @@ static ssize_t addr_exlevel_s_ns_store(struct device *dev, } static DEVICE_ATTR_RW(addr_exlevel_s_ns); +static ssize_t vinst_pe_cmp_start_stop_show(struct device *dev, + struct device_attribute *attr, + char *buf) +{ + unsigned long val; + struct etmv4_drvdata *drvdata = dev_get_drvdata(dev->parent); + struct etmv4_config *config = &drvdata->config; + + if (!drvdata->nr_pe_cmp) + return -EINVAL; + val = config->vipcssctlr; + return scnprintf(buf, PAGE_SIZE, "%#lx\n", val); +} +static ssize_t vinst_pe_cmp_start_stop_store(struct device *dev, + struct device_attribute *attr, + const char *buf, size_t size) +{ + unsigned long val; + struct etmv4_drvdata *drvdata = dev_get_drvdata(dev->parent); + struct etmv4_config *config = &drvdata->config; + + if (kstrtoul(buf, 16, &val)) + return -EINVAL; + if (!drvdata->nr_pe_cmp) + return -EINVAL; + + spin_lock(&drvdata->spinlock); + config->vipcssctlr = val; + spin_unlock(&drvdata->spinlock); + return size; +} +static DEVICE_ATTR_RW(vinst_pe_cmp_start_stop); + static ssize_t seq_idx_show(struct device *dev, struct device_attribute *attr, char *buf) @@ -2077,6 +2107,7 @@ static struct attribute *coresight_etmv4_attrs[] = { &dev_attr_addr_ctxtype.attr, &dev_attr_addr_context.attr, &dev_attr_addr_exlevel_s_ns.attr, + &dev_attr_vinst_pe_cmp_start_stop.attr, &dev_attr_seq_idx.attr, &dev_attr_seq_state.attr, &dev_attr_seq_event.attr, diff --git a/drivers/hwtracing/coresight/coresight-etm4x.c b/drivers/hwtracing/coresight/coresight-etm4x.c index 52b8876de157..d8b078d0cc7f 100644 --- a/drivers/hwtracing/coresight/coresight-etm4x.c +++ b/drivers/hwtracing/coresight/coresight-etm4x.c @@ -868,6 +868,7 @@ static void etm4_set_default_filter(struct etmv4_config *config) * in the started state */ config->vinst_ctrl |= BIT(9); + config->mode |= ETM_MODE_VIEWINST_STARTSTOP; /* No start-stop filtering for ViewInst */ config->vissctlr = 0x0; From patchwork Mon Aug 19 20:57:17 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Mike Leach X-Patchwork-Id: 11101935 Return-Path: Received: from mail.kernel.org (pdx-korg-mail-1.web.codeaurora.org [172.30.200.123]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id 7AAF2912 for ; Mon, 19 Aug 2019 20:59:20 +0000 (UTC) Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id 59BF922CEC for ; Mon, 19 Aug 2019 20:59:20 +0000 (UTC) Authentication-Results: mail.kernel.org; dkim=pass (2048-bit key) header.d=lists.infradead.org header.i=@lists.infradead.org header.b="SAb/k3Dw"; dkim=fail reason="signature verification failed" (2048-bit key) header.d=linaro.org header.i=@linaro.org header.b="yiAT2eAK" DMARC-Filter: OpenDMARC Filter v1.3.2 mail.kernel.org 59BF922CEC Authentication-Results: mail.kernel.org; dmarc=fail (p=none dis=none) header.from=linaro.org Authentication-Results: mail.kernel.org; spf=none smtp.mailfrom=linux-arm-kernel-bounces+patchwork-linux-arm=patchwork.kernel.org@lists.infradead.org DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=bombadil.20170209; h=Sender: Content-Transfer-Encoding:Content-Type:MIME-Version:Cc:List-Subscribe: List-Help:List-Post:List-Archive:List-Unsubscribe:List-Id:References: In-Reply-To:Message-Id:Date:Subject:To:From:Reply-To:Content-ID: Content-Description:Resent-Date:Resent-From:Resent-Sender:Resent-To:Resent-Cc :Resent-Message-ID:List-Owner; bh=g4xLFN0dpzweEpmkl609d1GF03ZlNLUpiphuqih09II=; b=SAb/k3Dw5kdQuEKHWljbuQO20+ P3a/8NuJ3nI0kx7Bjb0jECKcUToq0MIBwfpBtnVuUiLlRDcTUh65uD5KRue9HJI7Kjhy08hJ9faJC A5o9rFDvVK2yPRt2q/Tx+avlnoxbEl/dKFK1tCALwI1lD4eGwj1TZfz1gCtBaR88VGWFaPthJ3NLO kxJRnm3ZsT00ZedhUZgah5NypPTVcZz8U+hyd+9d9DEq69StSZqwpbA1lWm1kike5XrdMKjarP94F eH3fCoidGJ0TC/RdIZ1N0wNwgDzTffNQVo0zHXp6sE84Aj1UwoKcpOZw/1cepUXbiIHJwcLj3nKbu yaAaX1hw==; Received: from localhost ([127.0.0.1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.92 #3 (Red Hat Linux)) id 1hzokJ-0006sG-TS; Mon, 19 Aug 2019 20:59:19 +0000 Received: from mail-wr1-x441.google.com ([2a00:1450:4864:20::441]) by bombadil.infradead.org with esmtps (Exim 4.92 #3 (Red Hat Linux)) id 1hzoil-0005KM-EA for linux-arm-kernel@lists.infradead.org; Mon, 19 Aug 2019 20:57:46 +0000 Received: by mail-wr1-x441.google.com with SMTP id y8so10103462wrn.10 for ; Mon, 19 Aug 2019 13:57:43 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=CCul2VKIQZgegoP3u6Okg21ECz48xu4t9dJfpkQ2azg=; b=yiAT2eAKB3FXdoNQbJ9+VFnq7DZsit1uHZRu6LtysPLLPYT2bqCUIF9ejwFv+Qa4Ng nb4VCeUHi05ShNj0QU/8VeTRa7VdMJNHQan0ev+6T+SwN2quNZREqfhPdz3aKhFjZp5M w8y1tKDOJ6ptLoZWll0v7uj2c6VMhVehIx641LGt+6TgvIB6zNedDUWjY8vvcL4DL0DE lpxIkmQIsAldcCFXRdgW1bqyBovJLIrtP8ma1fLWPvNrWfUXEosepKyaKvK+rsMsBSRD JxV6GsQ6sCpuKrfJ2PofWlYizwLEj9mbVDIavu0LF0emZJGJnfSGvLiWT4syEzTlIeZ2 lF+g== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=CCul2VKIQZgegoP3u6Okg21ECz48xu4t9dJfpkQ2azg=; b=VX57mEBCQgztTS+s/y1fQq3tWVmASMEvXQ6YN3JOUMvWO5L9oceB78rwmXosjnJEGs a8ilHgA6NEsD0DU+8NVqvGJVHhZud9Iw/ZCU2ItI0NJODLiIiU4JQV1lm+vvglCgeeZ8 5pO18yPRdEtd6qE6KnTS0nErApU7QkJVMQ6peu22GjSVVdTKdujwShUP8N3sc97/zJtn 0JMgCCmQ9oFZNS7GVZFcI2XKHnb5yrd7JQbNmhBckluUjS2ZwCgl6uFiuFXujtACnwmS aAEW5vbOmajOz/ABo3lF59A5OxZty2u34aywqTW7npCS2Diq87tTTkszjltmVGh64R33 wTiQ== X-Gm-Message-State: APjAAAVL1vELdQ8PpLjDTgh7FmX6GnUQx5DE1ICh67I+eeBqPBrUlmxU uzjhv5h6E/nyIfBpZsYCGA2Z3Iqz/5w= X-Google-Smtp-Source: APXvYqwppDxb1CunFRcf3DDFG7GuwWBeMabtjmVdVgXFy0ayP6VnzrYS248hqoRYYoOqT+5FKi+mFA== X-Received: by 2002:adf:eac5:: with SMTP id o5mr31138765wrn.140.1566248262212; Mon, 19 Aug 2019 13:57:42 -0700 (PDT) Received: from linaro.org ([2a00:23c5:6815:3901:247e:6e55:2413:b21c]) by smtp.gmail.com with ESMTPSA id n9sm6698423wrx.76.2019.08.19.13.57.41 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 19 Aug 2019 13:57:41 -0700 (PDT) From: Mike Leach To: mathieu.poirier@linaro.org, linux-arm-kernel@lists.infradead.org, coresight@lists.linaro.org Subject: [PATCH 5/8] coresight: etm4x: Improve usability of sysfs API. Date: Mon, 19 Aug 2019 21:57:17 +0100 Message-Id: <20190819205720.24457-6-mike.leach@linaro.org> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20190819205720.24457-1-mike.leach@linaro.org> References: <20190819205720.24457-1-mike.leach@linaro.org> X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20190819_135743_625682_0614F4C7 X-CRM114-Status: GOOD ( 16.95 ) X-Spam-Score: -0.2 (/) X-Spam-Report: SpamAssassin version 3.4.2 on bombadil.infradead.org summary: Content analysis details: (-0.2 points) pts rule name description ---- ---------------------- -------------------------------------------------- -0.0 RCVD_IN_DNSWL_NONE RBL: Sender listed at https://www.dnswl.org/, no trust [2a00:1450:4864:20:0:0:0:441 listed in] [list.dnswl.org] -0.0 SPF_PASS SPF: sender matches SPF record 0.0 SPF_HELO_NONE SPF: HELO does not publish an SPF Record -0.1 DKIM_VALID_EF Message has a valid DKIM or DK signature from envelope-from domain -0.1 DKIM_VALID Message has at least one valid DKIM or DK signature -0.1 DKIM_VALID_AU Message has a valid DKIM or DK signature from author's domain 0.1 DKIM_SIGNED Message has a DKIM or DK signature, not necessarily valid X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: suzuki.poulose@arm.com, mike.leach@linaro.org MIME-Version: 1.0 Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+patchwork-linux-arm=patchwork.kernel.org@lists.infradead.org Some changes to make the sysfs programming more intuitive. 1) Setting include / exclude on a range had to be done by setting the bit in 'mode' before setting the range. However, setting this bit also had the effect of altering the current range as well. Changed to only set include / exclude setting of a range at the point of setting that range. Either use a 3rd input parameter as the include exclude value, or if not present use the current value of 'mode'. Do not change current range when 'mode' changes. 2) Context ID and VM ID masks required 2 value inputs, even when the second value is ignored as insufficient CID / VMID comparators are implemented. Permit a single value to be used if that is sufficient to cover all implemented comparators. Signed-off-by: Mike Leach Reviewed-by: Mathieu Poirier --- .../coresight/coresight-etm4x-sysfs.c | 24 +++++++++++++------ 1 file changed, 17 insertions(+), 7 deletions(-) diff --git a/drivers/hwtracing/coresight/coresight-etm4x-sysfs.c b/drivers/hwtracing/coresight/coresight-etm4x-sysfs.c index 3bcc260c9e55..baac5b48b7ac 100644 --- a/drivers/hwtracing/coresight/coresight-etm4x-sysfs.c +++ b/drivers/hwtracing/coresight/coresight-etm4x-sysfs.c @@ -297,8 +297,6 @@ static ssize_t mode_store(struct device *dev, spin_lock(&drvdata->spinlock); config->mode = val & ETMv4_MODE_ALL; - etm4_set_mode_exclude(drvdata, - config->mode & ETM_MODE_EXCLUDE ? true : false); if (drvdata->instrp0 == true) { /* start by clearing instruction P0 field */ @@ -972,8 +970,12 @@ static ssize_t addr_range_store(struct device *dev, unsigned long val1, val2; struct etmv4_drvdata *drvdata = dev_get_drvdata(dev->parent); struct etmv4_config *config = &drvdata->config; + int elements, exclude; - if (sscanf(buf, "%lx %lx", &val1, &val2) != 2) + elements = sscanf(buf, "%lx %lx %x", &val1, &val2, &exclude); + + /* exclude is optional, but need at least two parameter */ + if (elements < 2) return -EINVAL; /* lower address comparator cannot have a higher address value */ if (val1 > val2) @@ -1001,9 +1003,11 @@ static ssize_t addr_range_store(struct device *dev, /* * Program include or exclude control bits for vinst or vdata * whenever we change addr comparators to ETM_ADDR_TYPE_RANGE + * use supplied value, or default to bit set in 'mode' */ - etm4_set_mode_exclude(drvdata, - config->mode & ETM_MODE_EXCLUDE ? true : false); + if (elements != 3) + exclude = config->mode & ETM_MODE_EXCLUDE; + etm4_set_mode_exclude(drvdata, exclude ? true : false); spin_unlock(&drvdata->spinlock); return size; @@ -1787,6 +1791,7 @@ static ssize_t ctxid_masks_store(struct device *dev, unsigned long val1, val2, mask; struct etmv4_drvdata *drvdata = dev_get_drvdata(dev->parent); struct etmv4_config *config = &drvdata->config; + int nr_inputs; /* * Don't use contextID tracing if coming from a PID namespace. See @@ -1802,7 +1807,9 @@ static ssize_t ctxid_masks_store(struct device *dev, */ if (!drvdata->ctxid_size || !drvdata->numcidc) return -EINVAL; - if (sscanf(buf, "%lx %lx", &val1, &val2) != 2) + /* one mask if < 4 comparators, two for up to 8 */ + nr_inputs = sscanf(buf, "%lx %lx", &val1, &val2); + if ((drvdata->numcidc > 4) && (nr_inputs != 2)) return -EINVAL; spin_lock(&drvdata->spinlock); @@ -1976,6 +1983,7 @@ static ssize_t vmid_masks_store(struct device *dev, unsigned long val1, val2, mask; struct etmv4_drvdata *drvdata = dev_get_drvdata(dev->parent); struct etmv4_config *config = &drvdata->config; + int nr_inputs; /* * only implemented when vmid tracing is enabled, i.e. at least one @@ -1983,7 +1991,9 @@ static ssize_t vmid_masks_store(struct device *dev, */ if (!drvdata->vmid_size || !drvdata->numvmidc) return -EINVAL; - if (sscanf(buf, "%lx %lx", &val1, &val2) != 2) + /* one mask if < 4 comparators, two for up to 8 */ + nr_inputs = sscanf(buf, "%lx %lx", &val1, &val2); + if ((drvdata->numvmidc > 4) && (nr_inputs != 2)) return -EINVAL; spin_lock(&drvdata->spinlock); From patchwork Mon Aug 19 20:57:18 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Mike Leach X-Patchwork-Id: 11101941 Return-Path: Received: from mail.kernel.org (pdx-korg-mail-1.web.codeaurora.org [172.30.200.123]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id 57B871398 for ; Mon, 19 Aug 2019 21:00:05 +0000 (UTC) Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id 374832087E for ; Mon, 19 Aug 2019 21:00:05 +0000 (UTC) Authentication-Results: mail.kernel.org; dkim=pass (2048-bit key) header.d=lists.infradead.org header.i=@lists.infradead.org header.b="iGY3EcER"; dkim=fail reason="signature verification failed" (2048-bit key) header.d=linaro.org header.i=@linaro.org header.b="KV8XQCe0" DMARC-Filter: OpenDMARC Filter v1.3.2 mail.kernel.org 374832087E Authentication-Results: mail.kernel.org; dmarc=fail (p=none dis=none) header.from=linaro.org Authentication-Results: mail.kernel.org; spf=none smtp.mailfrom=linux-arm-kernel-bounces+patchwork-linux-arm=patchwork.kernel.org@lists.infradead.org DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=bombadil.20170209; h=Sender: Content-Transfer-Encoding:Content-Type:MIME-Version:Cc:List-Subscribe: List-Help:List-Post:List-Archive:List-Unsubscribe:List-Id:References: In-Reply-To:Message-Id:Date:Subject:To:From:Reply-To:Content-ID: Content-Description:Resent-Date:Resent-From:Resent-Sender:Resent-To:Resent-Cc :Resent-Message-ID:List-Owner; bh=Niv0X4BbujsHXsz2KUw8aeirciJ1KKZgkx/dhhU/uLM=; b=iGY3EcERQxKJXzIsq3Vq+bcZu8 C9KqxhbxJxJeeIjAtwtULzzFonuGGWZqgDUpFUgeixlI5xvxog8TaHBTYSiJpVv/wQl3eFudL+0Pv wmSL2lDvU4cfNaGNFIlk/iyU9jwo2BV85uTlKLmu3JugAjI52M0G5dD8WwB+bfKsQq3yBrwx3zowt h9++SdrKbI6BR4znkygi/F+QgoCpz4NFEiSHXTNjooPu7wx8ljUHQ0QfmugUJ2eY3aWi5ouK+8Kqq wvB2BdOaHrkWzjmGS8KBDEoG1IgMGfMPbIsTw4bldhqKLrIL/t//vHUkxSCpv+RwYVZw1DD0XHoTr BpdXB3Hw==; Received: from localhost ([127.0.0.1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.92 #3 (Red Hat Linux)) id 1hzol1-0007ni-Tm; Mon, 19 Aug 2019 21:00:04 +0000 Received: from mail-wr1-x442.google.com ([2a00:1450:4864:20::442]) by bombadil.infradead.org with esmtps (Exim 4.92 #3 (Red Hat Linux)) id 1hzoim-0005LO-5d for linux-arm-kernel@lists.infradead.org; Mon, 19 Aug 2019 20:57:47 +0000 Received: by mail-wr1-x442.google.com with SMTP id t16so10105166wra.6 for ; Mon, 19 Aug 2019 13:57:44 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=rIXOAcwB6RSkbnYr7iwW59gzGUF7TP7dSVI8BelwrWw=; b=KV8XQCe0teSz7Dn2RonP2FuQNeu2pH3jL6PBRNeAYTYZ4mkITy7xQqWm2FPZ63El8h vjTpWoJ2B8rQ+WiVsCLIEkuLmXOiFuUqON12BbUSq4bca9KpNJFdQNa31Y0QAXft1yrR MdWOg0TxyHl9HUVBY3qoRswpxqkuQy7jslUOEERxFMO0Ys54LnzD9aG2oKoLomZhv5rV dK5QbhFAwRTnmM18heaWsnLPJlDn7O0VG6126EWw3cwt+/OasRD99a2P1OfmzQQ8dD0y LDvzNzkZujVI4eVZpmJOpmpaC86icUx9Rf9VujSb7J+jDMB8bo3Uy5MJyk2iGodky+34 tZ1A== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=rIXOAcwB6RSkbnYr7iwW59gzGUF7TP7dSVI8BelwrWw=; b=Vav05zAOA5Uv2XtgpYqxp6J5pG35esw2kBSy9EyuaMDuEA1IIiWhGgJhcDahgFuNoo dFx9JYyS8aSHVwN46YYB+vRXM8Y96atCN1/lzimUcGK18bZIje2qz4kK2IZplz01F6SR 4ZbuOP6Ut2V/NRbIB8LNanVn7wXdp2c9nfi9vvl/ELxfK7sB0PTqAMZP3V/1GGcqtHeI k+jeQxzbk6CUOOSflNwlFomPCXUlU12ouFDZLCExzluCEW0eQd9naWwXQr6dIJmsau7N e0RwDeBZw/N88j3WYe3s5QzhLIyaKekDPP9Zvfq9W1AJ2veA/sHMrQf7EJecCUdp3JI7 UnMg== X-Gm-Message-State: APjAAAVkhZr9OR8tBttGqHBG+t04AQqA3c+R2aYOVn3X2twc9QPSz2A4 pFBMCulNlReOEbyMA4SzWRUWqw== X-Google-Smtp-Source: APXvYqwWmh8fIIZjaGPPncl0bGO01SK1MHioXHtVQ3EfU1aS8tOCmHFfC6ThUTybxGBZVdcw77zc3A== X-Received: by 2002:a5d:6606:: with SMTP id n6mr31276850wru.346.1566248262982; Mon, 19 Aug 2019 13:57:42 -0700 (PDT) Received: from linaro.org ([2a00:23c5:6815:3901:247e:6e55:2413:b21c]) by smtp.gmail.com with ESMTPSA id n9sm6698423wrx.76.2019.08.19.13.57.42 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 19 Aug 2019 13:57:42 -0700 (PDT) From: Mike Leach To: mathieu.poirier@linaro.org, linux-arm-kernel@lists.infradead.org, coresight@lists.linaro.org Subject: [PATCH 6/8] coresight: etm4x: Add view comparator settings API to sysfs. Date: Mon, 19 Aug 2019 21:57:18 +0100 Message-Id: <20190819205720.24457-7-mike.leach@linaro.org> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20190819205720.24457-1-mike.leach@linaro.org> References: <20190819205720.24457-1-mike.leach@linaro.org> X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20190819_135744_310309_A005E07F X-CRM114-Status: GOOD ( 14.79 ) X-Spam-Score: -0.2 (/) X-Spam-Report: SpamAssassin version 3.4.2 on bombadil.infradead.org summary: Content analysis details: (-0.2 points) pts rule name description ---- ---------------------- -------------------------------------------------- -0.0 RCVD_IN_DNSWL_NONE RBL: Sender listed at https://www.dnswl.org/, no trust [2a00:1450:4864:20:0:0:0:442 listed in] [list.dnswl.org] -0.0 SPF_PASS SPF: sender matches SPF record 0.0 SPF_HELO_NONE SPF: HELO does not publish an SPF Record -0.1 DKIM_VALID_EF Message has a valid DKIM or DK signature from envelope-from domain -0.1 DKIM_VALID Message has at least one valid DKIM or DK signature -0.1 DKIM_VALID_AU Message has a valid DKIM or DK signature from author's domain 0.1 DKIM_SIGNED Message has a DKIM or DK signature, not necessarily valid X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: suzuki.poulose@arm.com, mike.leach@linaro.org MIME-Version: 1.0 Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+patchwork-linux-arm=patchwork.kernel.org@lists.infradead.org Currently it is not possible to view the current settings of a given address comparator without knowing what type it is set to. For example, if a comparator is set as an addr_start comparator, attempting to read addr_stop for the same index will result in an error. addr_cmp_view is added to allow the user to see the current settings of the indexed address comparator without resorting to trail and error when the set type is not known. Signed-off-by: Mike Leach Reviewed-by: Mathieu Poirier Reviewed-by: Leo Yan --- .../coresight/coresight-etm4x-sysfs.c | 51 +++++++++++++++++++ 1 file changed, 51 insertions(+) diff --git a/drivers/hwtracing/coresight/coresight-etm4x-sysfs.c b/drivers/hwtracing/coresight/coresight-etm4x-sysfs.c index baac5b48b7ac..483976074779 100644 --- a/drivers/hwtracing/coresight/coresight-etm4x-sysfs.c +++ b/drivers/hwtracing/coresight/coresight-etm4x-sysfs.c @@ -1272,6 +1272,56 @@ static ssize_t addr_exlevel_s_ns_store(struct device *dev, } static DEVICE_ATTR_RW(addr_exlevel_s_ns); +static const char * const addr_type_names[] = { + "unused", + "single", + "range", + "start", + "stop" +}; + +static ssize_t addr_cmp_view_show(struct device *dev, + struct device_attribute *attr, char *buf) +{ + u8 idx, addr_type; + unsigned long addr_v, addr_v2, addr_ctrl; + struct etmv4_drvdata *drvdata = dev_get_drvdata(dev->parent); + struct etmv4_config *config = &drvdata->config; + int size = 0; + bool exclude = false; + + spin_lock(&drvdata->spinlock); + idx = config->addr_idx; + addr_v = config->addr_val[idx]; + addr_ctrl = config->addr_acc[idx]; + addr_type = config->addr_type[idx]; + if (addr_type == ETM_ADDR_TYPE_RANGE) { + if (idx%2) { + idx -= 1; + addr_v2 = addr_v; + addr_v = config->addr_val[idx]; + } else + addr_v2 = config->addr_val[idx+1]; + exclude = config->viiectlr & BIT(idx / 2 + 16); + } + spin_unlock(&drvdata->spinlock); + if (addr_type) { + size = scnprintf(buf, PAGE_SIZE, "addr_cmp[%i] %s %#lx", idx, + addr_type_names[addr_type], addr_v); + if (addr_type == ETM_ADDR_TYPE_RANGE) { + size += scnprintf(buf+size, PAGE_SIZE-size, + " %#lx %s", addr_v2, + exclude ? "exclude" : "include"); + } + size += scnprintf(buf+size, PAGE_SIZE-size, + " ctrl(%#lx)\n", addr_ctrl); + } else { + size = scnprintf(buf, PAGE_SIZE, "addr_cmp[%i] unused\n", idx); + } + return size; +} +static DEVICE_ATTR_RO(addr_cmp_view); + static ssize_t vinst_pe_cmp_start_stop_show(struct device *dev, struct device_attribute *attr, char *buf) @@ -2117,6 +2167,7 @@ static struct attribute *coresight_etmv4_attrs[] = { &dev_attr_addr_ctxtype.attr, &dev_attr_addr_context.attr, &dev_attr_addr_exlevel_s_ns.attr, + &dev_attr_addr_cmp_view.attr, &dev_attr_vinst_pe_cmp_start_stop.attr, &dev_attr_seq_idx.attr, &dev_attr_seq_state.attr, From patchwork Mon Aug 19 20:57:19 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Mike Leach X-Patchwork-Id: 11101937 Return-Path: Received: from mail.kernel.org (pdx-korg-mail-1.web.codeaurora.org [172.30.200.123]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id D09F6912 for ; Mon, 19 Aug 2019 20:59:33 +0000 (UTC) Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id 8E1942087E for ; Mon, 19 Aug 2019 20:59:33 +0000 (UTC) Authentication-Results: mail.kernel.org; dkim=pass (2048-bit key) header.d=lists.infradead.org header.i=@lists.infradead.org header.b="ThotLQcQ"; dkim=fail reason="signature verification failed" (2048-bit key) header.d=linaro.org header.i=@linaro.org header.b="pb4B7se1" DMARC-Filter: OpenDMARC Filter v1.3.2 mail.kernel.org 8E1942087E Authentication-Results: mail.kernel.org; dmarc=fail (p=none dis=none) header.from=linaro.org Authentication-Results: mail.kernel.org; spf=none smtp.mailfrom=linux-arm-kernel-bounces+patchwork-linux-arm=patchwork.kernel.org@lists.infradead.org DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=bombadil.20170209; h=Sender: Content-Transfer-Encoding:Content-Type:MIME-Version:Cc:List-Subscribe: List-Help:List-Post:List-Archive:List-Unsubscribe:List-Id:References: In-Reply-To:Message-Id:Date:Subject:To:From:Reply-To:Content-ID: Content-Description:Resent-Date:Resent-From:Resent-Sender:Resent-To:Resent-Cc :Resent-Message-ID:List-Owner; bh=/7L0zkaGbh4EMFb4+MmbOW4OcU0jspYAz+c60PFAvf0=; b=ThotLQcQXx/X+8DAsJe+5lk0vh c5J+EjPc77A/E3HipTtF3K/BcqYMPRN+cUdUg5Syg9ftSly0eiZj65Wdxp3NVUvlX8IDhCn3a9ewF qfnc6j6cz/sncANtBYcdWL/LFcaOvI/KKEYh7e8HMZeVIVDDIu0cP3JcLH7qMXaUQ6n7wQucRzjxU j4R1l+m6A3Mr8EBlzio8iMv6l9Zi1CjL0/BxTnhDLr4/zcUAWmUkUvWSXf1wcroVmTya6lB0p6ILL kg0RrBHQCGcJyEX9/uGJnBrSdnvUptrIv3T2LCAyaJI6wq1UPrjeRzr1j0UNf3dmioa1740URrq+r Lv9pTsgw==; Received: from localhost ([127.0.0.1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.92 #3 (Red Hat Linux)) id 1hzokW-0007BW-38; Mon, 19 Aug 2019 20:59:32 +0000 Received: from mail-wr1-x443.google.com ([2a00:1450:4864:20::443]) by bombadil.infradead.org with esmtps (Exim 4.92 #3 (Red Hat Linux)) id 1hzoin-0005MT-3q for linux-arm-kernel@lists.infradead.org; Mon, 19 Aug 2019 20:57:48 +0000 Received: by mail-wr1-x443.google.com with SMTP id t16so10105209wra.6 for ; Mon, 19 Aug 2019 13:57:45 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=F2ZJZGjejiuessQCMv9wUIUrF2/clINjo13+1ridXYA=; b=pb4B7se1pkbvnD3H1pB32rpwZvd41Jcz1mGx8YXWCYqY8sYcKf+MDTwTwE/X1XsaQ9 /g8C0VtSam3S0+zxrZQGrriqGe4TKxTnYHXvyF4ZBXCTx5gyZ+znQ84nvWtld2r+h57X Ud9GZnPt0t776xMCr8g89GC5UfbO67d1lkyRoilPZB7K4tPTNQe4dr4q2Gm5vi8xOwIj emwZpT0NEKNwLVHIElQyc9R5YGfJxPi6Mcv0+xq4YKt81Xr1qDgHi6u37DlrytufCfcz fEpRhfCzddaj9rNrfctFW7VZwHsaNhKH38O62W1Kn9oNGcyU0wo9sfCM710MvPWmmGa5 3jRA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=F2ZJZGjejiuessQCMv9wUIUrF2/clINjo13+1ridXYA=; b=ghBn9o3r/Z5xns4sPsIqyQQolgmu5PSxdb2WZqEx9hbGzAlk2GMxeXtfjN1XpaXelX SsItUCqnn0Z5omnwsxcmAhYHbyjPJPUI5B0ksZOo0Y/Ar1ex4IPkCRF1P5awNb4RlxTB B16y7Sh6wWvbHDUwoX2NsDVVfYlk6CsA05e+luKVX+Ja/mNqwGvF/mMnYCHankUTAM7g FN6gojAPlTTDmAd+6DR/83UDS9PoDb+Z/esxWOOU9jyVN1m2T9U3/HePFpcckmWwfSGB 5EJUYlXRY4KNr1sPUXgw2TlxNzDC95EYP54UiqWYSKlwUOSSar9SiAuGeEV4GOG4I+WN FeLA== X-Gm-Message-State: APjAAAUI4k/Anxhz9HUdg/cSLWVlSZHwDyQez2dOPzx6wnQ3refhvpfR OJGyqt8Vk1tAMK9QJWXL4Wdakoi6ACw= X-Google-Smtp-Source: APXvYqzpts2JdrWGs90xHi7jj8FOlfV2VjmLNe1SKbEHS025EUq49+f1U1OMTwle++q4FEvcM9EyIA== X-Received: by 2002:adf:d1b4:: with SMTP id w20mr29860264wrc.301.1566248263784; Mon, 19 Aug 2019 13:57:43 -0700 (PDT) Received: from linaro.org ([2a00:23c5:6815:3901:247e:6e55:2413:b21c]) by smtp.gmail.com with ESMTPSA id n9sm6698423wrx.76.2019.08.19.13.57.43 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 19 Aug 2019 13:57:43 -0700 (PDT) From: Mike Leach To: mathieu.poirier@linaro.org, linux-arm-kernel@lists.infradead.org, coresight@lists.linaro.org Subject: [PATCH 7/8] coresight: etm4x: Add missing single-shot control API to sysfs Date: Mon, 19 Aug 2019 21:57:19 +0100 Message-Id: <20190819205720.24457-8-mike.leach@linaro.org> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20190819205720.24457-1-mike.leach@linaro.org> References: <20190819205720.24457-1-mike.leach@linaro.org> X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20190819_135745_472873_E948D370 X-CRM114-Status: GOOD ( 16.52 ) X-Spam-Score: -0.2 (/) X-Spam-Report: SpamAssassin version 3.4.2 on bombadil.infradead.org summary: Content analysis details: (-0.2 points) pts rule name description ---- ---------------------- -------------------------------------------------- -0.0 RCVD_IN_DNSWL_NONE RBL: Sender listed at https://www.dnswl.org/, no trust [2a00:1450:4864:20:0:0:0:443 listed in] [list.dnswl.org] -0.0 SPF_PASS SPF: sender matches SPF record 0.0 SPF_HELO_NONE SPF: HELO does not publish an SPF Record -0.1 DKIM_VALID_EF Message has a valid DKIM or DK signature from envelope-from domain -0.1 DKIM_VALID Message has at least one valid DKIM or DK signature -0.1 DKIM_VALID_AU Message has a valid DKIM or DK signature from author's domain 0.1 DKIM_SIGNED Message has a DKIM or DK signature, not necessarily valid X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: suzuki.poulose@arm.com, mike.leach@linaro.org MIME-Version: 1.0 Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+patchwork-linux-arm=patchwork.kernel.org@lists.infradead.org An API to control single-shot comparator operation was missing from sysfs. This adds the parameters to sysfs to allow programming of this feature. Signed-off-by: Mike Leach --- .../coresight/coresight-etm4x-sysfs.c | 122 ++++++++++++++++++ drivers/hwtracing/coresight/coresight-etm4x.c | 26 +++- drivers/hwtracing/coresight/coresight-etm4x.h | 3 + 3 files changed, 150 insertions(+), 1 deletion(-) diff --git a/drivers/hwtracing/coresight/coresight-etm4x-sysfs.c b/drivers/hwtracing/coresight/coresight-etm4x-sysfs.c index 483976074779..7c019dda1236 100644 --- a/drivers/hwtracing/coresight/coresight-etm4x-sysfs.c +++ b/drivers/hwtracing/coresight/coresight-etm4x-sysfs.c @@ -239,6 +239,7 @@ static ssize_t reset_store(struct device *dev, for (i = 0; i < drvdata->nr_resource; i++) config->res_ctrl[i] = 0x0; + config->ss_idx = 0x0; for (i = 0; i < drvdata->nr_ss_cmp; i++) { config->ss_ctrl[i] = 0x0; config->ss_pe_cmp[i] = 0x0; @@ -1713,6 +1714,123 @@ static ssize_t res_ctrl_store(struct device *dev, } static DEVICE_ATTR_RW(res_ctrl); +static ssize_t sshot_idx_show(struct device *dev, + struct device_attribute *attr, char *buf) +{ + unsigned long val; + struct etmv4_drvdata *drvdata = dev_get_drvdata(dev->parent); + struct etmv4_config *config = &drvdata->config; + + val = config->ss_idx; + return scnprintf(buf, PAGE_SIZE, "%#lx\n", val); +} + +static ssize_t sshot_idx_store(struct device *dev, + struct device_attribute *attr, + const char *buf, size_t size) +{ + unsigned long val; + struct etmv4_drvdata *drvdata = dev_get_drvdata(dev->parent); + struct etmv4_config *config = &drvdata->config; + + if (kstrtoul(buf, 16, &val)) + return -EINVAL; + if (val >= drvdata->nr_ss_cmp) + return -EINVAL; + + spin_lock(&drvdata->spinlock); + config->ss_idx = val; + spin_unlock(&drvdata->spinlock); + return size; +} +static DEVICE_ATTR_RW(sshot_idx); + +static ssize_t sshot_ctrl_show(struct device *dev, + struct device_attribute *attr, + char *buf) +{ + unsigned long val; + struct etmv4_drvdata *drvdata = dev_get_drvdata(dev->parent); + struct etmv4_config *config = &drvdata->config; + + spin_lock(&drvdata->spinlock); + val = config->ss_ctrl[config->ss_idx]; + spin_unlock(&drvdata->spinlock); + return scnprintf(buf, PAGE_SIZE, "%#lx\n", val); +} + +static ssize_t sshot_ctrl_store(struct device *dev, + struct device_attribute *attr, + const char *buf, size_t size) +{ + u8 idx; + unsigned long val; + struct etmv4_drvdata *drvdata = dev_get_drvdata(dev->parent); + struct etmv4_config *config = &drvdata->config; + + if (kstrtoul(buf, 16, &val)) + return -EINVAL; + + spin_lock(&drvdata->spinlock); + idx = config->ss_idx; + config->ss_ctrl[idx] = val & GENMASK(24, 0); + /* must clear bit 31 in related status register on programming */ + config->ss_status[idx] &= ~BIT(31); + spin_unlock(&drvdata->spinlock); + return size; +} +static DEVICE_ATTR_RW(sshot_ctrl); + +static ssize_t sshot_status_show(struct device *dev, + struct device_attribute *attr, char *buf) +{ + unsigned long val; + struct etmv4_drvdata *drvdata = dev_get_drvdata(dev->parent); + struct etmv4_config *config = &drvdata->config; + + spin_lock(&drvdata->spinlock); + val = config->ss_status[config->ss_idx]; + spin_unlock(&drvdata->spinlock); + return scnprintf(buf, PAGE_SIZE, "%#lx\n", val); +} +static DEVICE_ATTR_RO(sshot_status); + +static ssize_t sshot_pe_ctrl_show(struct device *dev, + struct device_attribute *attr, + char *buf) +{ + unsigned long val; + struct etmv4_drvdata *drvdata = dev_get_drvdata(dev->parent); + struct etmv4_config *config = &drvdata->config; + + spin_lock(&drvdata->spinlock); + val = config->ss_pe_cmp[config->ss_idx]; + spin_unlock(&drvdata->spinlock); + return scnprintf(buf, PAGE_SIZE, "%#lx\n", val); +} + +static ssize_t sshot_pe_ctrl_store(struct device *dev, + struct device_attribute *attr, + const char *buf, size_t size) +{ + u8 idx; + unsigned long val; + struct etmv4_drvdata *drvdata = dev_get_drvdata(dev->parent); + struct etmv4_config *config = &drvdata->config; + + if (kstrtoul(buf, 16, &val)) + return -EINVAL; + + spin_lock(&drvdata->spinlock); + idx = config->ss_idx; + config->ss_ctrl[idx] = val & GENMASK(7, 0); + /* must clear bit 31 in related status register on programming */ + config->ss_status[idx] &= ~BIT(31); + spin_unlock(&drvdata->spinlock); + return size; +} +static DEVICE_ATTR_RW(sshot_pe_ctrl); + static ssize_t ctxid_idx_show(struct device *dev, struct device_attribute *attr, char *buf) @@ -2169,6 +2287,10 @@ static struct attribute *coresight_etmv4_attrs[] = { &dev_attr_addr_exlevel_s_ns.attr, &dev_attr_addr_cmp_view.attr, &dev_attr_vinst_pe_cmp_start_stop.attr, + &dev_attr_sshot_idx.attr, + &dev_attr_sshot_ctrl.attr, + &dev_attr_sshot_pe_ctrl.attr, + &dev_attr_sshot_status.attr, &dev_attr_seq_idx.attr, &dev_attr_seq_state.attr, &dev_attr_seq_event.attr, diff --git a/drivers/hwtracing/coresight/coresight-etm4x.c b/drivers/hwtracing/coresight/coresight-etm4x.c index d8b078d0cc7f..fb7083218410 100644 --- a/drivers/hwtracing/coresight/coresight-etm4x.c +++ b/drivers/hwtracing/coresight/coresight-etm4x.c @@ -149,6 +149,9 @@ static int etm4_enable_hw(struct etmv4_drvdata *drvdata) drvdata->base + TRCRSCTLRn(i)); for (i = 0; i < drvdata->nr_ss_cmp; i++) { + /* always clear status bit on restart if using single-shot */ + if (config->ss_ctrl[i] || config->ss_pe_cmp[i]) + config->ss_status[i] &= ~BIT(31); writel_relaxed(config->ss_ctrl[i], drvdata->base + TRCSSCCRn(i)); writel_relaxed(config->ss_status[i], @@ -448,6 +451,9 @@ static void etm4_disable_hw(void *info) { u32 control; struct etmv4_drvdata *drvdata = info; + struct etmv4_config *config = &drvdata->config; + struct device *etm_dev = &drvdata->csdev->dev; + int i; CS_UNLOCK(drvdata->base); @@ -470,6 +476,18 @@ static void etm4_disable_hw(void *info) isb(); writel_relaxed(control, drvdata->base + TRCPRGCTLR); + /* wait for TRCSTATR.PMSTABLE to go to '1' */ + if (coresight_timeout(drvdata->base, TRCSTATR, + TRCSTATR_PMSTABLE_BIT, 1)) + dev_err(etm_dev, + "timeout while waiting for PM stable Trace Status\n"); + + /* read the status of the single shot comparators */ + for (i = 0; i < drvdata->nr_ss_cmp; i++) { + config->ss_status[i] = + readl_relaxed(drvdata->base + TRCSSCSRn(i)); + } + coresight_disclaim_device_unlocked(drvdata->base); CS_LOCK(drvdata->base); @@ -576,6 +594,7 @@ static void etm4_init_arch_data(void *info) u32 etmidr4; u32 etmidr5; struct etmv4_drvdata *drvdata = info; + int i; /* Make sure all registers are accessible */ etm4_os_unlock(drvdata); @@ -699,9 +718,14 @@ static void etm4_init_arch_data(void *info) drvdata->nr_resource = BMVAL(etmidr4, 16, 19) + 1; /* * NUMSSCC, bits[23:20] the number of single-shot - * comparator control for tracing + * comparator control for tracing. Read any status regs as these + * also contain RO capability data. */ drvdata->nr_ss_cmp = BMVAL(etmidr4, 20, 23); + for (i = 0; i < drvdata->nr_ss_cmp; i++) { + drvdata->config.ss_status[i] = + readl_relaxed(drvdata->base + TRCSSCSRn(i)); + } /* NUMCIDC, bits[27:24] number of Context ID comparators for tracing */ drvdata->numcidc = BMVAL(etmidr4, 24, 27); /* NUMVMIDC, bits[31:28] number of VMID comparators for tracing */ diff --git a/drivers/hwtracing/coresight/coresight-etm4x.h b/drivers/hwtracing/coresight/coresight-etm4x.h index 60bc2fb5159b..be8b32ea1654 100644 --- a/drivers/hwtracing/coresight/coresight-etm4x.h +++ b/drivers/hwtracing/coresight/coresight-etm4x.h @@ -175,6 +175,7 @@ ETM_MODE_EXCL_USER) #define TRCSTATR_IDLE_BIT 0 +#define TRCSTATR_PMSTABLE_BIT 1 #define ETM_DEFAULT_ADDR_COMP 0 /* PowerDown Control Register bits */ @@ -226,6 +227,7 @@ * @cntr_val: Sets or returns the value for a counter. * @res_idx: Resource index selector. * @res_ctrl: Controls the selection of the resources in the trace unit. + * @ss_idx: Single-shot index selector. * @ss_ctrl: Controls the corresponding single-shot comparator resource. * @ss_status: The status of the corresponding single-shot comparator. * @ss_pe_cmp: Selects the PE comparator inputs for Single-shot control. @@ -269,6 +271,7 @@ struct etmv4_config { u32 cntr_val[ETMv4_MAX_CNTR]; u8 res_idx; u32 res_ctrl[ETM_MAX_RES_SEL]; + u8 ss_idx; u32 ss_ctrl[ETM_MAX_SS_CMP]; u32 ss_status[ETM_MAX_SS_CMP]; u32 ss_pe_cmp[ETM_MAX_SS_CMP]; From patchwork Mon Aug 19 20:57:20 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Mike Leach X-Patchwork-Id: 11101945 Return-Path: Received: from mail.kernel.org (pdx-korg-mail-1.web.codeaurora.org [172.30.200.123]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id 143F114DB for ; Mon, 19 Aug 2019 21:00:24 +0000 (UTC) Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id DB7682087E for ; Mon, 19 Aug 2019 21:00:23 +0000 (UTC) Authentication-Results: mail.kernel.org; dkim=pass (2048-bit key) header.d=lists.infradead.org header.i=@lists.infradead.org header.b="ScTxcIKR"; dkim=fail reason="signature verification failed" (2048-bit key) header.d=linaro.org header.i=@linaro.org header.b="hkZvQBbM" DMARC-Filter: OpenDMARC Filter v1.3.2 mail.kernel.org DB7682087E Authentication-Results: mail.kernel.org; dmarc=fail (p=none dis=none) header.from=linaro.org Authentication-Results: mail.kernel.org; spf=none smtp.mailfrom=linux-arm-kernel-bounces+patchwork-linux-arm=patchwork.kernel.org@lists.infradead.org DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=bombadil.20170209; h=Sender: Content-Transfer-Encoding:Content-Type:Cc:List-Subscribe:List-Help:List-Post: List-Archive:List-Unsubscribe:List-Id:MIME-Version:References:In-Reply-To: Message-Id:Date:Subject:To:From:Reply-To:Content-ID:Content-Description: Resent-Date:Resent-From:Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID: List-Owner; bh=1yFyPvMfiGQM5Dk8M50dJSHLT2SSCKwZB5s4kyBV9gI=; b=ScTxcIKRmVb8IM 5J3pdvze6iSEeam/JhdxQ2mp6jY60Q8+q/ZC6i5ZHgAKyfwm/bKQU6F3iXhn7KCRK6j5rkUpzo/nO UFViJPmwMfxlwpHES7XdBdeJRJqBjsHLxcRdNLQkScc6d/HLFtzt7JZcGvRYF/FgoiWkPDvB97b2z GhJT/y69+jDcJ7VWQfKdnVg0R4FGllzqd1xriv7ELk4boLbgEPKJ/Z8XYxMwiUXtJA/FYjM4IuAla G+opSJCmtjZKKCXuJOST/pZMBwCKMxwQu5Hiv+LKWvaLehdaT3a82pJ4fatng05kNuRLd4+r3HKeF VJgWniHWfYVrtA9bFwFw==; Received: from localhost ([127.0.0.1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.92 #3 (Red Hat Linux)) id 1hzolL-0000lg-2C; Mon, 19 Aug 2019 21:00:23 +0000 Received: from mail-wr1-x444.google.com ([2a00:1450:4864:20::444]) by bombadil.infradead.org with esmtps (Exim 4.92 #3 (Red Hat Linux)) id 1hzoip-0005OL-Eg for linux-arm-kernel@lists.infradead.org; Mon, 19 Aug 2019 20:57:52 +0000 Received: by mail-wr1-x444.google.com with SMTP id u16so10122653wrr.0 for ; Mon, 19 Aug 2019 13:57:47 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=Scv5iNeBMAgNmgnTtGbR0+ccmOTRuw3gX8B9xFVYy9M=; b=hkZvQBbMyZmfwxLJhMwq8GEDXtwUZF0TJDWEa0uqcPlikPoNVhmV7skdLTF6pmCs7B +PM6EjSl50lyo83vnA6vRoKNF1Z+iGVIIHeOSPysPvTK98DF9SMvd16OnnflsSdPUQbL tzmjWjXoLxUdsB6XooJJBlI+bmKBV+um3JuWnbnxWN9Etvr0N67aOXExsxOsV0MXcaGp H1my7vn8vYTbAfArJBSWe3fdpXhqHZy/hrytuff0BuzME6H8WXDrFnR4xIa14O5H3Fh9 44O2jnbfwKIv1Sxj1GaS4UeyDroZbCVYFMtTXOraRwCGk4FbT+z7EF7k9+Y0BB/lxbOE RyCA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=Scv5iNeBMAgNmgnTtGbR0+ccmOTRuw3gX8B9xFVYy9M=; b=pjFpxiBK4zPZldKArhAF+e/Ozb6kBj53dCAIBV91TdfAlbjY6nQ4eTlZfYCVQK4Qp5 VdDcc7wi/HEjUauJS8PW3Lh3eGptcKKrybzbfckq7naHRp7ivUzs9wE6RQwxKlnlhRBJ 7tcbhe8rqBSRqs3FfL67bBy6+iF+eSB/p0DwBAs+FuvFSGEPCOV66fT9U6tZD2jElWVV t+7cMwQWG4B1JpyZWjgqH/9ck/Bog+RVnJMRfnBVnALW9sHZUWsNyiJV0zZ7JR/bwIVD tMpGSNrcuxTXaXEdMAtokonmtCr9YF1C11fU8OqFOS2Wjx0uA47LmvSqg0P94FCFgr57 npIg== X-Gm-Message-State: APjAAAW3Z2+s2N2e3JsqWf/EkH1NdTxe3jFF34/DPhHHfuCXwsfo7P9N 6g4uzMIWJhLtwK78f3Cb9Pa1+a78YlY= X-Google-Smtp-Source: APXvYqw0ResAh76GirWpSFKIZRmR6uEseh3/2hxI9ejYgYF7W8/zKdV8Qg+BJHziVPvtuRc/Jq1nig== X-Received: by 2002:adf:ce8d:: with SMTP id r13mr21888537wrn.37.1566248265024; Mon, 19 Aug 2019 13:57:45 -0700 (PDT) Received: from linaro.org ([2a00:23c5:6815:3901:247e:6e55:2413:b21c]) by smtp.gmail.com with ESMTPSA id n9sm6698423wrx.76.2019.08.19.13.57.43 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 19 Aug 2019 13:57:44 -0700 (PDT) From: Mike Leach To: mathieu.poirier@linaro.org, linux-arm-kernel@lists.infradead.org, coresight@lists.linaro.org Subject: [PATCH 8/8] coresight: etm4x: docs: Additional documentation for ETM4x. Date: Mon, 19 Aug 2019 21:57:20 +0100 Message-Id: <20190819205720.24457-9-mike.leach@linaro.org> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20190819205720.24457-1-mike.leach@linaro.org> References: <20190819205720.24457-1-mike.leach@linaro.org> MIME-Version: 1.0 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20190819_135747_696579_984E08CA X-CRM114-Status: GOOD ( 11.58 ) X-Spam-Score: -0.2 (/) X-Spam-Report: SpamAssassin version 3.4.2 on bombadil.infradead.org summary: Content analysis details: (-0.2 points) pts rule name description ---- ---------------------- -------------------------------------------------- -0.0 RCVD_IN_DNSWL_NONE RBL: Sender listed at https://www.dnswl.org/, no trust [2a00:1450:4864:20:0:0:0:444 listed in] [list.dnswl.org] -0.0 SPF_PASS SPF: sender matches SPF record 0.0 SPF_HELO_NONE SPF: HELO does not publish an SPF Record -0.1 DKIM_VALID_EF Message has a valid DKIM or DK signature from envelope-from domain -0.1 DKIM_VALID Message has at least one valid DKIM or DK signature -0.1 DKIM_VALID_AU Message has a valid DKIM or DK signature from author's domain 0.1 DKIM_SIGNED Message has a DKIM or DK signature, not necessarily valid X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: suzuki.poulose@arm.com, mike.leach@linaro.org Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+patchwork-linux-arm=patchwork.kernel.org@lists.infradead.org Update existing docs for new sysfs API features. Add new ETMv4 reference document for sysfs programming. Move coresight documentation to common directory. Signed-off-by: Mike Leach --- .../testing/sysfs-bus-coresight-devices-etm4x | 183 ++++--- .../{ => coresight}/coresight-cpu-debug.txt | 0 .../coresight/coresight-etm4x-reference.txt | 459 ++++++++++++++++++ .../trace/{ => coresight}/coresight.txt | 0 MAINTAINERS | 3 +- 5 files changed, 575 insertions(+), 70 deletions(-) rename Documentation/trace/{ => coresight}/coresight-cpu-debug.txt (100%) create mode 100644 Documentation/trace/coresight/coresight-etm4x-reference.txt rename Documentation/trace/{ => coresight}/coresight.txt (100%) diff --git a/Documentation/ABI/testing/sysfs-bus-coresight-devices-etm4x b/Documentation/ABI/testing/sysfs-bus-coresight-devices-etm4x index 36258bc1b473..112c50ae9986 100644 --- a/Documentation/ABI/testing/sysfs-bus-coresight-devices-etm4x +++ b/Documentation/ABI/testing/sysfs-bus-coresight-devices-etm4x @@ -1,4 +1,4 @@ -What: /sys/bus/coresight/devices/.etm/enable_source +What: /sys/bus/coresight/devices/etm/enable_source Date: April 2015 KernelVersion: 4.01 Contact: Mathieu Poirier @@ -8,82 +8,82 @@ Description: (RW) Enable/disable tracing on this specific trace entiry. of coresight components linking the source to the sink is configured and managed automatically by the coresight framework. -What: /sys/bus/coresight/devices/.etm/cpu +What: /sys/bus/coresight/devices/etm/cpu Date: April 2015 KernelVersion: 4.01 Contact: Mathieu Poirier Description: (R) The CPU this tracing entity is associated with. -What: /sys/bus/coresight/devices/.etm/nr_pe_cmp +What: /sys/bus/coresight/devices/etm/nr_pe_cmp Date: April 2015 KernelVersion: 4.01 Contact: Mathieu Poirier Description: (R) Indicates the number of PE comparator inputs that are available for tracing. -What: /sys/bus/coresight/devices/.etm/nr_addr_cmp +What: /sys/bus/coresight/devices/etm/nr_addr_cmp Date: April 2015 KernelVersion: 4.01 Contact: Mathieu Poirier Description: (R) Indicates the number of address comparator pairs that are available for tracing. -What: /sys/bus/coresight/devices/.etm/nr_cntr +What: /sys/bus/coresight/devices/etm/nr_cntr Date: April 2015 KernelVersion: 4.01 Contact: Mathieu Poirier Description: (R) Indicates the number of counters that are available for tracing. -What: /sys/bus/coresight/devices/.etm/nr_ext_inp +What: /sys/bus/coresight/devices/etm/nr_ext_inp Date: April 2015 KernelVersion: 4.01 Contact: Mathieu Poirier Description: (R) Indicates how many external inputs are implemented. -What: /sys/bus/coresight/devices/.etm/numcidc +What: /sys/bus/coresight/devices/etm/numcidc Date: April 2015 KernelVersion: 4.01 Contact: Mathieu Poirier Description: (R) Indicates the number of Context ID comparators that are available for tracing. -What: /sys/bus/coresight/devices/.etm/numvmidc +What: /sys/bus/coresight/devices/etm/numvmidc Date: April 2015 KernelVersion: 4.01 Contact: Mathieu Poirier Description: (R) Indicates the number of VMID comparators that are available for tracing. -What: /sys/bus/coresight/devices/.etm/nrseqstate +What: /sys/bus/coresight/devices/etm/nrseqstate Date: April 2015 KernelVersion: 4.01 Contact: Mathieu Poirier Description: (R) Indicates the number of sequencer states that are implemented. -What: /sys/bus/coresight/devices/.etm/nr_resource +What: /sys/bus/coresight/devices/etm/nr_resource Date: April 2015 KernelVersion: 4.01 Contact: Mathieu Poirier Description: (R) Indicates the number of resource selection pairs that are available for tracing. -What: /sys/bus/coresight/devices/.etm/nr_ss_cmp +What: /sys/bus/coresight/devices/etm/nr_ss_cmp Date: April 2015 KernelVersion: 4.01 Contact: Mathieu Poirier Description: (R) Indicates the number of single-shot comparator controls that are available for tracing. -What: /sys/bus/coresight/devices/.etm/reset +What: /sys/bus/coresight/devices/etm/reset Date: April 2015 KernelVersion: 4.01 Contact: Mathieu Poirier Description: (W) Cancels all configuration on a trace unit and set it back to its boot configuration. -What: /sys/bus/coresight/devices/.etm/mode +What: /sys/bus/coresight/devices/etm/mode Date: April 2015 KernelVersion: 4.01 Contact: Mathieu Poirier @@ -91,302 +91,349 @@ Description: (RW) Controls various modes supported by this ETM, for example P0 instruction tracing, branch broadcast, cycle counting and context ID tracing. -What: /sys/bus/coresight/devices/.etm/pe +What: /sys/bus/coresight/devices/etm/pe Date: April 2015 KernelVersion: 4.01 Contact: Mathieu Poirier Description: (RW) Controls which PE to trace. -What: /sys/bus/coresight/devices/.etm/event +What: /sys/bus/coresight/devices/etm/event Date: April 2015 KernelVersion: 4.01 Contact: Mathieu Poirier Description: (RW) Controls the tracing of arbitrary events from bank 0 to 3. -What: /sys/bus/coresight/devices/.etm/event_instren +What: /sys/bus/coresight/devices/etm/event_instren Date: April 2015 KernelVersion: 4.01 Contact: Mathieu Poirier Description: (RW) Controls the behavior of the events in bank 0 to 3. -What: /sys/bus/coresight/devices/.etm/event_ts +What: /sys/bus/coresight/devices/etm/event_ts Date: April 2015 KernelVersion: 4.01 Contact: Mathieu Poirier Description: (RW) Controls the insertion of global timestamps in the trace streams. -What: /sys/bus/coresight/devices/.etm/syncfreq +What: /sys/bus/coresight/devices/etm/syncfreq Date: April 2015 KernelVersion: 4.01 Contact: Mathieu Poirier Description: (RW) Controls how often trace synchronization requests occur. -What: /sys/bus/coresight/devices/.etm/cyc_threshold +What: /sys/bus/coresight/devices/etm/cyc_threshold Date: April 2015 KernelVersion: 4.01 Contact: Mathieu Poirier Description: (RW) Sets the threshold value for cycle counting. -What: /sys/bus/coresight/devices/.etm/bb_ctrl +What: /sys/bus/coresight/devices/etm/bb_ctrl Date: April 2015 KernelVersion: 4.01 Contact: Mathieu Poirier Description: (RW) Controls which regions in the memory map are enabled to use branch broadcasting. -What: /sys/bus/coresight/devices/.etm/event_vinst +What: /sys/bus/coresight/devices/etm/event_vinst Date: April 2015 KernelVersion: 4.01 Contact: Mathieu Poirier Description: (RW) Controls instruction trace filtering. -What: /sys/bus/coresight/devices/.etm/s_exlevel_vinst +What: /sys/bus/coresight/devices/etm/s_exlevel_vinst Date: April 2015 KernelVersion: 4.01 Contact: Mathieu Poirier Description: (RW) In Secure state, each bit controls whether instruction tracing is enabled for the corresponding exception level. -What: /sys/bus/coresight/devices/.etm/ns_exlevel_vinst +What: /sys/bus/coresight/devices/etm/ns_exlevel_vinst Date: April 2015 KernelVersion: 4.01 Contact: Mathieu Poirier Description: (RW) In non-secure state, each bit controls whether instruction tracing is enabled for the corresponding exception level. -What: /sys/bus/coresight/devices/.etm/addr_idx +What: /sys/bus/coresight/devices/etm/addr_idx Date: April 2015 KernelVersion: 4.01 Contact: Mathieu Poirier Description: (RW) Select which address comparator or pair (of comparators) to work with. -What: /sys/bus/coresight/devices/.etm/addr_instdatatype +What: /sys/bus/coresight/devices/etm/addr_instdatatype Date: April 2015 KernelVersion: 4.01 Contact: Mathieu Poirier Description: (RW) Controls what type of comparison the trace unit performs. -What: /sys/bus/coresight/devices/.etm/addr_single +What: /sys/bus/coresight/devices/etm/addr_single Date: April 2015 KernelVersion: 4.01 Contact: Mathieu Poirier Description: (RW) Used to setup single address comparator values. -What: /sys/bus/coresight/devices/.etm/addr_range +What: /sys/bus/coresight/devices/etm/addr_range Date: April 2015 KernelVersion: 4.01 Contact: Mathieu Poirier Description: (RW) Used to setup address range comparator values. -What: /sys/bus/coresight/devices/.etm/seq_idx +What: /sys/bus/coresight/devices/etm/seq_idx Date: April 2015 KernelVersion: 4.01 Contact: Mathieu Poirier Description: (RW) Select which sequensor. -What: /sys/bus/coresight/devices/.etm/seq_state +What: /sys/bus/coresight/devices/etm/seq_state Date: April 2015 KernelVersion: 4.01 Contact: Mathieu Poirier Description: (RW) Use this to set, or read, the sequencer state. -What: /sys/bus/coresight/devices/.etm/seq_event +What: /sys/bus/coresight/devices/etm/seq_event Date: April 2015 KernelVersion: 4.01 Contact: Mathieu Poirier Description: (RW) Moves the sequencer state to a specific state. -What: /sys/bus/coresight/devices/.etm/seq_reset_event +What: /sys/bus/coresight/devices/etm/seq_reset_event Date: April 2015 KernelVersion: 4.01 Contact: Mathieu Poirier Description: (RW) Moves the sequencer to state 0 when a programmed event occurs. -What: /sys/bus/coresight/devices/.etm/cntr_idx +What: /sys/bus/coresight/devices/etm/cntr_idx Date: April 2015 KernelVersion: 4.01 Contact: Mathieu Poirier Description: (RW) Select which counter unit to work with. -What: /sys/bus/coresight/devices/.etm/cntrldvr +What: /sys/bus/coresight/devices/etm/cntrldvr Date: April 2015 KernelVersion: 4.01 Contact: Mathieu Poirier Description: (RW) This sets or returns the reload count value of the specific counter. -What: /sys/bus/coresight/devices/.etm/cntr_val +What: /sys/bus/coresight/devices/etm/cntr_val Date: April 2015 KernelVersion: 4.01 Contact: Mathieu Poirier Description: (RW) This sets or returns the current count value of the specific counter. -What: /sys/bus/coresight/devices/.etm/cntr_ctrl +What: /sys/bus/coresight/devices/etm/cntr_ctrl Date: April 2015 KernelVersion: 4.01 Contact: Mathieu Poirier Description: (RW) Controls the operation of the selected counter. -What: /sys/bus/coresight/devices/.etm/res_idx +What: /sys/bus/coresight/devices/etm/res_idx Date: April 2015 KernelVersion: 4.01 Contact: Mathieu Poirier Description: (RW) Select which resource selection unit to work with. -What: /sys/bus/coresight/devices/.etm/res_ctrl +What: /sys/bus/coresight/devices/etm/res_ctrl Date: April 2015 KernelVersion: 4.01 Contact: Mathieu Poirier Description: (RW) Controls the selection of the resources in the trace unit. -What: /sys/bus/coresight/devices/.etm/ctxid_idx +What: /sys/bus/coresight/devices/etm/ctxid_idx Date: April 2015 KernelVersion: 4.01 Contact: Mathieu Poirier Description: (RW) Select which context ID comparator to work with. -What: /sys/bus/coresight/devices/.etm/ctxid_pid +What: /sys/bus/coresight/devices/etm/ctxid_pid Date: April 2015 KernelVersion: 4.01 Contact: Mathieu Poirier Description: (RW) Get/Set the context ID comparator value to trigger on. -What: /sys/bus/coresight/devices/.etm/ctxid_masks +What: /sys/bus/coresight/devices/etm/ctxid_masks Date: April 2015 KernelVersion: 4.01 Contact: Mathieu Poirier Description: (RW) Mask for all 8 context ID comparator value registers (if implemented). -What: /sys/bus/coresight/devices/.etm/vmid_idx +What: /sys/bus/coresight/devices/etm/vmid_idx Date: April 2015 KernelVersion: 4.01 Contact: Mathieu Poirier Description: (RW) Select which virtual machine ID comparator to work with. -What: /sys/bus/coresight/devices/.etm/vmid_val +What: /sys/bus/coresight/devices/etm/vmid_val Date: April 2015 KernelVersion: 4.01 Contact: Mathieu Poirier Description: (RW) Get/Set the virtual machine ID comparator value to trigger on. -What: /sys/bus/coresight/devices/.etm/vmid_masks +What: /sys/bus/coresight/devices/etm/vmid_masks Date: April 2015 KernelVersion: 4.01 Contact: Mathieu Poirier Description: (RW) Mask for all 8 virtual machine ID comparator value registers (if implemented). -What: /sys/bus/coresight/devices/.etm/mgmt/trcoslsr +What: /sys/bus/coresight/devices/etm/addr_exlevel_s_ns +Date: August 2019 +KernelVersion: 5.4 +Contact: Mathieu Poirier +Description: (RW) Set the Exception Level matching bits for secure and + non-secure exception levels. + +What: /sys/bus/coresight/devices/etm/vinst_pe_cmp_start_stop +Date: August 2019 +KernelVersion: 5.4 +Contact: Mathieu Poirier +Description: (RW) Access the start stop control register for PE input + comparators. + +What: /sys/bus/coresight/devices/etm/addr_cmp_view +Date: August 2019 +KernelVersion: 5.4 +Contact: Mathieu Poirier +Description: (R) Print the current settings for the selected address + comparator. + +What: /sys/bus/coresight/devices/etm/sshot_idx +Date: August 2019 +KernelVersion: 5.4 +Contact: Mathieu Poirier +Description: (RW) Select the single shot control register to access. + +What: /sys/bus/coresight/devices/etm/sshot_ctrl +Date: August 2019 +KernelVersion: 5.4 +Contact: Mathieu Poirier +Description: (RW) Access the selected single shot control register. + +What: /sys/bus/coresight/devices/etm/sshot_status +Date: August 2019 +KernelVersion: 5.4 +Contact: Mathieu Poirier +Description: (R) Print the current value of the selected single shot + status register. + +What: /sys/bus/coresight/devices/etm/sshot_pe_ctrl +Date: August 2019 +KernelVersion: 5.4 +Contact: Mathieu Poirier +Description: (RW) Access the selected single show PE comparator control + register. + +What: /sys/bus/coresight/devices/etm/mgmt/trcoslsr Date: April 2015 KernelVersion: 4.01 Contact: Mathieu Poirier Description: (R) Print the content of the OS Lock Status Register (0x304). The value it taken directly from the HW. -What: /sys/bus/coresight/devices/.etm/mgmt/trcpdcr +What: /sys/bus/coresight/devices/etm/mgmt/trcpdcr Date: April 2015 KernelVersion: 4.01 Contact: Mathieu Poirier Description: (R) Print the content of the Power Down Control Register (0x310). The value is taken directly from the HW. -What: /sys/bus/coresight/devices/.etm/mgmt/trcpdsr +What: /sys/bus/coresight/devices/etm/mgmt/trcpdsr Date: April 2015 KernelVersion: 4.01 Contact: Mathieu Poirier Description: (R) Print the content of the Power Down Status Register (0x314). The value is taken directly from the HW. -What: /sys/bus/coresight/devices/.etm/mgmt/trclsr +What: /sys/bus/coresight/devices/etm/mgmt/trclsr Date: April 2015 KernelVersion: 4.01 Contact: Mathieu Poirier Description: (R) Print the content of the SW Lock Status Register (0xFB4). The value is taken directly from the HW. -What: /sys/bus/coresight/devices/.etm/mgmt/trcauthstatus +What: /sys/bus/coresight/devices/etm/mgmt/trcauthstatus Date: April 2015 KernelVersion: 4.01 Contact: Mathieu Poirier Description: (R) Print the content of the Authentication Status Register (0xFB8). The value is taken directly from the HW. -What: /sys/bus/coresight/devices/.etm/mgmt/trcdevid +What: /sys/bus/coresight/devices/etm/mgmt/trcdevid Date: April 2015 KernelVersion: 4.01 Contact: Mathieu Poirier Description: (R) Print the content of the Device ID Register (0xFC8). The value is taken directly from the HW. -What: /sys/bus/coresight/devices/.etm/mgmt/trcdevtype +What: /sys/bus/coresight/devices/etm/mgmt/trcdevtype Date: April 2015 KernelVersion: 4.01 Contact: Mathieu Poirier Description: (R) Print the content of the Device Type Register (0xFCC). The value is taken directly from the HW. -What: /sys/bus/coresight/devices/.etm/mgmt/trcpidr0 +What: /sys/bus/coresight/devices/etm/mgmt/trcpidr0 Date: April 2015 KernelVersion: 4.01 Contact: Mathieu Poirier Description: (R) Print the content of the Peripheral ID0 Register (0xFE0). The value is taken directly from the HW. -What: /sys/bus/coresight/devices/.etm/mgmt/trcpidr1 +What: /sys/bus/coresight/devices/etm/mgmt/trcpidr1 Date: April 2015 KernelVersion: 4.01 Contact: Mathieu Poirier Description: (R) Print the content of the Peripheral ID1 Register (0xFE4). The value is taken directly from the HW. -What: /sys/bus/coresight/devices/.etm/mgmt/trcpidr2 +What: /sys/bus/coresight/devices/etm/mgmt/trcpidr2 Date: April 2015 KernelVersion: 4.01 Contact: Mathieu Poirier Description: (R) Print the content of the Peripheral ID2 Register (0xFE8). The value is taken directly from the HW. -What: /sys/bus/coresight/devices/.etm/mgmt/trcpidr3 +What: /sys/bus/coresight/devices/etm/mgmt/trcpidr3 Date: April 2015 KernelVersion: 4.01 Contact: Mathieu Poirier Description: (R) Print the content of the Peripheral ID3 Register (0xFEC). The value is taken directly from the HW. -What: /sys/bus/coresight/devices/.etm/mgmt/trcconfig +What: /sys/bus/coresight/devices/etm/mgmt/trcconfig Date: February 2016 KernelVersion: 4.07 Contact: Mathieu Poirier Description: (R) Print the content of the trace configuration register (0x010) as currently set by SW. -What: /sys/bus/coresight/devices/.etm/mgmt/trctraceid +What: /sys/bus/coresight/devices/etm/mgmt/trctraceid Date: February 2016 KernelVersion: 4.07 Contact: Mathieu Poirier Description: (R) Print the content of the trace ID register (0x040). -What: /sys/bus/coresight/devices/.etm/trcidr/trcidr0 +What: /sys/bus/coresight/devices/etm/trcidr/trcidr0 Date: April 2015 KernelVersion: 4.01 Contact: Mathieu Poirier Description: (R) Returns the tracing capabilities of the trace unit (0x1E0). The value is taken directly from the HW. -What: /sys/bus/coresight/devices/.etm/trcidr/trcidr1 +What: /sys/bus/coresight/devices/etm/trcidr/trcidr1 Date: April 2015 KernelVersion: 4.01 Contact: Mathieu Poirier Description: (R) Returns the tracing capabilities of the trace unit (0x1E4). The value is taken directly from the HW. -What: /sys/bus/coresight/devices/.etm/trcidr/trcidr2 +What: /sys/bus/coresight/devices/etm/trcidr/trcidr2 Date: April 2015 KernelVersion: 4.01 Contact: Mathieu Poirier @@ -394,7 +441,7 @@ Description: (R) Returns the maximum size of the data value, data address, VMID, context ID and instuction address in the trace unit (0x1E8). The value is taken directly from the HW. -What: /sys/bus/coresight/devices/.etm/trcidr/trcidr3 +What: /sys/bus/coresight/devices/etm/trcidr/trcidr3 Date: April 2015 KernelVersion: 4.01 Contact: Mathieu Poirier @@ -403,42 +450,42 @@ Description: (R) Returns the value associated with various resources architecture specification for more details (0x1E8). The value is taken directly from the HW. -What: /sys/bus/coresight/devices/.etm/trcidr/trcidr4 +What: /sys/bus/coresight/devices/etm/trcidr/trcidr4 Date: April 2015 KernelVersion: 4.01 Contact: Mathieu Poirier Description: (R) Returns how many resources the trace unit supports (0x1F0). The value is taken directly from the HW. -What: /sys/bus/coresight/devices/.etm/trcidr/trcidr5 +What: /sys/bus/coresight/devices/etm/trcidr/trcidr5 Date: April 2015 KernelVersion: 4.01 Contact: Mathieu Poirier Description: (R) Returns how many resources the trace unit supports (0x1F4). The value is taken directly from the HW. -What: /sys/bus/coresight/devices/.etm/trcidr/trcidr8 +What: /sys/bus/coresight/devices/etm/trcidr/trcidr8 Date: April 2015 KernelVersion: 4.01 Contact: Mathieu Poirier Description: (R) Returns the maximum speculation depth of the instruction trace stream. (0x180). The value is taken directly from the HW. -What: /sys/bus/coresight/devices/.etm/trcidr/trcidr9 +What: /sys/bus/coresight/devices/etm/trcidr/trcidr9 Date: April 2015 KernelVersion: 4.01 Contact: Mathieu Poirier Description: (R) Returns the number of P0 right-hand keys that the trace unit can use (0x184). The value is taken directly from the HW. -What: /sys/bus/coresight/devices/.etm/trcidr/trcidr10 +What: /sys/bus/coresight/devices/etm/trcidr/trcidr10 Date: April 2015 KernelVersion: 4.01 Contact: Mathieu Poirier Description: (R) Returns the number of P1 right-hand keys that the trace unit can use (0x188). The value is taken directly from the HW. -What: /sys/bus/coresight/devices/.etm/trcidr/trcidr11 +What: /sys/bus/coresight/devices/etm/trcidr/trcidr11 Date: April 2015 KernelVersion: 4.01 Contact: Mathieu Poirier @@ -446,7 +493,7 @@ Description: (R) Returns the number of special P1 right-hand keys that the trace unit can use (0x18C). The value is taken directly from the HW. -What: /sys/bus/coresight/devices/.etm/trcidr/trcidr12 +What: /sys/bus/coresight/devices/etm/trcidr/trcidr12 Date: April 2015 KernelVersion: 4.01 Contact: Mathieu Poirier @@ -454,7 +501,7 @@ Description: (R) Returns the number of conditional P1 right-hand keys that the trace unit can use (0x190). The value is taken directly from the HW. -What: /sys/bus/coresight/devices/.etm/trcidr/trcidr13 +What: /sys/bus/coresight/devices/etm/trcidr/trcidr13 Date: April 2015 KernelVersion: 4.01 Contact: Mathieu Poirier diff --git a/Documentation/trace/coresight-cpu-debug.txt b/Documentation/trace/coresight/coresight-cpu-debug.txt similarity index 100% rename from Documentation/trace/coresight-cpu-debug.txt rename to Documentation/trace/coresight/coresight-cpu-debug.txt diff --git a/Documentation/trace/coresight/coresight-etm4x-reference.txt b/Documentation/trace/coresight/coresight-etm4x-reference.txt new file mode 100644 index 000000000000..72e81bbbef43 --- /dev/null +++ b/Documentation/trace/coresight/coresight-etm4x-reference.txt @@ -0,0 +1,459 @@ +ETMv4 sysfs linux driver programming reference - v2. +==================================================== + +Supplement to existing ETMv4 driver documentation. + +Sysfs files and directories +--------------------------- + +Root: /sys/bus/coresight/devices/etm + + +The following paragraphs explain the association between sysfs files and the +ETMv4 registers that they effect. Note the register names are given without +the ‘TRC’ prefix. + +File : mode (rw) +Trace Registers : {CONFIGR + others} +Notes : Bit select trace features. See ‘mode’ section below. Bits + in this will cause equivalent programming of trace config and + other registers to enable the features requested. +Syntax & eg : 'echo bitfield > mode' + bitfield up to 32 bits setting trace features. +Example : $> echo 0x > mode + +File : reset (wo) +Trace Registers : All +Notes : Reset all programming to trace nothing / no logic programmed. +Syntax : 'echo 1 > reset' + +File : enable_source (wo) +Trace Registers : PRGCTLR, All hardware regs. +Notes : >0: Programs up the hardware with the current values held in + the driver and enables trace. + 0: disable trace hardware. +Syntax : 'echo 1 > enable_source' + +File : cpu (ro) +Trace Registers : None. +Notes : CPU ID that this ETM is attached to. +Example :$> cat cpu + $> 0 + +File : addr_idx (rw) +Trace Registers : None. +Notes : Virtual register to index address comparator and range + features. Set index for first of the pair in a range. +Syntax : 'echo idx > addr_idx' + Where idx <  nr_addr_cmp x 2 + +File : addr_range (rw) +Trace Registers : ACVR[idx, idx+1], VIIECTLR +Notes : Pair of addresses for a range selected by addr_idx. Include + / exclude according to the optional parameter, or if omitted + uses the current ‘mode’ setting. Select comparator range in + control register. Error if index is odd value. +Depends : mode, addr_idx +Syntax : 'echo addr1 addr2 [exclude] > addr_range' + Where addr1 and addr2 define the range and addr1 < addr2. + Optional exclude value - 0 for include, 1 for exclude. +Example : $> echo 0x0000 0x2000 0 > addr_range + +File : addr_single (rw) +Trace Registers : ACVR[idx] +Notes : Set a single address comparator according to addr_idx. This + is used if the address comparator is used as part of event + generation logic etc. +Depends : addr_idx +Syntax : 'echo addr1 > addr_single' + +File : addr_start (rw) +Trace Registers : ACVR[idx], VISSCTLR +Notes : Set a trace start address comparator according to addr_idx. + Select comparator in control register. +Depends : addr_idx +Syntax : 'echo addr1 > addr_start' + +File : addr_stop (rw) +Trace Registers : ACVR[idx], VISSCTLR +Notes : Set a trace stop address comparator according to addr_idx. + Select comparator in control register. +Depends : addr_idx +Syntax : 'echo addr1 > addr_stop' + +File : addr_context (rw) +Trace Registers : ACATR[idx,{6:4}] +Notes : Link context ID comparator to address comparator addr_idx +Depends : addr_idx. +Syntax : 'echo ctxt_idx > addr_context' + Where ctxt_idx is the index of the linked context id / vmid + comparator. + +File : addr_ctxtype (rw) +Trace Registers : ACATR[idx,{3:2}] +Notes : Input value string. Set type for linked context ID comparator +Depends : addr_idx +Syntax : 'echo type > addr_ctxtype' + Type one of {all, vmid, ctxid, none} +Example : $> echo ctxid > addr_ctxtype + +File : addr_exlevel_s_ns (rw) +Trace Registers : ACATR[idx,{14:8}] +Notes : Set the ELx secure and non-secure  matching bits for the + selected address comparator +Depends : addr_idx +Syntax : 'echo val > addr_exlevel_s_ns' + val is a 7 bit value for exception levels to exclude. Input + value shifted to correct bits in register. +Example : $> echo 0x4F > addr_exlevel_s_ns + +File : addr_instdatatype (rw) +Trace Registers : ACATR[idx,{1:0}] +Notes : Set the comparator address type for matching. Driver only + supports setting instruction address type. +Depends : addr_idx + +File : addr_cmp_view (ro) +Trace Registers : ACVR[idx, idx+1], ACATR[idx], VIIECTLR +Notes : Read the currently selected address comparator. If part of + address range then display both addresses. +Depends : addr_idx +Syntax : 'cat addr_cmp_view' +Example : $> cat addr_cmp_view + addr_cmp[0] range 0x0 0xffffffffffffffff include ctrl(0x4b00) + +File : nr_addr_cmp (ro) +Trace Registers : From IDR4 +Notes : Number of address comparator pairs + +File : sshot_idx (rw) +Trace Registers : None +Notes : Select  single shot register set. + +File : sshot_ctrl (rw) +Trace Registers : SSCCR[idx] +Notes : Access a single shot comparator control register. +Depends : sshot_idx +Syntax : 'echo val > sshot_ctrl' + Writes val into the selected control register. + +File : sshot_status (ro) +Trace Registers : SSCSR[idx] +Notes : Read a single shot comparator status register +Depends : sshot_idx +Syntax : 'cat sshot_status' + Read status. +Example : $> cat sshot_status + 0x1 + +File : sshot_pe_ctrl (rw) +Trace Registers : SSPCICR[idx] +Notes : Access a single shot PE comparator input control register. +Depends : sshot_idx +Syntax : echo val > sshot_pe_ctrl + Writes val into the selected control register. + +File : ns_exlevel_vinst (rw) +Trace Registers : VICTLR{23:20} +Notes : Program non-secure exception level filters. Set / clear NS + exception filter bits. Setting ‘1’ excludes trace from the + exception level. +Syntax : 'echo bitfield > ns_exlevel_viinst' + Where bitfield contains bits to set clear for EL0 to EL2 +Example : %> echo 0x4 > ns_exlevel_viinst + ; Exclude EL2 NS trace. + +File : vinst_pe_cmp_start_stop (rw) +Trace Registers : VIPCSSCTLR +Notes : Access PE start stop comparator input control registers + +File : bb_ctrl (rw) +Trace Registers : BBCTLR +Notes : Define ranges that Branch Broadcast will operate in. + Default (0x0) is all addresses. +Depends : BB enabled. + +File : cyc_threshold (rw) +Trace Registers : CCCTLR +Notes : Set the threshold for which cycle counts will be emitted. + Error if attempt to set below minimum defined in IDR3, masked + to width of valid bits. +Depends : CC enabled. + +File : syncfreq (rw) +Trace Registers : SYNCPR +Notes : Set trace synchronisation period. Power of 2 value, 0 (off) + or 8-20. Driver defaults to 12 (every 4096 bytes). + +File : cntr_idx (rw) +Trace Registers : none +Notes : Select the counter to access +Syntax : 'echo idx > cntr_idx' + Where idx <  nr_cntr + +File : cntr_ctrl (rw) +Trace Registers : CNTCTLR[idx] +Notes : Set counter control value +Depends : cntr_idx +Syntax : 'echo val > cntr_ctrl' + Where val is per ETMv4 spec. + +File : cntrldvr (rw) +Trace Registers : CNTRLDVR[idx] +Notes : Set counter reload value +Depends : cntr_idx +Syntax : 'echo val > cntrldvr' + Where val is per ETMv4 spec. + +File : nr_cntr (ro) +Trace Registers : From IDR5 +Notes : Number of counters implemented. + +File : ctxid_idx (rw) +Trace Registers : None +Notes : Select the context ID comparator to access +Syntax : 'echo idx > ctxid_idx' + Where idx <  numcidc + +File : ctxid_pid (rw) +Trace Registers : CIDCVR[idx] +Notes : Set the context ID comparator value +Depends : ctxid_idx + +File : ctxid_masks (rw) +Trace Registers : CIDCCTLR0, CIDCCTLR1, CIDCVR<0-7> +Notes : Pair of values to set the byte masks for 1-8 context ID + comparators. Automatically clears masked bytes to 0 in CID + value registers. +Syntax : 'echo m3m2m1m0 [m7m6m5m4] > ctxid_masks' + 32 bit values made up of mask bytes, where mN represents a + byte mask value for Ctxt ID comparator N. + Second value not required on systems that have fewer than 4 + context ID comparators + +File : numcidc (ro) +Trace Registers : From IDR4 +Notes : Number of Context ID comparators + +File : vmid_idx (rw) +Trace Registers : None +Notes : Select the VM ID comparator to access. +Syntax : 'echo idx > vmid_idx' + Where idx <  numvmidc + +File : vmid_val (rw) +Trace Registers : VMIDCVR[idx] +Notes : Set the VM ID comparator value +Depends : vmid_idx + +File : vmid_masks (rw) +Trace Registers : VMIDCCTLR0, VMIDCCTLR1, VMIDCVR<0-7> +Notes : Pair of values to set the byte masks for 1-8 VM ID + comparators. Automatically clears masked bytes to 0 in VMID + value registers. +Syntax : 'echo m3m2m1m0 [m7m6m5m4] > vmid_masks' + Where mN represents a byte mask value for VMID comparator N. + Second value not required on systems that have fewer than + 4 VMID comparators. + +File : numvmidc (ro) +Trace Registers : From IDR4 +Notes : Number of VMID comparators + +File : res_idx (rw) +Trace Registers : None. +Notes : Select the resource selector control to access. Must be 2 or + higher as selectors 0 and 1 are hardwired. +Syntax : 'echo idx > res_idx' + Where 2 <= idx <  nr_resource x 2 + +File : res_ctrl (rw) +Trace Registers : RSCTLR[idx] +Notes : Set resource selector control value. Value per ETMv4 spec. +Depends : res_idx +Syntax : 'echo val > res_cntr' + Where val is per ETMv4 spec. + +File : nr_resource (ro) +Trace Registers : From IDR4 +Notes : Number of resource selector pairs + +File : event (rw) +Trace Registers : EVENTCTRL0R +Notes : Set up to 4 implemented event fields. +Syntax : 'echo ev3ev2ev1ev0 > event' + Where evN is an 8 bit event field. Up to 4 event fields make up + the 32bit input value. Number of valid fields implementation + dependent defined in IDR0. + +File : event_instren (rw) +Trace Registers : EVENTCTRL1R +Notes : Choose events which insert event packets into trace stream. +Depends : EVENTCTRL0R +Syntax : 'echo bitfield > event_instren' + Where bitfield is up to 4 bits according to number of event + fields. + +File : event_ts (rw) +Trace Registers : TSCTLR +Notes : Set the event that will generate timestamp requests. +Depends : TS activated +Syntax : 'echo evfield > event_ts' + Where evfield is an 8 bit event selector. + +File : seq_idx (rw) +Trace Registers : None +Notes : Sequencer event register select - 0 to 2 + + +File : seq_state (rw) +Trace Registers : SEQSTR +Notes : Sequencer current state - 0 to 3. + +File : seq_event (rw) +Trace Registers : SEQEVR[idx] +Notes : State transition event registers +Depends : seq_idx +Syntax : 'echo evBevF > seq_event' + Where evBevF is a 16 bit value made up of two event selectors, + evB - back, evF - forwards. + +File : seq_reset_event (rw) +Trace Registers : SEQRSTEVR +Notes : Sequencer reset event +Syntax : 'echo evfield > seq_reset_event' + Where evfield is an 8 bit event selector. + +File : nrseqstate (ro) +Trace Registers : From IDR5 +Notes : Number of sequencer states (0 or 4) + +File : nr_pe_cmp (ro) +Trace Registers : From IDR4 +Notes : Number of PE comparator inputs + +File : nr_ext_inp (ro) +Trace Registers : From IDR5 +Notes : Number of external inputs + +File : nr_ss_cmp (ro) +Trace Registers : From IDR4 +Notes : Number of Single Shot control registers + +Note: When programming any address comparator the driver will tag the +comparator with a type used - i.e. RANGE, SINGLE, START, STOP. Once this tag +is set, then only the values can be changed using the same sysfs file / type +used to program it. + +Thus:- +% echo 0 > addr_idx ; select address comparator 0 +% echo 0x1000 0x5000 0 > addr_range ; set address range on comparators 0 and 1. +% echo 0x2000 > addr_start ; this will error as comparator 0 is a + ; range comparator +% echo 2 > addr_idx ; select address comparator 2 +% echo 0x2000 > addr_start ; this is OK as comparator 2 is unused, +% echo 0x3000 > addr_stop ; this will error as comparator 2 a start + ; address comparator +% echo 2 > addr_idx ; select address comparator 3 +% echo 0x3000 > addr_stop ; this is OK + +To remove programming on all the comparators (and all the other hardware) use +the reset parameter: + +% echo 1 > reset + +The ‘mode’ sysfs parameter. +--------------------------- + +This is a bitfield selection parameter that sets the overall trace mode for the +ETM. The table below describes the bits, using the defines from the driver +source file, along with a description of the feature these represent. Many +features are optional and therefore dependent on implementation in the +hardware. + +Bit assignements shown below:- + +bit (0) : #define ETM_MODE_EXCLUDE +description : This is the default value for the include / exclude function when + setting address ranges. Set 1 for exclude range. When the mode + parameter is set this value is applied to the currently indexed + address range. + +bit (4) : #define ETM_MODE_BB +description : Set to enable branch broadcast if supported in hardware [IDR0]. + +bit (5) : #define ETMv4_MODE_CYCACC +description : Set to enable cycle accurate trace if supported [IDR0]. + +bit (6) : ETMv4_MODE_CTXID +description : Set to enable context ID tracing if supported in hardware [IDR2]. + +bit (7) : ETM_MODE_VMID +description : Set to enable virtual machine ID tracing if supported [IDR2]. + +bit (11) : ETMv4_MODE_TIMESTAMP +description : Set to enable timestamp generation if supported [IDR0]. + +bit (12) : ETM_MODE_RETURNSTACK +description : Set to enable trace return stack use if supported [IDR0]. + +bit (13-14) : ETM_MODE_QELEM(val) +description : ‘val’ determines level of Q element support enabled if + implemented by the ETM [IDR0] + +bit (19) : ETM_MODE_ATB_TRIGGER +description : Set to enable the ATBTRIGGER bit in the event control register + [EVENTCTLR1] if supported [IDR5]. + +bit (20) : ETM_MODE_LPOVERRIDE +description : Set to enable the LPOVERRIDE bit in the event control register + [EVENTCTLR1], if supported [IDR5]. + +bit (21) : ETM_MODE_ISTALL_EN +description : Set to enable the ISTALL bit in the stall control register + [STALLCTLR] + +bit (23) : ETM_MODE_INSTPRIO +description : Set to enable the INSTPRIORITY bit in the stall control register + [STALLCTLR] , if supported [IDR0]. + +bit (24) : ETM_MODE_NOOVERFLOW +description : Set to enable the NOOVERFLOW bit in the stall control register + [STALLCTLR], if supported [IDR3]. + +bit (25) : ETM_MODE_TRACE_RESET +description : Set to enable the TRCRESET bit in the viewinst control register + [VICTLR] , if supported [IDR3]. + +bit (26) : ETM_MODE_TRACE_ERR +description : Set to enable the TRCCTRL bit in the viewinst control register + [VICTLR]. + +bit (27) : ETM_MODE_VIEWINST_STARTSTOP +description : Set the initial state value of the ViewInst start / stop logic + in the viewinst control register [VICTLR] + +bit (30) : ETM_MODE_EXCL_KERN +description : Set default trace setup to exclude kernel mode trace (see note a) + +bit (31) : ETM_MODE_EXCL_USER +description : Set default trace setup to exclude user space trace (see note a) + +Note a) On startup the ETM is programmed to trace the complete address space +using address range comparator 0. ‘mode’ bits 30 / 31 modify this setting to +set EL exclude bits for NS state in either user space (EL0) or kernel space +(EL1) in the address range comparator. (the default setting excludes all +secure EL, and NS EL2) + +Once the reset parameter has been used, and/or custom programming has been +implemented - using these bits will result in the EL bits for address +comparator 0 being set in the same way. + +Note b) Bits 2-3, 8-10, 15-16, 18, 22, control features that only work with +data trace. As A profile data trace is architecturally prohibited in ETMv4, +these have been omitted here. Possible uses could be where a kernel has +support for control of R or M profile infrastructure as part of a heterogeneous +system. + +Bits 17, 28-29 are unused. + diff --git a/Documentation/trace/coresight.txt b/Documentation/trace/coresight/coresight.txt similarity index 100% rename from Documentation/trace/coresight.txt rename to Documentation/trace/coresight/coresight.txt diff --git a/MAINTAINERS b/MAINTAINERS index 783569e3c4b4..777b77fde29b 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -1582,8 +1582,7 @@ R: Suzuki K Poulose L: linux-arm-kernel@lists.infradead.org (moderated for non-subscribers) S: Maintained F: drivers/hwtracing/coresight/* -F: Documentation/trace/coresight.txt -F: Documentation/trace/coresight-cpu-debug.txt +F: Documentation/trace/coresight/* F: Documentation/devicetree/bindings/arm/coresight.txt F: Documentation/devicetree/bindings/arm/coresight-cpu-debug.txt F: Documentation/ABI/testing/sysfs-bus-coresight-devices-*