From patchwork Wed Aug 21 10:42:56 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Lukasz Luba X-Patchwork-Id: 11106321 Return-Path: Received: from mail.kernel.org (pdx-korg-mail-1.web.codeaurora.org [172.30.200.123]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id 0D13B14DB for ; Wed, 21 Aug 2019 10:44:05 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.kernel.org (Postfix) with ESMTP id D49CB233FC for ; Wed, 21 Aug 2019 10:44:04 +0000 (UTC) Authentication-Results: mail.kernel.org; dkim=pass (1024-bit key) header.d=samsung.com header.i=@samsung.com header.b="qXbjAUdl" Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1727115AbfHUKn7 (ORCPT ); Wed, 21 Aug 2019 06:43:59 -0400 Received: from mailout2.w1.samsung.com ([210.118.77.12]:35655 "EHLO mailout2.w1.samsung.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1727878AbfHUKnW (ORCPT ); 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Wed, 21 Aug 2019 10:43:16 +0000 (GMT) From: Lukasz Luba To: devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-pm@vger.kernel.org, linux-samsung-soc@vger.kernel.org, linux-clk@vger.kernel.org Cc: mturquette@baylibre.com, sboyd@kernel.org, b.zolnierkie@samsung.com, krzk@kernel.org, kgene@kernel.org, mark.rutland@arm.com, robh+dt@kernel.org, cw00.choi@samsung.com, kyungmin.park@samsung.com, m.szyprowski@samsung.com, s.nawrocki@samsung.com, myungjoo.ham@samsung.com, keescook@chromium.org, tony@atomide.com, jroedel@suse.de, treding@nvidia.com, digetx@gmail.com, gregkh@linuxfoundation.org, willy.mh.wolff.ml@gmail.com, Lukasz Luba Subject: [PATCH v13 1/8] dt-bindings: ddr: rename lpddr2 directory Date: Wed, 21 Aug 2019 12:42:56 +0200 Message-Id: <20190821104303.32079-2-l.luba@partner.samsung.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20190821104303.32079-1-l.luba@partner.samsung.com> X-Brightmail-Tracker: H4sIAAAAAAAAA0VSWUwTURT1zbQz02pxbIk+V7BR4xIRl+AzrhgwI4mJiT9ErTrqCERatWNd wMQqVgRbN4w2SkVjoFCrLYgNEjdKtUhRLBhcwaUmbnXBAhE1KGWq/p17lntuXh6Fy9vFw6gM zVZOq2EzlYRU5LrT3Th5UaxKFf88bzoqNzvE6FHHWzEq8twXowvtAYByzjsIVFBvwVDDQTU6 HPiIo8ZGJ4nu7Q2S6Kl+BGo3tolRc3UhgUImD0DmxhsYuuhpJVHxIz+G/PXJ6NmeUgIZrntI VBvMFaOelnIRuvkwBT37GYW66l6DBUMZ+xk7YLo6j4mYL48NJHNa7xcxV0+1kkyFLY9gblrs JGPK+UwwNZ+vYcyhShtgLvuymVDFqKUDlkvnrOcyM7Zx2inz1kjTbTU2fPM+2Q679QquB9f7 5wMJBekZsLnzuDgfSCk5XQpgW1kNIQwdAPpMHbgwhAD8afLifyO1HxtIQbAC6N3zhPwXaX5z oHcZRRF0HKyybQkHomkzgKffLQt7cPoVDg9dLARhQUEvhKZqIxbGInosrAu2gHBWRs+H5luz hLIYeMF5q69YQi+APUfu9t0K6WIKmozvCMGUBAteNGECVsAP3kpSwCPg76tFEZ6HetM5IOBd MHDYEvHMhrVef9/NOD0BOqqnCHQibN3n66MhHQUffxoUpvFeeMx1EhdoGTywXy64x8NK44NI 0WBotZ+ILGfg/Wo7JrxOAYAlZVewIyDm1P+yswDYwBBOx6vTOH6qhtsex7NqXqdJi1u3SV0B ej+ir8f7rQp0Nq11A5oCygGyqicrVHIxu43fqXYDSOHKaNmOwuUquWw9uzOL025ardVlcrwb DKdEyiGy7H4vV8jpNHYrt5HjNnPavypGSYbpgW1LwY/dA3XWhIQ1TV20vDshN5CVP6bfW1Vq 5/D545wvko4aN9zOTsQc3mTfzFCyJJj1KbHMpThomJ2TweaWt4UaVo3URqW/sqZs/K5Dl8aa Fz/clUd9dTNuLHba2vclR7+MnlS85Lfa4LSsTEk1uBRz47tbfmlcoxZJ+8dH82+UIj6dnToR 1/LsH7p9s/yEAwAA X-Brightmail-Tracker: H4sIAAAAAAAAA+NgFrrCIsWRmVeSWpSXmKPExsVy+t/xe7quCrGxBltWmFtsnLGe1eL6l+es FvOPnGO1WP3xMaNF8+L1bBaTT81lsjjTnWvR//g1s8X58xvYLc42vWG3uNUgY/Gx5x6rxeVd c9gsPvceYbSYcX4fk8XaI3fZLZZev8hkcfGUq8XtxhVsFq17j7BbHH7Tzmrx79pGFov9V7ws bv/ms/h24hGjg6THmnlrGD2+fZ3E4vH+Riu7x+yGiyweO2fdZffYtKqTzWP/3DXsHr3N79g8 Dr7bw+TRt2UVo8fm09UenzfJBfBE6dkU5ZeWpCpk5BeX2CpFG1oY6RlaWugZmVjqGRqbx1oZ mSrp29mkpOZklqUW6dsl6GWsOriKuaCFt2LN8q3MDYx7ubsYOTkkBEwkDr8+w97FyMUhJLCU UeJjxyQ2iISYxKR929khbGGJP9e62CCKPjFKbNnQz9zFyMHBJqAnsWNVIUhcRGAOo8TPrm2M IA6zwG9miYN3+8G6hQWcJHp39TCB2CwCqhIn3lxjBGnmFbCXmHHAEmKBvMTqDQeYQWxOAQeJ fxNOsoLYQkAlUze8ZZ3AyLeAkWEVo0hqaXFuem6xkV5xYm5xaV66XnJ+7iZGYIxuO/Zzyw7G rnfBhxgFOBiVeHh33IyOFWJNLCuuzD3EKMHBrCTCWzEnKlaINyWxsiq1KD++qDQntfgQoynQ TROZpUST84HpI68k3tDU0NzC0tDc2NzYzEJJnLdD4GCMkEB6YklqdmpqQWoRTB8TB6dUA6NY nPV66cIHcVsXBv5pUDANKHqqweh9fce1zH8CZituGwX/danSm7T5Bo/HEm7JaN2Xj1680uRr /X47JuRtvgXTpgeflq/f6tq2tcZr59urexgY/whbH5giZ3tsiQ5b+u7b3svq+jmf+S5V39t4 mE/vIG/7/4Om38R+NhxewCv+8tCiRXvifeWVWIozEg21mIuKEwHtua9Z5wIAAA== X-CMS-MailID: 20190821104318eucas1p1065a4a9d8366095e4d758519f88e8aba X-Msg-Generator: CA X-RootMTR: 20190821104318eucas1p1065a4a9d8366095e4d758519f88e8aba X-EPHeader: CA CMS-TYPE: 201P X-CMS-RootMailID: 20190821104318eucas1p1065a4a9d8366095e4d758519f88e8aba References: <20190821104303.32079-1-l.luba@partner.samsung.com> Sender: linux-pm-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-pm@vger.kernel.org Change directory name to be ready for new types of memories. Reviewed-by: Rob Herring Signed-off-by: Lukasz Luba --- .../devicetree/bindings/{lpddr2 => ddr}/lpddr2-timings.txt | 0 Documentation/devicetree/bindings/{lpddr2 => ddr}/lpddr2.txt | 2 +- 2 files changed, 1 insertion(+), 1 deletion(-) rename Documentation/devicetree/bindings/{lpddr2 => ddr}/lpddr2-timings.txt (100%) rename Documentation/devicetree/bindings/{lpddr2 => ddr}/lpddr2.txt (96%) diff --git a/Documentation/devicetree/bindings/lpddr2/lpddr2-timings.txt b/Documentation/devicetree/bindings/ddr/lpddr2-timings.txt similarity index 100% rename from Documentation/devicetree/bindings/lpddr2/lpddr2-timings.txt rename to Documentation/devicetree/bindings/ddr/lpddr2-timings.txt diff --git a/Documentation/devicetree/bindings/lpddr2/lpddr2.txt b/Documentation/devicetree/bindings/ddr/lpddr2.txt similarity index 96% rename from Documentation/devicetree/bindings/lpddr2/lpddr2.txt rename to Documentation/devicetree/bindings/ddr/lpddr2.txt index 58354a075e13..ddd40121e6f6 100644 --- a/Documentation/devicetree/bindings/lpddr2/lpddr2.txt +++ b/Documentation/devicetree/bindings/ddr/lpddr2.txt @@ -36,7 +36,7 @@ Child nodes: "lpddr2-timings" provides AC timing parameters of the device for a given speed-bin. The user may provide the timings for as many speed-bins as is required. Please see Documentation/devicetree/ - bindings/lpddr2/lpddr2-timings.txt for more information on "lpddr2-timings" + bindings/ddr/lpddr2-timings.txt for more information on "lpddr2-timings" Example: From patchwork Wed Aug 21 10:42:57 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Lukasz Luba X-Patchwork-Id: 11106327 Return-Path: Received: from mail.kernel.org (pdx-korg-mail-1.web.codeaurora.org [172.30.200.123]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id 6E5381805 for ; Wed, 21 Aug 2019 10:44:06 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.kernel.org (Postfix) with ESMTP id 4B7F12339F for ; Wed, 21 Aug 2019 10:44:06 +0000 (UTC) Authentication-Results: mail.kernel.org; dkim=pass (1024-bit key) header.d=samsung.com header.i=@samsung.com header.b="hNKmox1N" Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1727348AbfHUKoF (ORCPT ); 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Wed, 21 Aug 2019 10:43:17 +0000 (GMT) From: Lukasz Luba To: devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-pm@vger.kernel.org, linux-samsung-soc@vger.kernel.org, linux-clk@vger.kernel.org Cc: mturquette@baylibre.com, sboyd@kernel.org, b.zolnierkie@samsung.com, krzk@kernel.org, kgene@kernel.org, mark.rutland@arm.com, robh+dt@kernel.org, cw00.choi@samsung.com, kyungmin.park@samsung.com, m.szyprowski@samsung.com, s.nawrocki@samsung.com, myungjoo.ham@samsung.com, keescook@chromium.org, tony@atomide.com, jroedel@suse.de, treding@nvidia.com, digetx@gmail.com, gregkh@linuxfoundation.org, willy.mh.wolff.ml@gmail.com, Lukasz Luba Subject: [PATCH v13 2/8] dt-bindings: ddr: add LPDDR3 memories Date: Wed, 21 Aug 2019 12:42:57 +0200 Message-Id: <20190821104303.32079-3-l.luba@partner.samsung.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20190821104303.32079-1-l.luba@partner.samsung.com> X-Brightmail-Tracker: H4sIAAAAAAAAA0WSa1CMYRTHPfte22nNa4XjFtYwruU25nEZYlye8cGYCR80YfFOpXbLvoow ZlnXVSFNorJkyGybLppUE6V2RKXk1tII5bKzym3TjMFiexfffuec//n/zzzz8JT6EzOMj9Jv Fw16bYyGVdKlt781TV0+Ojx8mss5BxdlFDC4tecdgy32Jgbnfe5E2HSxgMWn6rMVuPGYDh/v fE/h5uZCDt/b38XhZ8YR+HNSO4MfVmSx2J1sRzij+aYC59ufc/hSa4sCt9QvxW37rrD44A07 h2u7DjPY86SIxlWPVuC27/1x750OFDKU2M7ZEOn9mkqTj46DHMk0ttCk/OxzjhRbj7KkKtvG kWTTB5bc+lCpICklVkSuNewm7uLAVf7rlPO3iDFRCaIheMFGZWRyRgMbVzR+50/XD86IXgSa kR8PwiyorKllzUjJq4UrCF7fuuErehA4O9IouXAjSHd/RGbE96007tsm93MRnHQ70L+N7O63 fSJWCIIy6zZvRICQgSDTGerVUMIrClLys5B3MFBYACntXxgv08I46LGk97FKWAiWtExavm8U 5BVWU172E0LAc+Iu4zUC4QIPrxxtlHzREnj8YrWsHwiuuhJO5hHwq9yikFkCY/IFJPMe6Dye 7dPMg9q6FsZrQwkToaAiWG4vgpL6HEZ27w+O7gHeNvUHU0tP+0JVcOSQWlZPgJKk+76gwZBr S/eZE8jx5Pue8BSCXkc1fQKNOvs/7DxCVjREjJd0EaI0Qy/uCJK0OileHxG0OVZXjP78wwZP XU8ZqvixqQYJPNL4q8qehoWrGW2ClKirQcBTmgDVzqx14WrVFm3iLtEQu8EQHyNKNWg4T2uG qHb3exmmFiK028VoUYwTDX+nCt5vmBEdDU2LTNy7VYDmkJxWTc65VXbF17wgDKlR0ctYK0o4 9qZh6GzPmY6AkSbTgZFjnF2XmhpdsfujJn9f7CxNW7po9ZwplcHUmfa3l7vWF1omx4XN6J4b ekRZ3FhlWRhpJrZq84Hocv/xSabc6ysfEG3g3ZV3yKA19NqwqzNd7fqxRENLkdrpkyiDpP0N VCdrOYMDAAA= X-Brightmail-Tracker: H4sIAAAAAAAAA+NgFrrCIsWRmVeSWpSXmKPExsVy+t/xe7ruCrGxBhu3MFlsnLGe1eL6l+es FvOPnGO1WP3xMaNF8+L1bBaTT81lsjjTnWvR//g1s8X58xvYLc42vWG3uNUgY/Gx5x6rxeVd c9gsPvceYbSYcX4fk8XaI3fZLZZev8hkcfGUq8XtxhVsFq17j7BbHH7Tzmrx79pGFov9V7ws bv/ms/h24hGjg6THmnlrGD2+fZ3E4vH+Riu7x+yGiyweO2fdZffYtKqTzWP/3DXsHr3N79g8 Dr7bw+TRt2UVo8fm09UenzfJBfBE6dkU5ZeWpCpk5BeX2CpFG1oY6RlaWugZmVjqGRqbx1oZ mSrp29mkpOZklqUW6dsl6GX0zjjNVrBRreLvqz/sDYz35boYOTgkBEwkzjQWdjFycQgJLGWU WLntCmMXIydQXExi0r7t7BC2sMSfa11sEEWfGCW+ze1gA2lmE9CT2LEKrFlEYA6jxM+ubYwg DrPAb2aJg3f7wbqFBewk+u59YgWxWQRUJb7MnwZm8wrYS8yfMpsFYoO8xOoNB5hBbE4BB4l/ E06C1QgB1Uzd8JZ1AiPfAkaGVYwiqaXFuem5xUZ6xYm5xaV56XrJ+bmbGIExuu3Yzy07GLve BR9iFOBgVOLh3XEzOlaINbGsuDL3EKMEB7OSCG/FnKhYId6UxMqq1KL8+KLSnNTiQ4ymQEdN ZJYSTc4Hpo+8knhDU0NzC0tDc2NzYzMLJXHeDoGDMUIC6YklqdmpqQWpRTB9TBycUg2MOnNs S59YTOf80THJQfdoRlpCqOTqYIFjT79OzEy8sFzzwazHJ4oFs43KjcrXGe6/x+ThtaktwPXS HE6V2dsXa/J12UnW391lYjPL4MDCa/Mv3cqIi1/AsJKnpF3oxjG5ay55xfbxvzLq2mdOOpS3 p4zr22czFcWDd5VEGTYnXu7MvLCvqPCWEktxRqKhFnNRcSIAFojHLucCAAA= X-CMS-MailID: 20190821104319eucas1p10db51f7a181cae024465cc775292d2b1 X-Msg-Generator: CA X-RootMTR: 20190821104319eucas1p10db51f7a181cae024465cc775292d2b1 X-EPHeader: CA CMS-TYPE: 201P X-CMS-RootMailID: 20190821104319eucas1p10db51f7a181cae024465cc775292d2b1 References: <20190821104303.32079-1-l.luba@partner.samsung.com> Sender: linux-pm-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-pm@vger.kernel.org Specifies the AC timing parameters of the LPDDR3 memory device. Reviewed-by: Rob Herring Signed-off-by: Lukasz Luba --- .../bindings/ddr/lpddr3-timings.txt | 58 +++++++++++ .../devicetree/bindings/ddr/lpddr3.txt | 97 +++++++++++++++++++ 2 files changed, 155 insertions(+) create mode 100644 Documentation/devicetree/bindings/ddr/lpddr3-timings.txt create mode 100644 Documentation/devicetree/bindings/ddr/lpddr3.txt diff --git a/Documentation/devicetree/bindings/ddr/lpddr3-timings.txt b/Documentation/devicetree/bindings/ddr/lpddr3-timings.txt new file mode 100644 index 000000000000..84705e50a3fd --- /dev/null +++ b/Documentation/devicetree/bindings/ddr/lpddr3-timings.txt @@ -0,0 +1,58 @@ +* AC timing parameters of LPDDR3 memories for a given speed-bin. + +The structures are based on LPDDR2 and extended where needed. + +Required properties: +- compatible : Should be "jedec,lpddr3-timings" +- min-freq : minimum DDR clock frequency for the speed-bin. Type is +- reg : maximum DDR clock frequency for the speed-bin. Type is + +Optional properties: + +The following properties represent AC timing parameters from the memory +data-sheet of the device for a given speed-bin. All these properties are +of type and the default unit is ps (pico seconds). +- tRFC +- tRRD +- tRPab +- tRPpb +- tRCD +- tRC +- tRAS +- tWTR +- tWR +- tRTP +- tW2W-C2C +- tR2R-C2C +- tFAW +- tXSR +- tXP +- tCKE +- tCKESR +- tMRD + +Example: + +timings_samsung_K3QF2F20DB_800mhz: lpddr3-timings@800000000 { + compatible = "jedec,lpddr3-timings"; + reg = <800000000>; /* workaround: it shows max-freq */ + min-freq = <100000000>; + tRFC = <65000>; + tRRD = <6000>; + tRPab = <12000>; + tRPpb = <12000>; + tRCD = <10000>; + tRC = <33750>; + tRAS = <23000>; + tWTR = <3750>; + tWR = <7500>; + tRTP = <3750>; + tW2W-C2C = <0>; + tR2R-C2C = <0>; + tFAW = <25000>; + tXSR = <70000>; + tXP = <3750>; + tCKE = <3750>; + tCKESR = <3750>; + tMRD = <7000>; +}; diff --git a/Documentation/devicetree/bindings/ddr/lpddr3.txt b/Documentation/devicetree/bindings/ddr/lpddr3.txt new file mode 100644 index 000000000000..3b2485b84b3f --- /dev/null +++ b/Documentation/devicetree/bindings/ddr/lpddr3.txt @@ -0,0 +1,97 @@ +* LPDDR3 SDRAM memories compliant to JEDEC JESD209-3C + +Required properties: +- compatible : Should be - "jedec,lpddr3" +- density : representing density in Mb (Mega bits) +- io-width : representing bus width. Possible values are 8, 16, 32, 64 +- #address-cells: Must be set to 1 +- #size-cells: Must be set to 0 + +Optional properties: + +The following optional properties represent the minimum value of some AC +timing parameters of the DDR device in terms of number of clock cycles. +These values shall be obtained from the device data-sheet. +- tRFC-min-tck +- tRRD-min-tck +- tRPab-min-tck +- tRPpb-min-tck +- tRCD-min-tck +- tRC-min-tck +- tRAS-min-tck +- tWTR-min-tck +- tWR-min-tck +- tRTP-min-tck +- tW2W-C2C-min-tck +- tR2R-C2C-min-tck +- tWL-min-tck +- tDQSCK-min-tck +- tRL-min-tck +- tFAW-min-tck +- tXSR-min-tck +- tXP-min-tck +- tCKE-min-tck +- tCKESR-min-tck +- tMRD-min-tck + +Child nodes: +- The lpddr3 node may have one or more child nodes of type "lpddr3-timings". + "lpddr3-timings" provides AC timing parameters of the device for + a given speed-bin. Please see Documentation/devicetree/ + bindings/ddr/lpddr3-timings.txt for more information on "lpddr3-timings" + +Example: + +samsung_K3QF2F20DB: lpddr3 { + compatible = "Samsung,K3QF2F20DB", "jedec,lpddr3"; + density = <16384>; + io-width = <32>; + #address-cells = <1>; + #size-cells = <0>; + + tRFC-min-tck = <17>; + tRRD-min-tck = <2>; + tRPab-min-tck = <2>; + tRPpb-min-tck = <2>; + tRCD-min-tck = <3>; + tRC-min-tck = <6>; + tRAS-min-tck = <5>; + tWTR-min-tck = <2>; + tWR-min-tck = <7>; + tRTP-min-tck = <2>; + tW2W-C2C-min-tck = <0>; + tR2R-C2C-min-tck = <0>; + tWL-min-tck = <8>; + tDQSCK-min-tck = <5>; + tRL-min-tck = <14>; + tFAW-min-tck = <5>; + tXSR-min-tck = <12>; + tXP-min-tck = <2>; + tCKE-min-tck = <2>; + tCKESR-min-tck = <2>; + tMRD-min-tck = <5>; + + timings_samsung_K3QF2F20DB_800mhz: lpddr3-timings@800000000 { + compatible = "jedec,lpddr3-timings"; + reg = <800000000>; /* workaround: it shows max-freq */ + min-freq = <100000000>; + tRFC = <65000>; + tRRD = <6000>; + tRPab = <12000>; + tRPpb = <12000>; + tRCD = <10000>; + tRC = <33750>; + tRAS = <23000>; + tWTR = <3750>; + tWR = <7500>; + tRTP = <3750>; + tW2W-C2C = <0>; + tR2R-C2C = <0>; + tFAW = <25000>; + tXSR = <70000>; + tXP = <3750>; + tCKE = <3750>; + tCKESR = <3750>; + tMRD = <7000>; + }; +} From patchwork Wed Aug 21 10:42:58 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Lukasz Luba X-Patchwork-Id: 11106319 Return-Path: Received: from mail.kernel.org (pdx-korg-mail-1.web.codeaurora.org [172.30.200.123]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id F38FB14DB for ; Wed, 21 Aug 2019 10:43:56 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.kernel.org (Postfix) with ESMTP id C8428233FD for ; Wed, 21 Aug 2019 10:43:56 +0000 (UTC) Authentication-Results: mail.kernel.org; dkim=pass (1024-bit key) header.d=samsung.com header.i=@samsung.com header.b="ho629vr0" Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1727467AbfHUKn4 (ORCPT ); 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Wed, 21 Aug 2019 10:43:19 +0000 (GMT) From: Lukasz Luba To: devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-pm@vger.kernel.org, linux-samsung-soc@vger.kernel.org, linux-clk@vger.kernel.org Cc: mturquette@baylibre.com, sboyd@kernel.org, b.zolnierkie@samsung.com, krzk@kernel.org, kgene@kernel.org, mark.rutland@arm.com, robh+dt@kernel.org, cw00.choi@samsung.com, kyungmin.park@samsung.com, m.szyprowski@samsung.com, s.nawrocki@samsung.com, myungjoo.ham@samsung.com, keescook@chromium.org, tony@atomide.com, jroedel@suse.de, treding@nvidia.com, digetx@gmail.com, gregkh@linuxfoundation.org, willy.mh.wolff.ml@gmail.com, Lukasz Luba Subject: [PATCH v13 3/8] drivers: memory: extend of_memory by LPDDR3 support Date: Wed, 21 Aug 2019 12:42:58 +0200 Message-Id: <20190821104303.32079-4-l.luba@partner.samsung.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20190821104303.32079-1-l.luba@partner.samsung.com> X-Brightmail-Tracker: H4sIAAAAAAAAA0WSWUwTURSGvZ2ZdgoUh4J6VRSt0ShRcEu8cddoHIkPRBNN0EqrTABtK3QE WXyoGyoKohgkLAIhUCglVUBkL6vIIlAXIAhGxYiyKWFRI4KMU/Xtu+f8/39OTi6JSb8SC0h/ zVlGq1GqZEIbvPDJj5Y19BK5fG136Wb0MN5EoI6xPgKl1LYQKGekF6BL6SYhim1MFqDmG2p0 q3cAQ62tD0To2cVBEerSOaORm28I9KIkSYhGo2oBim+tEKDc2h4RyuiwCJClcS96fSFLiK6U 14pQzeBVAk21P8SR+aUHev3THk08fQ92zqeN942Anhi/g9NfOq+I6ESdBaeLE3pEdJ7hupA2 JxtFdNSlYSFdNVwmoKMLDIDObwqnR/MWe9p52Wz1YVT+wYzWfbvCxi/z8qQg4Pv+kLrMVEIH Hm+LBCQJqY1woF0TCcSklMoCMPu2aySwmeExACs7fgH+MQpgTNeUiFNxhvHKOIxv6AFs6i8X /LOkNXdhXKyQcoNFhkDO4ETFA5j46RCnwah3GIzOTQJcw5E6AAcKyv4wTi2H2el3hRxLqB3w Vc4XnJ/mAnMeVGIci6mdcCqmgeCCIJVBwvKIRsCL9sCsiY8Yz46wv77AuqoznC5OEfDMQl1U mlV/HvbeSrZqtsCaegvBLY1Rq6CpxJ0v74INKcMEfyJ72DnkwJWxGbxTeA/jyxJ4LULKq1fC gptt1kFzod4YZw2n4Xj+B5w/TyyAScZkEANcEv4PSwXAAOYxQazal2E3aJhzbqxSzQZpfN1O nlHngZl/2DRVP14EKiZPVAOKBDI7iaLjqFxKKIPZUHU1gCQmc5KEJHnJpRIfZWgYoz3jrQ1S MWw1WEjisnmS8Flvj0opX+VZ5jTDBDDav10BKV6gA2bnObt7zUzYYqWnojskePu0esWx56tT CmV9+1pV/pvS1jeVaq9XpiqGl+umterzk1jZZ0OqXVC7Q0hdtbflBJTZ7ninOf5zxMN2aJHq sD46VPYtrCcwOPbUEbm+Kv/gWJH9ubb5EY+yb/TlLNPrfqgVKlPe5tuzndh1tifFS82EDGf9 lOtcMS2r/A29PCBdgwMAAA== X-Brightmail-Tracker: H4sIAAAAAAAAA+NgFrrKIsWRmVeSWpSXmKPExsVy+t/xe7oeCrGxBjOvcltsnLGe1eL6l+es FvOPnGO1WP3xMaNF8+L1bBaTT81lsjjTnWvR//g1s8X58xvYLc42vWG3uNUgY/Gx5x6rxeVd c9gsPvceYbSYcX4fk8XaI3fZLZZev8hkcfGUq8XtxhVsFq17j7BbHH7Tzmrx79pGFov9V7ws bv/ms/h24hGjg6THmnlrGD2+fZ3E4vH+Riu7x+yGiyweO2fdZffYtKqTzWP/3DXsHr3N79g8 Dr7bw+TRt2UVo8fm09UenzfJBfBE6dkU5ZeWpCpk5BeX2CpFG1oY6RlaWugZmVjqGRqbx1oZ mSrp29mkpOZklqUW6dsl6GUsa/nDVPDDs+LosgWsDYzbbbsYOTkkBEwkvh6YxtzFyMUhJLCU UWLaii52iISYxKR926FsYYk/17rYIIo+MUrceNrE0sXIwcEmoCexY1UhSFxEYA6jxM+ubYwg DrPAb2aJg3f7wbqFBXwkXm/ZwwhiswioSqxcPIUNxOYVsJe4uvo9C8QGeYnVGw4wg9icAg4S /yacZAWxhYBqpm54yzqBkW8BI8MqRpHU0uLc9NxiQ73ixNzi0rx0veT83E2MwCjdduzn5h2M lzYGH2IU4GBU4uHdcTM6Vog1say4MvcQowQHs5IIb8WcqFgh3pTEyqrUovz4otKc1OJDjKZA R01klhJNzgcmkLySeENTQ3MLS0NzY3NjMwslcd4OgYMxQgLpiSWp2ampBalFMH1MHJxSDYyK 7/rEFQ0iSs/or2t/aPHk2VVDQ6trjtsdeVn7rzy6Jem0jvX08R7fVTtuCz7scva/tIe/aC2/ mgaTrGGe4JvVriy8CdG6mSvenlVTSr/S3LfU3HfGrx4O5dJ9GzWdJGZNVmHjqp+27Tr/8eTZ CzYcvlx597jpLyfbz0KH3sXFFuxwui1eYa/EUpyRaKjFXFScCAADHH0M6AIAAA== X-CMS-MailID: 20190821104320eucas1p10c911c2ce59007bcf6c039f52b869656 X-Msg-Generator: CA X-RootMTR: 20190821104320eucas1p10c911c2ce59007bcf6c039f52b869656 X-EPHeader: CA CMS-TYPE: 201P X-CMS-RootMailID: 20190821104320eucas1p10c911c2ce59007bcf6c039f52b869656 References: <20190821104303.32079-1-l.luba@partner.samsung.com> Sender: linux-pm-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-pm@vger.kernel.org The patch adds AC timings information needed to support LPDDR3 and memory controllers. The structure is used in of_memory and currently in Exynos 5422 DMC. Add parsing data needed for LPDDR3 support. It is currently used in Exynos5422 Dynamic Memory Controller. Acked-by: Krzysztof Kozlowski Signed-off-by: Lukasz Luba --- drivers/memory/jedec_ddr.h | 61 +++++++++++++++ drivers/memory/of_memory.c | 149 +++++++++++++++++++++++++++++++++++++ drivers/memory/of_memory.h | 18 +++++ 3 files changed, 228 insertions(+) diff --git a/drivers/memory/jedec_ddr.h b/drivers/memory/jedec_ddr.h index 4a21b5044ff8..e59ccbd982d0 100644 --- a/drivers/memory/jedec_ddr.h +++ b/drivers/memory/jedec_ddr.h @@ -29,6 +29,7 @@ #define DDR_TYPE_LPDDR2_S4 3 #define DDR_TYPE_LPDDR2_S2 4 #define DDR_TYPE_LPDDR2_NVM 5 +#define DDR_TYPE_LPDDR3 6 /* DDR IO width */ #define DDR_IO_WIDTH_4 1 @@ -169,4 +170,64 @@ extern const struct lpddr2_timings lpddr2_jedec_timings[NUM_DDR_TIMING_TABLE_ENTRIES]; extern const struct lpddr2_min_tck lpddr2_jedec_min_tck; +/* + * Structure for timings for LPDDR3 based on LPDDR2 plus additional fields. + * All parameters are in pico seconds(ps) excluding max_freq, min_freq which + * are in Hz. + */ +struct lpddr3_timings { + u32 max_freq; + u32 min_freq; + u32 tRFC; + u32 tRRD; + u32 tRPab; + u32 tRPpb; + u32 tRCD; + u32 tRC; + u32 tRAS; + u32 tWTR; + u32 tWR; + u32 tRTP; + u32 tW2W_C2C; + u32 tR2R_C2C; + u32 tWL; + u32 tDQSCK; + u32 tRL; + u32 tFAW; + u32 tXSR; + u32 tXP; + u32 tCKE; + u32 tCKESR; + u32 tMRD; +}; + +/* + * Min value for some parameters in terms of number of tCK cycles(nCK) + * Please set to zero parameters that are not valid for a given memory + * type + */ +struct lpddr3_min_tck { + u32 tRFC; + u32 tRRD; + u32 tRPab; + u32 tRPpb; + u32 tRCD; + u32 tRC; + u32 tRAS; + u32 tWTR; + u32 tWR; + u32 tRTP; + u32 tW2W_C2C; + u32 tR2R_C2C; + u32 tWL; + u32 tDQSCK; + u32 tRL; + u32 tFAW; + u32 tXSR; + u32 tXP; + u32 tCKE; + u32 tCKESR; + u32 tMRD; +}; + #endif /* __JEDEC_DDR_H */ diff --git a/drivers/memory/of_memory.c b/drivers/memory/of_memory.c index 46539b27a3fb..71f26eac7350 100644 --- a/drivers/memory/of_memory.c +++ b/drivers/memory/of_memory.c @@ -3,6 +3,7 @@ * OpenFirmware helpers for memory drivers * * Copyright (C) 2012 Texas Instruments, Inc. + * Copyright (C) 2019 Samsung Electronics Co., Ltd. */ #include @@ -149,3 +150,151 @@ const struct lpddr2_timings *of_get_ddr_timings(struct device_node *np_ddr, return lpddr2_jedec_timings; } EXPORT_SYMBOL(of_get_ddr_timings); + +/** + * of_lpddr3_get_min_tck() - extract min timing values for lpddr3 + * @np: pointer to ddr device tree node + * @device: device requesting for min timing values + * + * Populates the lpddr3_min_tck structure by extracting data + * from device tree node. Returns a pointer to the populated + * structure. If any error in populating the structure, returns NULL. + */ +const struct lpddr3_min_tck *of_lpddr3_get_min_tck(struct device_node *np, + struct device *dev) +{ + int ret = 0; + struct lpddr3_min_tck *min; + + min = devm_kzalloc(dev, sizeof(*min), GFP_KERNEL); + if (!min) + goto default_min_tck; + + ret |= of_property_read_u32(np, "tRFC-min-tck", &min->tRFC); + ret |= of_property_read_u32(np, "tRRD-min-tck", &min->tRRD); + ret |= of_property_read_u32(np, "tRPab-min-tck", &min->tRPab); + ret |= of_property_read_u32(np, "tRPpb-min-tck", &min->tRPpb); + ret |= of_property_read_u32(np, "tRCD-min-tck", &min->tRCD); + ret |= of_property_read_u32(np, "tRC-min-tck", &min->tRC); + ret |= of_property_read_u32(np, "tRAS-min-tck", &min->tRAS); + ret |= of_property_read_u32(np, "tWTR-min-tck", &min->tWTR); + ret |= of_property_read_u32(np, "tWR-min-tck", &min->tWR); + ret |= of_property_read_u32(np, "tRTP-min-tck", &min->tRTP); + ret |= of_property_read_u32(np, "tW2W-C2C-min-tck", &min->tW2W_C2C); + ret |= of_property_read_u32(np, "tR2R-C2C-min-tck", &min->tR2R_C2C); + ret |= of_property_read_u32(np, "tWL-min-tck", &min->tWL); + ret |= of_property_read_u32(np, "tDQSCK-min-tck", &min->tDQSCK); + ret |= of_property_read_u32(np, "tRL-min-tck", &min->tRL); + ret |= of_property_read_u32(np, "tFAW-min-tck", &min->tFAW); + ret |= of_property_read_u32(np, "tXSR-min-tck", &min->tXSR); + ret |= of_property_read_u32(np, "tXP-min-tck", &min->tXP); + ret |= of_property_read_u32(np, "tCKE-min-tck", &min->tCKE); + ret |= of_property_read_u32(np, "tCKESR-min-tck", &min->tCKESR); + ret |= of_property_read_u32(np, "tMRD-min-tck", &min->tMRD); + + if (ret) { + dev_warn(dev, "%s: errors while parsing min-tck values\n", + __func__); + devm_kfree(dev, min); + goto default_min_tck; + } + + return min; + +default_min_tck: + dev_warn(dev, "%s: using default min-tck values\n", __func__); + return NULL; +} +EXPORT_SYMBOL(of_lpddr3_get_min_tck); + +static int of_lpddr3_do_get_timings(struct device_node *np, + struct lpddr3_timings *tim) +{ + int ret; + + /* The 'reg' param required since DT has changed, used as 'max-freq' */ + ret = of_property_read_u32(np, "reg", &tim->max_freq); + ret |= of_property_read_u32(np, "min-freq", &tim->min_freq); + ret |= of_property_read_u32(np, "tRFC", &tim->tRFC); + ret |= of_property_read_u32(np, "tRRD", &tim->tRRD); + ret |= of_property_read_u32(np, "tRPab", &tim->tRPab); + ret |= of_property_read_u32(np, "tRPpb", &tim->tRPpb); + ret |= of_property_read_u32(np, "tRCD", &tim->tRCD); + ret |= of_property_read_u32(np, "tRC", &tim->tRC); + ret |= of_property_read_u32(np, "tRAS", &tim->tRAS); + ret |= of_property_read_u32(np, "tWTR", &tim->tWTR); + ret |= of_property_read_u32(np, "tWR", &tim->tWR); + ret |= of_property_read_u32(np, "tRTP", &tim->tRTP); + ret |= of_property_read_u32(np, "tW2W-C2C", &tim->tW2W_C2C); + ret |= of_property_read_u32(np, "tR2R-C2C", &tim->tR2R_C2C); + ret |= of_property_read_u32(np, "tFAW", &tim->tFAW); + ret |= of_property_read_u32(np, "tXSR", &tim->tXSR); + ret |= of_property_read_u32(np, "tXP", &tim->tXP); + ret |= of_property_read_u32(np, "tCKE", &tim->tCKE); + ret |= of_property_read_u32(np, "tCKESR", &tim->tCKESR); + ret |= of_property_read_u32(np, "tMRD", &tim->tMRD); + + return ret; +} + +/** + * of_lpddr3_get_ddr_timings() - extracts the lpddr3 timings and updates no of + * frequencies available. + * @np_ddr: Pointer to ddr device tree node + * @dev: Device requesting for ddr timings + * @device_type: Type of ddr + * @nr_frequencies: No of frequencies available for ddr + * (updated by this function) + * + * Populates lpddr3_timings structure by extracting data from device + * tree node. Returns pointer to populated structure. If any error + * while populating, returns NULL. + */ +const struct lpddr3_timings +*of_lpddr3_get_ddr_timings(struct device_node *np_ddr, struct device *dev, + u32 device_type, u32 *nr_frequencies) +{ + struct lpddr3_timings *timings = NULL; + u32 arr_sz = 0, i = 0; + struct device_node *np_tim; + char *tim_compat = NULL; + + switch (device_type) { + case DDR_TYPE_LPDDR3: + tim_compat = "jedec,lpddr3-timings"; + break; + default: + dev_warn(dev, "%s: un-supported memory type\n", __func__); + } + + for_each_child_of_node(np_ddr, np_tim) + if (of_device_is_compatible(np_tim, tim_compat)) + arr_sz++; + + if (arr_sz) + timings = devm_kcalloc(dev, arr_sz, sizeof(*timings), + GFP_KERNEL); + + if (!timings) + goto default_timings; + + for_each_child_of_node(np_ddr, np_tim) { + if (of_device_is_compatible(np_tim, tim_compat)) { + if (of_lpddr3_do_get_timings(np_tim, &timings[i])) { + devm_kfree(dev, timings); + goto default_timings; + } + i++; + } + } + + *nr_frequencies = arr_sz; + + return timings; + +default_timings: + dev_warn(dev, "%s: failed to get timings\n", __func__); + *nr_frequencies = 0; + return NULL; +} +EXPORT_SYMBOL(of_lpddr3_get_ddr_timings); diff --git a/drivers/memory/of_memory.h b/drivers/memory/of_memory.h index b077cc836b0b..e39ecc4c733d 100644 --- a/drivers/memory/of_memory.h +++ b/drivers/memory/of_memory.h @@ -14,6 +14,11 @@ extern const struct lpddr2_min_tck *of_get_min_tck(struct device_node *np, extern const struct lpddr2_timings *of_get_ddr_timings(struct device_node *np_ddr, struct device *dev, u32 device_type, u32 *nr_frequencies); +extern const struct lpddr3_min_tck + *of_lpddr3_get_min_tck(struct device_node *np, struct device *dev); +extern const struct lpddr3_timings + *of_lpddr3_get_ddr_timings(struct device_node *np_ddr, + struct device *dev, u32 device_type, u32 *nr_frequencies); #else static inline const struct lpddr2_min_tck *of_get_min_tck(struct device_node *np, struct device *dev) @@ -27,6 +32,19 @@ static inline const struct lpddr2_timings { return NULL; } + +static inline const struct lpddr3_min_tck + *of_lpddr3_get_min_tck(struct device_node *np, struct device *dev) +{ + return NULL; +} + +static inline const struct lpddr3_timings + *of_lpddr3_get_ddr_timings(struct device_node *np_ddr, + struct device *dev, u32 device_type, u32 *nr_frequencies) +{ + return NULL; +} #endif /* CONFIG_OF && CONFIG_DDR */ #endif /* __LINUX_MEMORY_OF_REG_ */ From patchwork Wed Aug 21 10:42:59 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Lukasz Luba X-Patchwork-Id: 11106313 Return-Path: Received: from mail.kernel.org (pdx-korg-mail-1.web.codeaurora.org [172.30.200.123]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id 0E03714DB for ; Wed, 21 Aug 2019 10:43:52 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.kernel.org (Postfix) with ESMTP id CD2D3233A1 for ; Wed, 21 Aug 2019 10:43:51 +0000 (UTC) Authentication-Results: mail.kernel.org; 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Wed, 21 Aug 2019 10:43:21 +0000 (GMT) X-AuditID: cbfec7f5-92d689c000001116-5f-5d5d204a012a Received: from eusmtip2.samsung.com ( [203.254.199.222]) by eusmgms2.samsung.com (EUCPMTA) with SMTP id 3B.38.04117.9402D5D5; Wed, 21 Aug 2019 11:43:21 +0100 (BST) Received: from AMDC3778.DIGITAL.local (unknown [106.120.51.20]) by eusmtip2.samsung.com (KnoxPortal) with ESMTPA id 20190821104320eusmtip22013ef5d9a804467bdcbab1003fc5b2f~86iGNMDus1420714207eusmtip2O; Wed, 21 Aug 2019 10:43:20 +0000 (GMT) From: Lukasz Luba To: devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-pm@vger.kernel.org, linux-samsung-soc@vger.kernel.org, linux-clk@vger.kernel.org Cc: mturquette@baylibre.com, sboyd@kernel.org, b.zolnierkie@samsung.com, krzk@kernel.org, kgene@kernel.org, mark.rutland@arm.com, robh+dt@kernel.org, cw00.choi@samsung.com, kyungmin.park@samsung.com, m.szyprowski@samsung.com, s.nawrocki@samsung.com, myungjoo.ham@samsung.com, keescook@chromium.org, tony@atomide.com, jroedel@suse.de, treding@nvidia.com, digetx@gmail.com, gregkh@linuxfoundation.org, willy.mh.wolff.ml@gmail.com, Lukasz Luba Subject: [PATCH v13 4/8] dt-bindings: memory-controllers: add Exynos5422 DMC device description Date: Wed, 21 Aug 2019 12:42:59 +0200 Message-Id: <20190821104303.32079-5-l.luba@partner.samsung.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20190821104303.32079-1-l.luba@partner.samsung.com> X-Brightmail-Tracker: H4sIAAAAAAAAA0VSa1BMYRju23POnrON5bQ19SYjszNMDCEyn9G4zLicMSMN44eaRktnKnYr e1q5jdmYxNYWcmm6uYSS1XbZSUVh25HuLVI0GYSMSyShoWidxb/nfd7n+Z5n3vkYQvGRmszE xCbw2liVWil1JSvvjrTNWTstPHyeoWoSLssyU7jrSz+Fz9raKHx1sA/hQwVmKc5sypPgllQN zuh7R+D29lIatx58T+Mn+il4MO0phR/U5ErxkNGGcFZ7nQRfs/XS+FKXXYLtTatwT1KRFCfX 2mhc/z6FwmOPykh86+Fa3PNjIv567wVa7s2Z8k2I+zp8guQ+difTXI7eTnLV2b00V158VMrd yjPRnPHQgJS7M3BTwqVbihFX0byPGyqfGjIh1DUoklfH7OK1c5dGuEZbkiLj0313V1/ppPSo 39uAZAywC8Fq7pYakCujYIsQjLzsIMThC4Kkb62kOAwhyBwokfy1HDmZ7rQUIrAeHyP/WR5X jtIGxDBS1h+qinc6DB5sFoKcNxsdGoJ9TkD6tVzkWLizKjAOi3qSnQ6Db3QOWs4ug3MXsygx zBeult4mHFjGLoexY42U4x1g8xgwp712ilZCb0knLWJ3eNtgceIp8Kv6rLO1AHrjeSTi/dCX kefULIH6Bjvl6ECwM8FcM1ekV0B14cs/1YCdCN0f3Bw0MQ5PVJ4hRFoORw4rRLUfWNI6nEGe UGg67XRyUGCWiMfJRPCupoc8hnyz/2edQ6gYefE6QRPFCwti+UR/QaURdLFR/tviNOVo/Bs2 jzUMV6G6n1utiGWQcoI8oissXEGpdgl7NFYEDKH0kO/ODQ1XyCNVe/by2rgtWp2aF6zIhyGV XvJ9Ls/CFGyUKoHfwfPxvPbvVsLIJutR6HePAO/r91MD1SPui74bE4K9Ita4yBbf8aN/PJV5 K9Ylrs9XJCce0G+f3YJ04Ea+2mhJianI78i2ddWm9O/0ejtasOiJIdgnKIjJUQ+wPptCAm60 azxJbBjtdlv9cIbnBrtn2eVPppitvbW50Z8bi0oDi1oDEjNWX1ix+VNE3SklKUSr5s8itILq N31b1tuCAwAA X-Brightmail-Tracker: H4sIAAAAAAAAA+NgFrrMIsWRmVeSWpSXmKPExsVy+t/xe7qeCrGxBn/axS02zljPanH9y3NW i/lHzrFarP74mNGiefF6NovJp+YyWZzpzrXof/ya2eL8+Q3sFmeb3rBb3GqQsfjYc4/V4vKu OWwWn3uPMFrMOL+PyWLtkbvsFkuvX2SyuHjK1eJ24wo2i9a9R9gtDr9pZ7X4d20ji8X+K14W t3/zWXw78YjRQdJjzbw1jB7fvk5i8Xh/o5XdY3bDRRaPnbPusntsWtXJ5rF/7hp2j97md2we B9/tYfLo27KK0WPz6WqPz5vkAnii9GyK8ktLUhUy8otLbJWiDS2M9AwtLfSMTCz1DI3NY62M TJX07WxSUnMyy1KL9O0S9DK2NKYU9MlX7Fx5lbWB8blkFyMnh4SAiUTHlD62LkYuDiGBpYwS f5a/YYZIiElM2redHcIWlvhzrQuq6BOjRP/CE0BFHBxsAnoSO1YVgsRFBOYwSvzs2sYI4jAL /GaWOHi3H6xbWCBe4tjvH6wgDSwCqhIfX5SChHkF7CUWLJnBCrFAXmL1hgNgizkFHCT+TTgJ FhcCqpm64S3rBEa+BYwMqxhFUkuLc9Nzi430ihNzi0vz0vWS83M3MQIjdNuxn1t2MHa9Cz7E KMDBqMTDu+NmdKwQa2JZcWXuIUYJDmYlEd6KOVGxQrwpiZVVqUX58UWlOanFhxhNgW6ayCwl mpwPTB55JfGGpobmFpaG5sbmxmYWSuK8HQIHY4QE0hNLUrNTUwtSi2D6mDg4pRoY+5XM433/ c6jr/Tn20GNq7Dr3/7cEtA0uxvCvV52mf/hkQt0m34N76lYfX+A5+5wK+8GfpRs3K1inGTDp VYjkvn7atDmcYZ6jh/N/C7ZlsRs2W15vi+58WOXM+jD29zymGR5uAfP/as/sU1WdmcNz0lnx +u3p511ldZzMM0RdWU+fDOZ5eXqpEktxRqKhFnNRcSIAgzYIleYCAAA= X-CMS-MailID: 20190821104321eucas1p284816ade1890e9660008c0428c6d56e0 X-Msg-Generator: CA X-RootMTR: 20190821104321eucas1p284816ade1890e9660008c0428c6d56e0 X-EPHeader: CA CMS-TYPE: 201P X-CMS-RootMailID: 20190821104321eucas1p284816ade1890e9660008c0428c6d56e0 References: <20190821104303.32079-1-l.luba@partner.samsung.com> Sender: linux-pm-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-pm@vger.kernel.org The patch adds description for DT binding for a new Exynos5422 Dynamic Memory Controller device. Acked-by: Krzysztof Kozlowski Reviewed-by: Rob Herring Signed-off-by: Lukasz Luba --- .../memory-controllers/exynos5422-dmc.txt | 73 +++++++++++++++++++ 1 file changed, 73 insertions(+) create mode 100644 Documentation/devicetree/bindings/memory-controllers/exynos5422-dmc.txt diff --git a/Documentation/devicetree/bindings/memory-controllers/exynos5422-dmc.txt b/Documentation/devicetree/bindings/memory-controllers/exynos5422-dmc.txt new file mode 100644 index 000000000000..02aeb3b5a820 --- /dev/null +++ b/Documentation/devicetree/bindings/memory-controllers/exynos5422-dmc.txt @@ -0,0 +1,73 @@ +* Exynos5422 frequency and voltage scaling for Dynamic Memory Controller device + +The Samsung Exynos5422 SoC has DMC (Dynamic Memory Controller) to which the DRAM +memory chips are connected. The driver is to monitor the controller in runtime +and switch frequency and voltage. To monitor the usage of the controller in +runtime, the driver uses the PPMU (Platform Performance Monitoring Unit), which +is able to measure the current load of the memory. +When 'userspace' governor is used for the driver, an application is able to +switch the DMC and memory frequency. + +Required properties for DMC device for Exynos5422: +- compatible: Should be "samsung,exynos5422-dmc". +- clocks : list of clock specifiers, must contain an entry for each + required entry in clock-names for CLK_FOUT_SPLL, CLK_MOUT_SCLK_SPLL, + CLK_FF_DOUT_SPLL2, CLK_FOUT_BPLL, CLK_MOUT_BPLL, CLK_SCLK_BPLL, + CLK_MOUT_MX_MSPLL_CCORE, CLK_MOUT_MX_MSPLL_CCORE_PHY, CLK_MOUT_MCLK_CDREX, +- clock-names : should include "fout_spll", "mout_sclk_spll", "ff_dout_spll2", + "fout_bpll", "mout_bpll", "sclk_bpll", "mout_mx_mspll_ccore", + "mout_mclk_cdrex" entries +- devfreq-events : phandles for PPMU devices connected to this DMC. +- vdd-supply : phandle for voltage regulator which is connected. +- reg : registers of two CDREX controllers. +- operating-points-v2 : phandle for OPPs described in v2 definition. +- device-handle : phandle of the connected DRAM memory device. For more + information please refer to documentation file: + Documentation/devicetree/bindings/ddr/lpddr3.txt +- devfreq-events : phandles of the PPMU events used by the controller. +- samsung,syscon-clk : phandle of the clock register set used by the controller, + these registers are used for enabling a 'pause' feature and are not + exposed by clock framework but they must be used in a safe way. + The register offsets are in the driver code and specyfic for this SoC + type. + +Example: + + ppmu_dmc0_0: ppmu@10d00000 { + compatible = "samsung,exynos-ppmu"; + reg = <0x10d00000 0x2000>; + clocks = <&clock CLK_PCLK_PPMU_DREX0_0>; + clock-names = "ppmu"; + events { + ppmu_event_dmc0_0: ppmu-event3-dmc0_0 { + event-name = "ppmu-event3-dmc0_0"; + }; + }; + }; + + dmc: memory-controller@10c20000 { + compatible = "samsung,exynos5422-dmc"; + reg = <0x10c20000 0x100>, <0x10c30000 0x100>, + clocks = <&clock CLK_FOUT_SPLL>, + <&clock CLK_MOUT_SCLK_SPLL>, + <&clock CLK_FF_DOUT_SPLL2>, + <&clock CLK_FOUT_BPLL>, + <&clock CLK_MOUT_BPLL>, + <&clock CLK_SCLK_BPLL>, + <&clock CLK_MOUT_MX_MSPLL_CCORE>, + <&clock CLK_MOUT_MCLK_CDREX>, + clock-names = "fout_spll", + "mout_sclk_spll", + "ff_dout_spll2", + "fout_bpll", + "mout_bpll", + "sclk_bpll", + "mout_mx_mspll_ccore", + "mout_mclk_cdrex", + operating-points-v2 = <&dmc_opp_table>; + devfreq-events = <&ppmu_event3_dmc0_0>, <&ppmu_event3_dmc0_1>, + <&ppmu_event3_dmc1_0>, <&ppmu_event3_dmc1_1>; + device-handle = <&samsung_K3QF2F20DB>; + vdd-supply = <&buck1_reg>; + samsung,syscon-clk = <&clock>; + }; From patchwork Wed Aug 21 10:43:00 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Lukasz Luba X-Patchwork-Id: 11106289 Return-Path: Received: from mail.kernel.org (pdx-korg-mail-1.web.codeaurora.org [172.30.200.123]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id A3EB5184E for ; Wed, 21 Aug 2019 10:43:30 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.kernel.org (Postfix) with ESMTP id 645B3233A0 for ; Wed, 21 Aug 2019 10:43:30 +0000 (UTC) Authentication-Results: mail.kernel.org; dkim=pass (1024-bit key) header.d=samsung.com header.i=@samsung.com header.b="SkcVEuvj" Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1728335AbfHUKn3 (ORCPT ); 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Wed, 21 Aug 2019 10:43:21 +0000 (GMT) From: Lukasz Luba To: devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-pm@vger.kernel.org, linux-samsung-soc@vger.kernel.org, linux-clk@vger.kernel.org Cc: mturquette@baylibre.com, sboyd@kernel.org, b.zolnierkie@samsung.com, krzk@kernel.org, kgene@kernel.org, mark.rutland@arm.com, robh+dt@kernel.org, cw00.choi@samsung.com, kyungmin.park@samsung.com, m.szyprowski@samsung.com, s.nawrocki@samsung.com, myungjoo.ham@samsung.com, keescook@chromium.org, tony@atomide.com, jroedel@suse.de, treding@nvidia.com, digetx@gmail.com, gregkh@linuxfoundation.org, willy.mh.wolff.ml@gmail.com, Lukasz Luba Subject: [PATCH v13 5/8] drivers: memory: add DMC driver for Exynos5422 Date: Wed, 21 Aug 2019 12:43:00 +0200 Message-Id: <20190821104303.32079-6-l.luba@partner.samsung.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20190821104303.32079-1-l.luba@partner.samsung.com> X-Brightmail-Tracker: H4sIAAAAAAAAA0VSa2xLYRj2nUvPWbMuZ7XMa8RoIkGymUvkSyyMuBwWiUT4gYbiZC5r0aPo XFJmLrvSJrvZbMsw6zq7GGZ2U2W2oRrCGAsWGdtc22HIWHuKf8/zvM/zPe+bfCyp/EKHsVt0 uwS9ThOvksmpK7cHnRGx49XqqIGcKFyVXUHjJ54eGhc47tO47HM3wonFFTJsacsn8N0ULc7o 7iOx01nJ4HuH+xn8zDQWf07tovHDujwZdqc5EM52NhK43PGCweeeuAjsaluIOw9dkOGkBgeD b/Yfo/HQ4yoKNz1aijt/BuGvd16jmNG87YwN8V8HzBT/sSOJ4U+bXBR/LfcFw1dbT8j4pnwb w6clfpDxNz7UE3x6jRXxl9r38e7qccsDV8ujNwnxW3YL+qlz1ss3v8wuJXbcaSX2NnSmESZU mkokowAWuJlwz+WmkpGcVXIXEDRnuRmJeBB02AZpibgRWG78oP5G0lM8/kEJAtv7y8S/SEN7 4jBhWRkXCbXWnd5ACJeN4PTbFV4Pyb0iIb08D3k9I7nF8KbVtwfFTYQu93MfVnBz4VBVJSOV hUNZZTPpxQFcDAydbPUVA1fEQpuzn5RMC+BRcolMwiOht6XGHx4Lv68V+A8VwZRWhCS8H7oz 8v2e2XCzxUV79yG5yVBRN1WS50GOqdQnAxcEHe+DvTI5DM1XskhJVsDxo0rJPQlqUh/4i0Kh xJbpf5yHnE8ZPqzkLAg89lknUXju/65ChKxolGAQtXGCOF0n7IkUNVrRoIuL3LhdW42Gf2L7 UIunFtX92mBHHItUgYrap2vUSlqzWzRq7QhYUhWi2Ju3Wq1UbNIYEwT99nV6Q7wg2tEYllKN Uuwb8XKNkovT7BK2CcIOQf93SrABYSYUk9ElL5xwWZnV892eMuZqz/n7LiH36sW+g5TYHJ4T FDF0652xMfDZ2oSo2m+WmZl7ouvLHL395ulH5p/daHxXj0XrwpU/GntNMxLmHJhr0GnDwi2G 4gfjo2Ht1uBghfrI9ajQ20ZV293QXmZSkvnUuoHywSXp+tiBZX0RfeZPqxapKHGzZtoUUi9q /gANksNghQMAAA== X-Brightmail-Tracker: H4sIAAAAAAAAA+NgFrrGIsWRmVeSWpSXmKPExsVy+t/xe7peCrGxBq9fy1tsnLGe1eL6l+es FvOPnGO1WP3xMaNF8+L1bBaTT81lsjjTnWvR//g1s8X58xvYLc42vWG3uNUgY/Gx5x6rxeVd c9gsPvceYbSYcX4fk8XaI3fZLZZev8hkcfGUq8XtxhVsFq17j7BbHH7Tzmrx79pGFov9V7ws bv/ms/h24hGjg6THmnlrGD2+fZ3E4vH+Riu7x+yGiyweO2fdZffYtKqTzWP/3DXsHr3N79g8 Dr7bw+TRt2UVo8fm09UenzfJBfBE6dkU5ZeWpCpk5BeX2CpFG1oY6RlaWugZmVjqGRqbx1oZ mSrp29mkpOZklqUW6dsl6GU8mLGSqeDESaaKvbd7mRoYV/YwdTFyckgImEj0dX9h7WLk4hAS WMoocePlaTaIhJjEpH3b2SFsYYk/17rYIIo+MUrs+H2GpYuRg4NNQE9ix6pCkLiIwBxGiZ9d 2xhBHGaB38wSB+/2s4MUCQu4Szw9CbaNRUBV4t7nO2A2r4C9ROPGDVAL5CVWbzjADGJzCjhI /JtwkhXEFgKqmbrhLesERr4FjAyrGEVSS4tz03OLDfWKE3OLS/PS9ZLzczcxAuN027Gfm3cw XtoYfIhRgINRiYd3x83oWCHWxLLiytxDjBIczEoivBVzomKFeFMSK6tSi/Lji0pzUosPMZoC HTWRWUo0OR+YQvJK4g1NDc0tLA3Njc2NzSyUxHk7BA7GCAmkJ5akZqemFqQWwfQxcXBKNTA6 HGzomxrv1j11+oQqoeOn73rLT5okvux8R/8q9pCXSjKyFW81M3xNOfXOqdnKJPZ6mcQd8bBa baj/Jf9av4vmFK+FN/9xXCvv9TzTedT1V7+jU6GQxhQtuzgHcb8fu6Me7tTeeiws6q9S1zUh 89KDBRcOiOg+ldBplWe+2cL352Z25uaD85VYijMSDbWYi4oTAbk4eIbpAgAA X-CMS-MailID: 20190821104323eucas1p1ab979133de45373866e9db1a5f63fb76 X-Msg-Generator: CA X-RootMTR: 20190821104323eucas1p1ab979133de45373866e9db1a5f63fb76 X-EPHeader: CA CMS-TYPE: 201P X-CMS-RootMailID: 20190821104323eucas1p1ab979133de45373866e9db1a5f63fb76 References: <20190821104303.32079-1-l.luba@partner.samsung.com> Sender: linux-pm-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-pm@vger.kernel.org This patch adds driver for Exynos5422 Dynamic Memory Controller. The driver provides support for dynamic frequency and voltage scaling for DMC and DRAM. It supports changing timings of DRAM running with different frequency. There is also an algorithm to calculate timigns based on memory description provided in DT. The patch also contains needed MAINTAINERS file update. Signed-off-by: Lukasz Luba --- MAINTAINERS | 8 + drivers/memory/samsung/Kconfig | 13 + drivers/memory/samsung/Makefile | 1 + drivers/memory/samsung/exynos5422-dmc.c | 1257 +++++++++++++++++++++++ 4 files changed, 1279 insertions(+) create mode 100644 drivers/memory/samsung/exynos5422-dmc.c diff --git a/MAINTAINERS b/MAINTAINERS index 08176d64eed5..78302ccec834 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -4930,6 +4930,14 @@ F: include/linux/dma-direct.h F: include/linux/dma-mapping.h F: include/linux/dma-noncoherent.h +DMC FREQUENCY DRIVER FOR SAMSUNG EXYNOS5422 +M: Lukasz Luba +L: linux-pm@vger.kernel.org +L: linux-samsung-soc@vger.kernel.org +S: Maintained +F: drivers/memory/samsung/exynos5422-dmc.c +F: Documentation/devicetree/bindings/memory-controllers/exynos5422-dmc.txt + DME1737 HARDWARE MONITOR DRIVER M: Juerg Haefliger L: linux-hwmon@vger.kernel.org diff --git a/drivers/memory/samsung/Kconfig b/drivers/memory/samsung/Kconfig index 79ce7ea58903..e9c3ce92350c 100644 --- a/drivers/memory/samsung/Kconfig +++ b/drivers/memory/samsung/Kconfig @@ -7,6 +7,19 @@ config SAMSUNG_MC if SAMSUNG_MC +config EXYNOS5422_DMC + tristate "EXYNOS5422 Dynamic Memory Controller driver" + depends on ARCH_EXYNOS || (COMPILE_TEST && HAS_IOMEM) + select DDR + depends on DEVFREQ_GOV_SIMPLE_ONDEMAND + depends on (PM_DEVFREQ && PM_DEVFREQ_EVENT) + help + This adds driver for Exynos5422 DMC (Dynamic Memory Controller). + The driver provides support for Dynamic Voltage and Frequency Scaling in + DMC and DRAM. It also supports changing timings of DRAM running with + different frequency. The timings are calculated based on DT memory + information. + config EXYNOS_SROM bool "Exynos SROM controller driver" if COMPILE_TEST depends on (ARM && ARCH_EXYNOS) || (COMPILE_TEST && HAS_IOMEM) diff --git a/drivers/memory/samsung/Makefile b/drivers/memory/samsung/Makefile index 00587be66211..ea071be21c44 100644 --- a/drivers/memory/samsung/Makefile +++ b/drivers/memory/samsung/Makefile @@ -1,2 +1,3 @@ # SPDX-License-Identifier: GPL-2.0 +obj-$(CONFIG_EXYNOS5422_DMC) += exynos5422-dmc.o obj-$(CONFIG_EXYNOS_SROM) += exynos-srom.o diff --git a/drivers/memory/samsung/exynos5422-dmc.c b/drivers/memory/samsung/exynos5422-dmc.c new file mode 100644 index 000000000000..8c2ec29a7d57 --- /dev/null +++ b/drivers/memory/samsung/exynos5422-dmc.c @@ -0,0 +1,1257 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Copyright (c) 2019 Samsung Electronics Co., Ltd. + * Author: Lukasz Luba + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include "../jedec_ddr.h" +#include "../of_memory.h" + +#define EXYNOS5_DREXI_TIMINGAREF (0x0030) +#define EXYNOS5_DREXI_TIMINGROW0 (0x0034) +#define EXYNOS5_DREXI_TIMINGDATA0 (0x0038) +#define EXYNOS5_DREXI_TIMINGPOWER0 (0x003C) +#define EXYNOS5_DREXI_TIMINGROW1 (0x00E4) +#define EXYNOS5_DREXI_TIMINGDATA1 (0x00E8) +#define EXYNOS5_DREXI_TIMINGPOWER1 (0x00EC) +#define CDREX_PAUSE (0x2091c) +#define CDREX_LPDDR3PHY_CON3 (0x20a20) +#define CDREX_LPDDR3PHY_CLKM_SRC (0x20700) +#define EXYNOS5_TIMING_SET_SWI BIT(28) +#define USE_MX_MSPLL_TIMINGS (1) +#define USE_BPLL_TIMINGS (0) +#define EXYNOS5_AREF_NORMAL (0x2e) + +/** + * struct dmc_opp_table - Operating level desciption + * + * Covers frequency and voltage settings of the DMC operating mode. + */ +struct dmc_opp_table { + u32 freq_hz; + u32 volt_uv; +}; + +/** + * struct exynos5_dmc - main structure describing DMC device + * + * The main structure for the Dynamic Memory Controller which covers clocks, + * memory regions, HW information, parameters and current operating mode. + */ +struct exynos5_dmc { + struct device *dev; + struct devfreq *df; + struct devfreq_simple_ondemand_data gov_data; + void __iomem *base_drexi0; + void __iomem *base_drexi1; + struct regmap *clk_regmap; + struct mutex lock; + unsigned long curr_rate; + unsigned long curr_volt; + unsigned long bypass_rate; + struct dmc_opp_table *opp; + struct dmc_opp_table opp_bypass; + int opp_count; + u32 timings_arr_size; + u32 *timing_row; + u32 *timing_data; + u32 *timing_power; + const struct lpddr3_timings *timings; + const struct lpddr3_min_tck *min_tck; + u32 bypass_timing_row; + u32 bypass_timing_data; + u32 bypass_timing_power; + struct regulator *vdd_mif; + struct clk *fout_spll; + struct clk *fout_bpll; + struct clk *mout_spll; + struct clk *mout_bpll; + struct clk *mout_mclk_cdrex; + struct clk *mout_mx_mspll_ccore; + struct clk *mx_mspll_ccore_phy; + struct clk *mout_mx_mspll_ccore_phy; + struct devfreq_event_dev **counter; + int num_counters; +}; + +#define TIMING_FIELD(t_name, t_bit_beg, t_bit_end) \ + { .name = t_name, .bit_beg = t_bit_beg, .bit_end = t_bit_end } + +#define TIMING_VAL2REG(timing, t_val) \ +({ \ + u32 __val; \ + __val = (t_val) << (timing)->bit_beg; \ + __val; \ +}) + +struct timing_reg { + char *name; + int bit_beg; + int bit_end; + unsigned int val; +}; + +static const struct timing_reg timing_row[] = { + TIMING_FIELD("tRFC", 24, 31), + TIMING_FIELD("tRRD", 20, 23), + TIMING_FIELD("tRP", 16, 19), + TIMING_FIELD("tRCD", 12, 15), + TIMING_FIELD("tRC", 6, 11), + TIMING_FIELD("tRAS", 0, 5), +}; + +static const struct timing_reg timing_data[] = { + TIMING_FIELD("tWTR", 28, 31), + TIMING_FIELD("tWR", 24, 27), + TIMING_FIELD("tRTP", 20, 23), + TIMING_FIELD("tW2W-C2C", 14, 14), + TIMING_FIELD("tR2R-C2C", 12, 12), + TIMING_FIELD("WL", 8, 11), + TIMING_FIELD("tDQSCK", 4, 7), + TIMING_FIELD("RL", 0, 3), +}; + +static const struct timing_reg timing_power[] = { + TIMING_FIELD("tFAW", 26, 31), + TIMING_FIELD("tXSR", 16, 25), + TIMING_FIELD("tXP", 8, 15), + TIMING_FIELD("tCKE", 4, 7), + TIMING_FIELD("tMRD", 0, 3), +}; + +#define TIMING_COUNT (ARRAY_SIZE(timing_row) + ARRAY_SIZE(timing_data) + \ + ARRAY_SIZE(timing_power)) + +static int exynos5_counters_set_event(struct exynos5_dmc *dmc) +{ + int i, ret; + + for (i = 0; i < dmc->num_counters; i++) { + if (!dmc->counter[i]) + continue; + ret = devfreq_event_set_event(dmc->counter[i]); + if (ret < 0) + return ret; + } + return 0; +} + +static int exynos5_counters_enable_edev(struct exynos5_dmc *dmc) +{ + int i, ret; + + for (i = 0; i < dmc->num_counters; i++) { + if (!dmc->counter[i]) + continue; + ret = devfreq_event_enable_edev(dmc->counter[i]); + if (ret < 0) + return ret; + } + return 0; +} + +static int exynos5_counters_disable_edev(struct exynos5_dmc *dmc) +{ + int i, ret; + + for (i = 0; i < dmc->num_counters; i++) { + if (!dmc->counter[i]) + continue; + ret = devfreq_event_disable_edev(dmc->counter[i]); + if (ret < 0) + return ret; + } + return 0; +} + +/** + * find_target_freq_id() - Finds requested frequency in local DMC configuration + * @dmc: device for which the information is checked + * @target_rate: requested frequency in KHz + * + * Seeks in the local DMC driver structure for the requested frequency value + * and returns index or error value. + */ +static int find_target_freq_idx(struct exynos5_dmc *dmc, + unsigned long target_rate) +{ + int i; + + for (i = dmc->opp_count - 1; i >= 0; i--) + if (dmc->opp[i].freq_hz <= target_rate) + return i; + + return -EINVAL; +} + +/** + * exynos5_switch_timing_regs() - Changes bank register set for DRAM timings + * @dmc: device for which the new settings is going to be applied + * @set: boolean variable passing set value + * + * Changes the register set, which holds timing parameters. + * There is two register sets: 0 and 1. The register set 0 + * is used in normal operation when the clock is provided from main PLL. + * The bank register set 1 is used when the main PLL frequency is going to be + * changed and the clock is taken from alternative, stable source. + * This function switches between these banks according to the + * currently used clock source. + */ +static void exynos5_switch_timing_regs(struct exynos5_dmc *dmc, bool set) +{ + unsigned int reg; + int ret; + + ret = regmap_read(dmc->clk_regmap, CDREX_LPDDR3PHY_CON3, ®); + + if (set) + reg |= EXYNOS5_TIMING_SET_SWI; + else + reg &= ~EXYNOS5_TIMING_SET_SWI; + + regmap_write(dmc->clk_regmap, CDREX_LPDDR3PHY_CON3, reg); +} + +/** + * exynos5_init_freq_table() - Initialized PM OPP framework + * @dmc: DMC device for which the frequencies are used for OPP init + * @profile: devfreq device's profile + * + * Populate the devfreq device's OPP table based on current frequency, voltage. + */ +static int exynos5_init_freq_table(struct exynos5_dmc *dmc, + struct devfreq_dev_profile *profile) +{ + int i, ret; + int idx; + unsigned long freq; + + ret = dev_pm_opp_of_add_table(dmc->dev); + if (ret < 0) { + dev_err(dmc->dev, "Failed to get OPP table\n"); + return ret; + } + + dmc->opp_count = dev_pm_opp_get_opp_count(dmc->dev); + + dmc->opp = devm_kmalloc_array(dmc->dev, dmc->opp_count, + sizeof(struct dmc_opp_table), GFP_KERNEL); + if (!dmc->opp) + goto err_opp; + + idx = dmc->opp_count - 1; + for (i = 0, freq = ULONG_MAX; i < dmc->opp_count; i++, freq--) { + struct dev_pm_opp *opp; + + opp = dev_pm_opp_find_freq_floor(dmc->dev, &freq); + if (IS_ERR(opp)) + goto err_free_tables; + + dmc->opp[idx - i].freq_hz = freq; + dmc->opp[idx - i].volt_uv = dev_pm_opp_get_voltage(opp); + + dev_pm_opp_put(opp); + } + + return 0; + +err_free_tables: + kfree(dmc->opp); +err_opp: + dev_pm_opp_of_remove_table(dmc->dev); + + return -EINVAL; +} + +/** + * exynos5_set_bypass_dram_timings() - Low-level changes of the DRAM timings + * @dmc: device for which the new settings is going to be applied + * @param: DRAM parameters which passes timing data + * + * Low-level function for changing timings for DRAM memory clocking from + * 'bypass' clock source (fixed frequency @400MHz). + * It uses timing bank registers set 1. + */ +static void exynos5_set_bypass_dram_timings(struct exynos5_dmc *dmc) +{ + writel(EXYNOS5_AREF_NORMAL, + dmc->base_drexi0 + EXYNOS5_DREXI_TIMINGAREF); + + writel(dmc->bypass_timing_row, + dmc->base_drexi0 + EXYNOS5_DREXI_TIMINGROW1); + writel(dmc->bypass_timing_row, + dmc->base_drexi1 + EXYNOS5_DREXI_TIMINGROW1); + writel(dmc->bypass_timing_data, + dmc->base_drexi0 + EXYNOS5_DREXI_TIMINGDATA1); + writel(dmc->bypass_timing_data, + dmc->base_drexi1 + EXYNOS5_DREXI_TIMINGDATA1); + writel(dmc->bypass_timing_power, + dmc->base_drexi0 + EXYNOS5_DREXI_TIMINGPOWER1); + writel(dmc->bypass_timing_power, + dmc->base_drexi1 + EXYNOS5_DREXI_TIMINGPOWER1); +} + +/** + * exynos5_dram_change_timings() - Low-level changes of the DRAM final timings + * @dmc: device for which the new settings is going to be applied + * @target_rate: target frequency of the DMC + * + * Low-level function for changing timings for DRAM memory operating from main + * clock source (BPLL), which can have different frequencies. Thus, each + * frequency must have corresponding timings register values in order to keep + * the needed delays. + * It uses timing bank registers set 0. + */ +static int exynos5_dram_change_timings(struct exynos5_dmc *dmc, + unsigned long target_rate) +{ + int idx; + + for (idx = dmc->opp_count - 1; idx >= 0; idx--) + if (dmc->opp[idx].freq_hz <= target_rate) + break; + + if (idx < 0) + return -EINVAL; + + writel(EXYNOS5_AREF_NORMAL, + dmc->base_drexi0 + EXYNOS5_DREXI_TIMINGAREF); + + writel(dmc->timing_row[idx], + dmc->base_drexi0 + EXYNOS5_DREXI_TIMINGROW0); + writel(dmc->timing_row[idx], + dmc->base_drexi1 + EXYNOS5_DREXI_TIMINGROW0); + writel(dmc->timing_data[idx], + dmc->base_drexi0 + EXYNOS5_DREXI_TIMINGDATA0); + writel(dmc->timing_data[idx], + dmc->base_drexi1 + EXYNOS5_DREXI_TIMINGDATA0); + writel(dmc->timing_power[idx], + dmc->base_drexi0 + EXYNOS5_DREXI_TIMINGPOWER0); + writel(dmc->timing_power[idx], + dmc->base_drexi1 + EXYNOS5_DREXI_TIMINGPOWER0); + + return 0; +} + +/** + * exynos5_dmc_align_target_voltage() - Sets the final voltage for the DMC + * @dmc: device for which it is going to be set + * @target_volt: new voltage which is chosen to be final + * + * Function tries to align voltage to the safe level for 'normal' mode. + * It checks the need of higher voltage and changes the value. The target + * voltage might be lower that currently set and still the system will be + * stable. + */ +static int exynos5_dmc_align_target_voltage(struct exynos5_dmc *dmc, + unsigned long target_volt) +{ + int ret = 0; + + if (dmc->curr_volt <= target_volt) + return 0; + + ret = regulator_set_voltage(dmc->vdd_mif, target_volt, + target_volt); + if (!ret) + dmc->curr_volt = target_volt; + + return ret; +} + +/** + * exynos5_dmc_align_bypass_voltage() - Sets the voltage for the DMC + * @dmc: device for which it is going to be set + * @target_volt: new voltage which is chosen to be final + * + * Function tries to align voltage to the safe level for the 'bypass' mode. + * It checks the need of higher voltage and changes the value. + * The target voltage must not be less than currently needed, because + * for current frequency the device might become unstable. + */ +static int exynos5_dmc_align_bypass_voltage(struct exynos5_dmc *dmc, + unsigned long target_volt) +{ + int ret = 0; + unsigned long bypass_volt = dmc->opp_bypass.volt_uv; + + target_volt = max(bypass_volt, target_volt); + + if (dmc->curr_volt >= target_volt) + return 0; + + ret = regulator_set_voltage(dmc->vdd_mif, target_volt, + target_volt); + if (!ret) + dmc->curr_volt = target_volt; + + return ret; +} + +/** + * exynos5_dmc_align_bypass_dram_timings() - Chooses and sets DRAM timings + * @dmc: device for which it is going to be set + * @target_rate: new frequency which is chosen to be final + * + * Function changes the DRAM timings for the temporary 'bypass' mode. + */ +static int exynos5_dmc_align_bypass_dram_timings(struct exynos5_dmc *dmc, + unsigned long target_rate) +{ + int idx = find_target_freq_idx(dmc, target_rate); + + if (idx < 0) + return -EINVAL; + + exynos5_set_bypass_dram_timings(dmc); + + return 0; +} + +/** + * exynos5_dmc_switch_to_bypass_configuration() - Switching to temporary clock + * @dmc: DMC device for which the switching is going to happen + * @target_rate: new frequency which is going to be set as a final + * @target_volt: new voltage which is going to be set as a final + * + * Function configures DMC and clocks for operating in temporary 'bypass' mode. + * This mode is used only temporary but if required, changes voltage and timings + * for DRAM chips. It switches the main clock to stable clock source for the + * period of the main PLL reconfiguration. + */ +static int +exynos5_dmc_switch_to_bypass_configuration(struct exynos5_dmc *dmc, + unsigned long target_rate, + unsigned long target_volt) +{ + int ret; + + /* + * Having higher voltage for a particular frequency does not harm + * the chip. Use it for the temporary frequency change when one + * voltage manipulation might be avoided. + */ + ret = exynos5_dmc_align_bypass_voltage(dmc, target_volt); + if (ret) + return ret; + + /* + * Longer delays for DRAM does not cause crash, the opposite does. + */ + ret = exynos5_dmc_align_bypass_dram_timings(dmc, target_rate); + if (ret) + return ret; + + /* + * Delays are long enough, so use them for the new coming clock. + */ + exynos5_switch_timing_regs(dmc, USE_MX_MSPLL_TIMINGS); + + return ret; +} + +/** + * exynos5_dmc_change_freq_and_volt() - Changes voltage and frequency of the DMC + * using safe procedure + * @dmc: device for which the frequency is going to be changed + * @target_rate: requested new frequency + * @target_volt: requested voltage which corresponds to the new frequency + * + * The DMC frequency change procedure requires a few steps. + * The main requirement is to change the clock source in the clk mux + * for the time of main clock PLL locking. The assumption is that the + * alternative clock source set as parent is stable. + * The second parent's clock frequency is fixed to 400MHz, it is named 'bypass' + * clock. This requires alignment in DRAM timing parameters for the new + * T-period. There is two bank sets for keeping DRAM + * timings: set 0 and set 1. The set 0 is used when main clock source is + * chosen. The 2nd set of regs is used for 'bypass' clock. Switching between + * the two bank sets is part of the process. + * The voltage must also be aligned to the minimum required level. There is + * this intermediate step with switching to 'bypass' parent clock source. + * if the old voltage is lower, it requires an increase of the voltage level. + * The complexity of the voltage manipulation is hidden in low level function. + * In this function there is last alignment of the voltage level at the end. + */ +static int +exynos5_dmc_change_freq_and_volt(struct exynos5_dmc *dmc, + unsigned long target_rate, + unsigned long target_volt) +{ + int ret; + + ret = exynos5_dmc_switch_to_bypass_configuration(dmc, target_rate, + target_volt); + if (ret) + return ret; + + /* + * Voltage is set at least to a level needed for this frequency, + * so switching clock source is safe now. + */ + clk_prepare_enable(dmc->fout_spll); + clk_prepare_enable(dmc->mout_spll); + clk_prepare_enable(dmc->mout_mx_mspll_ccore); + + ret = clk_set_parent(dmc->mout_mclk_cdrex, dmc->mout_mx_mspll_ccore); + if (ret) + goto disable_clocks; + + /* + * We are safe to increase the timings for current bypass frequency. + * Thanks to this the settings will be ready for the upcoming clock + * source change. + */ + exynos5_dram_change_timings(dmc, target_rate); + + clk_set_rate(dmc->fout_bpll, target_rate); + + exynos5_switch_timing_regs(dmc, USE_BPLL_TIMINGS); + + ret = clk_set_parent(dmc->mout_mclk_cdrex, dmc->mout_bpll); + if (ret) + goto disable_clocks; + + /* + * Make sure if the voltage is not from 'bypass' settings and align to + * the right level for power efficiency. + */ + ret = exynos5_dmc_align_target_voltage(dmc, target_volt); + +disable_clocks: + clk_disable_unprepare(dmc->mout_mx_mspll_ccore); + clk_disable_unprepare(dmc->mout_spll); + clk_disable_unprepare(dmc->fout_spll); + + return ret; +} + +/** + * exynos5_dmc_get_volt_freq() - Gets the frequency and voltage from the OPP + * table. + * @dmc: device for which the frequency is going to be changed + * @freq: requested frequency in KHz + * @target_rate: returned frequency which is the same or lower than + * requested + * @target_volt: returned voltage which corresponds to the returned + * frequency + * + * Function gets requested frequency and checks OPP framework for needed + * frequency and voltage. It populates the values 'target_rate' and + * 'target_volt' or returns error value when OPP framework fails. + */ +static int exynos5_dmc_get_volt_freq(struct exynos5_dmc *dmc, + unsigned long *freq, + unsigned long *target_rate, + unsigned long *target_volt, u32 flags) +{ + struct dev_pm_opp *opp; + + opp = devfreq_recommended_opp(dmc->dev, freq, flags); + if (IS_ERR(opp)) + return PTR_ERR(opp); + + *target_rate = dev_pm_opp_get_freq(opp); + *target_volt = dev_pm_opp_get_voltage(opp); + dev_pm_opp_put(opp); + + return 0; +} + +/** + * exynos5_dmc_target() - Function responsible for changing frequency of DMC + * @dev: device for which the frequency is going to be changed + * @freq: requested frequency in KHz + * @flags: flags provided for this frequency change request + * + * An entry function provided to the devfreq framework which provides frequency + * change of the DMC. The function gets the possible rate from OPP table based + * on requested frequency. It calls the next function responsible for the + * frequency and voltage change. In case of failure, does not set 'curr_rate' + * and returns error value to the framework. + */ +static int exynos5_dmc_target(struct device *dev, unsigned long *freq, + u32 flags) +{ + struct exynos5_dmc *dmc = dev_get_drvdata(dev); + unsigned long target_rate = 0; + unsigned long target_volt = 0; + int ret; + + ret = exynos5_dmc_get_volt_freq(dmc, freq, &target_rate, &target_volt, + flags); + + if (ret) + return ret; + + if (target_rate == dmc->curr_rate) + return 0; + + mutex_lock(&dmc->lock); + + ret = exynos5_dmc_change_freq_and_volt(dmc, target_rate, target_volt); + + if (ret) { + mutex_unlock(&dmc->lock); + return ret; + } + + dmc->curr_rate = target_rate; + + mutex_unlock(&dmc->lock); + return 0; +} + +/** + * exynos5_counters_get() - Gets the performance counters values. + * @dmc: device for which the counters are going to be checked + * @load_count: variable which is populated with counter value + * @total_count: variable which is used as 'wall clock' reference + * + * Function which provides performance counters values. It sums up counters for + * two DMC channels. The 'total_count' is used as a reference and max value. + * The ratio 'load_count/total_count' shows the busy percentage [0%, 100%]. + */ +static int exynos5_counters_get(struct exynos5_dmc *dmc, + unsigned long *load_count, + unsigned long *total_count) +{ + unsigned long total = 0; + struct devfreq_event_data event; + int ret, i; + + *load_count = 0; + + /* Take into account only read+write counters, but stop all */ + for (i = 0; i < dmc->num_counters; i++) { + if (!dmc->counter[i]) + continue; + + ret = devfreq_event_get_event(dmc->counter[i], &event); + if (ret < 0) + return ret; + + *load_count += event.load_count; + + if (total < event.total_count) + total = event.total_count; + } + + *total_count = total; + + return 0; +} + +/** + * exynos5_dmc_get_status() - Read current DMC performance statistics. + * @dev: device for which the statistics are requested + * @stat: structure which has statistic fields + * + * Function reads the DMC performance counters and calculates 'busy_time' + * and 'total_time'. To protect from overflow, the values are shifted right + * by 10. After read out the counters are setup to count again. + */ +static int exynos5_dmc_get_status(struct device *dev, + struct devfreq_dev_status *stat) +{ + struct exynos5_dmc *dmc = dev_get_drvdata(dev); + unsigned long load, total; + int ret; + + ret = exynos5_counters_get(dmc, &load, &total); + if (ret < 0) + return -EINVAL; + + /* To protect from overflow in calculation ratios, divide by 1024 */ + stat->busy_time = load >> 10; + stat->total_time = total >> 10; + + ret = exynos5_counters_set_event(dmc); + if (ret < 0) { + dev_err(dev, "could not set event counter\n"); + return ret; + } + + return 0; +} + +/** + * exynos5_dmc_get_cur_freq() - Function returns current DMC frequency + * @dev: device for which the framework checks operating frequency + * @freq: returned frequency value + * + * It returns the currently used frequency of the DMC. The real operating + * frequency might be lower when the clock source value could not be divided + * to the requested value. + */ +static int exynos5_dmc_get_cur_freq(struct device *dev, unsigned long *freq) +{ + struct exynos5_dmc *dmc = dev_get_drvdata(dev); + + mutex_lock(&dmc->lock); + *freq = dmc->curr_rate; + mutex_unlock(&dmc->lock); + + return 0; +} + +/** + * exynos5_dmc_df_profile - Devfreq governor's profile structure + * + * It provides to the devfreq framework needed functions and polling period. + */ +static struct devfreq_dev_profile exynos5_dmc_df_profile = { + .polling_ms = 500, + .target = exynos5_dmc_target, + .get_dev_status = exynos5_dmc_get_status, + .get_cur_freq = exynos5_dmc_get_cur_freq, +}; + +/** + * exynos5_dmc_align_initial_frequency() - Align initial frequency value + * @dmc: device for which the frequency is going to be set + * @bootloader_init_freq: initial frequency set by the bootloader in KHz + * + * The initial bootloader frequency, which is present during boot, might be + * different that supported frequency values in the driver. It is possible + * due to different PLL settings or used PLL as a source. + * This function provides the 'initial_freq' for the devfreq framework + * statistics engine which supports only registered values. Thus, some alignment + * must be made. + */ +unsigned long +exynos5_dmc_align_init_freq(struct exynos5_dmc *dmc, + unsigned long bootloader_init_freq) +{ + unsigned long aligned_freq; + int idx; + + idx = find_target_freq_idx(dmc, bootloader_init_freq); + if (idx >= 0) + aligned_freq = dmc->opp[idx].freq_hz; + else + aligned_freq = dmc->opp[dmc->opp_count - 1].freq_hz; + + return aligned_freq; +} + +/** + * create_timings_aligned() - Create register values and align with standard + * @dmc: device for which the frequency is going to be set + * @idx: speed bin in the OPP table + * @clk_period_ps: the period of the clock, known as tCK + * + * The function calculates timings and creates a register value ready for + * a frequency transition. The register contains a few timings. They are + * shifted by a known offset. The timing value is calculated based on memory + * specyfication: minimal time required and minimal cycles required. + */ +static int create_timings_aligned(struct exynos5_dmc *dmc, u32 *reg_timing_row, + u32 *reg_timing_data, u32 *reg_timing_power, + u32 clk_period_ps) +{ + u32 val; + const struct timing_reg *reg; + + if (clk_period_ps == 0) + return -EINVAL; + + *reg_timing_row = 0; + *reg_timing_data = 0; + *reg_timing_power = 0; + + val = dmc->timings->tRFC / clk_period_ps; + val += dmc->timings->tRFC % clk_period_ps ? 1 : 0; + val = max(val, dmc->min_tck->tRFC); + reg = &timing_row[0]; + *reg_timing_row |= TIMING_VAL2REG(reg, val); + + val = dmc->timings->tRRD / clk_period_ps; + val += dmc->timings->tRRD % clk_period_ps ? 1 : 0; + val = max(val, dmc->min_tck->tRRD); + reg = &timing_row[1]; + *reg_timing_row |= TIMING_VAL2REG(reg, val); + + val = dmc->timings->tRPab / clk_period_ps; + val += dmc->timings->tRPab % clk_period_ps ? 1 : 0; + val = max(val, dmc->min_tck->tRPab); + reg = &timing_row[2]; + *reg_timing_row |= TIMING_VAL2REG(reg, val); + + val = dmc->timings->tRCD / clk_period_ps; + val += dmc->timings->tRCD % clk_period_ps ? 1 : 0; + val = max(val, dmc->min_tck->tRCD); + reg = &timing_row[3]; + *reg_timing_row |= TIMING_VAL2REG(reg, val); + + val = dmc->timings->tRC / clk_period_ps; + val += dmc->timings->tRC % clk_period_ps ? 1 : 0; + val = max(val, dmc->min_tck->tRC); + reg = &timing_row[4]; + *reg_timing_row |= TIMING_VAL2REG(reg, val); + + val = dmc->timings->tRAS / clk_period_ps; + val += dmc->timings->tRAS % clk_period_ps ? 1 : 0; + val = max(val, dmc->min_tck->tRAS); + reg = &timing_row[5]; + *reg_timing_row |= TIMING_VAL2REG(reg, val); + + /* data related timings */ + val = dmc->timings->tWTR / clk_period_ps; + val += dmc->timings->tWTR % clk_period_ps ? 1 : 0; + val = max(val, dmc->min_tck->tWTR); + reg = &timing_data[0]; + *reg_timing_data |= TIMING_VAL2REG(reg, val); + + val = dmc->timings->tWR / clk_period_ps; + val += dmc->timings->tWR % clk_period_ps ? 1 : 0; + val = max(val, dmc->min_tck->tWR); + reg = &timing_data[1]; + *reg_timing_data |= TIMING_VAL2REG(reg, val); + + val = dmc->timings->tRTP / clk_period_ps; + val += dmc->timings->tRTP % clk_period_ps ? 1 : 0; + val = max(val, dmc->min_tck->tRTP); + reg = &timing_data[2]; + *reg_timing_data |= TIMING_VAL2REG(reg, val); + + val = dmc->timings->tW2W_C2C / clk_period_ps; + val += dmc->timings->tW2W_C2C % clk_period_ps ? 1 : 0; + val = max(val, dmc->min_tck->tW2W_C2C); + reg = &timing_data[3]; + *reg_timing_data |= TIMING_VAL2REG(reg, val); + + val = dmc->timings->tR2R_C2C / clk_period_ps; + val += dmc->timings->tR2R_C2C % clk_period_ps ? 1 : 0; + val = max(val, dmc->min_tck->tR2R_C2C); + reg = &timing_data[4]; + *reg_timing_data |= TIMING_VAL2REG(reg, val); + + val = dmc->timings->tWL / clk_period_ps; + val += dmc->timings->tWL % clk_period_ps ? 1 : 0; + val = max(val, dmc->min_tck->tWL); + reg = &timing_data[5]; + *reg_timing_data |= TIMING_VAL2REG(reg, val); + + val = dmc->timings->tDQSCK / clk_period_ps; + val += dmc->timings->tDQSCK % clk_period_ps ? 1 : 0; + val = max(val, dmc->min_tck->tDQSCK); + reg = &timing_data[6]; + *reg_timing_data |= TIMING_VAL2REG(reg, val); + + val = dmc->timings->tRL / clk_period_ps; + val += dmc->timings->tRL % clk_period_ps ? 1 : 0; + val = max(val, dmc->min_tck->tRL); + reg = &timing_data[7]; + *reg_timing_data |= TIMING_VAL2REG(reg, val); + + /* power related timings */ + val = dmc->timings->tFAW / clk_period_ps; + val += dmc->timings->tFAW % clk_period_ps ? 1 : 0; + val = max(val, dmc->min_tck->tXP); + reg = &timing_power[0]; + *reg_timing_power |= TIMING_VAL2REG(reg, val); + + val = dmc->timings->tXSR / clk_period_ps; + val += dmc->timings->tXSR % clk_period_ps ? 1 : 0; + val = max(val, dmc->min_tck->tXSR); + reg = &timing_power[1]; + *reg_timing_power |= TIMING_VAL2REG(reg, val); + + val = dmc->timings->tXP / clk_period_ps; + val += dmc->timings->tXP % clk_period_ps ? 1 : 0; + val = max(val, dmc->min_tck->tXP); + reg = &timing_power[2]; + *reg_timing_power |= TIMING_VAL2REG(reg, val); + + val = dmc->timings->tCKE / clk_period_ps; + val += dmc->timings->tCKE % clk_period_ps ? 1 : 0; + val = max(val, dmc->min_tck->tCKE); + reg = &timing_power[3]; + *reg_timing_power |= TIMING_VAL2REG(reg, val); + + val = dmc->timings->tMRD / clk_period_ps; + val += dmc->timings->tMRD % clk_period_ps ? 1 : 0; + val = max(val, dmc->min_tck->tMRD); + reg = &timing_power[4]; + *reg_timing_power |= TIMING_VAL2REG(reg, val); + + return 0; +} + +/** + * of_get_dram_timings() - helper function for parsing DT settings for DRAM + * @dmc: device for which the frequency is going to be set + * + * The function parses DT entries with DRAM information. + */ +static int of_get_dram_timings(struct exynos5_dmc *dmc) +{ + int ret = 0; + int idx; + struct device_node *np_ddr; + u32 freq_mhz, clk_period_ps; + + np_ddr = of_parse_phandle(dmc->dev->of_node, "device-handle", 0); + if (!np_ddr) { + dev_warn(dmc->dev, "could not find 'device-handle' in DT\n"); + return -EINVAL; + } + + dmc->timing_row = devm_kmalloc_array(dmc->dev, TIMING_COUNT, + sizeof(u32), GFP_KERNEL); + if (!dmc->timing_row) + return -ENOMEM; + + dmc->timing_data = devm_kmalloc_array(dmc->dev, TIMING_COUNT, + sizeof(u32), GFP_KERNEL); + if (!dmc->timing_data) + return -ENOMEM; + + dmc->timing_power = devm_kmalloc_array(dmc->dev, TIMING_COUNT, + sizeof(u32), GFP_KERNEL); + if (!dmc->timing_power) + return -ENOMEM; + + dmc->timings = of_lpddr3_get_ddr_timings(np_ddr, dmc->dev, + DDR_TYPE_LPDDR3, + &dmc->timings_arr_size); + if (!dmc->timings) { + of_node_put(np_ddr); + dev_warn(dmc->dev, "could not get timings from DT\n"); + return -EINVAL; + } + + dmc->min_tck = of_lpddr3_get_min_tck(np_ddr, dmc->dev); + if (!dmc->min_tck) { + of_node_put(np_ddr); + dev_warn(dmc->dev, "could not get tck from DT\n"); + return -EINVAL; + } + + /* Sorted array of OPPs with frequency ascending */ + for (idx = 0; idx < dmc->opp_count; idx++) { + freq_mhz = dmc->opp[idx].freq_hz / 1000000; + clk_period_ps = 1000000 / freq_mhz; + + ret = create_timings_aligned(dmc, &dmc->timing_row[idx], + &dmc->timing_data[idx], + &dmc->timing_power[idx], + clk_period_ps); + } + + of_node_put(np_ddr); + + /* Take the highest frequency's timings as 'bypass' */ + dmc->bypass_timing_row = dmc->timing_row[idx - 1]; + dmc->bypass_timing_data = dmc->timing_data[idx - 1]; + dmc->bypass_timing_power = dmc->timing_power[idx - 1]; + + return ret; +} + +/** + * exynos5_dmc_init_clks() - Initialize clocks needed for DMC operation. + * @dmc: DMC structure containing needed fields + * + * Get the needed clocks defined in DT device, enable and set the right parents. + * Read current frequency and initialize the initial rate for governor. + */ +static int exynos5_dmc_init_clks(struct exynos5_dmc *dmc) +{ + int ret; + unsigned long target_volt = 0; + unsigned long target_rate = 0; + unsigned int tmp; + + dmc->fout_spll = devm_clk_get(dmc->dev, "fout_spll"); + if (IS_ERR(dmc->fout_spll)) + return PTR_ERR(dmc->fout_spll); + + dmc->fout_bpll = devm_clk_get(dmc->dev, "fout_bpll"); + if (IS_ERR(dmc->fout_bpll)) + return PTR_ERR(dmc->fout_bpll); + + dmc->mout_mclk_cdrex = devm_clk_get(dmc->dev, "mout_mclk_cdrex"); + if (IS_ERR(dmc->mout_mclk_cdrex)) + return PTR_ERR(dmc->mout_mclk_cdrex); + + dmc->mout_bpll = devm_clk_get(dmc->dev, "mout_bpll"); + if (IS_ERR(dmc->mout_bpll)) + return PTR_ERR(dmc->mout_bpll); + + dmc->mout_mx_mspll_ccore = devm_clk_get(dmc->dev, + "mout_mx_mspll_ccore"); + if (IS_ERR(dmc->mout_mx_mspll_ccore)) + return PTR_ERR(dmc->mout_mx_mspll_ccore); + + dmc->mout_spll = devm_clk_get(dmc->dev, "ff_dout_spll2"); + if (IS_ERR(dmc->mout_spll)) { + dmc->mout_spll = devm_clk_get(dmc->dev, "mout_sclk_spll"); + if (IS_ERR(dmc->mout_spll)) + return PTR_ERR(dmc->mout_spll); + } + + /* + * Convert frequency to KHz values and set it for the governor. + */ + dmc->curr_rate = clk_get_rate(dmc->mout_mclk_cdrex); + dmc->curr_rate = exynos5_dmc_align_init_freq(dmc, dmc->curr_rate); + exynos5_dmc_df_profile.initial_freq = dmc->curr_rate; + + ret = exynos5_dmc_get_volt_freq(dmc, &dmc->curr_rate, &target_rate, + &target_volt, 0); + if (ret) + return ret; + + dmc->curr_volt = target_volt; + + clk_set_parent(dmc->mout_mx_mspll_ccore, dmc->mout_spll); + + dmc->bypass_rate = clk_get_rate(dmc->mout_mx_mspll_ccore); + + clk_prepare_enable(dmc->fout_bpll); + clk_prepare_enable(dmc->mout_bpll); + + /* + * Some bootloaders do not set clock routes correctly. + * Stop one path in clocks to PHY. + */ + regmap_read(dmc->clk_regmap, CDREX_LPDDR3PHY_CLKM_SRC, &tmp); + tmp &= ~(BIT(1) | BIT(0)); + regmap_write(dmc->clk_regmap, CDREX_LPDDR3PHY_CLKM_SRC, tmp); + + return 0; +} + +/** + * exynos5_performance_counters_init() - Initializes performance DMC's counters + * @dmc: DMC for which it does the setup + * + * Initialization of performance counters in DMC for estimating usage. + * The counter's values are used for calculation of a memory bandwidth and based + * on that the governor changes the frequency. + * The counters are not used when the governor is GOVERNOR_USERSPACE. + */ +static int exynos5_performance_counters_init(struct exynos5_dmc *dmc) +{ + int counters_size; + int ret, i; + + dmc->num_counters = devfreq_event_get_edev_count(dmc->dev); + if (dmc->num_counters < 0) { + dev_err(dmc->dev, "could not get devfreq-event counters\n"); + return dmc->num_counters; + } + + counters_size = sizeof(struct devfreq_event_dev) * dmc->num_counters; + dmc->counter = devm_kzalloc(dmc->dev, counters_size, GFP_KERNEL); + if (!dmc->counter) + return -ENOMEM; + + for (i = 0; i < dmc->num_counters; i++) { + dmc->counter[i] = + devfreq_event_get_edev_by_phandle(dmc->dev, i); + if (IS_ERR_OR_NULL(dmc->counter[i])) + return -EPROBE_DEFER; + } + + ret = exynos5_counters_enable_edev(dmc); + if (ret < 0) { + dev_err(dmc->dev, "could not enable event counter\n"); + return ret; + } + + ret = exynos5_counters_set_event(dmc); + if (ret < 0) { + exynos5_counters_disable_edev(dmc); + dev_err(dmc->dev, "counld not set event counter\n"); + return ret; + } + + return 0; +} + +/** + * exynos5_dmc_set_pause_on_switching() - Controls a pause feature in DMC + * @dmc: device which is used for changing this feature + * @set: a boolean state passing enable/disable request + * + * There is a need of pausing DREX DMC when divider or MUX in clock tree + * changes its configuration. In such situation access to the memory is blocked + * in DMC automatically. This feature is used when clock frequency change + * request appears and touches clock tree. + */ +static inline int exynos5_dmc_set_pause_on_switching(struct exynos5_dmc *dmc) +{ + unsigned int val; + int ret; + + ret = regmap_read(dmc->clk_regmap, CDREX_PAUSE, &val); + if (ret) + return ret; + + val |= 1UL; + regmap_write(dmc->clk_regmap, CDREX_PAUSE, val); + + return 0; +} + +/** + * exynos5_dmc_probe() - Probe function for the DMC driver + * @pdev: platform device for which the driver is going to be initialized + * + * Initialize basic components: clocks, regulators, performance counters, etc. + * Read out product version and based on the information setup + * internal structures for the controller (frequency and voltage) and for DRAM + * memory parameters: timings for each operating frequency. + * Register new devfreq device for controlling DVFS of the DMC. + */ +static int exynos5_dmc_probe(struct platform_device *pdev) +{ + int ret = 0; + struct device *dev = &pdev->dev; + struct device_node *np = dev->of_node; + struct exynos5_dmc *dmc; + struct resource *res; + + dmc = devm_kzalloc(dev, sizeof(*dmc), GFP_KERNEL); + if (!dmc) + return -ENOMEM; + + mutex_init(&dmc->lock); + + dmc->dev = dev; + platform_set_drvdata(pdev, dmc); + + res = platform_get_resource(pdev, IORESOURCE_MEM, 0); + dmc->base_drexi0 = devm_ioremap_resource(dev, res); + if (IS_ERR(dmc->base_drexi0)) + return PTR_ERR(dmc->base_drexi0); + + res = platform_get_resource(pdev, IORESOURCE_MEM, 1); + dmc->base_drexi1 = devm_ioremap_resource(dev, res); + if (IS_ERR(dmc->base_drexi1)) + return PTR_ERR(dmc->base_drexi1); + + dmc->clk_regmap = syscon_regmap_lookup_by_phandle(np, + "samsung,syscon-clk"); + if (IS_ERR(dmc->clk_regmap)) + return PTR_ERR(dmc->clk_regmap); + + ret = exynos5_init_freq_table(dmc, &exynos5_dmc_df_profile); + if (ret) { + dev_warn(dev, "couldn't initialize frequency settings\n"); + return ret; + } + + dmc->vdd_mif = devm_regulator_get(dev, "vdd"); + if (IS_ERR(dmc->vdd_mif)) { + ret = PTR_ERR(dmc->vdd_mif); + return ret; + } + + ret = exynos5_dmc_init_clks(dmc); + if (ret) + return ret; + + ret = of_get_dram_timings(dmc); + if (ret) { + dev_warn(dev, "couldn't initialize timings settings\n"); + goto remove_clocks; + } + + ret = exynos5_performance_counters_init(dmc); + if (ret) { + dev_warn(dev, "couldn't probe performance counters\n"); + goto remove_clocks; + } + + ret = exynos5_dmc_set_pause_on_switching(dmc); + if (ret) { + dev_warn(dev, "couldn't get access to PAUSE register\n"); + goto err_devfreq_add; + } + + /* + * Setup default thresholds for the devfreq governor. + * The values are chosen based on experiments. + */ + dmc->gov_data.upthreshold = 30; + dmc->gov_data.downdifferential = 5; + + dmc->df = devm_devfreq_add_device(dev, &exynos5_dmc_df_profile, + DEVFREQ_GOV_SIMPLE_ONDEMAND, + &dmc->gov_data); + + if (IS_ERR(dmc->df)) { + ret = PTR_ERR(dmc->df); + goto err_devfreq_add; + } + + dev_info(dev, "DMC initialized\n"); + + return 0; + +err_devfreq_add: + exynos5_counters_disable_edev(dmc); +remove_clocks: + clk_disable_unprepare(dmc->mout_bpll); + clk_disable_unprepare(dmc->fout_bpll); + + return ret; +} + +/** + * exynos5_dmc_remove() - Remove function for the platform device + * @pdev: platform device which is going to be removed + * + * The function relies on 'devm' framework function which automatically + * clean the device's resources. It just calls explicitly disable function for + * the performance counters. + */ +static int exynos5_dmc_remove(struct platform_device *pdev) +{ + struct exynos5_dmc *dmc = dev_get_drvdata(&pdev->dev); + + exynos5_counters_disable_edev(dmc); + + clk_disable_unprepare(dmc->mout_bpll); + clk_disable_unprepare(dmc->fout_bpll); + + dev_pm_opp_remove_table(dmc->dev); + + return 0; +} + +static const struct of_device_id exynos5_dmc_of_match[] = { + { .compatible = "samsung,exynos5422-dmc", }, + { }, +}; +MODULE_DEVICE_TABLE(of, exynos5_dmc_of_match); + +static struct platform_driver exynos5_dmc_platdrv = { + .probe = exynos5_dmc_probe, + .remove = exynos5_dmc_remove, + .driver = { + .name = "exynos5-dmc", + .of_match_table = exynos5_dmc_of_match, + }, +}; +module_platform_driver(exynos5_dmc_platdrv); +MODULE_DESCRIPTION("Driver for Exynos5422 Dynamic Memory Controller dynamic frequency and voltage change"); +MODULE_LICENSE("GPL v2"); +MODULE_AUTHOR("Lukasz Luba"); From patchwork Wed Aug 21 10:43:01 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Lukasz Luba X-Patchwork-Id: 11106303 Return-Path: Received: from mail.kernel.org (pdx-korg-mail-1.web.codeaurora.org [172.30.200.123]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id 3382914DB for ; Wed, 21 Aug 2019 10:43:37 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.kernel.org (Postfix) with ESMTP id 1459322D6D for ; Wed, 21 Aug 2019 10:43:37 +0000 (UTC) Authentication-Results: mail.kernel.org; dkim=pass (1024-bit key) header.d=samsung.com header.i=@samsung.com header.b="V76VPvy1" Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1728324AbfHUKng (ORCPT ); Wed, 21 Aug 2019 06:43:36 -0400 Received: from mailout1.w1.samsung.com ([210.118.77.11]:53360 "EHLO mailout1.w1.samsung.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1728332AbfHUKn1 (ORCPT ); Wed, 21 Aug 2019 06:43:27 -0400 Received: from eucas1p1.samsung.com (unknown [182.198.249.206]) by mailout1.w1.samsung.com (KnoxPortal) with ESMTP id 20190821104325euoutp01417f62635845b98de6609e168887cce2~86iLdJz6_0803008030euoutp01K for ; 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Wed, 21 Aug 2019 10:43:23 +0000 (GMT) Received: from eusmgms2.samsung.com (unknown [182.198.249.180]) by eusmtrp2.samsung.com (KnoxPortal) with ESMTP id 20190821104323eusmtrp27be02219a1d95f1d60364d7419e8d8e0~86iJeJtSy2827528275eusmtrp2B; Wed, 21 Aug 2019 10:43:23 +0000 (GMT) X-AuditID: cbfec7f5-4ddff70000001116-67-5d5d204cf493 Received: from eusmtip2.samsung.com ( [203.254.199.222]) by eusmgms2.samsung.com (EUCPMTA) with SMTP id 3E.38.04117.B402D5D5; Wed, 21 Aug 2019 11:43:23 +0100 (BST) Received: from AMDC3778.DIGITAL.local (unknown [106.120.51.20]) by eusmtip2.samsung.com (KnoxPortal) with ESMTPA id 20190821104322eusmtip2b6225e2653a8b87e9565a8e795f368ac~86iIYaLVV1273812738eusmtip2h; Wed, 21 Aug 2019 10:43:22 +0000 (GMT) From: Lukasz Luba To: devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-pm@vger.kernel.org, linux-samsung-soc@vger.kernel.org, linux-clk@vger.kernel.org Cc: mturquette@baylibre.com, sboyd@kernel.org, b.zolnierkie@samsung.com, krzk@kernel.org, kgene@kernel.org, mark.rutland@arm.com, robh+dt@kernel.org, cw00.choi@samsung.com, kyungmin.park@samsung.com, m.szyprowski@samsung.com, s.nawrocki@samsung.com, myungjoo.ham@samsung.com, keescook@chromium.org, tony@atomide.com, jroedel@suse.de, treding@nvidia.com, digetx@gmail.com, gregkh@linuxfoundation.org, willy.mh.wolff.ml@gmail.com, Lukasz Luba Subject: [PATCH v13 6/8] ARM: dts: exynos: add syscon to clock compatible Date: Wed, 21 Aug 2019 12:43:01 +0200 Message-Id: <20190821104303.32079-7-l.luba@partner.samsung.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20190821104303.32079-1-l.luba@partner.samsung.com> X-Brightmail-Tracker: H4sIAAAAAAAAA0VSa1BMURx39t679+5Om2trONIU2zBK2qjGMQyZ0cz1+GCY8SEWS9cWu6v2 9kLMxpREj/GoJiWN52yRklTouYkesoO2URkqJKlJD5JZut0a337n95z5z6Ew+SDhRIXow1mD Xq1ViKV4ybPxluVbF6pU3o8fLUaFGQUEso58IVCO+SWB8oa6ATp9vUCMLjZki1DTOR1K6f6G oZaW+yRqPtVPondGZzR0/j2BXpdnidFwkhmgjJYKEbpr7iTRTatFhCwNAag99o4YxT01k6i2 /wyBbK2FOKp8sxm1T9ijseddwH8+k381HzBjoxdwZrAtjmSuGC04U5bZSTJFprNipjI7n2SS Tg+ImeqBJyImudgEmAeNx5nhIpdtdoHStUGsNiSSNSjX7ZMGm7/fAqEvJdHWjt8iI4ijEoGE grQvrL/3FUsEUkpO3wGwLyUX5wU5PQJgz7UTgjAMYNeNfmwmYSuqAoJwG8DWhhRSeEwm6vq+ TMYpSkx7wVJTGB9wpDMAvNK7g/dg9EcMJt/NArzgQG+CPb8uT7Xi9GI43nNJxGdl9HrY27NF GHOFeferpiwS2h/aUl8QfA+kcymYV/IQCKaNsLr9Ey5gB9hXX0wK2Bn+LcsRCZiDxqTcaX8M 7E7JnvasgbX1FoLfxWh3WFCuFOgN0Bo7JOZpSNvDtu9zeBqbhBdK0jGBlsGEeLngXgqLz7+a HpoLb+enTZczsCy+kxDueRHAZ61LU4Fr5v+tawCYwDw2gtNpWM5Hz0Z5cWodF6HXeB04oisC k9+w0VY/Wgoq/uyvATQFFHayfdZdKjmhjuSO6moApDCFoyw6K1AllwWpjx5jDUf2GiK0LFcD FlC4Yp7s+KwPu+S0Rh3OHmbZUNYwo4ooiZMRxNakOe5dvVLrk97poV/o9mCDf/VuJ50ypm72 KklzdEifUVMsJXW1ltDPhzyxX4m947Uyt3uJ291/BLzd09xk8njtp0RjymiVxrbn0U699mfw bJfArLAXePmA+y3vZQXEJr+JBTbfQcfBr43b3UOXnEjb7NRxsvBgq2ezYdF4VAKjwLlg9QoP zMCp/wEicnClggMAAA== X-Brightmail-Tracker: H4sIAAAAAAAAA+NgFrrCIsWRmVeSWpSXmKPExsVy+t/xe7reCrGxBp23NSw2zljPanH9y3NW i/lHzrFarP74mNGiefF6NovJp+YyWZzpzrXof/ya2eL8+Q3sFmeb3rBb3GqQsfjYc4/V4vKu OWwWn3uPMFrMOL+PyWLtkbvsFkuvX2SyuHjK1eJ24wo2i9a9R9gtDr9pZ7X4d20ji8X+K14W t3/zWXw78YjRQdJjzbw1jB7fvk5i8Xh/o5XdY3bDRRaPnbPusntsWtXJ5rF/7hp2j97md2we B9/tYfLo27KK0WPz6WqPz5vkAnii9GyK8ktLUhUy8otLbJWiDS2M9AwtLfSMTCz1DI3NY62M TJX07WxSUnMyy1KL9O0S9DKOvF3GWHCOs+L6nV9MDYytHF2MnBwSAiYS/zYdYOxi5OIQEljK KNF68QoLREJMYtK+7ewQtrDEn2tdbBBFnxgl7vZOY+1i5OBgE9CT2LGqECQuIjCHUeJn1zaw ScwCv5klDt7tB+sWFvCUePJjKjOIzSKgKvHzyRQmkGZeAXuJF0+8IRbIS6zecACshFPAQeLf hJOsILYQUMnUDW9ZJzDyLWBkWMUoklpanJueW2ykV5yYW1yal66XnJ+7iREYo9uO/dyyg7Hr XfAhRgEORiUe3h03o2OFWBPLiitzDzFKcDArifBWzImKFeJNSaysSi3Kjy8qzUktPsRoCnTT RGYp0eR8YPrIK4k3NDU0t7A0NDc2NzazUBLn7RA4GCMkkJ5YkpqdmlqQWgTTx8TBKdXAyPCb qzxsQwuf7Uqv3T9Vl6YousccTS6RbfhktTVKoCenYvnxntIpF8wYb1S/XVaS+Spz94O8s6GZ c0JfOm7ImTkjuaiE22u30d6mZecDc1bVHYybzDdlU8wXRcbb53+sbSioq3r6N7vt1QFJyX2M zq0bltaH6/s6Wfhv/nkqmv1yScSZX+f2KrEUZyQaajEXFScCABVCIHfnAgAA X-CMS-MailID: 20190821104323eucas1p2e0956d08d3d6c3934760ea76c2de0d57 X-Msg-Generator: CA X-RootMTR: 20190821104323eucas1p2e0956d08d3d6c3934760ea76c2de0d57 X-EPHeader: CA CMS-TYPE: 201P X-CMS-RootMailID: 20190821104323eucas1p2e0956d08d3d6c3934760ea76c2de0d57 References: <20190821104303.32079-1-l.luba@partner.samsung.com> Sender: linux-pm-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-pm@vger.kernel.org In order to get the clock by phandle and use it with regmap it needs to be compatible with syscon. The DMC driver uses two registers from clock register set and needs the regmap of them. Signed-off-by: Lukasz Luba --- arch/arm/boot/dts/exynos5420.dtsi | 2 +- arch/arm/boot/dts/exynos5800.dtsi | 2 +- 2 files changed, 2 insertions(+), 2 deletions(-) diff --git a/arch/arm/boot/dts/exynos5420.dtsi b/arch/arm/boot/dts/exynos5420.dtsi index 55d4dbf6f83a..97dc10915680 100644 --- a/arch/arm/boot/dts/exynos5420.dtsi +++ b/arch/arm/boot/dts/exynos5420.dtsi @@ -175,7 +175,7 @@ }; clock: clock-controller@10010000 { - compatible = "samsung,exynos5420-clock"; + compatible = "samsung,exynos5420-clock", "syscon"; reg = <0x10010000 0x30000>; #clock-cells = <1>; }; diff --git a/arch/arm/boot/dts/exynos5800.dtsi b/arch/arm/boot/dts/exynos5800.dtsi index 57d3b319fd65..0a2b3287ed92 100644 --- a/arch/arm/boot/dts/exynos5800.dtsi +++ b/arch/arm/boot/dts/exynos5800.dtsi @@ -17,7 +17,7 @@ }; &clock { - compatible = "samsung,exynos5800-clock"; + compatible = "samsung,exynos5800-clock", "syscon"; }; &cluster_a15_opp_table { From patchwork Wed Aug 21 10:43:02 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Lukasz Luba X-Patchwork-Id: 11106297 Return-Path: Received: from mail.kernel.org (pdx-korg-mail-1.web.codeaurora.org [172.30.200.123]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id 2DFD7184E for ; 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a=rsa-sha256; c=relaxed/relaxed; d=samsung.com; s=mail20170921; t=1566384206; bh=TAPWPPhwwkIk8EwgyjxnFQvKK3TRw7k8bAwvjvG/ja4=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=m8aFdpVeksx8I5eonW2H1y26JML78EDEso5qqa8T+rHzYJ+OyyOlvIqe2hn/1cXBI W3or+w2UDLDlIMRbycLvkVSfrcv6cQb52HRrbJfIHFvdOhqI+OPeDmO1pSarNfsiPr FeB6C7WLE++IZbweMTZ6y0HWl0kriKPy16A7kC3o= Received: from eusmges3new.samsung.com (unknown [203.254.199.245]) by eucas1p2.samsung.com (KnoxPortal) with ESMTP id 20190821104325eucas1p2404caecca8fe338ba49b457907d19fb5~86iLXMTpz0891408914eucas1p2K; Wed, 21 Aug 2019 10:43:25 +0000 (GMT) Received: from eucas1p2.samsung.com ( [182.198.249.207]) by eusmges3new.samsung.com (EUCPMTA) with SMTP id 00.B6.04374.D402D5D5; Wed, 21 Aug 2019 11:43:25 +0100 (BST) Received: from eusmtrp2.samsung.com (unknown [182.198.249.139]) by eucas1p1.samsung.com (KnoxPortal) with ESMTPA id 20190821104324eucas1p16bdeb27250c8c9fa87591d6bd9743a17~86iKgWQ_d1333613336eucas1p1X; Wed, 21 Aug 2019 10:43:24 +0000 (GMT) Received: from eusmgms2.samsung.com (unknown [182.198.249.180]) by eusmtrp2.samsung.com (KnoxPortal) with ESMTP id 20190821104324eusmtrp2a365a112a2efa3b90bf2616b2d7539fc~86iKfsF9I2827428274eusmtrp2H; Wed, 21 Aug 2019 10:43:24 +0000 (GMT) X-AuditID: cbfec7f5-4ddff70000001116-6d-5d5d204dc56a Received: from eusmtip2.samsung.com ( [203.254.199.222]) by eusmgms2.samsung.com (EUCPMTA) with SMTP id 71.48.04117.C402D5D5; Wed, 21 Aug 2019 11:43:24 +0100 (BST) Received: from AMDC3778.DIGITAL.local (unknown [106.120.51.20]) by eusmtip2.samsung.com (KnoxPortal) with ESMTPA id 20190821104323eusmtip2f9f79e629f802dc6ff89f2776eea528c~86iJbtZJi1732517325eusmtip22; Wed, 21 Aug 2019 10:43:23 +0000 (GMT) From: Lukasz Luba To: devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-pm@vger.kernel.org, linux-samsung-soc@vger.kernel.org, linux-clk@vger.kernel.org Cc: mturquette@baylibre.com, sboyd@kernel.org, b.zolnierkie@samsung.com, krzk@kernel.org, kgene@kernel.org, mark.rutland@arm.com, robh+dt@kernel.org, cw00.choi@samsung.com, kyungmin.park@samsung.com, m.szyprowski@samsung.com, s.nawrocki@samsung.com, myungjoo.ham@samsung.com, keescook@chromium.org, tony@atomide.com, jroedel@suse.de, treding@nvidia.com, digetx@gmail.com, gregkh@linuxfoundation.org, willy.mh.wolff.ml@gmail.com, Lukasz Luba Subject: [PATCH v13 7/8] ARM: dts: exynos: add DMC device for exynos5422 Date: Wed, 21 Aug 2019 12:43:02 +0200 Message-Id: <20190821104303.32079-8-l.luba@partner.samsung.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20190821104303.32079-1-l.luba@partner.samsung.com> X-Brightmail-Tracker: H4sIAAAAAAAAA0WSe0yNYRzHPee91jp5nUw/NOksG7YK+eMZ5rK5vGM2zT9WOzj0dplO5bwV YXawyFEHlUp1cmmU1DqlteLkUmdSIkdXWW6xUFJL0WUHr/c0/31+3+/393yfPXtYQjVEzWMj o+MEfbQ2Sk27klWPx1v8ti/UaJZZbV64PLuMwp0/+ih8xfacwreHexE+VVBG4/QmswI3n9Ph 8739BG5psTD42ckBBncbvPBwyhsKt97No/FIqg3h7Jb7Clxq62HwjU67AtubNuHXJ4ponFRr Y3D9wBkKOzrKSfygbSt+PemOx558QOvn8iX5JYgfG00j+e9dSQyfa7CTfE1OD8NXFJ+l+Qfm EoZPPTVI848GrQreVFmM+DtPj/IjFQt2uAW7rgkVoiITBH3A2r2uEVPtn1Hsx4DDA0kpyIBS fY3IhQVuJXSVTxJG5MqquCIE/VNtjDz8QGBKG6PkYQTBY6tRMb2S0XTaaRQiSC69R0rGv5UX Od5GxLI05w/VxQcleTaXjSD3804pT3DvCTCV5iHJ8OB4+J01QUlMcosg/0sjLe0quXWQ1+Un d3nDbctDQmIXbj04LjT+6wXuGgvZAxZKDm2E5JOXaJk94GtDJSOzF/yuueK8tAiG1GtI5mPQ e97szKyG+gY7JfUS3BIouxsgyxvAVmllJBk4d+j6NkuSib+YVpVFyLISkk+r5PRiqEx54Sya A4Ulmc7DebhenuV8z3QEHx019AXknfO/7CpCxchTiBd14YIYGC0c8he1OjE+Otx/f4yuAv39 h08dDaPV6P7UvjrEsUjtptzbGaJRUdoEMVFXh4Al1LOVh/OCNSplqDbxiKCP2aOPjxLEOjSf JdWeyqMz3oWouHBtnHBAEGIF/bSrYF3mGRBKg3bzJ/vawAJNaOYct7mthT9376iHd+SvPost yKRrWx4q/HpVZU08ezFiqXlssLXTccbD8/Kbt80TQ47rq46vSIls3Fa3ZeLRrIf9Rpsltjbd 58DNXTkd2oXJYd0NYZ4emX0rfHp9gzLu+U2OWsf7MkLG3V8i08TMW36br24M4dWkGKFdvpTQ i9o/Z3Y2wYMDAAA= X-Brightmail-Tracker: H4sIAAAAAAAAA+NgFrrCIsWRmVeSWpSXmKPExsVy+t/xe7o+CrGxBvfeGlhsnLGe1eL6l+es FvOPnGO1WP3xMaNF8+L1bBaTT81lsjjTnWvR//g1s8X58xvYLc42vWG3uNUgY/Gx5x6rxeVd c9gsPvceYbSYcX4fk8XaI3fZLZZev8hkcfGUq8XtxhVsFq17j7BbHH7Tzmrx79pGFov9V7ws bv/ms/h24hGjg6THmnlrGD2+fZ3E4vH+Riu7x+yGiyweO2fdZffYtKqTzWP/3DXsHr3N79g8 Dr7bw+TRt2UVo8fm09UenzfJBfBE6dkU5ZeWpCpk5BeX2CpFG1oY6RlaWugZmVjqGRqbx1oZ mSrp29mkpOZklqUW6dsl6GX8ufqCseCJfsWb1h7GBsZelS5GTg4JAROJKafaWLsYuTiEBJYy SvQeX8gMkRCTmLRvOzuELSzx51oXG0TRJ0aJs3tbmLoYOTjYBPQkdqwqBImLCMxhlPjZtY0R xGEW+M0scfBuP1i3sICHxP/pv1hBbBYBVYl5L0+ygTTzCthLzLmhC7FAXmL1hgNgizkFHCT+ TTgJVi4EVDJ1w1vWCYx8CxgZVjGKpJYW56bnFhvpFSfmFpfmpesl5+duYgTG6LZjP7fsYOx6 F3yIUYCDUYmHd8fN6Fgh1sSy4srcQ4wSHMxKIrwVc6JihXhTEiurUovy44tKc1KLDzGaAt00 kVlKNDkfmD7ySuINTQ3NLSwNzY3Njc0slMR5OwQOxggJpCeWpGanphakFsH0MXFwSjUw8mfk Fmy8dX7ppvB1F4wv7v20WuRD9FoTLm3NMI81W0/+2bSt6IHWviOvTc7s+Vuqy5Ma7R8imCK/ zc5Qa/eeyh5GK6eAE0u+r1q9ZveclI0fEn/tYS0Sn/UwOcqx6jzHSssVWnL86Xv1ii3+Khqd dXF88+aBa1OxzORJLpXGD3nEbSOXruk7q8RSnJFoqMVcVJwIAOkkrK3nAgAA X-CMS-MailID: 20190821104324eucas1p16bdeb27250c8c9fa87591d6bd9743a17 X-Msg-Generator: CA X-RootMTR: 20190821104324eucas1p16bdeb27250c8c9fa87591d6bd9743a17 X-EPHeader: CA CMS-TYPE: 201P X-CMS-RootMailID: 20190821104324eucas1p16bdeb27250c8c9fa87591d6bd9743a17 References: <20190821104303.32079-1-l.luba@partner.samsung.com> Sender: linux-pm-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-pm@vger.kernel.org Add description of Dynamic Memory Controller and PPMU counters. They are used by exynos5422-dmc driver. There is a definition of the memory chip, which is then used during calculation of timings for each OPP. The algorithm in the driver needs these two sets to bound the timings. Signed-off-by: Lukasz Luba --- arch/arm/boot/dts/exynos5420.dtsi | 71 +++++++++++ arch/arm/boot/dts/exynos5422-odroid-core.dtsi | 116 ++++++++++++++++++ 2 files changed, 187 insertions(+) diff --git a/arch/arm/boot/dts/exynos5420.dtsi b/arch/arm/boot/dts/exynos5420.dtsi index 97dc10915680..ac49373baae7 100644 --- a/arch/arm/boot/dts/exynos5420.dtsi +++ b/arch/arm/boot/dts/exynos5420.dtsi @@ -237,6 +237,29 @@ status = "disabled"; }; + dmc: memory-controller@10c20000 { + compatible = "samsung,exynos5422-dmc"; + reg = <0x10c20000 0x100>, <0x10c30000 0x100>; + clocks = <&clock CLK_FOUT_SPLL>, + <&clock CLK_MOUT_SCLK_SPLL>, + <&clock CLK_FF_DOUT_SPLL2>, + <&clock CLK_FOUT_BPLL>, + <&clock CLK_MOUT_BPLL>, + <&clock CLK_SCLK_BPLL>, + <&clock CLK_MOUT_MX_MSPLL_CCORE>, + <&clock CLK_MOUT_MCLK_CDREX>; + clock-names = "fout_spll", + "mout_sclk_spll", + "ff_dout_spll2", + "fout_bpll", + "mout_bpll", + "sclk_bpll", + "mout_mx_mspll_ccore", + "mout_mclk_cdrex"; + samsung,syscon-clk = <&clock>; + status = "disabled"; + }; + nocp_mem0_0: nocp@10ca1000 { compatible = "samsung,exynos5420-nocp"; reg = <0x10CA1000 0x200>; @@ -273,6 +296,54 @@ status = "disabled"; }; + ppmu_dmc0_0: ppmu@10d00000 { + compatible = "samsung,exynos-ppmu"; + reg = <0x10d00000 0x2000>; + clocks = <&clock CLK_PCLK_PPMU_DREX0_0>; + clock-names = "ppmu"; + events { + ppmu_event3_dmc0_0: ppmu-event3-dmc0_0 { + event-name = "ppmu-event3-dmc0_0"; + }; + }; + }; + + ppmu_dmc0_1: ppmu@10d10000 { + compatible = "samsung,exynos-ppmu"; + reg = <0x10d10000 0x2000>; + clocks = <&clock CLK_PCLK_PPMU_DREX0_1>; + clock-names = "ppmu"; + events { + ppmu_event3_dmc0_1: ppmu-event3-dmc0_1 { + event-name = "ppmu-event3-dmc0_1"; + }; + }; + }; + + ppmu_dmc1_0: ppmu@10d60000 { + compatible = "samsung,exynos-ppmu"; + reg = <0x10d60000 0x2000>; + clocks = <&clock CLK_PCLK_PPMU_DREX1_0>; + clock-names = "ppmu"; + events { + ppmu_event3_dmc1_0: ppmu-event3-dmc1_0 { + event-name = "ppmu-event3-dmc1_0"; + }; + }; + }; + + ppmu_dmc1_1: ppmu@10d70000 { + compatible = "samsung,exynos-ppmu"; + reg = <0x10d70000 0x2000>; + clocks = <&clock CLK_PCLK_PPMU_DREX1_1>; + clock-names = "ppmu"; + events { + ppmu_event3_dmc1_1: ppmu-event3-dmc1_1 { + event-name = "ppmu-event3-dmc1_1"; + }; + }; + }; + gsc_pd: power-domain@10044000 { compatible = "samsung,exynos4210-pd"; reg = <0x10044000 0x20>; diff --git a/arch/arm/boot/dts/exynos5422-odroid-core.dtsi b/arch/arm/boot/dts/exynos5422-odroid-core.dtsi index 829147e320e0..fe885ca969af 100644 --- a/arch/arm/boot/dts/exynos5422-odroid-core.dtsi +++ b/arch/arm/boot/dts/exynos5422-odroid-core.dtsi @@ -34,6 +34,97 @@ clock-frequency = <24000000>; }; }; + + dmc_opp_table: opp_table2 { + compatible = "operating-points-v2"; + + opp00 { + opp-hz = /bits/ 64 <165000000>; + opp-microvolt = <875000>; + }; + opp01 { + opp-hz = /bits/ 64 <206000000>; + opp-microvolt = <875000>; + }; + opp02 { + opp-hz = /bits/ 64 <275000000>; + opp-microvolt = <875000>; + }; + opp03 { + opp-hz = /bits/ 64 <413000000>; + opp-microvolt = <887500>; + }; + opp04 { + opp-hz = /bits/ 64 <543000000>; + opp-microvolt = <937500>; + }; + opp05 { + opp-hz = /bits/ 64 <633000000>; + opp-microvolt = <1012500>; + }; + opp06 { + opp-hz = /bits/ 64 <728000000>; + opp-microvolt = <1037500>; + }; + opp07 { + opp-hz = /bits/ 64 <825000000>; + opp-microvolt = <1050000>; + }; + }; + + samsung_K3QF2F20DB: lpddr3 { + compatible = "samsung,K3QF2F20DB", "jedec,lpddr3"; + density = <16384>; + io-width = <32>; + #address-cells = <1>; + #size-cells = <0>; + + tRFC-min-tck = <17>; + tRRD-min-tck = <2>; + tRPab-min-tck = <2>; + tRPpb-min-tck = <2>; + tRCD-min-tck = <3>; + tRC-min-tck = <6>; + tRAS-min-tck = <5>; + tWTR-min-tck = <2>; + tWR-min-tck = <7>; + tRTP-min-tck = <2>; + tW2W-C2C-min-tck = <0>; + tR2R-C2C-min-tck = <0>; + tWL-min-tck = <8>; + tDQSCK-min-tck = <5>; + tRL-min-tck = <14>; + tFAW-min-tck = <5>; + tXSR-min-tck = <12>; + tXP-min-tck = <2>; + tCKE-min-tck = <2>; + tCKESR-min-tck = <2>; + tMRD-min-tck = <5>; + + timings_samsung_K3QF2F20DB_800mhz: lpddr3-timings@800000000 { + compatible = "jedec,lpddr3-timings"; + reg = <800000000>; /* workaround: it shows max-freq */ + min-freq = <100000000>; + tRFC = <65000>; + tRRD = <6000>; + tRPab = <12000>; + tRPpb = <12000>; + tRCD = <10000>; + tRC = <33750>; + tRAS = <23000>; + tWTR = <3750>; + tWR = <7500>; + tRTP = <3750>; + tW2W-C2C = <0>; + tR2R-C2C = <0>; + tFAW = <25000>; + tXSR = <70000>; + tXP = <3750>; + tCKE = <3750>; + tCKESR = <3750>; + tMRD = <7000>; + }; + }; }; &adc { @@ -132,6 +223,15 @@ cpu-supply = <&buck2_reg>; }; +&dmc { + devfreq-events = <&ppmu_event3_dmc0_0>, <&ppmu_event3_dmc0_1>, + <&ppmu_event3_dmc1_0>, <&ppmu_event3_dmc1_1>; + device-handle = <&samsung_K3QF2F20DB>; + operating-points-v2 = <&dmc_opp_table>; + vdd-supply = <&buck1_reg>; + status = "okay"; +}; + &hsi2c_4 { status = "okay"; @@ -634,6 +734,22 @@ }; }; +&ppmu_dmc0_0 { + status = "okay"; +}; + +&ppmu_dmc0_1 { + status = "okay"; +}; + +&ppmu_dmc1_0 { + status = "okay"; +}; + +&ppmu_dmc1_1 { + status = "okay"; +}; + &tmu_cpu0 { vtmu-supply = <&ldo7_reg>; }; From patchwork Wed Aug 21 10:43:03 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Lukasz Luba X-Patchwork-Id: 11106293 Return-Path: Received: from mail.kernel.org (pdx-korg-mail-1.web.codeaurora.org [172.30.200.123]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id 9654F14DB for ; Wed, 21 Aug 2019 10:43:34 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.kernel.org (Postfix) with ESMTP id 6A9F6233A1 for ; Wed, 21 Aug 2019 10:43:34 +0000 (UTC) Authentication-Results: mail.kernel.org; dkim=pass (1024-bit key) header.d=samsung.com header.i=@samsung.com header.b="nkGGS6wI" Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1728355AbfHUKna (ORCPT ); Wed, 21 Aug 2019 06:43:30 -0400 Received: from mailout2.w1.samsung.com ([210.118.77.12]:35693 "EHLO mailout2.w1.samsung.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1728354AbfHUKn3 (ORCPT ); Wed, 21 Aug 2019 06:43:29 -0400 Received: from eucas1p2.samsung.com (unknown [182.198.249.207]) by mailout2.w1.samsung.com (KnoxPortal) with ESMTP id 20190821104328euoutp02c94c7fe877147ccb9b855bb482d0def3~86iOBYt6H0339203392euoutp02P for ; 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Wed, 21 Aug 2019 10:43:26 +0000 (GMT) Received: from eusmgms1.samsung.com (unknown [182.198.249.179]) by eusmtrp2.samsung.com (KnoxPortal) with ESMTP id 20190821104326eusmtrp2075e87e6d1380e7694de89786cd77d6f~86iLn8F_k2827428274eusmtrp2J; Wed, 21 Aug 2019 10:43:26 +0000 (GMT) X-AuditID: cbfec7f2-569ff70000001175-38-5d5d204e7dcb Received: from eusmtip2.samsung.com ( [203.254.199.222]) by eusmgms1.samsung.com (EUCPMTA) with SMTP id 0F.A6.04166.D402D5D5; Wed, 21 Aug 2019 11:43:25 +0100 (BST) Received: from AMDC3778.DIGITAL.local (unknown [106.120.51.20]) by eusmtip2.samsung.com (KnoxPortal) with ESMTPA id 20190821104324eusmtip24bfb5fa911274810401b3b87b8b017d0~86iKf58ZG1735217352eusmtip2s; Wed, 21 Aug 2019 10:43:24 +0000 (GMT) From: Lukasz Luba To: devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-pm@vger.kernel.org, linux-samsung-soc@vger.kernel.org, linux-clk@vger.kernel.org Cc: mturquette@baylibre.com, sboyd@kernel.org, b.zolnierkie@samsung.com, krzk@kernel.org, kgene@kernel.org, mark.rutland@arm.com, robh+dt@kernel.org, cw00.choi@samsung.com, kyungmin.park@samsung.com, m.szyprowski@samsung.com, s.nawrocki@samsung.com, myungjoo.ham@samsung.com, keescook@chromium.org, tony@atomide.com, jroedel@suse.de, treding@nvidia.com, digetx@gmail.com, gregkh@linuxfoundation.org, willy.mh.wolff.ml@gmail.com, Lukasz Luba Subject: [PATCH v13 8/8] ARM: exynos_defconfig: enable DMC driver Date: Wed, 21 Aug 2019 12:43:03 +0200 Message-Id: <20190821104303.32079-9-l.luba@partner.samsung.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20190821104303.32079-1-l.luba@partner.samsung.com> X-Brightmail-Tracker: H4sIAAAAAAAAA0WSe0hTYRjG+3Z2Lg4nxxn5lVIxClTIMgy+6GaUcCoIMSrSlk49mOWW7XjN LjNRy7Jkdhnl3cyYllfKxDLncKXZUjNv2U3CTJvoUtJA83Ss/vt97/s87/Py8lGYzIovoyLU 0axGrYyUExLxw+Zpy5q9KxWKdd9nvFGlvhxH3T+GcJRneoWj0vFBgJKLygmU1ZIjQi8vqdDV wREMWSwVJGo7P0qiPq0rGr/8HkedddkEsmWYANJbnorQfdMAiYq720WovcUX9SfdI1DKExOJ mkbTcDT7tlKMGt7sRv2/HNDU88/AZylTllsGmKlJnZgZ60khmdvadjHz+NYAyVQZLhJMQ04Z yWQkWwmm0VovYq7UGABT3ZrI2KqW+9kHSDaHsZERsaxm7dZgydHqqS4QNYbHTzQU4lpwHU8H dhSkvaFxvEmUDiSUjL4HYGHqV0x4/ACwLV9P8ioZbQOwrmTTX8ed3PO4ICoB0JzSiv9zTNe3 iNMBRRG0J6w1nOQNi2k9gLe/7uM1GP0Jg1fuZwO+4URvh7aCLzivF9OrocG4ni9L6W2wta+U FMJWwNKKZxjPdrQPnM188ScL0gUU7M4cwQTRTjjz6jUhsBP8Zq5ZMLvCucd5IoE5qM0oAAKf hoNXcxY0m2CTuf3PDhjtDsvr1vII51cbbXYR0AH2fHfkxdg86h7exISyFF5IlQkz3GDN5dcL OUtgSdmNhdkMvDZWTQgXzAKwK9kvE6y49T8qHwADcGZjOFU4y3mp2ThPTqniYtThnqEnVFVg /he2zponasFkR4gR0BSQ20trewMVMlwZyyWojABSmHyxND47QCGThikTTrGaE0GamEiWMwIX Six3liYu+hgoo8OV0exxlo1iNX+7IspumRYEjXzKHzZ3YsNz9p0GiX+I488ko867Yki/68G5 xrwPzbtMcdv8RW2TRUW9SWNqlfOQ683naYkRL/YfSOh4hx7pLDt0xYum4ZnDRw5Frw+2WTfq AyJ7f4KiZKtCsmrV2eE8h6yTvn61E2ywx5YNU+tO+29PC3U75t6VEHq3ec/B/hi5mDuq9PLA NJzyN5TVkhmBAwAA X-Brightmail-Tracker: H4sIAAAAAAAAA+NgFrrCIsWRmVeSWpSXmKPExsVy+t/xe7q+CrGxBts/WltsnLGe1eL6l+es FvOPnGO1WP3xMaNF8+L1bBaTT81lsjjTnWvR//g1s8X58xvYLc42vWG3uNUgY/Gx5x6rxeVd c9gsPvceYbSYcX4fk8XaI3fZLZZev8hkcfGUq8XtxhVsFq17j7BbHH7Tzmrx79pGFov9V7ws bv/ms/h24hGjg6THmnlrGD2+fZ3E4vH+Riu7x+yGiyweO2fdZffYtKqTzWP/3DXsHr3N79g8 Dr7bw+TRt2UVo8fm09UenzfJBfBE6dkU5ZeWpCpk5BeX2CpFG1oY6RlaWugZmVjqGRqbx1oZ mSrp29mkpOZklqUW6dsl6GVs/naVseA9a8Wn/YtYGxinsnYxcnJICJhILJnXBGRzcQgJLGWU uPn0CyNEQkxi0r7t7BC2sMSfa11sEEWfGCX6up8wdzFycLAJ6EnsWFUIEhcRmMMo8bNrGyOI wyzwm1ni4N1+sG5hAUeJzwufsoI0sAioSqw6ZAQS5hWwlzh9azXUAnmJ1RsOMIPYnAIOEv8m nAS7TgioZuqGt6wTGPkWMDKsYhRJLS3OTc8tNtQrTswtLs1L10vOz93ECIzRbcd+bt7BeGlj 8CFGAQ5GJR7eHTejY4VYE8uKK3MPMUpwMCuJ8FbMiYoV4k1JrKxKLcqPLyrNSS0+xGgKdNNE ZinR5Hxg+sgriTc0NTS3sDQ0NzY3NrNQEuftEDgYIySQnliSmp2aWpBaBNPHxMEp1cDIVHJg Tc+NOoH0r4enbJpcdURY+lvJje1ehnXFR2Li+jf/eaXSHWOwXubthrAbJz07jCZE2co3RByP 6FN6xP/+7joG75g9Bfn+pof1y9Tn87oe9jPwKzcx+RHO4st3q9H44sZrasysN3MW+S4MXP9Q aoLE6TOua02/3K+PvPR1i9y9Ble7BgklluKMREMt5qLiRABiOSnK5wIAAA== X-CMS-MailID: 20190821104326eucas1p1f22b49095a17f0b303910c391ff1e906 X-Msg-Generator: CA X-RootMTR: 20190821104326eucas1p1f22b49095a17f0b303910c391ff1e906 X-EPHeader: CA CMS-TYPE: 201P X-CMS-RootMailID: 20190821104326eucas1p1f22b49095a17f0b303910c391ff1e906 References: <20190821104303.32079-1-l.luba@partner.samsung.com> Sender: linux-pm-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-pm@vger.kernel.org Enable driver for Exynos5422 Dynamic Memory Controller supporting dynamic frequency and voltage scaling in Exynos5422 SoCs. Signed-off-by: Lukasz Luba --- arch/arm/configs/exynos_defconfig | 1 + 1 file changed, 1 insertion(+) diff --git a/arch/arm/configs/exynos_defconfig b/arch/arm/configs/exynos_defconfig index 2e6a863d25aa..ebed93236a47 100644 --- a/arch/arm/configs/exynos_defconfig +++ b/arch/arm/configs/exynos_defconfig @@ -291,6 +291,7 @@ CONFIG_DEVFREQ_GOV_PERFORMANCE=y CONFIG_DEVFREQ_GOV_POWERSAVE=y CONFIG_DEVFREQ_GOV_USERSPACE=y CONFIG_ARM_EXYNOS_BUS_DEVFREQ=y +CONFIG_EXYNOS5422_DMC=y CONFIG_DEVFREQ_EVENT_EXYNOS_NOCP=y CONFIG_EXTCON=y CONFIG_EXTCON_MAX14577=y