From patchwork Wed Aug 21 22:24:16 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Guillaume LA ROQUE X-Patchwork-Id: 11108241 X-Patchwork-Delegate: eduardo.valentin@ti.com Return-Path: Received: from mail.kernel.org (pdx-korg-mail-1.web.codeaurora.org [172.30.200.123]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id F21011813 for ; Wed, 21 Aug 2019 22:24:49 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.kernel.org (Postfix) with ESMTP id CFEBC233A2 for ; Wed, 21 Aug 2019 22:24:49 +0000 (UTC) Authentication-Results: mail.kernel.org; dkim=pass (2048-bit key) header.d=baylibre-com.20150623.gappssmtp.com header.i=@baylibre-com.20150623.gappssmtp.com header.b="Y19lRcDF" Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1731130AbfHUWY1 (ORCPT ); Wed, 21 Aug 2019 18:24:27 -0400 Received: from mail-wr1-f66.google.com ([209.85.221.66]:45576 "EHLO mail-wr1-f66.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1729758AbfHUWY0 (ORCPT ); Wed, 21 Aug 2019 18:24:26 -0400 Received: by mail-wr1-f66.google.com with SMTP id q12so3456145wrj.12 for ; Wed, 21 Aug 2019 15:24:25 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=baylibre-com.20150623.gappssmtp.com; s=20150623; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=XcX2XfXI5RWl+qmPGtbnaP1+JiH+jtO4YYoKGP+64Jw=; b=Y19lRcDFSb95UM2o4oHaVdAKInX7LjtGZ7ONvY71k8sb/Qi4XJNB5NDm0gZnNN4X7m vNc1hVwSIMSEFjOv1lkFOHTZ1V9W26/uHhYWFn/Srei6PxJpDIF0gAasNX14rLuRZ4Mh m1MSnZcfCTJ+ZtRwjEmGq84hSXItsG/4WnwE3H4WiM3OqI6ZsuufCsxY1bZimNfMcBVE IDLvgqkRptXGX4iul+cGO8JqMB+n9kJiwCSJgSFQRnfBqc+QXSDOJBq6yie8VCCyaBX4 ni0i6EQ5dKFOjV1IWf19d14VDfXrE/2LrshZ02orC624BzJvRl+WRTMxcVbcbiLx34wH JLDw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=XcX2XfXI5RWl+qmPGtbnaP1+JiH+jtO4YYoKGP+64Jw=; b=rvL7Z801Gnu3hSCIElXoGbeYxNhD8qqn5l70VdzpSdFQn/LxYMvLnwtx80GVQmD6pV UJpNw582R+H4edCpdbX0McjnitamOntEc2CCJr5H+ILXLb+e6OGJntWyMORPt01aBzKo NNLXxr31gWd5WlCZ6X1RlIEjal0j/CKHsUgl8L5amO0sYm5VWiBEZh8xViZqDee0C1Sk MyPl2Uoa1guxMECwrnD03dgYbwY+EZbpPkHrUyAMmL5fmcVJqXun8DWzUVP7cRY6HKsg M9LHklH9AtjPMnvlv7AhxZJEVtLHikfGWPbJKPCFMwmu5gaG4wWSv3+NqoyiR45Zvymz JtFw== X-Gm-Message-State: APjAAAULEIkjnM7TKxQFVpeU1c3314kfmb6hkmxd+SIP469K6CcIVvjE 6FSELQ8gtIVRSGLcwqfztnuqdQ== X-Google-Smtp-Source: APXvYqzio+ssPLSEM+HBqzThdCWa9cLYSj5TVfppU45s05F6VnVEL6giT+0XA9MorRrbp7MOZttjaQ== X-Received: by 2002:a5d:6606:: with SMTP id n6mr45412511wru.346.1566426264948; Wed, 21 Aug 2019 15:24:24 -0700 (PDT) Received: from localhost.localdomain ([2a01:cb1d:6e7:d500:82a9:347a:43f3:d2ca]) by smtp.gmail.com with ESMTPSA id f197sm3548549wme.22.2019.08.21.15.24.23 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 21 Aug 2019 15:24:24 -0700 (PDT) From: Guillaume La Roque To: rui.zhang@intel.com, edubezval@gmail.com, daniel.lezcano@linaro.org Cc: linux-pm@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-amlogic@lists.infradead.org Subject: [PATCH v4 1/6] dt-bindings: thermal: Add DT bindings documentation for Amlogic Thermal Date: Thu, 22 Aug 2019 00:24:16 +0200 Message-Id: <20190821222421.30242-2-glaroque@baylibre.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20190821222421.30242-1-glaroque@baylibre.com> References: <20190821222421.30242-1-glaroque@baylibre.com> Sender: linux-pm-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-pm@vger.kernel.org Adding the devicetree binding documentation for the Amlogic temperature sensor found in the Amlogic Meson G12 SoCs. the G12A and G12B SoCs are supported. Signed-off-by: Guillaume La Roque Reviewed-by: Rob Herring --- .../bindings/thermal/amlogic,thermal.yaml | 54 +++++++++++++++++++ 1 file changed, 54 insertions(+) create mode 100644 Documentation/devicetree/bindings/thermal/amlogic,thermal.yaml diff --git a/Documentation/devicetree/bindings/thermal/amlogic,thermal.yaml b/Documentation/devicetree/bindings/thermal/amlogic,thermal.yaml new file mode 100644 index 000000000000..f761681e4c0d --- /dev/null +++ b/Documentation/devicetree/bindings/thermal/amlogic,thermal.yaml @@ -0,0 +1,54 @@ +# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/thermal/amlogic,thermal.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Amlogic Thermal + +maintainers: + - Guillaume La Roque + +description: Binding for Amlogic Thermal + +properties: + compatible: + items: + - enum: + - amlogic,g12a-cpu-thermal + - amlogic,g12a-ddr-thermal + - const: amlogic,g12a-thermal + + reg: + maxItems: 1 + + interrupts: + maxItems: 1 + + clocks: + maxItems: 1 + + amlogic,ao-secure: + description: phandle to the ao-secure syscon + $ref: '/schemas/types.yaml#/definitions/phandle' + + +required: + - compatible + - reg + - interrupts + - clocks + - amlogic,ao-secure + +examples: + - | + cpu_temp: temperature-sensor@ff634800 { + compatible = "amlogic,g12a-cpu-thermal", + "amlogic,g12a-thermal"; + reg = <0xff634800 0x50>; + interrupts = <0x0 0x24 0x0>; + clocks = <&clk 164>; + #thermal-sensor-cells = <0>; + amlogic,ao-secure = <&sec_AO>; + }; +... From patchwork Wed Aug 21 22:24:17 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Guillaume LA ROQUE X-Patchwork-Id: 11108225 X-Patchwork-Delegate: eduardo.valentin@ti.com Return-Path: Received: from mail.kernel.org (pdx-korg-mail-1.web.codeaurora.org [172.30.200.123]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id D35E2112C for ; Wed, 21 Aug 2019 22:24:29 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.kernel.org (Postfix) with ESMTP id 9E16D2332A for ; Wed, 21 Aug 2019 22:24:29 +0000 (UTC) Authentication-Results: mail.kernel.org; dkim=pass (2048-bit key) header.d=baylibre-com.20150623.gappssmtp.com header.i=@baylibre-com.20150623.gappssmtp.com header.b="XvS1z6uk" Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1731147AbfHUWY3 (ORCPT ); Wed, 21 Aug 2019 18:24:29 -0400 Received: from mail-wm1-f67.google.com ([209.85.128.67]:39206 "EHLO mail-wm1-f67.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1731125AbfHUWY2 (ORCPT ); Wed, 21 Aug 2019 18:24:28 -0400 Received: by mail-wm1-f67.google.com with SMTP id i63so3700229wmg.4 for ; Wed, 21 Aug 2019 15:24:26 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=baylibre-com.20150623.gappssmtp.com; s=20150623; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=o4B5g7ymsZFF76xtNscU9JetOxGjq+u94RReojQK+6Q=; b=XvS1z6ukqYhIPpcYXAY5r6awY7mdGho/3IgCtIioKUF8rfwGCgymajKFkaYk69+dfS yyjAZ1mFur4n0TC9LLwTkmaYG4V/P20Jzpb5B1Ihk4woDyYY1Yxbzf0Vgb3d8YwBcWe2 OSazH/Z1BRSzphlSHxiJzb0r6rxKWwBFyINLtuTKiKSIN5u7vB71nQnYimgqidgYXfw9 BldbWN6JAD6EsA8wvTDv7BYrz4z1QtvHsN0aMX/WrwdBGrmPZ4hJ9jcce5IB6Dah6qLn JX6qEZG8BZvulDVByOu/K68iyigND/59phYFfZl1CxGGue2nZMKr0KKLGgsA0YiTA02Z FCPA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=o4B5g7ymsZFF76xtNscU9JetOxGjq+u94RReojQK+6Q=; b=O1szhd4ndngYsi9czEgHnOxYlC4/gSQS68DV+HumEY/4jYf8IBxfq6nuBJozojqcxl KrJktrybcIUpuJ7Vfz2SYXmpYy2kmHONixZWJiT3ytdLfN2qxUCfSgPR+Q+EGnaKdOyR 5JReUA73u3wAFopkPhJ5Oi0BbwjRGT6Xcj6WeoeIsRw3RMmnitOLSIC6dbgkDqPoGE2+ Vapb9cy19XXE6dPX47t8nmOjfBA6wRpJTpfbQTM48PF1unbsn2bu1fsU5eX9eoZYI3xh w9E6svEZj/xkyXFlMJBPYz5j7LwGEwUJLBZFVYmnjDDmK+sO8gXyvYQfLPw1cXlJc04W 9GEQ== X-Gm-Message-State: APjAAAV7kNJmgba8fUWj1TigNTOK37bIpjEf0otAZOWtN9Fx3dcSMZOv wQdjumkH02n5pQwv3iKAXOuTHQli6tc= X-Google-Smtp-Source: APXvYqxMWVZj0HFKTX2paTQvCqKDq6ltjFRYlzoMrl/h6uDg1GcCSsjpwAVwOSG8LXjNhb7tGslQZg== X-Received: by 2002:a1c:7611:: with SMTP id r17mr2325745wmc.117.1566426266039; Wed, 21 Aug 2019 15:24:26 -0700 (PDT) Received: from localhost.localdomain ([2a01:cb1d:6e7:d500:82a9:347a:43f3:d2ca]) by smtp.gmail.com with ESMTPSA id f197sm3548549wme.22.2019.08.21.15.24.25 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 21 Aug 2019 15:24:25 -0700 (PDT) From: Guillaume La Roque To: rui.zhang@intel.com, edubezval@gmail.com, daniel.lezcano@linaro.org Cc: linux-pm@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-amlogic@lists.infradead.org Subject: [PATCH v4 2/6] thermal: amlogic: Add thermal driver to support G12 SoCs Date: Thu, 22 Aug 2019 00:24:17 +0200 Message-Id: <20190821222421.30242-3-glaroque@baylibre.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20190821222421.30242-1-glaroque@baylibre.com> References: <20190821222421.30242-1-glaroque@baylibre.com> Sender: linux-pm-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-pm@vger.kernel.org Amlogic G12A and G12B SoCs integrate two thermal sensors with the same design. One is located close to the DDR controller and the other one is located close to the PLLs (between the CPU and GPU). The calibration data for each of the thermal sensors instance is stored in a different location within the AO region. Implement reading the temperature from each thermal sensor. The IP block has more functionality, which may be added to this driver in the future: - chip reset when the temperature exceeds a configurable threshold - up to four interrupts when the temperature has risen above a configurable threshold - up to four interrupts when the temperature has fallen below a configurable threshold Signed-off-by: Guillaume La Roque --- drivers/thermal/Kconfig | 11 + drivers/thermal/Makefile | 1 + drivers/thermal/amlogic_thermal.c | 335 ++++++++++++++++++++++++++++++ 3 files changed, 347 insertions(+) create mode 100644 drivers/thermal/amlogic_thermal.c diff --git a/drivers/thermal/Kconfig b/drivers/thermal/Kconfig index 9966364a6deb..0f31bb4bc372 100644 --- a/drivers/thermal/Kconfig +++ b/drivers/thermal/Kconfig @@ -348,6 +348,17 @@ config MTK_THERMAL Enable this option if you want to have support for thermal management controller present in Mediatek SoCs +config AMLOGIC_THERMAL + tristate "Amlogic Thermal Support" + default ARCH_MESON + depends on OF && ARCH_MESON + help + If you say yes here you get support for Amlogic Thermal + for G12 SoC Family. + + This driver can also be built as a module. If so, the module will + be called amlogic_thermal. + menu "Intel thermal drivers" depends on X86 || X86_INTEL_QUARK || COMPILE_TEST source "drivers/thermal/intel/Kconfig" diff --git a/drivers/thermal/Makefile b/drivers/thermal/Makefile index 74a37c7f847a..baeb70bf0568 100644 --- a/drivers/thermal/Makefile +++ b/drivers/thermal/Makefile @@ -54,3 +54,4 @@ obj-$(CONFIG_MTK_THERMAL) += mtk_thermal.o obj-$(CONFIG_GENERIC_ADC_THERMAL) += thermal-generic-adc.o obj-$(CONFIG_ZX2967_THERMAL) += zx2967_thermal.o obj-$(CONFIG_UNIPHIER_THERMAL) += uniphier_thermal.o +obj-$(CONFIG_AMLOGIC_THERMAL) += amlogic_thermal.o diff --git a/drivers/thermal/amlogic_thermal.c b/drivers/thermal/amlogic_thermal.c new file mode 100644 index 000000000000..173d808048d2 --- /dev/null +++ b/drivers/thermal/amlogic_thermal.c @@ -0,0 +1,335 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Amlogic Thermal Sensor Driver + * + * Copyright (C) 2017 Huan Biao + * Copyright (C) 2019 Guillaume La Roque + * + * Register value to celsius temperature formulas: + * Read_Val m * U + * U = ---------, Uptat = --------- + * 2^16 1 + n * U + * + * Temperature = A * ( Uptat + u_efuse / 2^16 )- B + * + * A B m n : calibration parameters + * u_efuse : fused calibration value, it's a signed 16 bits value + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#include "thermal_core.h" + +#define TSENSOR_CFG_REG1 0x4 + #define TSENSOR_CFG_REG1_RSET_VBG BIT(12) + #define TSENSOR_CFG_REG1_RSET_ADC BIT(11) + #define TSENSOR_CFG_REG1_VCM_EN BIT(10) + #define TSENSOR_CFG_REG1_VBG_EN BIT(9) + #define TSENSOR_CFG_REG1_OUT_CTL BIT(6) + #define TSENSOR_CFG_REG1_FILTER_EN BIT(5) + #define TSENSOR_CFG_REG1_DEM_EN BIT(3) + #define TSENSOR_CFG_REG1_CH_SEL GENMASK(1, 0) + #define TSENSOR_CFG_REG1_ENABLE \ + (TSENSOR_CFG_REG1_FILTER_EN | \ + TSENSOR_CFG_REG1_VCM_EN | \ + TSENSOR_CFG_REG1_VBG_EN | \ + TSENSOR_CFG_REG1_DEM_EN | \ + TSENSOR_CFG_REG1_CH_SEL) + +#define TSENSOR_STAT0 0x40 + +#define TSENSOR_STAT9 0x64 + +#define TSENSOR_READ_TEMP_MASK GENMASK(15, 0) +#define TSENSOR_TEMP_MASK GENMASK(11, 0) + +#define TSENSOR_TRIM_SIGN_MASK BIT(15) +#define TSENSOR_TRIM_TEMP_MASK GENMASK(14, 0) +#define TSENSOR_TRIM_VERSION_MASK GENMASK(31, 24) + +#define TSENSOR_TRIM_VERSION(_version) \ + FIELD_GET(TSENSOR_TRIM_VERSION_MASK, _version) + +#define TSENSOR_TRIM_CALIB_VALID_MASK (GENMASK(3, 2) | BIT(7)) + +#define TSENSOR_CALIB_OFFSET 1 +#define TSENSOR_CALIB_SHIFT 4 + +/** + * struct amlogic_thermal_soc_calib_data + * @A, B, m, n: calibration parameters + * This structure is required for configuration of amlogic thermal driver. + */ +struct amlogic_thermal_soc_calib_data { + int A; + int B; + int m; + int n; +}; + +/** + * struct amlogic_thermal_data + * @u_efuse_off: register offset to read fused calibration value + * @soc: calibration parameters structure pointer + * @regmap_config: regmap config for the device + * This structure is required for configuration of amlogic thermal driver. + */ +struct amlogic_thermal_data { + int u_efuse_off; + const struct amlogic_thermal_soc_calib_data *calibration_parameters; + const struct regmap_config *regmap_config; +}; + +struct amlogic_thermal { + struct platform_device *pdev; + const struct amlogic_thermal_data *data; + struct regmap *regmap; + struct regmap *sec_ao_map; + struct clk *clk; + struct thermal_zone_device *tzd; + u32 trim_info; +}; + +/* + * Calculate a temperature value from a temperature code. + * The unit of the temperature is degree milliCelsius. + */ +static int amlogic_thermal_code_to_millicelsius(struct amlogic_thermal *pdata, + int temp_code) +{ + const struct amlogic_thermal_soc_calib_data *param = + pdata->data->calibration_parameters; + int temp; + s64 factor, Uptat, uefuse; + + uefuse = pdata->trim_info & TSENSOR_TRIM_SIGN_MASK ? + ~(pdata->trim_info & TSENSOR_TRIM_TEMP_MASK) + 1 : + (pdata->trim_info & TSENSOR_TRIM_TEMP_MASK); + + factor = param->n * temp_code; + factor = div_s64(factor, 100); + + Uptat = temp_code * param->m; + Uptat = div_s64(Uptat, 100); + Uptat = Uptat * BIT(16); + Uptat = div_s64(Uptat, BIT(16) + factor); + + temp = (Uptat + uefuse) * param->A; + temp = div_s64(temp, BIT(16)); + temp = (temp - param->B) * 100; + + return temp; +} + +static int amlogic_thermal_initialize(struct amlogic_thermal *pdata) +{ + int ret = 0; + int ver; + + regmap_read(pdata->sec_ao_map, pdata->data->u_efuse_off, + &pdata->trim_info); + + ver = TSENSOR_TRIM_VERSION(pdata->trim_info); + + if ((ver & TSENSOR_TRIM_CALIB_VALID_MASK) == 0) { + ret = -EINVAL; + dev_err(&pdata->pdev->dev, + "tsensor thermal calibration not supported: 0x%x!\n", + ver); + } + + return ret; +} + +static int amlogic_thermal_enable(struct amlogic_thermal *data) +{ + int ret; + + ret = clk_prepare_enable(data->clk); + if (ret) + return ret; + + regmap_update_bits(data->regmap, TSENSOR_CFG_REG1, + TSENSOR_CFG_REG1_ENABLE, TSENSOR_CFG_REG1_ENABLE); + + return 0; +} + +static int amlogic_thermal_disable(struct amlogic_thermal *data) +{ + regmap_update_bits(data->regmap, TSENSOR_CFG_REG1, + TSENSOR_CFG_REG1_ENABLE, 0); + clk_disable_unprepare(data->clk); + + return 0; +} + +static int amlogic_thermal_get_temp(void *data, int *temp) +{ + unsigned int tval; + struct amlogic_thermal *pdata = data; + + if (!data) + return -EINVAL; + + regmap_read(pdata->regmap, TSENSOR_STAT0, &tval); + *temp = + amlogic_thermal_code_to_millicelsius(pdata, + tval & TSENSOR_READ_TEMP_MASK); + + return 0; +} + +static const struct thermal_zone_of_device_ops amlogic_thermal_ops = { + .get_temp = amlogic_thermal_get_temp, +}; + +static const struct regmap_config amlogic_thermal_regmap_config_g12a = { + .reg_bits = 8, + .val_bits = 32, + .reg_stride = 4, + .max_register = TSENSOR_STAT9, +}; + +static const struct amlogic_thermal_soc_calib_data amlogic_thermal_g12a = { + .A = 9411, + .B = 3159, + .m = 424, + .n = 324, +}; + +static const struct amlogic_thermal_data amlogic_thermal_g12a_cpu_param = { + .u_efuse_off = 0x128, + .calibration_parameters = &amlogic_thermal_g12a, + .regmap_config = &amlogic_thermal_regmap_config_g12a, +}; + +static const struct amlogic_thermal_data amlogic_thermal_g12a_ddr_param = { + .u_efuse_off = 0xf0, + .calibration_parameters = &amlogic_thermal_g12a, + .regmap_config = &amlogic_thermal_regmap_config_g12a, +}; + +static const struct of_device_id of_amlogic_thermal_match[] = { + { + .compatible = "amlogic,g12a-ddr-thermal", + .data = &amlogic_thermal_g12a_ddr_param, + }, + { + .compatible = "amlogic,g12a-cpu-thermal", + .data = &amlogic_thermal_g12a_cpu_param, + }, + { /* sentinel */ } +}; +MODULE_DEVICE_TABLE(of, of_amlogic_thermal_match); + +static int amlogic_thermal_probe(struct platform_device *pdev) +{ + struct amlogic_thermal *pdata; + struct device *dev = &pdev->dev; + struct resource *res; + void __iomem *base; + int ret; + + pdata = devm_kzalloc(dev, sizeof(*pdata), GFP_KERNEL); + if (!pdata) + return -ENOMEM; + + pdata->data = of_device_get_match_data(dev); + pdata->pdev = pdev; + platform_set_drvdata(pdev, pdata); + + res = platform_get_resource(pdev, IORESOURCE_MEM, 0); + base = devm_ioremap_resource(dev, res); + if (IS_ERR(base)) { + dev_err(dev, "failed to get io address\n"); + return PTR_ERR(base); + } + + pdata->regmap = devm_regmap_init_mmio(dev, base, + pdata->data->regmap_config); + if (IS_ERR(pdata->regmap)) + return PTR_ERR(pdata->regmap); + + pdata->clk = devm_clk_get(dev, NULL); + if (IS_ERR(pdata->clk)) { + if (PTR_ERR(pdata->clk) != -EPROBE_DEFER) + dev_err(dev, "failed to get clock\n"); + return PTR_ERR(pdata->clk); + } + + pdata->sec_ao_map = syscon_regmap_lookup_by_phandle + (pdev->dev.of_node, "amlogic,ao-secure"); + if (IS_ERR(pdata->sec_ao_map)) { + dev_err(dev, "syscon regmap lookup failed.\n"); + return PTR_ERR(pdata->sec_ao_map); + } + + pdata->tzd = devm_thermal_zone_of_sensor_register(&pdev->dev, + 0, + pdata, + &amlogic_thermal_ops); + if (IS_ERR(pdata->tzd)) { + ret = PTR_ERR(pdata->tzd); + dev_err(dev, "Failed to register tsensor: %d\n", ret); + return PTR_ERR(pdata->tzd); + } + + ret = amlogic_thermal_initialize(pdata); + if (ret) + return ret; + + ret = amlogic_thermal_enable(pdata); + + return ret; +} + +static int amlogic_thermal_remove(struct platform_device *pdev) +{ + struct amlogic_thermal *data = platform_get_drvdata(pdev); + + return amlogic_thermal_disable(data); +} + +static int __maybe_unused amlogic_thermal_suspend(struct device *dev) +{ + struct amlogic_thermal *data = dev_get_drvdata(dev); + + return amlogic_thermal_disable(data); +} + +static int __maybe_unused amlogic_thermal_resume(struct device *dev) +{ + struct amlogic_thermal *data = dev_get_drvdata(dev); + + return amlogic_thermal_enable(data); +} + +static SIMPLE_DEV_PM_OPS(amlogic_thermal_pm_ops, + amlogic_thermal_suspend, amlogic_thermal_resume); + +static struct platform_driver amlogic_thermal_driver = { + .driver = { + .name = "amlogic_thermal", + .pm = &amlogic_thermal_pm_ops, + .of_match_table = of_amlogic_thermal_match, + }, + .probe = amlogic_thermal_probe, + .remove = amlogic_thermal_remove, +}; + +module_platform_driver(amlogic_thermal_driver); + +MODULE_AUTHOR("Guillaume La Roque "); +MODULE_DESCRIPTION("Amlogic thermal driver"); +MODULE_LICENSE("GPL v2"); From patchwork Wed Aug 21 22:24:18 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Guillaume LA ROQUE X-Patchwork-Id: 11108239 X-Patchwork-Delegate: eduardo.valentin@ti.com Return-Path: Received: from mail.kernel.org (pdx-korg-mail-1.web.codeaurora.org [172.30.200.123]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id 699D0112C for ; Wed, 21 Aug 2019 22:24:48 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.kernel.org (Postfix) with ESMTP id 47205233A2 for ; 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Wed, 21 Aug 2019 15:24:26 -0700 (PDT) From: Guillaume La Roque To: rui.zhang@intel.com, edubezval@gmail.com, daniel.lezcano@linaro.org Cc: linux-pm@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-amlogic@lists.infradead.org Subject: [PATCH v4 3/6] arm64: dts: amlogic: g12: add temperature sensor Date: Thu, 22 Aug 2019 00:24:18 +0200 Message-Id: <20190821222421.30242-4-glaroque@baylibre.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20190821222421.30242-1-glaroque@baylibre.com> References: <20190821222421.30242-1-glaroque@baylibre.com> Sender: linux-pm-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-pm@vger.kernel.org Add cpu and ddr temperature sensors for G12 Socs Signed-off-by: Guillaume La Roque Reviewed-by: Martin Blumenstingl --- .../boot/dts/amlogic/meson-g12-common.dtsi | 20 +++++++++++++++++++ 1 file changed, 20 insertions(+) diff --git a/arch/arm64/boot/dts/amlogic/meson-g12-common.dtsi b/arch/arm64/boot/dts/amlogic/meson-g12-common.dtsi index 06e186ca41e3..ce13c7c2e454 100644 --- a/arch/arm64/boot/dts/amlogic/meson-g12-common.dtsi +++ b/arch/arm64/boot/dts/amlogic/meson-g12-common.dtsi @@ -1353,6 +1353,26 @@ }; }; + cpu_temp: temperature-sensor@34800 { + compatible = "amlogic,g12a-cpu-thermal", + "amlogic,g12a-thermal"; + reg = <0x0 0x34800 0x0 0x50>; + interrupts = ; + clocks = <&clkc CLKID_TS>; + #thermal-sensor-cells = <0>; + amlogic,ao-secure = <&sec_AO>; + }; + + ddr_temp: temperature-sensor@34c00 { + compatible = "amlogic,g12a-ddr-thermal", + "amlogic,g12a-thermal"; + reg = <0x0 0x34c00 0x0 0x50>; + interrupts = ; + clocks = <&clkc CLKID_TS>; + #thermal-sensor-cells = <0>; + amlogic,ao-secure = <&sec_AO>; + }; + usb2_phy0: phy@36000 { compatible = "amlogic,g12a-usb2-phy"; reg = <0x0 0x36000 0x0 0x2000>; From patchwork Wed Aug 21 22:24:19 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Guillaume LA ROQUE X-Patchwork-Id: 11108237 X-Patchwork-Delegate: eduardo.valentin@ti.com Return-Path: Received: from mail.kernel.org (pdx-korg-mail-1.web.codeaurora.org [172.30.200.123]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id C2D4D1813 for ; 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Wed, 21 Aug 2019 15:24:28 -0700 (PDT) Received: from localhost.localdomain ([2a01:cb1d:6e7:d500:82a9:347a:43f3:d2ca]) by smtp.gmail.com with ESMTPSA id f197sm3548549wme.22.2019.08.21.15.24.27 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 21 Aug 2019 15:24:27 -0700 (PDT) From: Guillaume La Roque To: rui.zhang@intel.com, edubezval@gmail.com, daniel.lezcano@linaro.org Cc: linux-pm@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-amlogic@lists.infradead.org Subject: [PATCH v4 4/6] arm64: dts: meson: sei510: Add minimal thermal zone Date: Thu, 22 Aug 2019 00:24:19 +0200 Message-Id: <20190821222421.30242-5-glaroque@baylibre.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20190821222421.30242-1-glaroque@baylibre.com> References: <20190821222421.30242-1-glaroque@baylibre.com> Sender: linux-pm-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-pm@vger.kernel.org Add minimal thermal zone for two temperature sensor One is located close to the DDR and the other one is located close to the PLLs (between the CPU and GPU) Signed-off-by: Guillaume La Roque Acked-by: Martin Blumenstingl --- .../boot/dts/amlogic/meson-g12a-sei510.dts | 70 +++++++++++++++++++ 1 file changed, 70 insertions(+) diff --git a/arch/arm64/boot/dts/amlogic/meson-g12a-sei510.dts b/arch/arm64/boot/dts/amlogic/meson-g12a-sei510.dts index c9fa23a56562..35d2ebbd6d4e 100644 --- a/arch/arm64/boot/dts/amlogic/meson-g12a-sei510.dts +++ b/arch/arm64/boot/dts/amlogic/meson-g12a-sei510.dts @@ -10,6 +10,7 @@ #include #include #include +#include / { compatible = "seirobotics,sei510", "amlogic,g12a"; @@ -33,6 +34,67 @@ ethernet0 = ðmac; }; + thermal-zones { + cpu-thermal { + polling-delay = <1000>; + polling-delay-passive = <100>; + thermal-sensors = <&cpu_temp>; + + trips { + cpu_hot: cpu-hot { + temperature = <85000>; /* millicelsius */ + hysteresis = <2000>; /* millicelsius */ + type = "hot"; + }; + + cpu_critical: cpu-critical { + temperature = <110000>; /* millicelsius */ + hysteresis = <2000>; /* millicelsius */ + type = "critical"; + }; + }; + + cooling-maps { + map0 { + trip = <&cpu_hot>; + cooling-device = <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&cpu1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&cpu2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&cpu3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; + }; + + map1 { + trip = <&cpu_critical>; + cooling-device = <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&cpu1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&cpu2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&cpu3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; + }; + }; + }; + + ddr-thermal { + polling-delay = <1000>; + polling-delay-passive = <100>; + thermal-sensors = <&ddr_temp>; + + trips { + ddr_critical: ddr-critical { + temperature = <110000>; /* millicelsius */ + hysteresis = <2000>; /* millicelsius */ + type = "critical"; + }; + }; + + cooling-maps { + map { + trip = <&ddr_critical>; + cooling-device = <&mali THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; + }; + }; + }; + }; + mono_dac: audio-codec-0 { compatible = "maxim,max98357a"; #sound-dai-cells = <0>; @@ -321,6 +383,7 @@ operating-points-v2 = <&cpu_opp_table>; clocks = <&clkc CLKID_CPU_CLK>; clock-latency = <50000>; + #cooling-cells = <2>; }; &cpu1 { @@ -328,6 +391,7 @@ operating-points-v2 = <&cpu_opp_table>; clocks = <&clkc CLKID_CPU_CLK>; clock-latency = <50000>; + #cooling-cells = <2>; }; &cpu2 { @@ -335,6 +399,7 @@ operating-points-v2 = <&cpu_opp_table>; clocks = <&clkc CLKID_CPU_CLK>; clock-latency = <50000>; + #cooling-cells = <2>; }; &cpu3 { @@ -342,6 +407,7 @@ operating-points-v2 = <&cpu_opp_table>; clocks = <&clkc CLKID_CPU_CLK>; clock-latency = <50000>; + #cooling-cells = <2>; }; &cvbs_vdac_port { @@ -368,6 +434,10 @@ status = "okay"; }; +&mali { + #cooling-cells = <2>; +}; + &hdmi_tx { status = "okay"; pinctrl-0 = <&hdmitx_hpd_pins>, <&hdmitx_ddc_pins>; From patchwork Wed Aug 21 22:24:20 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Guillaume LA ROQUE X-Patchwork-Id: 11108235 X-Patchwork-Delegate: eduardo.valentin@ti.com Return-Path: Received: from mail.kernel.org (pdx-korg-mail-1.web.codeaurora.org [172.30.200.123]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id B28261813 for ; Wed, 21 Aug 2019 22:24:44 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.kernel.org (Postfix) with ESMTP id 873F3233A1 for ; Wed, 21 Aug 2019 22:24:44 +0000 (UTC) Authentication-Results: mail.kernel.org; dkim=pass (2048-bit key) header.d=baylibre-com.20150623.gappssmtp.com header.i=@baylibre-com.20150623.gappssmtp.com header.b="JIROksQB" Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1731158AbfHUWYn (ORCPT ); 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Wed, 21 Aug 2019 15:24:28 -0700 (PDT) From: Guillaume La Roque To: rui.zhang@intel.com, edubezval@gmail.com, daniel.lezcano@linaro.org Cc: linux-pm@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-amlogic@lists.infradead.org Subject: [PATCH v4 5/6] arm64: dts: amlogic: odroid-n2: add minimal thermal zone Date: Thu, 22 Aug 2019 00:24:20 +0200 Message-Id: <20190821222421.30242-6-glaroque@baylibre.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20190821222421.30242-1-glaroque@baylibre.com> References: <20190821222421.30242-1-glaroque@baylibre.com> Sender: linux-pm-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-pm@vger.kernel.org Add minimal thermal zone for two temperature sensor One is located close to the DDR and the other one is located close to the PLLs (between the CPU and GPU) Signed-off-by: Guillaume La Roque Acked-by: Martin Blumenstingl --- .../boot/dts/amlogic/meson-g12b-odroid-n2.dts | 76 +++++++++++++++++++ 1 file changed, 76 insertions(+) diff --git a/arch/arm64/boot/dts/amlogic/meson-g12b-odroid-n2.dts b/arch/arm64/boot/dts/amlogic/meson-g12b-odroid-n2.dts index 777bfb938854..8d7c73bad4aa 100644 --- a/arch/arm64/boot/dts/amlogic/meson-g12b-odroid-n2.dts +++ b/arch/arm64/boot/dts/amlogic/meson-g12b-odroid-n2.dts @@ -10,6 +10,7 @@ #include #include #include +#include / { compatible = "hardkernel,odroid-n2", "amlogic,g12b"; @@ -20,6 +21,71 @@ ethernet0 = ðmac; }; + thermal-zones { + cpu-thermal { + polling-delay = <1000>; + polling-delay-passive = <100>; + thermal-sensors = <&cpu_temp>; + + trips { + cpu_hot: cpu-hot { + temperature = <85000>; /* millicelsius */ + hysteresis = <2000>; /* millicelsius */ + type = "hot"; + }; + + cpu_critical: cpu-critical { + temperature = <110000>; /* millicelsius */ + hysteresis = <2000>; /* millicelsius */ + type = "critical"; + }; + }; + + cooling-maps { + map0 { + trip = <&cpu_hot>; + cooling-device = <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&cpu1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&cpu100 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&cpu101 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&cpu102 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&cpu103 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; + }; + + map1 { + trip = <&cpu_critical>; + cooling-device = <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&cpu1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&cpu100 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&cpu101 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&cpu102 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&cpu103 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; + }; + }; + }; + + ddr-thermal { + polling-delay = <1000>; + polling-delay-passive = <100>; + thermal-sensors = <&ddr_temp>; + + trips { + ddr_critical: ddr-critical { + temperature = <110000>; /* millicelsius */ + hysteresis = <2000>; /* millicelsius */ + type = "critical"; + }; + }; + + cooling-maps { + map { + trip = <&ddr_critical>; + cooling-device = <&mali THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; + }; + }; + }; + }; + chosen { stdout-path = "serial0:115200n8"; }; @@ -289,6 +355,7 @@ operating-points-v2 = <&cpu_opp_table_0>; clocks = <&clkc CLKID_CPU_CLK>; clock-latency = <50000>; + #cooling-cells = <2>; }; &cpu1 { @@ -296,6 +363,7 @@ operating-points-v2 = <&cpu_opp_table_0>; clocks = <&clkc CLKID_CPU_CLK>; clock-latency = <50000>; + #cooling-cells = <2>; }; &cpu100 { @@ -303,6 +371,7 @@ operating-points-v2 = <&cpub_opp_table_1>; clocks = <&clkc CLKID_CPUB_CLK>; clock-latency = <50000>; + #cooling-cells = <2>; }; &cpu101 { @@ -310,6 +379,7 @@ operating-points-v2 = <&cpub_opp_table_1>; clocks = <&clkc CLKID_CPUB_CLK>; clock-latency = <50000>; + #cooling-cells = <2>; }; &cpu102 { @@ -317,6 +387,7 @@ operating-points-v2 = <&cpub_opp_table_1>; clocks = <&clkc CLKID_CPUB_CLK>; clock-latency = <50000>; + #cooling-cells = <2>; }; &cpu103 { @@ -324,6 +395,7 @@ operating-points-v2 = <&cpub_opp_table_1>; clocks = <&clkc CLKID_CPUB_CLK>; clock-latency = <50000>; + #cooling-cells = <2>; }; &ext_mdio { @@ -378,6 +450,10 @@ }; }; +&mali { + #cooling-cells = <2>; +}; + &hdmi_tx { status = "okay"; pinctrl-0 = <&hdmitx_hpd_pins>, <&hdmitx_ddc_pins>; From patchwork Wed Aug 21 22:24:21 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Guillaume LA ROQUE X-Patchwork-Id: 11108229 X-Patchwork-Delegate: eduardo.valentin@ti.com Return-Path: Received: from mail.kernel.org (pdx-korg-mail-1.web.codeaurora.org [172.30.200.123]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id F36CB1813 for ; Wed, 21 Aug 2019 22:24:35 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.kernel.org (Postfix) with ESMTP id D0E4C2339F for ; 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Wed, 21 Aug 2019 15:24:30 -0700 (PDT) From: Guillaume La Roque To: rui.zhang@intel.com, edubezval@gmail.com, daniel.lezcano@linaro.org Cc: linux-pm@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-amlogic@lists.infradead.org Subject: [PATCH v4 6/6] MAINTAINERS: add entry for Amlogic Thermal driver Date: Thu, 22 Aug 2019 00:24:21 +0200 Message-Id: <20190821222421.30242-7-glaroque@baylibre.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20190821222421.30242-1-glaroque@baylibre.com> References: <20190821222421.30242-1-glaroque@baylibre.com> Sender: linux-pm-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-pm@vger.kernel.org Add myself as maintainer for Amlogic Thermal driver. Signed-off-by: Guillaume La Roque Reviewed-by: Neil Armstrong --- MAINTAINERS | 9 +++++++++ 1 file changed, 9 insertions(+) diff --git a/MAINTAINERS b/MAINTAINERS index fb2b12f75c37..299f27d11058 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -15910,6 +15910,15 @@ F: Documentation/driver-api/thermal/cpu-cooling-api.rst F: drivers/thermal/cpu_cooling.c F: include/linux/cpu_cooling.h +THERMAL DRIVER FOR AMLOGIC SOCS +M: Guillaume La Roque +L: linux-pm@vger.kernel.org +L: linux-amlogic@lists.infradead.org +W: http://linux-meson.com/ +S: Supported +F: drivers/thermal/amlogic_thermal.c +F: Documentation/devicetree/bindings/thermal/amlogic,thermal.yaml + THINKPAD ACPI EXTRAS DRIVER M: Henrique de Moraes Holschuh L: ibm-acpi-devel@lists.sourceforge.net