From patchwork Fri Aug 23 12:56:14 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Peter Ujfalusi X-Patchwork-Id: 11111635 Return-Path: Received: from mail.kernel.org (pdx-korg-mail-1.web.codeaurora.org [172.30.200.123]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id 7835814DB for ; Fri, 23 Aug 2019 12:56:42 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.kernel.org (Postfix) with ESMTP id 568F723405 for ; Fri, 23 Aug 2019 12:56:42 +0000 (UTC) Authentication-Results: mail.kernel.org; dkim=pass (1024-bit key) header.d=ti.com header.i=@ti.com header.b="pIDS9PRE" Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S2389846AbfHWM4K (ORCPT ); Fri, 23 Aug 2019 08:56:10 -0400 Received: from fllv0015.ext.ti.com ([198.47.19.141]:58864 "EHLO fllv0015.ext.ti.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1726197AbfHWM4K (ORCPT ); Fri, 23 Aug 2019 08:56:10 -0400 Received: from fllv0035.itg.ti.com ([10.64.41.0]) by fllv0015.ext.ti.com (8.15.2/8.15.2) with ESMTP id x7NCu3Aq103808; Fri, 23 Aug 2019 07:56:04 -0500 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=ti.com; s=ti-com-17Q1; t=1566564964; bh=GXDyiG/PPmHFuQlZYe5lHx0rEDkmlewlyaVELKgzcow=; h=From:To:CC:Subject:Date:In-Reply-To:References; b=pIDS9PREJWRUQO5xoR+AfT1NASJB+hkayTXAdV1jBQCPqU3tkY0dDBGbUzRMXZ0T5 tF7tRVsnk4OYRTuqBr/fbPZ2LyyUgAHGq/RcWAgy+LsTfCag5yYuSqZfahuBKpmULq K5oZvidNkaKv92JyAnBiyvKtG9pmOD57EQkAJnt0= Received: from DLEE100.ent.ti.com (dlee100.ent.ti.com [157.170.170.30]) by fllv0035.itg.ti.com (8.15.2/8.15.2) with ESMTPS id x7NCu3UV015095 (version=TLSv1.2 cipher=AES256-GCM-SHA384 bits=256 verify=FAIL); Fri, 23 Aug 2019 07:56:03 -0500 Received: from DLEE107.ent.ti.com (157.170.170.37) by DLEE100.ent.ti.com (157.170.170.30) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.1713.5; Fri, 23 Aug 2019 07:56:03 -0500 Received: from lelv0327.itg.ti.com (10.180.67.183) by DLEE107.ent.ti.com (157.170.170.37) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.1713.5 via Frontend Transport; Fri, 23 Aug 2019 07:56:03 -0500 Received: from feketebors.ti.com (ileax41-snat.itg.ti.com [10.172.224.153]) by lelv0327.itg.ti.com (8.15.2/8.15.2) with ESMTP id x7NCtwkf092319; Fri, 23 Aug 2019 07:56:01 -0500 From: Peter Ujfalusi To: , CC: , , , , , Subject: [PATCH 1/5] dmaengine: ti: edma: Do not reset reserved paRAM slots Date: Fri, 23 Aug 2019 15:56:14 +0300 Message-ID: <20190823125618.8133-2-peter.ujfalusi@ti.com> X-Mailer: git-send-email 2.23.0 In-Reply-To: <20190823125618.8133-1-peter.ujfalusi@ti.com> References: <20190823125618.8133-1-peter.ujfalusi@ti.com> MIME-Version: 1.0 X-EXCLAIMER-MD-CONFIG: e1e8a2fd-e40a-4ac6-ac9b-f7e9cc9ee180 Sender: dmaengine-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: dmaengine@vger.kernel.org Skip resetting paRAM slots marked as reserved as they might be used by other cores. Signed-off-by: Peter Ujfalusi --- drivers/dma/ti/edma.c | 9 ++++++--- 1 file changed, 6 insertions(+), 3 deletions(-) diff --git a/drivers/dma/ti/edma.c b/drivers/dma/ti/edma.c index 54895112ba59..1aae95cc0d4b 100644 --- a/drivers/dma/ti/edma.c +++ b/drivers/dma/ti/edma.c @@ -2338,9 +2338,6 @@ static int edma_probe(struct platform_device *pdev) ecc->default_queue = info->default_queue; - for (i = 0; i < ecc->num_slots; i++) - edma_write_slot(ecc, i, &dummy_paramset); - if (info->rsv) { /* Set the reserved slots in inuse list */ rsv_slots = info->rsv->rsv_slots; @@ -2353,6 +2350,12 @@ static int edma_probe(struct platform_device *pdev) } } + for (i = 0; i < ecc->num_slots; i++) { + /* Reset only unused - not reserved - paRAM slots */ + if (!test_bit(i, ecc->slot_inuse)) + edma_write_slot(ecc, i, &dummy_paramset); + } + /* Clear the xbar mapped channels in unused list */ xbar_chans = info->xbar_chans; if (xbar_chans) { From patchwork Fri Aug 23 12:56:15 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Peter Ujfalusi X-Patchwork-Id: 11111629 Return-Path: Received: from mail.kernel.org (pdx-korg-mail-1.web.codeaurora.org [172.30.200.123]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id 9E92914DE for ; Fri, 23 Aug 2019 12:56:39 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.kernel.org (Postfix) with ESMTP id 7C777233A2 for ; Fri, 23 Aug 2019 12:56:39 +0000 (UTC) Authentication-Results: mail.kernel.org; dkim=pass (1024-bit key) header.d=ti.com header.i=@ti.com header.b="byBQEq30" Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S2394982AbfHWM4M (ORCPT ); Fri, 23 Aug 2019 08:56:12 -0400 Received: from fllv0015.ext.ti.com ([198.47.19.141]:58866 "EHLO fllv0015.ext.ti.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1726197AbfHWM4L (ORCPT ); Fri, 23 Aug 2019 08:56:11 -0400 Received: from lelv0266.itg.ti.com ([10.180.67.225]) by fllv0015.ext.ti.com (8.15.2/8.15.2) with ESMTP id x7NCu6uB103832; Fri, 23 Aug 2019 07:56:06 -0500 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=ti.com; s=ti-com-17Q1; t=1566564966; bh=z7aNVn0YYauCti4+ZL7WkTdhJclZFoX05/eUquPIZnU=; h=From:To:CC:Subject:Date:In-Reply-To:References; b=byBQEq30ILKRQAB4n4ESMgjjmPpVKcmVZoaZtDu7Sv1yotDwZAmksKVMSJcEbfaba /PgiYi0KmJ6aQCNtQ9iDq9hA0JgT9fpdLX94yMT/ItaNQbWhZ2AaXe1zgnPrG7R6oD qwvMwBOCSOEYpUQcw+ox0zqUOUfCi1X5+rs27kdA= Received: from DFLE103.ent.ti.com (dfle103.ent.ti.com [10.64.6.24]) by lelv0266.itg.ti.com (8.15.2/8.15.2) with ESMTPS id x7NCu6Em080831 (version=TLSv1.2 cipher=AES256-GCM-SHA384 bits=256 verify=FAIL); Fri, 23 Aug 2019 07:56:06 -0500 Received: from DFLE108.ent.ti.com (10.64.6.29) by DFLE103.ent.ti.com (10.64.6.24) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.1713.5; Fri, 23 Aug 2019 07:56:05 -0500 Received: from lelv0327.itg.ti.com (10.180.67.183) by DFLE108.ent.ti.com (10.64.6.29) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.1713.5 via Frontend Transport; Fri, 23 Aug 2019 07:56:06 -0500 Received: from feketebors.ti.com (ileax41-snat.itg.ti.com [10.172.224.153]) by lelv0327.itg.ti.com (8.15.2/8.15.2) with ESMTP id x7NCtwkg092319; Fri, 23 Aug 2019 07:56:03 -0500 From: Peter Ujfalusi To: , CC: , , , , , Subject: [PATCH 2/5] dmaengine: ti: edma: Only reset region0 access registers Date: Fri, 23 Aug 2019 15:56:15 +0300 Message-ID: <20190823125618.8133-3-peter.ujfalusi@ti.com> X-Mailer: git-send-email 2.23.0 In-Reply-To: <20190823125618.8133-1-peter.ujfalusi@ti.com> References: <20190823125618.8133-1-peter.ujfalusi@ti.com> MIME-Version: 1.0 X-EXCLAIMER-MD-CONFIG: e1e8a2fd-e40a-4ac6-ac9b-f7e9cc9ee180 Sender: dmaengine-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: dmaengine@vger.kernel.org Region0 is used by Linux, do not reset other registers controlling access for other shadow regions. Signed-off-by: Peter Ujfalusi --- drivers/dma/ti/edma.c | 9 ++++----- 1 file changed, 4 insertions(+), 5 deletions(-) diff --git a/drivers/dma/ti/edma.c b/drivers/dma/ti/edma.c index 1aae95cc0d4b..87450431f336 100644 --- a/drivers/dma/ti/edma.c +++ b/drivers/dma/ti/edma.c @@ -2434,11 +2434,10 @@ static int edma_probe(struct platform_device *pdev) edma_assign_priority_to_queue(ecc, queue_priority_mapping[i][0], queue_priority_mapping[i][1]); - for (i = 0; i < ecc->num_region; i++) { - edma_write_array2(ecc, EDMA_DRAE, i, 0, 0x0); - edma_write_array2(ecc, EDMA_DRAE, i, 1, 0x0); - edma_write_array(ecc, EDMA_QRAE, i, 0x0); - } + edma_write_array2(ecc, EDMA_DRAE, 0, 0, 0x0); + edma_write_array2(ecc, EDMA_DRAE, 0, 1, 0x0); + edma_write_array(ecc, EDMA_QRAE, 0, 0x0); + ecc->info = info; /* Init the dma device and channels */ From patchwork Fri Aug 23 12:56:16 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Peter Ujfalusi X-Patchwork-Id: 11111611 Return-Path: Received: from mail.kernel.org (pdx-korg-mail-1.web.codeaurora.org [172.30.200.123]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id 8188014DB for ; Fri, 23 Aug 2019 12:56:16 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.kernel.org (Postfix) with ESMTP id 603BD2339D for ; Fri, 23 Aug 2019 12:56:16 +0000 (UTC) Authentication-Results: mail.kernel.org; dkim=pass (1024-bit key) header.d=ti.com header.i=@ti.com header.b="ma39mbRl" Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1726197AbfHWM4P (ORCPT ); Fri, 23 Aug 2019 08:56:15 -0400 Received: from fllv0016.ext.ti.com ([198.47.19.142]:46416 "EHLO fllv0016.ext.ti.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S2394996AbfHWM4O (ORCPT ); Fri, 23 Aug 2019 08:56:14 -0400 Received: from lelv0266.itg.ti.com ([10.180.67.225]) by fllv0016.ext.ti.com (8.15.2/8.15.2) with ESMTP id x7NCu8hU073766; Fri, 23 Aug 2019 07:56:08 -0500 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=ti.com; s=ti-com-17Q1; t=1566564968; bh=4p8x7v8EaQ++SIjoJmr4MK1Cg7JXqSOfe+y4BO9Mvv8=; h=From:To:CC:Subject:Date:In-Reply-To:References; b=ma39mbRlT65De5gN1ZfuqkKvk3VI5qahfCk9z+mz41wwyAKyaEIXAwShQhP/YTkxO cSVx5vr5PFc4cSizYXixue33OmXD7hPyD2QqY44YC4hTjM9+12UhG9eVETFAX+hO44 SzPJ0SoUoGucEYxknHIDKx8JqmApUJ4OVeWPCtf8= Received: from DFLE104.ent.ti.com (dfle104.ent.ti.com [10.64.6.25]) by lelv0266.itg.ti.com (8.15.2/8.15.2) with ESMTPS id x7NCu8uG080903 (version=TLSv1.2 cipher=AES256-GCM-SHA384 bits=256 verify=FAIL); Fri, 23 Aug 2019 07:56:08 -0500 Received: from DFLE103.ent.ti.com (10.64.6.24) by DFLE104.ent.ti.com (10.64.6.25) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.1713.5; Fri, 23 Aug 2019 07:56:08 -0500 Received: from lelv0327.itg.ti.com (10.180.67.183) by DFLE103.ent.ti.com (10.64.6.24) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.1713.5 via Frontend Transport; Fri, 23 Aug 2019 07:56:07 -0500 Received: from feketebors.ti.com (ileax41-snat.itg.ti.com [10.172.224.153]) by lelv0327.itg.ti.com (8.15.2/8.15.2) with ESMTP id x7NCtwkh092319; Fri, 23 Aug 2019 07:56:06 -0500 From: Peter Ujfalusi To: , CC: , , , , , Subject: [PATCH 3/5] dmaengine: ti: edma: Use bitmap_set() instead of open coded edma_set_bits() Date: Fri, 23 Aug 2019 15:56:16 +0300 Message-ID: <20190823125618.8133-4-peter.ujfalusi@ti.com> X-Mailer: git-send-email 2.23.0 In-Reply-To: <20190823125618.8133-1-peter.ujfalusi@ti.com> References: <20190823125618.8133-1-peter.ujfalusi@ti.com> MIME-Version: 1.0 X-EXCLAIMER-MD-CONFIG: e1e8a2fd-e40a-4ac6-ac9b-f7e9cc9ee180 Sender: dmaengine-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: dmaengine@vger.kernel.org bitmap_set() is the standard way of setting an area in the bitfield. Signed-off-by: Peter Ujfalusi --- drivers/dma/ti/edma.c | 17 +++++------------ 1 file changed, 5 insertions(+), 12 deletions(-) diff --git a/drivers/dma/ti/edma.c b/drivers/dma/ti/edma.c index 87450431f336..ba7c4f07fcd6 100644 --- a/drivers/dma/ti/edma.c +++ b/drivers/dma/ti/edma.c @@ -15,6 +15,7 @@ #include #include +#include #include #include #include @@ -423,12 +424,6 @@ static inline void edma_param_or(struct edma_cc *ecc, int offset, int param_no, edma_or(ecc, EDMA_PARM + offset + (param_no << 5), or); } -static inline void edma_set_bits(int offset, int len, unsigned long *p) -{ - for (; len > 0; len--) - set_bit(offset + (len - 1), p); -} - static void edma_assign_priority_to_queue(struct edma_cc *ecc, int queue_no, int priority) { @@ -2254,7 +2249,7 @@ static int edma_probe(struct platform_device *pdev) { struct edma_soc_info *info = pdev->dev.platform_data; s8 (*queue_priority_mapping)[2]; - int i, off, ln; + int i, off; const s16 (*rsv_slots)[2]; const s16 (*xbar_chans)[2]; int irq; @@ -2342,11 +2337,9 @@ static int edma_probe(struct platform_device *pdev) /* Set the reserved slots in inuse list */ rsv_slots = info->rsv->rsv_slots; if (rsv_slots) { - for (i = 0; rsv_slots[i][0] != -1; i++) { - off = rsv_slots[i][0]; - ln = rsv_slots[i][1]; - edma_set_bits(off, ln, ecc->slot_inuse); - } + for (i = 0; rsv_slots[i][0] != -1; i++) + bitmap_set(ecc->slot_inuse, rsv_slots[i][0], + rsv_slots[i][1]); } } From patchwork Fri Aug 23 12:56:17 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Peter Ujfalusi X-Patchwork-Id: 11111619 Return-Path: Received: from mail.kernel.org (pdx-korg-mail-1.web.codeaurora.org [172.30.200.123]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id 89BB7112C for ; Fri, 23 Aug 2019 12:56:28 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.kernel.org (Postfix) with ESMTP id 6869923406 for ; Fri, 23 Aug 2019 12:56:28 +0000 (UTC) Authentication-Results: mail.kernel.org; dkim=pass (1024-bit key) header.d=ti.com header.i=@ti.com header.b="xj/QnMIM" Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S2395045AbfHWM41 (ORCPT ); Fri, 23 Aug 2019 08:56:27 -0400 Received: from fllv0015.ext.ti.com ([198.47.19.141]:58904 "EHLO fllv0015.ext.ti.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S2395018AbfHWM40 (ORCPT ); Fri, 23 Aug 2019 08:56:26 -0400 Received: from fllv0034.itg.ti.com ([10.64.40.246]) by fllv0015.ext.ti.com (8.15.2/8.15.2) with ESMTP id x7NCuMxp103966; Fri, 23 Aug 2019 07:56:22 -0500 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=ti.com; s=ti-com-17Q1; t=1566564982; bh=j4TqG6chto4nwAxIP2tkUry0a7Nx+tqpySHSQ8Tzdn4=; h=From:To:CC:Subject:Date:In-Reply-To:References; b=xj/QnMIMuz/G6lYM9K3Z6SF5gzH3wKmEwidvHzuoPr1dmPCsuL9uTFe4UxAZ1pCIW PB3n+SJ2NjWyUmkin4yOE2oGALZvQC/RqMWs8ruxJTWyDJs++sKLpreegQ08f62g08 79e+1t3RnndM2JSCCcgh6PxG3uTkMqArQcSiomUw= Received: from DFLE100.ent.ti.com (dfle100.ent.ti.com [10.64.6.21]) by fllv0034.itg.ti.com (8.15.2/8.15.2) with ESMTPS id x7NCuLhe016495 (version=TLSv1.2 cipher=AES256-GCM-SHA384 bits=256 verify=FAIL); Fri, 23 Aug 2019 07:56:22 -0500 Received: from DFLE111.ent.ti.com (10.64.6.32) by DFLE100.ent.ti.com (10.64.6.21) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.1713.5; Fri, 23 Aug 2019 07:56:10 -0500 Received: from lelv0327.itg.ti.com (10.180.67.183) by DFLE111.ent.ti.com (10.64.6.32) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.1713.5 via Frontend Transport; Fri, 23 Aug 2019 07:56:10 -0500 Received: from feketebors.ti.com (ileax41-snat.itg.ti.com [10.172.224.153]) by lelv0327.itg.ti.com (8.15.2/8.15.2) with ESMTP id x7NCtwki092319; Fri, 23 Aug 2019 07:56:08 -0500 From: Peter Ujfalusi To: , CC: , , , , , Subject: [PATCH 4/5] dt-bindings: dma: ti-edma: Add option for reserved channel ranges Date: Fri, 23 Aug 2019 15:56:17 +0300 Message-ID: <20190823125618.8133-5-peter.ujfalusi@ti.com> X-Mailer: git-send-email 2.23.0 In-Reply-To: <20190823125618.8133-1-peter.ujfalusi@ti.com> References: <20190823125618.8133-1-peter.ujfalusi@ti.com> MIME-Version: 1.0 X-EXCLAIMER-MD-CONFIG: e1e8a2fd-e40a-4ac6-ac9b-f7e9cc9ee180 Sender: dmaengine-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: dmaengine@vger.kernel.org Similarly to paRAM slots, channels can be used by other cores. Add optional property to configure the reserved channel ranges. Signed-off-by: Peter Ujfalusi --- Documentation/devicetree/bindings/dma/ti-edma.txt | 5 +++++ 1 file changed, 5 insertions(+) diff --git a/Documentation/devicetree/bindings/dma/ti-edma.txt b/Documentation/devicetree/bindings/dma/ti-edma.txt index 4bbc94d829c8..1198682ada99 100644 --- a/Documentation/devicetree/bindings/dma/ti-edma.txt +++ b/Documentation/devicetree/bindings/dma/ti-edma.txt @@ -42,6 +42,9 @@ Optional properties: - ti,edma-reserved-slot-ranges: PaRAM slot ranges which should not be used by the driver, they are allocated to be used by for example the DSP. See example. +- ti,edma-reserved-chan-ranges: channel ranges which should not be used by + the driver, they are allocated to be used by for example the + DSP. See example. ------------------------------------------------------------------------------ eDMA3 Transfer Controller @@ -91,6 +94,8 @@ edma: edma@49000000 { ti,edma-memcpy-channels = <20 21>; /* The following PaRAM slots are reserved: 35-44 and 100-109 */ ti,edma-reserved-slot-ranges = <35 10>, <100 10>; + /* The following channels are reserved: 35-44 */ + ti,edma-reserved-chan-ranges = <35 10>; }; edma_tptc0: tptc@49800000 { From patchwork Fri Aug 23 12:56:18 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Peter Ujfalusi X-Patchwork-Id: 11111617 Return-Path: Received: from mail.kernel.org (pdx-korg-mail-1.web.codeaurora.org [172.30.200.123]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id A6EE0112C for ; Fri, 23 Aug 2019 12:56:21 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.kernel.org (Postfix) with ESMTP id 824C922CEC for ; Fri, 23 Aug 2019 12:56:21 +0000 (UTC) Authentication-Results: mail.kernel.org; dkim=pass (1024-bit key) header.d=ti.com header.i=@ti.com header.b="JkuBIF0K" Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S2395028AbfHWM4T (ORCPT ); Fri, 23 Aug 2019 08:56:19 -0400 Received: from fllv0016.ext.ti.com ([198.47.19.142]:46462 "EHLO fllv0016.ext.ti.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S2395018AbfHWM4T (ORCPT ); Fri, 23 Aug 2019 08:56:19 -0400 Received: from fllv0034.itg.ti.com ([10.64.40.246]) by fllv0016.ext.ti.com (8.15.2/8.15.2) with ESMTP id x7NCuDVd073814; Fri, 23 Aug 2019 07:56:13 -0500 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=ti.com; s=ti-com-17Q1; t=1566564973; bh=YzETJQzcjwwuCGbcFqt2yh0/B3OCbpsu/i5Eo/6kFzk=; h=From:To:CC:Subject:Date:In-Reply-To:References; b=JkuBIF0K21oaMUR8d4+RXAoDtsuQXZqzc6i3dIwsbEhUDPS7DZt+TnETrJpJa1yCf kfhdUnbZSGLN2wiozBiLopS9lMqouL4aWI1oix0nLbS0ZbdDLk2bM7DzdNyPL0k0Zo yU/YDVQIHcQLLpGNmMP7pdHcSD9scf6PKd3icUK8= Received: from DLEE101.ent.ti.com (dlee101.ent.ti.com [157.170.170.31]) by fllv0034.itg.ti.com (8.15.2/8.15.2) with ESMTPS id x7NCuDFa016228 (version=TLSv1.2 cipher=AES256-GCM-SHA384 bits=256 verify=FAIL); Fri, 23 Aug 2019 07:56:13 -0500 Received: from DLEE103.ent.ti.com (157.170.170.33) by DLEE101.ent.ti.com (157.170.170.31) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.1713.5; Fri, 23 Aug 2019 07:56:12 -0500 Received: from lelv0327.itg.ti.com (10.180.67.183) by DLEE103.ent.ti.com (157.170.170.33) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.1713.5 via Frontend Transport; Fri, 23 Aug 2019 07:56:12 -0500 Received: from feketebors.ti.com (ileax41-snat.itg.ti.com [10.172.224.153]) by lelv0327.itg.ti.com (8.15.2/8.15.2) with ESMTP id x7NCtwkj092319; Fri, 23 Aug 2019 07:56:10 -0500 From: Peter Ujfalusi To: , CC: , , , , , Subject: [PATCH 5/5] dmaengine: ti: edma: Add support for handling reserved channels Date: Fri, 23 Aug 2019 15:56:18 +0300 Message-ID: <20190823125618.8133-6-peter.ujfalusi@ti.com> X-Mailer: git-send-email 2.23.0 In-Reply-To: <20190823125618.8133-1-peter.ujfalusi@ti.com> References: <20190823125618.8133-1-peter.ujfalusi@ti.com> MIME-Version: 1.0 X-EXCLAIMER-MD-CONFIG: e1e8a2fd-e40a-4ac6-ac9b-f7e9cc9ee180 Sender: dmaengine-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: dmaengine@vger.kernel.org Like paRAM slots, channels could be used by other cores and in this case we need to make sure that the driver do not alter these channels. Move the reserved slot/channel query from DT to a separate function for cleaner implementation. Signed-off-by: Peter Ujfalusi --- drivers/dma/ti/edma.c | 161 +++++++++++++++++++++++++++--------------- 1 file changed, 106 insertions(+), 55 deletions(-) diff --git a/drivers/dma/ti/edma.c b/drivers/dma/ti/edma.c index ba7c4f07fcd6..5201aeebf5c1 100644 --- a/drivers/dma/ti/edma.c +++ b/drivers/dma/ti/edma.c @@ -260,6 +260,9 @@ struct edma_cc { */ unsigned long *slot_inuse; + /* for tracking reserved channels used by DSP */ + unsigned long *reserved_chans; + struct dma_device dma_slave; struct dma_device *dma_memcpy; struct edma_chan *slave_chans; @@ -716,6 +719,12 @@ static int edma_alloc_channel(struct edma_chan *echan, struct edma_cc *ecc = echan->ecc; int channel = EDMA_CHAN_SLOT(echan->ch_num); + if (test_bit(echan->ch_num, ecc->reserved_chans)) { + dev_err(ecc->dev, "Channel%d is reserved, can not be used!\n", + echan->ch_num); + return -EINVAL; + } + /* ensure access through shadow region 0 */ edma_or_array2(ecc, EDMA_DRAE, 0, EDMA_REG_ARRAY_INDEX(channel), EDMA_CHANNEL_BIT(channel)); @@ -2096,6 +2105,76 @@ static int edma_xbar_event_map(struct device *dev, struct edma_soc_info *pdata, return 0; } +static struct edma_rsv_info *edma_get_reserved_ranges_dt(struct device *dev) +{ + static const char * const prop_names[] = { + "ti,edma-reserved-slot-ranges", + "ti,edma-reserved-chan-ranges" + }; + struct edma_rsv_info *rsv_info = NULL; + struct property *props[2]; + int sz[2], i, ret; + + for (i = 0; i < 2; i++) + props[i] = of_find_property(dev->of_node, prop_names[i], + &sz[i]); + + if (!props[0] && !props[1]) + return NULL; + + rsv_info = devm_kzalloc(dev, sizeof(*rsv_info), GFP_KERNEL); + if (!rsv_info) + return ERR_PTR(-ENOMEM); + + for (i = 0; i < 2; i++) { + u32 (*tmp)[2]; + s16 (*reserved)[2]; + size_t nelm; + int j; + + if (!props[i]) + continue; + + nelm = sz[i] / sizeof(*tmp); + if (!nelm) + continue; + + tmp = kcalloc(nelm, sizeof(*tmp), GFP_KERNEL); + if (!tmp) + return ERR_PTR(-ENOMEM); + + reserved = devm_kcalloc(dev, nelm + 1, sizeof(*reserved), + GFP_KERNEL); + if (!reserved) { + kfree(tmp); + return ERR_PTR(-ENOMEM); + } + + ret = of_property_read_u32_array(dev->of_node, prop_names[i], + (u32 *)tmp, nelm * 2); + if (ret) { + kfree(tmp); + return ERR_PTR(ret); + } + + for (j = 0; j < nelm; j++) { + reserved[j][0] = tmp[j][0]; + reserved[j][1] = tmp[j][1]; + } + reserved[nelm][0] = -1; + reserved[nelm][1] = -1; + + if (i == 0) + rsv_info->rsv_slots = (const s16 (*)[2])reserved; + else if (i == 1) + rsv_info->rsv_chans = (const s16 (*)[2])reserved; + + kfree(tmp); + } + + return rsv_info; +} + static struct edma_soc_info *edma_setup_info_from_dt(struct device *dev, bool legacy_mode) { @@ -2139,55 +2218,9 @@ static struct edma_soc_info *edma_setup_info_from_dt(struct device *dev, info->memcpy_channels = memcpy_ch; } - prop = of_find_property(dev->of_node, "ti,edma-reserved-slot-ranges", - &sz); - if (prop) { - const char pname[] = "ti,edma-reserved-slot-ranges"; - u32 (*tmp)[2]; - s16 (*rsv_slots)[2]; - size_t nelm = sz / sizeof(*tmp); - struct edma_rsv_info *rsv_info; - int i; - - if (!nelm) - return info; - - tmp = kcalloc(nelm, sizeof(*tmp), GFP_KERNEL); - if (!tmp) - return ERR_PTR(-ENOMEM); - - rsv_info = devm_kzalloc(dev, sizeof(*rsv_info), GFP_KERNEL); - if (!rsv_info) { - kfree(tmp); - return ERR_PTR(-ENOMEM); - } - - rsv_slots = devm_kcalloc(dev, nelm + 1, sizeof(*rsv_slots), - GFP_KERNEL); - if (!rsv_slots) { - kfree(tmp); - return ERR_PTR(-ENOMEM); - } - - ret = of_property_read_u32_array(dev->of_node, pname, - (u32 *)tmp, nelm * 2); - if (ret) { - kfree(tmp); - return ERR_PTR(ret); - } - - for (i = 0; i < nelm; i++) { - rsv_slots[i][0] = tmp[i][0]; - rsv_slots[i][1] = tmp[i][1]; - } - rsv_slots[nelm][0] = -1; - rsv_slots[nelm][1] = -1; - - info->rsv = rsv_info; - info->rsv->rsv_slots = (const s16 (*)[2])rsv_slots; - - kfree(tmp); - } + info->rsv = edma_get_reserved_ranges_dt(dev); + if (IS_ERR(info->rsv)) + return ERR_CAST(info->rsv); return info; } @@ -2250,7 +2283,7 @@ static int edma_probe(struct platform_device *pdev) struct edma_soc_info *info = pdev->dev.platform_data; s8 (*queue_priority_mapping)[2]; int i, off; - const s16 (*rsv_slots)[2]; + const s16 (*reserved)[2]; const s16 (*xbar_chans)[2]; int irq; char *irq_name; @@ -2331,15 +2364,29 @@ static int edma_probe(struct platform_device *pdev) if (!ecc->slot_inuse) return -ENOMEM; + ecc->reserved_chans = devm_kcalloc(dev, + BITS_TO_LONGS(ecc->num_channels), + sizeof(unsigned long), GFP_KERNEL); + if (!ecc->reserved_chans) + return -ENOMEM; + ecc->default_queue = info->default_queue; if (info->rsv) { /* Set the reserved slots in inuse list */ - rsv_slots = info->rsv->rsv_slots; - if (rsv_slots) { - for (i = 0; rsv_slots[i][0] != -1; i++) - bitmap_set(ecc->slot_inuse, rsv_slots[i][0], - rsv_slots[i][1]); + reserved = info->rsv->rsv_slots; + if (reserved) { + for (i = 0; reserved[i][0] != -1; i++) + bitmap_set(ecc->slot_inuse, reserved[i][0], + reserved[i][1]); + } + + /* Mark reserved channels */ + reserved = info->rsv->rsv_chans; + if (reserved) { + for (i = 0; reserved[i][0] != -1; i++) + bitmap_set(ecc->reserved_chans, reserved[i][0], + reserved[i][1]); } } @@ -2437,6 +2484,10 @@ static int edma_probe(struct platform_device *pdev) edma_dma_init(ecc, legacy_mode); for (i = 0; i < ecc->num_channels; i++) { + /* Do not touch reserved channels */ + if (test_bit(i, ecc->reserved_chans)) + continue; + /* Assign all channels to the default queue */ edma_assign_channel_eventq(&ecc->slave_chans[i], info->default_queue);