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[97.113.7.119]) by smtp.gmail.com with ESMTPSA id a6sm10414039pfa.162.2019.08.25.12.37.59 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sun, 25 Aug 2019 12:37:59 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Date: Sun, 25 Aug 2019 12:37:57 -0700 Message-Id: <20190825193757.16297-2-richard.henderson@linaro.org> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20190825193757.16297-1-richard.henderson@linaro.org> References: <20190825193757.16297-1-richard.henderson@linaro.org> X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:4864:20::643 Subject: [Qemu-devel] [PULL 1/1] target/alpha: fix tlb_fill trap_arg2 value for instruction fetch X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: peter.maydell@linaro.org, qemu-stable@nongnu.org, Aurelien Jarno Errors-To: qemu-devel-bounces+patchwork-qemu-devel=patchwork.kernel.org@nongnu.org Sender: "Qemu-devel" From: Aurelien Jarno Commit e41c94529740cc26 ("target/alpha: Convert to CPUClass::tlb_fill") slightly changed the way the trap_arg2 value is computed in case of TLB fill. The type of the variable used in the ternary operator has been changed from an int to an enum. This causes the -1 value to not be sign-extended to 64-bit in case of an instruction fetch. The trap_arg2 ends up with 0xffffffff instead of 0xffffffffffffffff. Fix that by changing the -1 into -1LL. This fixes the execution of user space processes in qemu-system-alpha. Fixes: e41c94529740cc26 Cc: qemu-stable@nongnu.org Signed-off-by: Aurelien Jarno [rth: Test MMU_DATA_LOAD and MMU_DATA_STORE instead of implying them.] Signed-off-by: Richard Henderson --- target/alpha/helper.c | 4 +++- 1 file changed, 3 insertions(+), 1 deletion(-) diff --git a/target/alpha/helper.c b/target/alpha/helper.c index c6998348df..19cda0a2db 100644 --- a/target/alpha/helper.c +++ b/target/alpha/helper.c @@ -283,7 +283,9 @@ bool alpha_cpu_tlb_fill(CPUState *cs, vaddr addr, int size, cs->exception_index = EXCP_MMFAULT; env->trap_arg0 = addr; env->trap_arg1 = fail; - env->trap_arg2 = (access_type == MMU_INST_FETCH ? -1 : access_type); + env->trap_arg2 = (access_type == MMU_DATA_LOAD ? 0ull : + access_type == MMU_DATA_STORE ? 1ull : + /* access_type == MMU_INST_FETCH */ -1ull); cpu_loop_exit_restore(cs, retaddr); }