From patchwork Mon Aug 26 07:31:38 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Vidya Sagar X-Patchwork-Id: 11114165 Return-Path: Received: from mail.kernel.org (pdx-korg-mail-1.web.codeaurora.org [172.30.200.123]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id 80DBC1398 for ; Mon, 26 Aug 2019 07:31:59 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.kernel.org (Postfix) with ESMTP id 5D9D9206BA for ; Mon, 26 Aug 2019 07:31:59 +0000 (UTC) Authentication-Results: mail.kernel.org; dkim=pass (2048-bit key) header.d=nvidia.com header.i=@nvidia.com header.b="BX88ouuc" Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1730180AbfHZHb6 (ORCPT ); Mon, 26 Aug 2019 03:31:58 -0400 Received: from hqemgate15.nvidia.com ([216.228.121.64]:1300 "EHLO hqemgate15.nvidia.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1730144AbfHZHb6 (ORCPT ); Mon, 26 Aug 2019 03:31:58 -0400 Received: from hqpgpgate101.nvidia.com (Not Verified[216.228.121.13]) by hqemgate15.nvidia.com (using TLS: TLSv1.2, DES-CBC3-SHA) id ; Mon, 26 Aug 2019 00:31:59 -0700 Received: from hqmail.nvidia.com ([172.20.161.6]) by hqpgpgate101.nvidia.com (PGP Universal service); Mon, 26 Aug 2019 00:31:57 -0700 X-PGP-Universal: processed; by hqpgpgate101.nvidia.com on Mon, 26 Aug 2019 00:31:57 -0700 Received: from HQMAIL109.nvidia.com (172.20.187.15) by HQMAIL107.nvidia.com (172.20.187.13) with Microsoft SMTP Server (TLS) id 15.0.1473.3; Mon, 26 Aug 2019 07:31:57 +0000 Received: from HQMAIL111.nvidia.com (172.20.187.18) by HQMAIL109.nvidia.com (172.20.187.15) with Microsoft SMTP Server (TLS) id 15.0.1473.3; Mon, 26 Aug 2019 07:31:56 +0000 Received: from hqnvemgw01.nvidia.com (172.20.150.20) by HQMAIL111.nvidia.com (172.20.187.18) with Microsoft SMTP Server (TLS) id 15.0.1473.3 via Frontend Transport; Mon, 26 Aug 2019 07:31:56 +0000 Received: from vidyas-desktop.nvidia.com (Not Verified[10.24.37.38]) by hqnvemgw01.nvidia.com with Trustwave SEG (v7,5,8,10121) id ; Mon, 26 Aug 2019 00:31:56 -0700 From: Vidya Sagar To: , , , , CC: , , , , , , , , , , , , Subject: [PATCH 1/6] dt-bindings: PCI: tegra: Add sideband pins configuration entries Date: Mon, 26 Aug 2019 13:01:38 +0530 Message-ID: <20190826073143.4582-2-vidyas@nvidia.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20190826073143.4582-1-vidyas@nvidia.com> References: <20190826073143.4582-1-vidyas@nvidia.com> X-NVConfidentiality: public MIME-Version: 1.0 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=nvidia.com; s=n1; t=1566804719; bh=jVsQ77MHmcaFLC4s0eTgGVoxDo/A2MJu8aiRKpUsI/Q=; h=X-PGP-Universal:From:To:CC:Subject:Date:Message-ID:X-Mailer: In-Reply-To:References:X-NVConfidentiality:MIME-Version: Content-Type; b=BX88ouucSggVa8KCQO3Bl2bAB0tI6aUNO8erv2/5t72+dQwwHKdtdWaqFUdD/1zg5 CoDuzH3Oso0hnDZQxNZdHvdpdr4L8AQqOvz6FXb2E9TTEc4V/9cngOw4T1KqHssbM3 oGbgV16zaIn2Z3FxedxDHRGHPmlu1kmZAtbTrfwKbTck0uF9ZcT0PBgn8wmUfqB71X X9T6EnNHrCjT0s9r6+5NJZ6RRj2UGVHXdmlqmMK+hZcASoDJoyBrhmmunmU+5KoCJc o9m3zcAChdZjLfHhzCEL2sKND/q5fadD5Hj+KQbj95rpjccyvISnOi8NDJG7g8oKTM 8+KImlUGtrkCw== Sender: linux-pci-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-pci@vger.kernel.org Add optional bindings "pinctrl-names" and "pinctrl-0" to describe pin configuration information of a particular PCIe controller. Signed-off-by: Vidya Sagar --- .../devicetree/bindings/pci/nvidia,tegra194-pcie.txt | 8 ++++++++ 1 file changed, 8 insertions(+) diff --git a/Documentation/devicetree/bindings/pci/nvidia,tegra194-pcie.txt b/Documentation/devicetree/bindings/pci/nvidia,tegra194-pcie.txt index 674e5adb2895..0ac1b867ac24 100644 --- a/Documentation/devicetree/bindings/pci/nvidia,tegra194-pcie.txt +++ b/Documentation/devicetree/bindings/pci/nvidia,tegra194-pcie.txt @@ -83,6 +83,11 @@ Required properties: - vddio-pex-ctl-supply: Regulator supply for PCIe side band signals Optional properties: +- pinctrl-names: A list of pinctrl state names. + It is mandatory for C5 controller and optional for other controllers. + - "default": Configures PCIe I/O for proper operation. +- pinctrl-0: phandle for the 'default' state of pin configuration. + It is mandatory for C5 controller and optional for other controllers. - supports-clkreq: Refer to Documentation/devicetree/bindings/pci/pci.txt - nvidia,update-fc-fixup: This is a boolean property and needs to be present to improve performance when a platform is designed in such a way that it @@ -120,6 +125,9 @@ Tegra194: num-lanes = <8>; linux,pci-domain = <0>; + pinctrl-names = "default"; + pinctrl-0 = <&pex_rst_c5_out_state>, <&clkreq_c5_bi_dir_state>; + clocks = <&bpmp TEGRA194_CLK_PEX0_CORE_0>; clock-names = "core"; From patchwork Mon Aug 26 07:31:39 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Vidya Sagar X-Patchwork-Id: 11114167 Return-Path: Received: from mail.kernel.org (pdx-korg-mail-1.web.codeaurora.org [172.30.200.123]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id 1E8CE14DB for ; Mon, 26 Aug 2019 07:32:05 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.kernel.org (Postfix) with ESMTP id EF18F22CF7 for ; Mon, 26 Aug 2019 07:32:04 +0000 (UTC) Authentication-Results: mail.kernel.org; dkim=pass (2048-bit key) header.d=nvidia.com header.i=@nvidia.com header.b="enioegNB" Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1730144AbfHZHcE (ORCPT ); Mon, 26 Aug 2019 03:32:04 -0400 Received: from hqemgate14.nvidia.com ([216.228.121.143]:19142 "EHLO hqemgate14.nvidia.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1730006AbfHZHcD (ORCPT ); Mon, 26 Aug 2019 03:32:03 -0400 Received: from hqpgpgate101.nvidia.com (Not Verified[216.228.121.13]) by hqemgate14.nvidia.com (using TLS: TLSv1.2, DES-CBC3-SHA) id ; Mon, 26 Aug 2019 00:32:03 -0700 Received: from hqmail.nvidia.com ([172.20.161.6]) by hqpgpgate101.nvidia.com (PGP Universal service); Mon, 26 Aug 2019 00:32:02 -0700 X-PGP-Universal: processed; by hqpgpgate101.nvidia.com on Mon, 26 Aug 2019 00:32:02 -0700 Received: from HQMAIL109.nvidia.com (172.20.187.15) by HQMAIL107.nvidia.com (172.20.187.13) with Microsoft SMTP Server (TLS) id 15.0.1473.3; Mon, 26 Aug 2019 07:32:02 +0000 Received: from HQMAIL101.nvidia.com (172.20.187.10) by HQMAIL109.nvidia.com (172.20.187.15) with Microsoft SMTP Server (TLS) id 15.0.1473.3; Mon, 26 Aug 2019 07:32:02 +0000 Received: from hqnvemgw01.nvidia.com (172.20.150.20) by HQMAIL101.nvidia.com (172.20.187.10) with Microsoft SMTP Server (TLS) id 15.0.1473.3 via Frontend Transport; Mon, 26 Aug 2019 07:32:02 +0000 Received: from vidyas-desktop.nvidia.com (Not Verified[10.24.37.38]) by hqnvemgw01.nvidia.com with Trustwave SEG (v7,5,8,10121) id ; Mon, 26 Aug 2019 00:32:01 -0700 From: Vidya Sagar To: , , , , CC: , , , , , , , , , , , , Subject: [PATCH 2/6] arm64: tegra: Add configuration for PCIe C5 sideband signals Date: Mon, 26 Aug 2019 13:01:39 +0530 Message-ID: <20190826073143.4582-3-vidyas@nvidia.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20190826073143.4582-1-vidyas@nvidia.com> References: <20190826073143.4582-1-vidyas@nvidia.com> X-NVConfidentiality: public MIME-Version: 1.0 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=nvidia.com; s=n1; t=1566804723; bh=haHXWsGgD8MESPMvbZs2yQ/SLeRmS1gQyc9LUmqIL08=; h=X-PGP-Universal:From:To:CC:Subject:Date:Message-ID:X-Mailer: In-Reply-To:References:X-NVConfidentiality:MIME-Version: Content-Type; b=enioegNBwGCOT2yISiZYdP1kIxO403F96JdyOLm+PfeeD3pmboxHreNCa+wwGs0B7 YDD44xpHZapFBDlc+d6XPMfhP0HHtGmhSQ2npgdVa68WHSkm3MyyqZTizkBM5+RiXk f3vN2TtLI19NHMR0KyWX2FKvgINcR96LeMJxjrrpqmsWwCDkbtJ+J30kK9jyROEKAL fFqPyH+3L9RpcA82qr/8FBEV0OVvV/rYizx3q4PW++BtSVylBp0ZcJ7PMLxiM6vkk2 7BXBz0Zf0xlCgaznTMpWDzZiWxgBEH+fug4pZxwc3Up7ROGxGVHFreUavdFf8fNrG3 33dUVIDvUQFjQ== Sender: linux-pci-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-pci@vger.kernel.org Add support to configure PCIe C5's sideband signals PERST# and CLKREQ# as output and bi-directional signals respectively which unlike other PCIe controllers sideband signals are not configured by default. Signed-off-by: Vidya Sagar --- arch/arm64/boot/dts/nvidia/tegra194.dtsi | 38 +++++++++++++++++++++++- 1 file changed, 37 insertions(+), 1 deletion(-) diff --git a/arch/arm64/boot/dts/nvidia/tegra194.dtsi b/arch/arm64/boot/dts/nvidia/tegra194.dtsi index adebbbf36bd0..3c0cf54f0aab 100644 --- a/arch/arm64/boot/dts/nvidia/tegra194.dtsi +++ b/arch/arm64/boot/dts/nvidia/tegra194.dtsi @@ -3,8 +3,9 @@ #include #include #include -#include +#include #include +#include #include / { @@ -130,6 +131,38 @@ }; }; + pinmux: pinmux@2430000 { + compatible = "nvidia,tegra194-pinmux"; + reg = <0x2430000 0x17000 + 0xc300000 0x4000>; + + status = "okay"; + + pex_rst_c5_out_state: pex_rst_c5_out { + pex_rst { + nvidia,pins = "pex_l5_rst_n_pgg1"; + nvidia,schmitt = ; + nvidia,lpdr = ; + nvidia,enable-input = ; + nvidia,io-high-voltage = ; + nvidia,tristate = ; + nvidia,pull = ; + }; + }; + + clkreq_c5_bi_dir_state: clkreq_c5_bi_dir { + clkreq { + nvidia,pins = "pex_l5_clkreq_n_pgg0"; + nvidia,schmitt = ; + nvidia,lpdr = ; + nvidia,enable-input = ; + nvidia,io-high-voltage = ; + nvidia,tristate = ; + nvidia,pull = ; + }; + }; + }; + uarta: serial@3100000 { compatible = "nvidia,tegra194-uart", "nvidia,tegra20-uart"; reg = <0x03100000 0x40>; @@ -1365,6 +1398,9 @@ num-viewport = <8>; linux,pci-domain = <5>; + pinctrl-names = "default"; + pinctrl-0 = <&pex_rst_c5_out_state>, <&clkreq_c5_bi_dir_state>; + clocks = <&bpmp TEGRA194_CLK_PEX1_CORE_5>, <&bpmp TEGRA194_CLK_PEX1_CORE_5M>; clock-names = "core", "core_m"; From patchwork Mon Aug 26 07:31:40 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Vidya Sagar X-Patchwork-Id: 11114169 Return-Path: Received: from mail.kernel.org (pdx-korg-mail-1.web.codeaurora.org [172.30.200.123]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id 682B2174A for ; Mon, 26 Aug 2019 07:32:10 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.kernel.org (Postfix) with ESMTP id 43A3722CF7 for ; Mon, 26 Aug 2019 07:32:10 +0000 (UTC) Authentication-Results: mail.kernel.org; dkim=pass (2048-bit key) header.d=nvidia.com header.i=@nvidia.com header.b="jeTwYT2i" Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1730211AbfHZHcJ (ORCPT ); Mon, 26 Aug 2019 03:32:09 -0400 Received: from hqemgate16.nvidia.com ([216.228.121.65]:10958 "EHLO hqemgate16.nvidia.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1730006AbfHZHcJ (ORCPT ); Mon, 26 Aug 2019 03:32:09 -0400 Received: from hqpgpgate102.nvidia.com (Not Verified[216.228.121.13]) by hqemgate16.nvidia.com (using TLS: TLSv1.2, DES-CBC3-SHA) id ; Mon, 26 Aug 2019 00:32:09 -0700 Received: from hqmail.nvidia.com ([172.20.161.6]) by hqpgpgate102.nvidia.com (PGP Universal service); Mon, 26 Aug 2019 00:32:08 -0700 X-PGP-Universal: processed; by hqpgpgate102.nvidia.com on Mon, 26 Aug 2019 00:32:08 -0700 Received: from HQMAIL109.nvidia.com (172.20.187.15) by HQMAIL105.nvidia.com (172.20.187.12) with Microsoft SMTP Server (TLS) id 15.0.1473.3; Mon, 26 Aug 2019 07:32:08 +0000 Received: from HQMAIL101.nvidia.com (172.20.187.10) by HQMAIL109.nvidia.com (172.20.187.15) with Microsoft SMTP Server (TLS) id 15.0.1473.3; Mon, 26 Aug 2019 07:32:07 +0000 Received: from hqnvemgw01.nvidia.com (172.20.150.20) by HQMAIL101.nvidia.com (172.20.187.10) with Microsoft SMTP Server (TLS) id 15.0.1473.3 via Frontend Transport; Mon, 26 Aug 2019 07:32:08 +0000 Received: from vidyas-desktop.nvidia.com (Not Verified[10.24.37.38]) by hqnvemgw01.nvidia.com with Trustwave SEG (v7,5,8,10121) id ; Mon, 26 Aug 2019 00:32:07 -0700 From: Vidya Sagar To: , , , , CC: , , , , , , , , , , , , Subject: [PATCH 3/6] PCI: tegra: Add support to configure sideband pins Date: Mon, 26 Aug 2019 13:01:40 +0530 Message-ID: <20190826073143.4582-4-vidyas@nvidia.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20190826073143.4582-1-vidyas@nvidia.com> References: <20190826073143.4582-1-vidyas@nvidia.com> X-NVConfidentiality: public MIME-Version: 1.0 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=nvidia.com; s=n1; t=1566804729; bh=ADNWY6D18iASNntieqTjCPp7lsXA6jQML9nnBWw895Q=; h=X-PGP-Universal:From:To:CC:Subject:Date:Message-ID:X-Mailer: In-Reply-To:References:X-NVConfidentiality:MIME-Version: Content-Type; b=jeTwYT2iS12PPwyC0Ld8lTHD+FIuHUtHKTLihXLYR01J92uIwHuS1SM5KPu0l1+7R tkU+QwWZDkarpFCcFuZypPCqT8LaXzkBbS4sjg6XFtEHwnO/JsYd1YOH61vUrDoFxM ZO4JLVXN6+h4rC6+OAYDL0WDSuxdHtygD19VkaFfsjvk2PBumgRdBhL1Ma0W/aL0zg XRMeX2EvgZWOVHfjTtIf5m7GCc9wJfekjjQnzjOmWCOi5ROPRU5+vX1u3Ndy8L8nUS GRBZj0erUOlYsKcH7z+n90eDDpzz2hUBPb1muYLvH52BRKd4TI24ZfalA8Z8E5h+4T 8Mpn/LJ85VQZQ== Sender: linux-pci-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-pci@vger.kernel.org Add support to configure sideband signal pins when information is present in respective controller's device-tree node. Signed-off-by: Vidya Sagar --- drivers/pci/controller/dwc/pcie-tegra194.c | 6 ++++++ 1 file changed, 6 insertions(+) diff --git a/drivers/pci/controller/dwc/pcie-tegra194.c b/drivers/pci/controller/dwc/pcie-tegra194.c index fc0dbeb31d78..8a27b25893c9 100644 --- a/drivers/pci/controller/dwc/pcie-tegra194.c +++ b/drivers/pci/controller/dwc/pcie-tegra194.c @@ -1308,6 +1308,12 @@ static int tegra_pcie_config_rp(struct tegra_pcie_dw *pcie) return ret; } + ret = pinctrl_pm_select_default_state(pcie->dev); + if (ret < 0) { + dev_err(pcie->dev, "Failed to configure sideband pins\n"); + return ret; + } + tegra_pcie_init_controller(pcie); pcie->link_state = tegra_pcie_dw_link_up(&pcie->pci); From patchwork Mon Aug 26 07:31:41 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Vidya Sagar X-Patchwork-Id: 11114173 Return-Path: Received: from mail.kernel.org (pdx-korg-mail-1.web.codeaurora.org [172.30.200.123]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id 3616D1398 for ; Mon, 26 Aug 2019 07:32:19 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.kernel.org (Postfix) with ESMTP id 12F83206BA for ; Mon, 26 Aug 2019 07:32:19 +0000 (UTC) Authentication-Results: mail.kernel.org; dkim=pass (2048-bit key) header.d=nvidia.com header.i=@nvidia.com header.b="JtAXxIZR" Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1730006AbfHZHcS (ORCPT ); Mon, 26 Aug 2019 03:32:18 -0400 Received: from hqemgate15.nvidia.com ([216.228.121.64]:1324 "EHLO hqemgate15.nvidia.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1729972AbfHZHcS (ORCPT ); Mon, 26 Aug 2019 03:32:18 -0400 Received: from hqpgpgate101.nvidia.com (Not Verified[216.228.121.13]) by hqemgate15.nvidia.com (using TLS: TLSv1.2, DES-CBC3-SHA) id ; Mon, 26 Aug 2019 00:32:19 -0700 Received: from hqmail.nvidia.com ([172.20.161.6]) by hqpgpgate101.nvidia.com (PGP Universal service); Mon, 26 Aug 2019 00:32:17 -0700 X-PGP-Universal: processed; by hqpgpgate101.nvidia.com on Mon, 26 Aug 2019 00:32:17 -0700 Received: from HQMAIL111.nvidia.com (172.20.187.18) by HQMAIL105.nvidia.com (172.20.187.12) with Microsoft SMTP Server (TLS) id 15.0.1473.3; Mon, 26 Aug 2019 07:32:17 +0000 Received: from HQMAIL111.nvidia.com (172.20.187.18) by HQMAIL111.nvidia.com (172.20.187.18) with Microsoft SMTP Server (TLS) id 15.0.1473.3; Mon, 26 Aug 2019 07:32:16 +0000 Received: from hqnvemgw01.nvidia.com (172.20.150.20) by HQMAIL111.nvidia.com (172.20.187.18) with Microsoft SMTP Server (TLS) id 15.0.1473.3 via Frontend Transport; Mon, 26 Aug 2019 07:32:16 +0000 Received: from vidyas-desktop.nvidia.com (Not Verified[10.24.37.38]) by hqnvemgw01.nvidia.com with Trustwave SEG (v7,5,8,10121) id ; Mon, 26 Aug 2019 00:32:16 -0700 From: Vidya Sagar To: , , , , CC: , , , , , , , , , , , , Subject: [PATCH 4/6] dt-bindings: PCI: tegra: Add PCIe slot supplies regulator entries Date: Mon, 26 Aug 2019 13:01:41 +0530 Message-ID: <20190826073143.4582-5-vidyas@nvidia.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20190826073143.4582-1-vidyas@nvidia.com> References: <20190826073143.4582-1-vidyas@nvidia.com> X-NVConfidentiality: public MIME-Version: 1.0 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=nvidia.com; s=n1; t=1566804739; bh=THHme64xuMDnn8JFy08KngJ0DOWHH0RnZQtdKa8+w6g=; h=X-PGP-Universal:From:To:CC:Subject:Date:Message-ID:X-Mailer: In-Reply-To:References:X-NVConfidentiality:MIME-Version: Content-Type; b=JtAXxIZR2KbkHKUcheNVSeiuAfqWRf9MjLWqtWgMhPuejB4t8raw40whvOtK3jnz1 EEXKiHfzRjpgCe8+8bJvP78CsdfyGMxO6M20IFl660MwEFombTqoskI/oZdvTtmw5o 3+XHJS1hO2Beu21th7soTJmglXifzUw/cOT9F5aOo/EwWGbV5w8j20kGEKEToJwogi QQdZJl8jccQSCzFrf9zaVb0AwoCG/18w+6e93TlKIE10dObmeFQs4g5fiGZ2N+I3he Z/Ikp1nmGQooTBQ/1VzfHEDY2rtXzOWx+rMTHIsF/BgGBGS+fnV4iLVr9bv1LjPMfb hdf1Iz+2510jQ== Sender: linux-pci-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-pci@vger.kernel.org Add optional bindings "vpcie3v3-supply" and "vpcie12v-supply" to describe regulators of a PCIe slot's supplies 3.3V and 12V provided the platform is designed to have regulator controlled slot supplies. Signed-off-by: Vidya Sagar --- .../devicetree/bindings/pci/nvidia,tegra194-pcie.txt | 8 ++++++++ 1 file changed, 8 insertions(+) diff --git a/Documentation/devicetree/bindings/pci/nvidia,tegra194-pcie.txt b/Documentation/devicetree/bindings/pci/nvidia,tegra194-pcie.txt index 0ac1b867ac24..b739f92da58e 100644 --- a/Documentation/devicetree/bindings/pci/nvidia,tegra194-pcie.txt +++ b/Documentation/devicetree/bindings/pci/nvidia,tegra194-pcie.txt @@ -104,6 +104,12 @@ Optional properties: specified in microseconds - nvidia,aspm-l0s-entrance-latency-us: ASPM L0s entrance latency to be specified in microseconds +- vpcie3v3-supply: A phandle to the regulator node that supplies 3.3V to the slot + if the platform has one such slot. (Ex:- x16 slot owned by C5 controller + in p2972-0000 platform). +- vpcie12v-supply: A phandle to the regulator node that supplies 12V to the slot + if the platform has one such slot. (Ex:- x16 slot owned by C5 controller + in p2972-0000 platform). Examples: ========= @@ -156,6 +162,8 @@ Tegra194: 0xc2000000 0x18 0x00000000 0x18 0x00000000 0x4 0x00000000>; /* prefetchable memory (16GB) */ vddio-pex-ctl-supply = <&vdd_1v8ao>; + vpcie3v3-supply = <&vdd_3v3_pcie>; + vpcie12v-supply = <&vdd_12v_pcie>; phys = <&p2u_hsio_2>, <&p2u_hsio_3>, <&p2u_hsio_4>, <&p2u_hsio_5>; From patchwork Mon Aug 26 07:31:42 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Vidya Sagar X-Patchwork-Id: 11114175 Return-Path: Received: from mail.kernel.org (pdx-korg-mail-1.web.codeaurora.org [172.30.200.123]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id 77D3014DB for ; Mon, 26 Aug 2019 07:32:27 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.kernel.org (Postfix) with ESMTP id 5551320874 for ; Mon, 26 Aug 2019 07:32:27 +0000 (UTC) Authentication-Results: mail.kernel.org; dkim=pass (2048-bit key) header.d=nvidia.com header.i=@nvidia.com header.b="oV4MrL1v" Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1730114AbfHZHcX (ORCPT ); Mon, 26 Aug 2019 03:32:23 -0400 Received: from hqemgate14.nvidia.com ([216.228.121.143]:19187 "EHLO hqemgate14.nvidia.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1729972AbfHZHcX (ORCPT ); Mon, 26 Aug 2019 03:32:23 -0400 Received: from hqpgpgate101.nvidia.com (Not Verified[216.228.121.13]) by hqemgate14.nvidia.com (using TLS: TLSv1.2, DES-CBC3-SHA) id ; Mon, 26 Aug 2019 00:32:22 -0700 Received: from hqmail.nvidia.com ([172.20.161.6]) by hqpgpgate101.nvidia.com (PGP Universal service); Mon, 26 Aug 2019 00:32:22 -0700 X-PGP-Universal: processed; by hqpgpgate101.nvidia.com on Mon, 26 Aug 2019 00:32:22 -0700 Received: from HQMAIL107.nvidia.com (172.20.187.13) by HQMAIL107.nvidia.com (172.20.187.13) with Microsoft SMTP Server (TLS) id 15.0.1473.3; Mon, 26 Aug 2019 07:32:22 +0000 Received: from hqnvemgw01.nvidia.com (172.20.150.20) by HQMAIL107.nvidia.com (172.20.187.13) with Microsoft SMTP Server (TLS) id 15.0.1473.3 via Frontend Transport; Mon, 26 Aug 2019 07:32:22 +0000 Received: from vidyas-desktop.nvidia.com (Not Verified[10.24.37.38]) by hqnvemgw01.nvidia.com with Trustwave SEG (v7,5,8,10121) id ; Mon, 26 Aug 2019 00:32:21 -0700 From: Vidya Sagar To: , , , , CC: , , , , , , , , , , , , Subject: [PATCH 5/6] arm64: tegra: Add PCIe slot supply information in p2972-0000 platform Date: Mon, 26 Aug 2019 13:01:42 +0530 Message-ID: <20190826073143.4582-6-vidyas@nvidia.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20190826073143.4582-1-vidyas@nvidia.com> References: <20190826073143.4582-1-vidyas@nvidia.com> X-NVConfidentiality: public MIME-Version: 1.0 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=nvidia.com; s=n1; t=1566804742; bh=1l/zTksvu80Z55hksPpgQGoCPRt7hW3qacYfvwGt8KU=; h=X-PGP-Universal:From:To:CC:Subject:Date:Message-ID:X-Mailer: In-Reply-To:References:X-NVConfidentiality:MIME-Version: Content-Type; b=oV4MrL1vCoU09RPnBi/AAMK9996jTrszeYA8U3/AfCtwYPORzlRyzokGBeRIf6EDD RAnFQSwQeU7L6GWLoQCqg7JE/3kxo4dX68k7SPTGc3isqyLiw81YaXlkJkqh0HICXm FPRbbGdzOgzjHMlrnTK9RpwYTq6gA4b9CyxLuxvPqiGKkk84lJ88jjiq5i+Z9k1hTq 1TA2CH18FKJEK92i3855KG3tvHbd1YJDRkycd5HDs46oXQ/jVf+I2ZwgtXPebYT357 7nbiefcaVxGp+51OXjuBlgOL7kgLmVkDc0p6IZJdO9Y10hQTHeo138ci/kuULOEHVa 7XuWEFqbJB0Eg== Sender: linux-pci-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-pci@vger.kernel.org Add 3.3V and 12V supplies regulators information of x16 PCIe slot in p2972-0000 platform which is owned by C5 controller and also enable C5 controller. Signed-off-by: Vidya Sagar --- .../arm64/boot/dts/nvidia/tegra194-p2888.dtsi | 24 +++++++++++++++++++ .../boot/dts/nvidia/tegra194-p2972-0000.dts | 4 +++- 2 files changed, 27 insertions(+), 1 deletion(-) diff --git a/arch/arm64/boot/dts/nvidia/tegra194-p2888.dtsi b/arch/arm64/boot/dts/nvidia/tegra194-p2888.dtsi index 62e07e1197cc..4c38426a6969 100644 --- a/arch/arm64/boot/dts/nvidia/tegra194-p2888.dtsi +++ b/arch/arm64/boot/dts/nvidia/tegra194-p2888.dtsi @@ -289,5 +289,29 @@ gpio = <&gpio TEGRA194_MAIN_GPIO(A, 3) GPIO_ACTIVE_HIGH>; enable-active-high; }; + + vdd_3v3_pcie: regulator@2 { + compatible = "regulator-fixed"; + reg = <2>; + + regulator-name = "PEX_3V3"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + gpio = <&gpio TEGRA194_MAIN_GPIO(Z, 2) GPIO_ACTIVE_HIGH>; + regulator-boot-on; + enable-active-high; + }; + + vdd_12v_pcie: regulator@3 { + compatible = "regulator-fixed"; + reg = <3>; + + regulator-name = "VDD_12V"; + regulator-min-microvolt = <1200000>; + regulator-max-microvolt = <1200000>; + gpio = <&gpio TEGRA194_MAIN_GPIO(A, 1) GPIO_ACTIVE_LOW>; + regulator-boot-on; + enable-active-low; + }; }; }; diff --git a/arch/arm64/boot/dts/nvidia/tegra194-p2972-0000.dts b/arch/arm64/boot/dts/nvidia/tegra194-p2972-0000.dts index 23597d53c9c9..d47cd8c4dd24 100644 --- a/arch/arm64/boot/dts/nvidia/tegra194-p2972-0000.dts +++ b/arch/arm64/boot/dts/nvidia/tegra194-p2972-0000.dts @@ -93,9 +93,11 @@ }; pcie@141a0000 { - status = "disabled"; + status = "okay"; vddio-pex-ctl-supply = <&vdd_1v8ao>; + vpcie3v3-supply = <&vdd_3v3_pcie>; + vpcie12v-supply = <&vdd_12v_pcie>; phys = <&p2u_nvhs_0>, <&p2u_nvhs_1>, <&p2u_nvhs_2>, <&p2u_nvhs_3>, <&p2u_nvhs_4>, <&p2u_nvhs_5>, From patchwork Mon Aug 26 07:31:43 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Vidya Sagar X-Patchwork-Id: 11114179 Return-Path: Received: from mail.kernel.org (pdx-korg-mail-1.web.codeaurora.org [172.30.200.123]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id B957C1398 for ; Mon, 26 Aug 2019 07:32:37 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.kernel.org (Postfix) with ESMTP id 8D24422CF9 for ; Mon, 26 Aug 2019 07:32:37 +0000 (UTC) Authentication-Results: mail.kernel.org; dkim=pass (2048-bit key) header.d=nvidia.com header.i=@nvidia.com header.b="JaujQeaT" Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1730110AbfHZHcd (ORCPT ); Mon, 26 Aug 2019 03:32:33 -0400 Received: from hqemgate16.nvidia.com ([216.228.121.65]:10982 "EHLO hqemgate16.nvidia.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1729972AbfHZHcd (ORCPT ); Mon, 26 Aug 2019 03:32:33 -0400 Received: from hqpgpgate102.nvidia.com (Not Verified[216.228.121.13]) by hqemgate16.nvidia.com (using TLS: TLSv1.2, DES-CBC3-SHA) id ; Mon, 26 Aug 2019 00:32:32 -0700 Received: from hqmail.nvidia.com ([172.20.161.6]) by hqpgpgate102.nvidia.com (PGP Universal service); Mon, 26 Aug 2019 00:32:31 -0700 X-PGP-Universal: processed; by hqpgpgate102.nvidia.com on Mon, 26 Aug 2019 00:32:31 -0700 Received: from HQMAIL110.nvidia.com (172.18.146.15) by HQMAIL107.nvidia.com (172.20.187.13) with Microsoft SMTP Server (TLS) id 15.0.1473.3; Mon, 26 Aug 2019 07:32:31 +0000 Received: from HQMAIL107.nvidia.com (172.20.187.13) by hqmail110.nvidia.com (172.18.146.15) with Microsoft SMTP Server (TLS) id 15.0.1473.3; Mon, 26 Aug 2019 07:32:30 +0000 Received: from hqnvemgw01.nvidia.com (172.20.150.20) by HQMAIL107.nvidia.com (172.20.187.13) with Microsoft SMTP Server (TLS) id 15.0.1473.3 via Frontend Transport; Mon, 26 Aug 2019 07:32:30 +0000 Received: from vidyas-desktop.nvidia.com (Not Verified[10.24.37.38]) by hqnvemgw01.nvidia.com with Trustwave SEG (v7,5,8,10121) id ; Mon, 26 Aug 2019 00:32:30 -0700 From: Vidya Sagar To: , , , , CC: , , , , , , , , , , , , Subject: [PATCH 6/6] PCI: tegra: Add support to enable slot regulators Date: Mon, 26 Aug 2019 13:01:43 +0530 Message-ID: <20190826073143.4582-7-vidyas@nvidia.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20190826073143.4582-1-vidyas@nvidia.com> References: <20190826073143.4582-1-vidyas@nvidia.com> X-NVConfidentiality: public MIME-Version: 1.0 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=nvidia.com; s=n1; t=1566804752; bh=R2egLAnwrR5Kvqmt17u69HmZzQMYG/5d8VrvWFOXbpY=; h=X-PGP-Universal:From:To:CC:Subject:Date:Message-ID:X-Mailer: In-Reply-To:References:X-NVConfidentiality:MIME-Version: Content-Type; b=JaujQeaTdJ7Mv1xTSoHp3/21NufFQ56AfePO58wxUGs4ChOtXH3vYnIGFemJDMNq2 4z6r0bx18WX4ZxogQ00QMymI3PK5mDsyaTdH2zPQ6OrmTCfcugm6uyDdGl27LZevq9 aKHfDCfIvLFI8n4jWvnHdqro4oYtLsM90u2j9A/1zzGmnEdtLt+THxNetA6gVWXUOn OAfiCPwH3MTzEQ3P5c+5jPLpE3AlUaca1YNOdsw+BcY9sxrSG23dcYy7HmX5Mwq3VT nGEMU7YTb+0Y33bxPOuyesrVonfz/iwQ3CZKeIsTWhUd6ZxJHmupjOjMebWk5Izi+a BiQgAABaWR3Rw== Sender: linux-pci-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-pci@vger.kernel.org Add support to get regulator information of 3.3V and 12V supplies of a PCIe slot from the respective controller's device-tree node and enable those supplies. This is required in platforms like p2972-0000 where the supplies to x16 slot owned by C5 controller need to be enabled before attempting to enumerate the devices. Signed-off-by: Vidya Sagar --- drivers/pci/controller/dwc/pcie-tegra194.c | 65 ++++++++++++++++++++++ 1 file changed, 65 insertions(+) diff --git a/drivers/pci/controller/dwc/pcie-tegra194.c b/drivers/pci/controller/dwc/pcie-tegra194.c index 8a27b25893c9..97de2151a738 100644 --- a/drivers/pci/controller/dwc/pcie-tegra194.c +++ b/drivers/pci/controller/dwc/pcie-tegra194.c @@ -278,6 +278,8 @@ struct tegra_pcie_dw { u32 aspm_l0s_enter_lat; struct regulator *pex_ctl_supply; + struct regulator *slot_ctl_3v3; + struct regulator *slot_ctl_12v; unsigned int phy_count; struct phy **phys; @@ -1047,6 +1049,59 @@ static void tegra_pcie_downstream_dev_to_D0(struct tegra_pcie_dw *pcie) } } +static void tegra_pcie_get_slot_regulators(struct tegra_pcie_dw *pcie) +{ + pcie->slot_ctl_3v3 = devm_regulator_get_optional(pcie->dev, "vpcie3v3"); + if (IS_ERR(pcie->slot_ctl_3v3)) + pcie->slot_ctl_3v3 = NULL; + + pcie->slot_ctl_12v = devm_regulator_get_optional(pcie->dev, "vpcie12v"); + if (IS_ERR(pcie->slot_ctl_12v)) + pcie->slot_ctl_12v = NULL; +} + +static int tegra_pcie_enable_slot_regulators(struct tegra_pcie_dw *pcie) +{ + int ret; + + if (pcie->slot_ctl_3v3) { + ret = regulator_enable(pcie->slot_ctl_3v3); + if (ret < 0) { + dev_err(pcie->dev, + "Failed to enable 3V3 slot supply: %d\n", ret); + return ret; + } + } + + if (pcie->slot_ctl_12v) { + ret = regulator_enable(pcie->slot_ctl_12v); + if (ret < 0) { + dev_err(pcie->dev, + "Failed to enable 12V slot supply: %d\n", ret); + if (pcie->slot_ctl_3v3) + regulator_disable(pcie->slot_ctl_3v3); + return ret; + } + } + + /* + * According to PCI Express Card Electromechanical Specification + * Revision 1.1, Table-2.4, T_PVPERL (Power stable to PERST# inactive) + * should be a minimum of 100ms. + */ + msleep(100); + + return 0; +} + +static void tegra_pcie_disable_slot_regulators(struct tegra_pcie_dw *pcie) +{ + if (pcie->slot_ctl_12v) + regulator_disable(pcie->slot_ctl_12v); + if (pcie->slot_ctl_3v3) + regulator_disable(pcie->slot_ctl_3v3); +} + static int tegra_pcie_config_controller(struct tegra_pcie_dw *pcie, bool en_hw_hot_rst) { @@ -1060,6 +1115,10 @@ static int tegra_pcie_config_controller(struct tegra_pcie_dw *pcie, return ret; } + ret = tegra_pcie_enable_slot_regulators(pcie); + if (ret < 0) + goto fail_slot_reg_en; + ret = regulator_enable(pcie->pex_ctl_supply); if (ret < 0) { dev_err(pcie->dev, "Failed to enable regulator: %d\n", ret); @@ -1142,6 +1201,8 @@ static int tegra_pcie_config_controller(struct tegra_pcie_dw *pcie, fail_core_clk: regulator_disable(pcie->pex_ctl_supply); fail_reg_en: + tegra_pcie_disable_slot_regulators(pcie); +fail_slot_reg_en: tegra_pcie_bpmp_set_ctrl_state(pcie, false); return ret; @@ -1174,6 +1235,8 @@ static int __deinit_controller(struct tegra_pcie_dw *pcie) return ret; } + tegra_pcie_disable_slot_regulators(pcie); + ret = tegra_pcie_bpmp_set_ctrl_state(pcie, false); if (ret) { dev_err(pcie->dev, "Failed to disable controller %d: %d\n", @@ -1372,6 +1435,8 @@ static int tegra_pcie_dw_probe(struct platform_device *pdev) return ret; } + tegra_pcie_get_slot_regulators(pcie); + pcie->pex_ctl_supply = devm_regulator_get(dev, "vddio-pex-ctl"); if (IS_ERR(pcie->pex_ctl_supply)) { dev_err(dev, "Failed to get regulator: %ld\n",