From patchwork Tue Aug 27 08:52:50 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Jiaxun Yang X-Patchwork-Id: 11116407 Return-Path: Received: from mail.kernel.org (pdx-korg-mail-1.web.codeaurora.org [172.30.200.123]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id 5472414F7 for ; Tue, 27 Aug 2019 08:53:57 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.kernel.org (Postfix) with ESMTP id 1235A21881 for ; Tue, 27 Aug 2019 08:53:56 +0000 (UTC) Authentication-Results: mail.kernel.org; dkim=pass (1024-bit key) header.d=flygoat.com header.i=@flygoat.com header.b="SJLjormH" Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1726025AbfH0Ix4 (ORCPT ); Tue, 27 Aug 2019 04:53:56 -0400 Received: from forward102j.mail.yandex.net ([5.45.198.243]:50864 "EHLO forward102j.mail.yandex.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1728999AbfH0Ix4 (ORCPT ); Tue, 27 Aug 2019 04:53:56 -0400 Received: from mxback4o.mail.yandex.net (mxback4o.mail.yandex.net [IPv6:2a02:6b8:0:1a2d::1e]) by forward102j.mail.yandex.net (Yandex) with ESMTP id 00627F21B50; Tue, 27 Aug 2019 11:53:49 +0300 (MSK) Received: from smtp1p.mail.yandex.net (smtp1p.mail.yandex.net [2a02:6b8:0:1472:2741:0:8b6:6]) by mxback4o.mail.yandex.net (nwsmtp/Yandex) with ESMTP id newrb0eazh-rmVidK2C; Tue, 27 Aug 2019 11:53:48 +0300 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=flygoat.com; s=mail; t=1566896028; bh=cBHr6ia9EVOb1pCmb6h2l4pQZuJ4M9Xld6bKEZZOlYw=; h=In-Reply-To:Subject:To:From:Cc:References:Date:Message-Id; b=SJLjormHLtmQfd8znQ6P/RIe/BWB/uiOv2tQ4OpjMigepcwxDgObcKKCpLAc/IIRs 4KMfEAmwslrGLCGzpDbTxWfPwiA1zCW9q+iYwo3O1V/j+VouiQeBppWt+9wXpTHBvE y0VOrsueUNlZomDVDSLp4QDZM34jXqo9c+OA75EA= Authentication-Results: mxback4o.mail.yandex.net; dkim=pass header.i=@flygoat.com Received: by smtp1p.mail.yandex.net (nwsmtp/Yandex) with ESMTPSA id JOqUfE8LDO-retCqVFK; Tue, 27 Aug 2019 11:53:45 +0300 (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits)) (Client certificate not present) From: Jiaxun Yang To: linux-mips@vger.kernel.org Cc: chenhc@lemote.com, paul.burton@mips.com, tglx@linutronix.de, jason@lakedaemon.net, maz@kernel.org, linux-kernel@vger.kernel.org, robh+dt@kernel.org, mark.rutland@arm.co, devicetree@vger.kernel.org, Jiaxun Yang Subject: [PATCH 01/13] MIPS: Loongson64: Rename CPU TYPES Date: Tue, 27 Aug 2019 16:52:50 +0800 Message-Id: <20190827085302.5197-2-jiaxun.yang@flygoat.com> X-Mailer: git-send-email 2.22.0 In-Reply-To: <20190827085302.5197-1-jiaxun.yang@flygoat.com> References: <20190827085302.5197-1-jiaxun.yang@flygoat.com> MIME-Version: 1.0 Sender: linux-mips-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-mips@vger.kernel.org CPU_LOONGSON2 -> CPU_LOONGSON2EF CPU_LOONGSON3 -> CPU_LOONGSON64 As newer loongson-2 products (2G/2H/2K1000) can share kernel implementation with loongson-3 while 2E/2F are less similar with other LOONGSON64 products. Signed-off-by: Jiaxun Yang --- arch/mips/Kconfig | 28 ++++++++-------- arch/mips/include/asm/cop2.h | 2 +- arch/mips/include/asm/cpu-type.h | 6 ++-- arch/mips/include/asm/cpu.h | 4 +-- arch/mips/include/asm/hazards.h | 2 +- arch/mips/include/asm/io.h | 2 +- arch/mips/include/asm/irqflags.h | 2 +- .../mach-loongson64/cpu-feature-overrides.h | 2 +- arch/mips/include/asm/mach-loongson64/irq.h | 2 +- .../asm/mach-loongson64/kernel-entry-init.h | 4 +-- .../include/asm/mach-loongson64/loongson.h | 2 +- arch/mips/include/asm/mach-loongson64/pci.h | 2 +- arch/mips/include/asm/module.h | 8 ++--- arch/mips/include/asm/pgtable-bits.h | 2 +- arch/mips/include/asm/processor.h | 2 +- arch/mips/include/asm/r4kcache.h | 4 +-- arch/mips/kernel/cpu-probe.c | 14 ++++---- arch/mips/kernel/idle.c | 2 +- arch/mips/kernel/perf_event_mipsxx.c | 4 +-- arch/mips/kernel/setup.c | 2 +- arch/mips/kernel/traps.c | 2 +- arch/mips/lib/csum_partial.S | 4 +-- arch/mips/loongson64/Kconfig | 2 +- arch/mips/loongson64/Makefile | 2 +- arch/mips/loongson64/Platform | 12 +++---- arch/mips/loongson64/common/pci.c | 2 +- arch/mips/mm/c-r4k.c | 32 +++++++++---------- arch/mips/mm/page.c | 2 +- arch/mips/mm/tlb-r4k.c | 4 +-- arch/mips/mm/tlbex.c | 6 ++-- arch/mips/oprofile/Makefile | 4 +-- arch/mips/oprofile/common.c | 4 +-- drivers/gpio/Kconfig | 2 +- drivers/gpio/gpio-loongson.c | 2 +- include/drm/drm_cache.h | 2 +- 35 files changed, 89 insertions(+), 89 deletions(-) diff --git a/arch/mips/Kconfig b/arch/mips/Kconfig index d50fafd7bf3a..cbc76f00d1fc 100644 --- a/arch/mips/Kconfig +++ b/arch/mips/Kconfig @@ -1367,9 +1367,9 @@ choice prompt "CPU type" default CPU_R4X00 -config CPU_LOONGSON3 - bool "Loongson 3 CPU" - depends on SYS_HAS_CPU_LOONGSON3 +config CPU_LOONGSON64 + bool "Loongson GSx64 Family CPU" + depends on SYS_HAS_CPU_LOONGSON64 select ARCH_HAS_PHYS_TO_DMA select CPU_SUPPORTS_64BIT_KERNEL select CPU_SUPPORTS_HIGHMEM @@ -1382,15 +1382,15 @@ config CPU_LOONGSON3 select GPIOLIB select SWIOTLB help - The Loongson 3 processor implements the MIPS64R2 instruction - set with many extensions. + The Loongson GSx64 Family cores including Loongson-3A/3B/2series-soc + implements the MIPS64R2 instruction set with many extensions. config LOONGSON3_ENHANCEMENT bool "New Loongson 3 CPU Enhancements" default n select CPU_MIPSR2 select CPU_HAS_PREFETCH - depends on CPU_LOONGSON3 + depends on CPU_LOONGSON64 help New Loongson 3 CPU (since Loongson-3A R2, as opposed to Loongson-3A R1, Loongson-3B R1 and Loongson-3B R2) has many enhancements, such as @@ -1406,7 +1406,7 @@ config LOONGSON3_ENHANCEMENT config CPU_LOONGSON3_WORKAROUNDS bool "Old Loongson 3 LLSC Workarounds" default y if SMP - depends on CPU_LOONGSON3 + depends on CPU_LOONGSON64 help Loongson 3 processors have the llsc issues which require workarounds. Without workarounds the system may hang unexpectedly. @@ -1421,7 +1421,7 @@ config CPU_LOONGSON3_WORKAROUNDS config CPU_LOONGSON2E bool "Loongson 2E" depends on SYS_HAS_CPU_LOONGSON2E - select CPU_LOONGSON2 + select CPU_LOONGSON2EF help The Loongson 2E processor implements the MIPS III instruction set with many extensions. @@ -1432,7 +1432,7 @@ config CPU_LOONGSON2E config CPU_LOONGSON2F bool "Loongson 2F" depends on SYS_HAS_CPU_LOONGSON2F - select CPU_LOONGSON2 + select CPU_LOONGSON2EF select GPIOLIB help The Loongson 2F processor implements the MIPS III instruction set @@ -1870,7 +1870,7 @@ config SYS_SUPPORTS_ZBOOT_UART_PROM bool select SYS_SUPPORTS_ZBOOT -config CPU_LOONGSON2 +config CPU_LOONGSON2EF bool select CPU_SUPPORTS_32BIT_KERNEL select CPU_SUPPORTS_64BIT_KERNEL @@ -1913,7 +1913,7 @@ config CPU_BMIPS5000 select SYS_SUPPORTS_HOTPLUG_CPU select CPU_HAS_RIXI -config SYS_HAS_CPU_LOONGSON3 +config SYS_HAS_CPU_LOONGSON64 bool select CPU_SUPPORTS_CPUFREQ select CPU_HAS_RIXI @@ -2183,7 +2183,7 @@ choice config PAGE_SIZE_4KB bool "4kB" - depends on !CPU_LOONGSON2 && !CPU_LOONGSON3 + depends on !CPU_LOONGSON2EF && !CPU_LOONGSON64 help This option select the standard 4kB Linux page size. On some R3000-family processors this is the only available page size. Using @@ -2631,7 +2631,7 @@ config CPU_SUPPORTS_MSA config ARCH_FLATMEM_ENABLE def_bool y - depends on !NUMA && !CPU_LOONGSON2 + depends on !NUMA && !CPU_LOONGSON2EF config ARCH_DISCONTIGMEM_ENABLE bool @@ -2721,7 +2721,7 @@ config NODES_SHIFT config HW_PERF_EVENTS bool "Enable hardware performance counter support for perf events" - depends on PERF_EVENTS && !OPROFILE && (CPU_MIPS32 || CPU_MIPS64 || CPU_R10000 || CPU_SB1 || CPU_CAVIUM_OCTEON || CPU_XLP || CPU_LOONGSON3) + depends on PERF_EVENTS && !OPROFILE && (CPU_MIPS32 || CPU_MIPS64 || CPU_R10000 || CPU_SB1 || CPU_CAVIUM_OCTEON || CPU_XLP || CPU_LOONGSON64) default y help Enable hardware performance counter support for perf events. If diff --git a/arch/mips/include/asm/cop2.h b/arch/mips/include/asm/cop2.h index 63b3468ede4c..6b7396a6a115 100644 --- a/arch/mips/include/asm/cop2.h +++ b/arch/mips/include/asm/cop2.h @@ -33,7 +33,7 @@ extern void nlm_cop2_restore(struct nlm_cop2_state *); #define cop2_present 1 #define cop2_lazy_restore 0 -#elif defined(CONFIG_CPU_LOONGSON3) +#elif defined(CONFIG_CPU_LOONGSON64) #define cop2_present 1 #define cop2_lazy_restore 1 diff --git a/arch/mips/include/asm/cpu-type.h b/arch/mips/include/asm/cpu-type.h index a45af3de075d..3d8911f8252b 100644 --- a/arch/mips/include/asm/cpu-type.h +++ b/arch/mips/include/asm/cpu-type.h @@ -17,11 +17,11 @@ static inline int __pure __get_cpu_type(const int cpu_type) switch (cpu_type) { #if defined(CONFIG_SYS_HAS_CPU_LOONGSON2E) || \ defined(CONFIG_SYS_HAS_CPU_LOONGSON2F) - case CPU_LOONGSON2: + case CPU_LOONGSON2EF: #endif -#ifdef CONFIG_SYS_HAS_CPU_LOONGSON3 - case CPU_LOONGSON3: +#ifdef CONFIG_SYS_HAS_CPU_LOONGSON64 + case CPU_LOONGSON64: #endif #if defined(CONFIG_SYS_HAS_CPU_LOONGSON1B) || \ diff --git a/arch/mips/include/asm/cpu.h b/arch/mips/include/asm/cpu.h index 290369fa44a4..9f30234b2a3d 100644 --- a/arch/mips/include/asm/cpu.h +++ b/arch/mips/include/asm/cpu.h @@ -322,8 +322,8 @@ enum cpu_type_enum { /* * MIPS64 class processors */ - CPU_5KC, CPU_5KE, CPU_20KC, CPU_25KF, CPU_SB1, CPU_SB1A, CPU_LOONGSON2, - CPU_LOONGSON3, CPU_CAVIUM_OCTEON, CPU_CAVIUM_OCTEON_PLUS, + CPU_5KC, CPU_5KE, CPU_20KC, CPU_25KF, CPU_SB1, CPU_SB1A, CPU_LOONGSON2EF, + CPU_LOONGSON64, CPU_CAVIUM_OCTEON, CPU_CAVIUM_OCTEON_PLUS, CPU_CAVIUM_OCTEON2, CPU_CAVIUM_OCTEON3, CPU_XLR, CPU_XLP, CPU_I6500, CPU_QEMU_GENERIC, diff --git a/arch/mips/include/asm/hazards.h b/arch/mips/include/asm/hazards.h index 0fa27446869a..a4f48b0f5541 100644 --- a/arch/mips/include/asm/hazards.h +++ b/arch/mips/include/asm/hazards.h @@ -158,7 +158,7 @@ do { \ } while (0) #elif defined(CONFIG_MIPS_ALCHEMY) || defined(CONFIG_CPU_CAVIUM_OCTEON) || \ - defined(CONFIG_CPU_LOONGSON2) || defined(CONFIG_LOONGSON3_ENHANCEMENT) || \ + defined(CONFIG_CPU_LOONGSON2EF) || defined(CONFIG_LOONGSON3_ENHANCEMENT) || \ defined(CONFIG_CPU_R10000) || defined(CONFIG_CPU_R5500) || defined(CONFIG_CPU_XLR) /* diff --git a/arch/mips/include/asm/io.h b/arch/mips/include/asm/io.h index 97a280640daf..173801d04faa 100644 --- a/arch/mips/include/asm/io.h +++ b/arch/mips/include/asm/io.h @@ -317,7 +317,7 @@ static inline void iounmap(const volatile void __iomem *addr) #undef __IS_KSEG1 } -#if defined(CONFIG_CPU_CAVIUM_OCTEON) || defined(CONFIG_CPU_LOONGSON3) +#if defined(CONFIG_CPU_CAVIUM_OCTEON) || defined(CONFIG_CPU_LOONGSON64) #define war_io_reorder_wmb() wmb() #else #define war_io_reorder_wmb() barrier() diff --git a/arch/mips/include/asm/irqflags.h b/arch/mips/include/asm/irqflags.h index f0b862a83816..4d742acf2be0 100644 --- a/arch/mips/include/asm/irqflags.h +++ b/arch/mips/include/asm/irqflags.h @@ -41,7 +41,7 @@ static inline unsigned long arch_local_irq_save(void) " .set push \n" " .set reorder \n" " .set noat \n" -#if defined(CONFIG_CPU_LOONGSON3) || defined (CONFIG_CPU_LOONGSON1) +#if defined(CONFIG_CPU_LOONGSON64) || defined (CONFIG_CPU_LOONGSON1) " mfc0 %[flags], $12 \n" " di \n" #else diff --git a/arch/mips/include/asm/mach-loongson64/cpu-feature-overrides.h b/arch/mips/include/asm/mach-loongson64/cpu-feature-overrides.h index 581915ce231c..153b6042e174 100644 --- a/arch/mips/include/asm/mach-loongson64/cpu-feature-overrides.h +++ b/arch/mips/include/asm/mach-loongson64/cpu-feature-overrides.h @@ -45,7 +45,7 @@ #define cpu_has_watch 1 #define cpu_has_local_ebase 0 -#ifdef CONFIG_CPU_LOONGSON3 +#ifdef CONFIG_CPU_LOONGSON64 #define cpu_has_wsbh 1 #define cpu_has_ic_fills_f_dc 1 #define cpu_hwrena_impl_bits 0xc0000000 diff --git a/arch/mips/include/asm/mach-loongson64/irq.h b/arch/mips/include/asm/mach-loongson64/irq.h index be9f727a9328..557e069c400c 100644 --- a/arch/mips/include/asm/mach-loongson64/irq.h +++ b/arch/mips/include/asm/mach-loongson64/irq.h @@ -4,7 +4,7 @@ #include -#ifdef CONFIG_CPU_LOONGSON3 +#ifdef CONFIG_CPU_LOONGSON64 /* cpu core interrupt numbers */ #define MIPS_CPU_IRQ_BASE 56 diff --git a/arch/mips/include/asm/mach-loongson64/kernel-entry-init.h b/arch/mips/include/asm/mach-loongson64/kernel-entry-init.h index b5e288a12dfe..74d94fc1ed53 100644 --- a/arch/mips/include/asm/mach-loongson64/kernel-entry-init.h +++ b/arch/mips/include/asm/mach-loongson64/kernel-entry-init.h @@ -17,7 +17,7 @@ * Override macros used in arch/mips/kernel/head.S. */ .macro kernel_entry_setup -#ifdef CONFIG_CPU_LOONGSON3 +#ifdef CONFIG_CPU_LOONGSON64 .set push .set mips64 /* Set LPA on LOONGSON3 config3 */ @@ -46,7 +46,7 @@ * Do SMP slave processor setup. */ .macro smp_slave_setup -#ifdef CONFIG_CPU_LOONGSON3 +#ifdef CONFIG_CPU_LOONGSON64 .set push .set mips64 /* Set LPA on LOONGSON3 config3 */ diff --git a/arch/mips/include/asm/mach-loongson64/loongson.h b/arch/mips/include/asm/mach-loongson64/loongson.h index 694a58574ec0..40a24b76b874 100644 --- a/arch/mips/include/asm/mach-loongson64/loongson.h +++ b/arch/mips/include/asm/mach-loongson64/loongson.h @@ -109,7 +109,7 @@ static inline void do_perfcnt_IRQ(void) #define LOONGSON_PCICFG_SIZE 0x00000800 /* 2K */ #define LOONGSON_PCICFG_TOP (LOONGSON_PCICFG_BASE+LOONGSON_PCICFG_SIZE-1) -#ifdef CONFIG_CPU_LOONGSON3 +#ifdef CONFIG_CPU_LOONGSON64 #define LOONGSON_PCIIO_BASE loongson_sysconf.pci_io_base #else #define LOONGSON_PCIIO_BASE 0x1fd00000 diff --git a/arch/mips/include/asm/mach-loongson64/pci.h b/arch/mips/include/asm/mach-loongson64/pci.h index 97f807fb2117..05cc9052772f 100644 --- a/arch/mips/include/asm/mach-loongson64/pci.h +++ b/arch/mips/include/asm/mach-loongson64/pci.h @@ -35,7 +35,7 @@ extern struct pci_ops loongson_pci_ops; #else /* loongson2f/32bit & loongson2e */ /* this pci memory space is mapped by pcimap in pci.c */ -#ifdef CONFIG_CPU_LOONGSON3 +#ifdef CONFIG_CPU_LOONGSON64 #define LOONGSON_PCI_MEM_START 0x40000000UL #define LOONGSON_PCI_MEM_END 0x7effffffUL #else diff --git a/arch/mips/include/asm/module.h b/arch/mips/include/asm/module.h index 6dc0b21b8acd..2e5aee37bade 100644 --- a/arch/mips/include/asm/module.h +++ b/arch/mips/include/asm/module.h @@ -127,10 +127,10 @@ search_module_dbetables(unsigned long addr) #define MODULE_PROC_FAMILY "SB1 " #elif defined CONFIG_CPU_LOONGSON1 #define MODULE_PROC_FAMILY "LOONGSON1 " -#elif defined CONFIG_CPU_LOONGSON2 -#define MODULE_PROC_FAMILY "LOONGSON2 " -#elif defined CONFIG_CPU_LOONGSON3 -#define MODULE_PROC_FAMILY "LOONGSON3 " +#elif defined CONFIG_CPU_LOONGSON2EF +#define MODULE_PROC_FAMILY "LOONGSON2EF " +#elif defined CONFIG_CPU_LOONGSON64 +#define MODULE_PROC_FAMILY "LOONGSON64 " #elif defined CONFIG_CPU_CAVIUM_OCTEON #define MODULE_PROC_FAMILY "OCTEON " #elif defined CONFIG_CPU_XLR diff --git a/arch/mips/include/asm/pgtable-bits.h b/arch/mips/include/asm/pgtable-bits.h index f88a48cd68b2..9807f05945fc 100644 --- a/arch/mips/include/asm/pgtable-bits.h +++ b/arch/mips/include/asm/pgtable-bits.h @@ -216,7 +216,7 @@ static inline uint64_t pte_to_entrylo(unsigned long pte_val) #define _CACHE_CACHABLE_NONCOHERENT (5<<_CACHE_SHIFT) -#elif defined(CONFIG_CPU_LOONGSON3) +#elif defined(CONFIG_CPU_LOONGSON64) /* Using COHERENT flag for NONCOHERENT doesn't hurt. */ diff --git a/arch/mips/include/asm/processor.h b/arch/mips/include/asm/processor.h index aca909bd7841..684efaa990ee 100644 --- a/arch/mips/include/asm/processor.h +++ b/arch/mips/include/asm/processor.h @@ -390,7 +390,7 @@ unsigned long get_wchan(struct task_struct *p); #define KSTK_ESP(tsk) (task_pt_regs(tsk)->regs[29]) #define KSTK_STATUS(tsk) (task_pt_regs(tsk)->cp0_status) -#ifdef CONFIG_CPU_LOONGSON3 +#ifdef CONFIG_CPU_LOONGSON64 /* * Loongson-3's SFB (Store-Fill-Buffer) may buffer writes indefinitely when a * tight read loop is executed, because reads take priority over writes & the diff --git a/arch/mips/include/asm/r4kcache.h b/arch/mips/include/asm/r4kcache.h index 7f4a32d3345a..769d8b63f9fa 100644 --- a/arch/mips/include/asm/r4kcache.h +++ b/arch/mips/include/asm/r4kcache.h @@ -67,7 +67,7 @@ static inline void flush_scache_line_indexed(unsigned long addr) static inline void flush_icache_line(unsigned long addr) { switch (boot_cpu_type()) { - case CPU_LOONGSON2: + case CPU_LOONGSON2EF: cache_op(Hit_Invalidate_I_Loongson2, addr); break; @@ -149,7 +149,7 @@ static inline void flush_scache_line(unsigned long addr) static inline int protected_flush_icache_line(unsigned long addr) { switch (boot_cpu_type()) { - case CPU_LOONGSON2: + case CPU_LOONGSON2EF: return protected_cache_op(Hit_Invalidate_I_Loongson2, addr); default: diff --git a/arch/mips/kernel/cpu-probe.c b/arch/mips/kernel/cpu-probe.c index 9635c1db3ae6..b0517bfc2100 100644 --- a/arch/mips/kernel/cpu-probe.c +++ b/arch/mips/kernel/cpu-probe.c @@ -608,7 +608,7 @@ static int set_ftlb_enable(struct cpuinfo_mips *c, enum ftlb_flags flags) if (!(flags & FTLB_EN)) return 1; return 0; - case CPU_LOONGSON3: + case CPU_LOONGSON64: /* Flush ITLB, DTLB, VTLB and FTLB */ write_c0_diag(LOONGSON_DIAG_ITLB | LOONGSON_DIAG_DTLB | LOONGSON_DIAG_VTLB | LOONGSON_DIAG_FTLB); @@ -1555,28 +1555,28 @@ static inline void cpu_probe_legacy(struct cpuinfo_mips *c, unsigned int cpu) case PRID_IMP_LOONGSON_64: /* Loongson-2/3 */ switch (c->processor_id & PRID_REV_MASK) { case PRID_REV_LOONGSON2E: - c->cputype = CPU_LOONGSON2; + c->cputype = CPU_LOONGSON2EF; __cpu_name[cpu] = "ICT Loongson-2"; set_elf_platform(cpu, "loongson2e"); set_isa(c, MIPS_CPU_ISA_III); c->fpu_msk31 |= FPU_CSR_CONDX; break; case PRID_REV_LOONGSON2F: - c->cputype = CPU_LOONGSON2; + c->cputype = CPU_LOONGSON2EF; __cpu_name[cpu] = "ICT Loongson-2"; set_elf_platform(cpu, "loongson2f"); set_isa(c, MIPS_CPU_ISA_III); c->fpu_msk31 |= FPU_CSR_CONDX; break; case PRID_REV_LOONGSON3A_R1: - c->cputype = CPU_LOONGSON3; + c->cputype = CPU_LOONGSON64; __cpu_name[cpu] = "ICT Loongson-3"; set_elf_platform(cpu, "loongson3a"); set_isa(c, MIPS_CPU_ISA_M64R1); break; case PRID_REV_LOONGSON3B_R1: case PRID_REV_LOONGSON3B_R2: - c->cputype = CPU_LOONGSON3; + c->cputype = CPU_LOONGSON64; __cpu_name[cpu] = "ICT Loongson-3"; set_elf_platform(cpu, "loongson3b"); set_isa(c, MIPS_CPU_ISA_M64R1); @@ -1929,14 +1929,14 @@ static inline void cpu_probe_loongson(struct cpuinfo_mips *c, unsigned int cpu) switch (c->processor_id & PRID_REV_MASK) { case PRID_REV_LOONGSON3A_R2_0: case PRID_REV_LOONGSON3A_R2_1: - c->cputype = CPU_LOONGSON3; + c->cputype = CPU_LOONGSON64; __cpu_name[cpu] = "ICT Loongson-3"; set_elf_platform(cpu, "loongson3a"); set_isa(c, MIPS_CPU_ISA_M64R2); break; case PRID_REV_LOONGSON3A_R3_0: case PRID_REV_LOONGSON3A_R3_1: - c->cputype = CPU_LOONGSON3; + c->cputype = CPU_LOONGSON64; __cpu_name[cpu] = "ICT Loongson-3"; set_elf_platform(cpu, "loongson3a"); set_isa(c, MIPS_CPU_ISA_M64R2); diff --git a/arch/mips/kernel/idle.c b/arch/mips/kernel/idle.c index 7388f1374d5f..2524da19fafb 100644 --- a/arch/mips/kernel/idle.c +++ b/arch/mips/kernel/idle.c @@ -179,7 +179,7 @@ void __init check_wait(void) case CPU_XLP: cpu_wait = r4k_wait; break; - case CPU_LOONGSON3: + case CPU_LOONGSON64: if ((c->processor_id & PRID_REV_MASK) >= PRID_REV_LOONGSON3A_R2_0) cpu_wait = r4k_wait; break; diff --git a/arch/mips/kernel/perf_event_mipsxx.c b/arch/mips/kernel/perf_event_mipsxx.c index a3e2da8391ea..0af456a94916 100644 --- a/arch/mips/kernel/perf_event_mipsxx.c +++ b/arch/mips/kernel/perf_event_mipsxx.c @@ -1623,7 +1623,7 @@ static const struct mips_perf_event *mipsxx_pmu_map_raw_event(u64 config) raw_event.cntr_mask = raw_id > 127 ? CNTR_ODD : CNTR_EVEN; break; - case CPU_LOONGSON3: + case CPU_LOONGSON64: raw_event.cntr_mask = raw_id > 127 ? CNTR_ODD : CNTR_EVEN; break; } @@ -1769,7 +1769,7 @@ init_hw_perf_events(void) mipspmu.general_event_map = &mipsxxcore_event_map; mipspmu.cache_event_map = &mipsxxcore_cache_map; break; - case CPU_LOONGSON3: + case CPU_LOONGSON64: mipspmu.name = "mips/loongson3"; mipspmu.general_event_map = &loongson3_event_map; mipspmu.cache_event_map = &loongson3_cache_map; diff --git a/arch/mips/kernel/setup.c b/arch/mips/kernel/setup.c index ceef8240f171..3765893824f3 100644 --- a/arch/mips/kernel/setup.c +++ b/arch/mips/kernel/setup.c @@ -282,7 +282,7 @@ static unsigned long __init init_initrd(void) * Initialize the bootmem allocator. It also setup initrd related data * if needed. */ -#if defined(CONFIG_SGI_IP27) || (defined(CONFIG_CPU_LOONGSON3) && defined(CONFIG_NUMA)) +#if defined(CONFIG_SGI_IP27) || (defined(CONFIG_CPU_LOONGSON64) && defined(CONFIG_NUMA)) static void __init bootmem_init(void) { diff --git a/arch/mips/kernel/traps.c b/arch/mips/kernel/traps.c index 342e41de9d64..0c2570e6fcf6 100644 --- a/arch/mips/kernel/traps.c +++ b/arch/mips/kernel/traps.c @@ -2394,7 +2394,7 @@ void __init trap_init(void) else { if (cpu_has_vtag_icache) set_except_vector(EXCCODE_RI, handle_ri_rdhwr_tlbp); - else if (current_cpu_type() == CPU_LOONGSON3) + else if (current_cpu_type() == CPU_LOONGSON64) set_except_vector(EXCCODE_RI, handle_ri_rdhwr_tlbp); else set_except_vector(EXCCODE_RI, handle_ri_rdhwr); diff --git a/arch/mips/lib/csum_partial.S b/arch/mips/lib/csum_partial.S index 2ff84f4b1717..fda7b57b826e 100644 --- a/arch/mips/lib/csum_partial.S +++ b/arch/mips/lib/csum_partial.S @@ -279,7 +279,7 @@ EXPORT_SYMBOL(csum_partial) #endif /* odd buffer alignment? */ -#if defined(CONFIG_CPU_MIPSR2) || defined(CONFIG_CPU_LOONGSON3) +#if defined(CONFIG_CPU_MIPSR2) || defined(CONFIG_CPU_LOONGSON64) .set push .set arch=mips32r2 wsbh v1, sum @@ -732,7 +732,7 @@ EXPORT_SYMBOL(csum_partial) addu sum, v1 #endif -#if defined(CONFIG_CPU_MIPSR2) || defined(CONFIG_CPU_LOONGSON3) +#if defined(CONFIG_CPU_MIPSR2) || defined(CONFIG_CPU_LOONGSON64) .set push .set arch=mips32r2 wsbh v1, sum diff --git a/arch/mips/loongson64/Kconfig b/arch/mips/loongson64/Kconfig index 4c14a11525f4..d08b20ff2b27 100644 --- a/arch/mips/loongson64/Kconfig +++ b/arch/mips/loongson64/Kconfig @@ -79,7 +79,7 @@ config LOONGSON_MACH3X select I8259 select IRQ_MIPS_CPU select NR_CPUS_DEFAULT_4 - select SYS_HAS_CPU_LOONGSON3 + select SYS_HAS_CPU_LOONGSON64 select SYS_HAS_EARLY_PRINTK select SYS_SUPPORTS_SMP select SYS_SUPPORTS_HOTPLUG_CPU diff --git a/arch/mips/loongson64/Makefile b/arch/mips/loongson64/Makefile index 1a5df773707d..c74bc0251e9d 100644 --- a/arch/mips/loongson64/Makefile +++ b/arch/mips/loongson64/Makefile @@ -21,4 +21,4 @@ obj-$(CONFIG_LEMOTE_MACH2F) += lemote-2f/ # All Loongson-3 family machines # -obj-$(CONFIG_CPU_LOONGSON3) += loongson-3/ +obj-$(CONFIG_CPU_LOONGSON64) += loongson-3/ diff --git a/arch/mips/loongson64/Platform b/arch/mips/loongson64/Platform index c1a4d4dc4665..b4d2582eb1ef 100644 --- a/arch/mips/loongson64/Platform +++ b/arch/mips/loongson64/Platform @@ -3,7 +3,7 @@ # # Only gcc >= 4.4 have Loongson specific support -cflags-$(CONFIG_CPU_LOONGSON2) += -Wa,--trap +cflags-$(CONFIG_CPU_LOONGSON2EF) += -Wa,--trap cflags-$(CONFIG_CPU_LOONGSON2E) += \ $(call cc-option,-march=loongson2e,-march=r4600) cflags-$(CONFIG_CPU_LOONGSON2F) += \ @@ -22,7 +22,7 @@ ifdef CONFIG_CPU_LOONGSON2F_WORKAROUNDS endif endif -cflags-$(CONFIG_CPU_LOONGSON3) += -Wa,--trap +cflags-$(CONFIG_CPU_LOONGSON64) += -Wa,--trap # # Some versions of binutils, not currently mainline as of 2019/02/04, support @@ -44,7 +44,7 @@ cflags-$(CONFIG_CPU_LOONGSON3) += -Wa,--trap # binutils does not merge support for the flag then we can revisit & remove # this later - for now it ensures vendor toolchains don't cause problems. # -cflags-$(CONFIG_CPU_LOONGSON3) += $(call as-option,-Wa$(comma)-mno-fix-loongson3-llsc,) +cflags-$(CONFIG_CPU_LOONGSON64) += $(call as-option,-Wa$(comma)-mno-fix-loongson3-llsc,) # # binutils from v2.25 on and gcc starting from v4.9.0 treat -march=loongson3a @@ -55,14 +55,14 @@ cflags-$(CONFIG_CPU_LOONGSON3) += $(call as-option,-Wa$(comma)-mno-fix-loongson3 # ifeq ($(call cc-ifversion, -ge, 0409, y), y) ifeq ($(call ld-ifversion, -ge, 225000000, y), y) - cflags-$(CONFIG_CPU_LOONGSON3) += \ + cflags-$(CONFIG_CPU_LOONGSON64) += \ $(call cc-option,-march=loongson3a -U_MIPS_ISA -D_MIPS_ISA=_MIPS_ISA_MIPS64) else - cflags-$(CONFIG_CPU_LOONGSON3) += \ + cflags-$(CONFIG_CPU_LOONGSON64) += \ $(call cc-option,-march=mips64r2,-mips64r2 -U_MIPS_ISA -D_MIPS_ISA=_MIPS_ISA_MIPS64) endif else - cflags-$(CONFIG_CPU_LOONGSON3) += \ + cflags-$(CONFIG_CPU_LOONGSON64) += \ $(call cc-option,-march=mips64r2,-mips64r2 -U_MIPS_ISA -D_MIPS_ISA=_MIPS_ISA_MIPS64) endif diff --git a/arch/mips/loongson64/common/pci.c b/arch/mips/loongson64/common/pci.c index c47bb7bf3aa4..2d9755c49524 100644 --- a/arch/mips/loongson64/common/pci.c +++ b/arch/mips/loongson64/common/pci.c @@ -87,7 +87,7 @@ static int __init pcibios_init(void) #endif register_pci_controller(&loongson_pci_controller); -#ifdef CONFIG_CPU_LOONGSON3 +#ifdef CONFIG_CPU_LOONGSON64 sbx00_acpi_init(); #endif diff --git a/arch/mips/mm/c-r4k.c b/arch/mips/mm/c-r4k.c index 5166e38cd1c6..38ed99b605a4 100644 --- a/arch/mips/mm/c-r4k.c +++ b/arch/mips/mm/c-r4k.c @@ -320,7 +320,7 @@ static void r4k_blast_icache_page_setup(void) r4k_blast_icache_page = (void *)cache_noop; else if (ic_lsize == 16) r4k_blast_icache_page = blast_icache16_page; - else if (ic_lsize == 32 && current_cpu_type() == CPU_LOONGSON2) + else if (ic_lsize == 32 && current_cpu_type() == CPU_LOONGSON2EF) r4k_blast_icache_page = loongson2_blast_icache32_page; else if (ic_lsize == 32) r4k_blast_icache_page = blast_icache32_page; @@ -369,7 +369,7 @@ static void r4k_blast_icache_page_indexed_setup(void) else if (TX49XX_ICACHE_INDEX_INV_WAR) r4k_blast_icache_page_indexed = tx49_blast_icache32_page_indexed; - else if (current_cpu_type() == CPU_LOONGSON2) + else if (current_cpu_type() == CPU_LOONGSON2EF) r4k_blast_icache_page_indexed = loongson2_blast_icache32_page_indexed; else @@ -395,7 +395,7 @@ static void r4k_blast_icache_setup(void) r4k_blast_icache = blast_r4600_v1_icache32; else if (TX49XX_ICACHE_INDEX_INV_WAR) r4k_blast_icache = tx49_blast_icache32; - else if (current_cpu_type() == CPU_LOONGSON2) + else if (current_cpu_type() == CPU_LOONGSON2EF) r4k_blast_icache = loongson2_blast_icache32; else r4k_blast_icache = blast_icache32; @@ -465,7 +465,7 @@ static void r4k_blast_scache_node_setup(void) { unsigned long sc_lsize = cpu_scache_line_size(); - if (current_cpu_type() != CPU_LOONGSON3) + if (current_cpu_type() != CPU_LOONGSON64) r4k_blast_scache_node = (void *)cache_noop; else if (sc_lsize == 16) r4k_blast_scache_node = blast_scache16_node; @@ -480,7 +480,7 @@ static void r4k_blast_scache_node_setup(void) static inline void local_r4k___flush_cache_all(void * args) { switch (current_cpu_type()) { - case CPU_LOONGSON2: + case CPU_LOONGSON2EF: case CPU_R4000SC: case CPU_R4000MC: case CPU_R4400SC: @@ -497,7 +497,7 @@ static inline void local_r4k___flush_cache_all(void * args) r4k_blast_scache(); break; - case CPU_LOONGSON3: + case CPU_LOONGSON64: /* Use get_ebase_cpunum() for both NUMA=y/n */ r4k_blast_scache_node(get_ebase_cpunum() >> 2); break; @@ -770,7 +770,7 @@ static inline void __local_r4k_flush_icache_range(unsigned long start, r4k_blast_icache(); else { switch (boot_cpu_type()) { - case CPU_LOONGSON2: + case CPU_LOONGSON2EF: protected_loongson2_blast_icache_range(start, end); break; @@ -863,7 +863,7 @@ static void r4k_dma_cache_wback_inv(unsigned long addr, unsigned long size) preempt_disable(); if (cpu_has_inclusive_pcaches) { if (size >= scache_size) { - if (current_cpu_type() != CPU_LOONGSON3) + if (current_cpu_type() != CPU_LOONGSON64) r4k_blast_scache(); else r4k_blast_scache_node(pa_to_nid(addr)); @@ -904,7 +904,7 @@ static void r4k_dma_cache_inv(unsigned long addr, unsigned long size) preempt_disable(); if (cpu_has_inclusive_pcaches) { if (size >= scache_size) { - if (current_cpu_type() != CPU_LOONGSON3) + if (current_cpu_type() != CPU_LOONGSON64) r4k_blast_scache(); else r4k_blast_scache_node(pa_to_nid(addr)); @@ -1226,7 +1226,7 @@ static void probe_pcache(void) c->options |= MIPS_CPU_PREFETCH; break; - case CPU_LOONGSON2: + case CPU_LOONGSON2EF: icache_size = 1 << (12 + ((config & CONF_IC) >> 9)); c->icache.linesz = 16 << ((config & CONF_IB) >> 5); if (prid & 0x3) @@ -1244,7 +1244,7 @@ static void probe_pcache(void) c->dcache.waybit = 0; break; - case CPU_LOONGSON3: + case CPU_LOONGSON64: config1 = read_c0_config1(); lsize = (config1 >> 19) & 7; if (lsize) @@ -1454,7 +1454,7 @@ static void probe_pcache(void) c->dcache.flags &= ~MIPS_CACHE_ALIASES; break; - case CPU_LOONGSON2: + case CPU_LOONGSON2EF: /* * LOONGSON2 has 4 way icache, but when using indexed cache op, * one op will act on all 4 ways @@ -1480,7 +1480,7 @@ static void probe_vcache(void) struct cpuinfo_mips *c = ¤t_cpu_data; unsigned int config2, lsize; - if (current_cpu_type() != CPU_LOONGSON3) + if (current_cpu_type() != CPU_LOONGSON64) return; config2 = read_c0_config2(); @@ -1655,11 +1655,11 @@ static void setup_scache(void) #endif return; - case CPU_LOONGSON2: + case CPU_LOONGSON2EF: loongson2_sc_init(); return; - case CPU_LOONGSON3: + case CPU_LOONGSON64: loongson3_sc_init(); return; @@ -1928,7 +1928,7 @@ void r4k_cache_init(void) /* Optimization: an L2 flush implicitly flushes the L1 */ current_cpu_data.options |= MIPS_CPU_INCLUSIVE_CACHES; break; - case CPU_LOONGSON3: + case CPU_LOONGSON64: /* Loongson-3 maintains cache coherency by hardware */ __flush_cache_all = cache_noop; __flush_cache_vmap = cache_noop; diff --git a/arch/mips/mm/page.c b/arch/mips/mm/page.c index 56e4f8bffd4c..c5578897a4fa 100644 --- a/arch/mips/mm/page.c +++ b/arch/mips/mm/page.c @@ -187,7 +187,7 @@ static void set_prefetch_parameters(void) } break; - case CPU_LOONGSON3: + case CPU_LOONGSON64: /* Loongson-3 only support the Pref_Load/Pref_Store. */ pref_bias_clear_store = 128; pref_bias_copy_load = 128; diff --git a/arch/mips/mm/tlb-r4k.c b/arch/mips/mm/tlb-r4k.c index c13e46ced425..83b450ddbbc2 100644 --- a/arch/mips/mm/tlb-r4k.c +++ b/arch/mips/mm/tlb-r4k.c @@ -35,10 +35,10 @@ extern void build_tlb_refill_handler(void); static inline void flush_micro_tlb(void) { switch (current_cpu_type()) { - case CPU_LOONGSON2: + case CPU_LOONGSON2EF: write_c0_diag(LOONGSON_DIAG_ITLB); break; - case CPU_LOONGSON3: + case CPU_LOONGSON64: write_c0_diag(LOONGSON_DIAG_ITLB | LOONGSON_DIAG_DTLB); break; default: diff --git a/arch/mips/mm/tlbex.c b/arch/mips/mm/tlbex.c index 144ceb0fba88..05e64217842e 100644 --- a/arch/mips/mm/tlbex.c +++ b/arch/mips/mm/tlbex.c @@ -572,8 +572,8 @@ void build_tlb_write_entry(u32 **p, struct uasm_label **l, case CPU_BMIPS4350: case CPU_BMIPS4380: case CPU_BMIPS5000: - case CPU_LOONGSON2: - case CPU_LOONGSON3: + case CPU_LOONGSON2EF: + case CPU_LOONGSON64: case CPU_R5500: if (m4kc_tlbp_war()) uasm_i_nop(p); @@ -1372,7 +1372,7 @@ static void build_r4000_tlb_refill_handler(void) switch (boot_cpu_type()) { default: if (sizeof(long) == 4) { - case CPU_LOONGSON2: + case CPU_LOONGSON2EF: /* Loongson2 ebase is different than r4k, we have more space */ if ((p - tlb_handler) > 64) panic("TLB refill handler space exceeded"); diff --git a/arch/mips/oprofile/Makefile b/arch/mips/oprofile/Makefile index 011cf9f891e7..e10f216d0422 100644 --- a/arch/mips/oprofile/Makefile +++ b/arch/mips/oprofile/Makefile @@ -14,5 +14,5 @@ oprofile-$(CONFIG_CPU_MIPS64) += op_model_mipsxx.o oprofile-$(CONFIG_CPU_R10000) += op_model_mipsxx.o oprofile-$(CONFIG_CPU_SB1) += op_model_mipsxx.o oprofile-$(CONFIG_CPU_XLR) += op_model_mipsxx.o -oprofile-$(CONFIG_CPU_LOONGSON2) += op_model_loongson2.o -oprofile-$(CONFIG_CPU_LOONGSON3) += op_model_loongson3.o +oprofile-$(CONFIG_CPU_LOONGSON2EF) += op_model_loongson2.o +oprofile-$(CONFIG_CPU_LOONGSON64) += op_model_loongson3.o diff --git a/arch/mips/oprofile/common.c b/arch/mips/oprofile/common.c index 2f33992f6dff..25cfa70f0ae4 100644 --- a/arch/mips/oprofile/common.c +++ b/arch/mips/oprofile/common.c @@ -104,10 +104,10 @@ int __init oprofile_arch_init(struct oprofile_operations *ops) lmodel = &op_model_mipsxx_ops; break; - case CPU_LOONGSON2: + case CPU_LOONGSON2EF: lmodel = &op_model_loongson2_ops; break; - case CPU_LOONGSON3: + case CPU_LOONGSON64: lmodel = &op_model_loongson3_ops; break; }; diff --git a/drivers/gpio/Kconfig b/drivers/gpio/Kconfig index bb13c266c329..6ed3f380a45e 100644 --- a/drivers/gpio/Kconfig +++ b/drivers/gpio/Kconfig @@ -298,7 +298,7 @@ config GPIO_IXP4XX config GPIO_LOONGSON bool "Loongson-2/3 GPIO support" - depends on CPU_LOONGSON2 || CPU_LOONGSON3 + depends on CPU_LOONGSON2EF || CPU_LOONGSON64 help driver for GPIO functionality on Loongson-2F/3A/3B processors. diff --git a/drivers/gpio/gpio-loongson.c b/drivers/gpio/gpio-loongson.c index 00943170ce36..a42145873cc9 100644 --- a/drivers/gpio/gpio-loongson.c +++ b/drivers/gpio/gpio-loongson.c @@ -22,7 +22,7 @@ #define STLS2F_N_GPIO 4 #define STLS3A_N_GPIO 16 -#ifdef CONFIG_CPU_LOONGSON3 +#ifdef CONFIG_CPU_LOONGSON64 #define LOONGSON_N_GPIO STLS3A_N_GPIO #else #define LOONGSON_N_GPIO STLS2F_N_GPIO diff --git a/include/drm/drm_cache.h b/include/drm/drm_cache.h index 987ff16b9420..e9ad4863d915 100644 --- a/include/drm/drm_cache.h +++ b/include/drm/drm_cache.h @@ -45,7 +45,7 @@ static inline bool drm_arch_can_wc_memory(void) { #if defined(CONFIG_PPC) && !defined(CONFIG_NOT_COHERENT_CACHE) return false; -#elif defined(CONFIG_MIPS) && defined(CONFIG_CPU_LOONGSON3) +#elif defined(CONFIG_MIPS) && defined(CONFIG_CPU_LOONGSON64) return false; #elif defined(CONFIG_ARM) || defined(CONFIG_ARM64) /* From patchwork Tue Aug 27 08:52:51 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Jiaxun Yang X-Patchwork-Id: 11116413 Return-Path: Received: from mail.kernel.org (pdx-korg-mail-1.web.codeaurora.org [172.30.200.123]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id 114F31399 for ; Tue, 27 Aug 2019 08:54:21 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.kernel.org (Postfix) with ESMTP id A9A242173E for ; Tue, 27 Aug 2019 08:54:20 +0000 (UTC) Authentication-Results: mail.kernel.org; dkim=pass (1024-bit key) header.d=flygoat.com header.i=@flygoat.com header.b="P9jT3t2T" Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1729493AbfH0IyU (ORCPT ); Tue, 27 Aug 2019 04:54:20 -0400 Received: from forward101o.mail.yandex.net ([37.140.190.181]:59265 "EHLO forward101o.mail.yandex.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1728999AbfH0IyT (ORCPT ); Tue, 27 Aug 2019 04:54:19 -0400 Received: from mxback12j.mail.yandex.net (mxback12j.mail.yandex.net [IPv6:2a02:6b8:0:1619::87]) by forward101o.mail.yandex.net (Yandex) with ESMTP id 86DE73C02213; Tue, 27 Aug 2019 11:53:59 +0300 (MSK) Received: from smtp1p.mail.yandex.net (smtp1p.mail.yandex.net [2a02:6b8:0:1472:2741:0:8b6:6]) by mxback12j.mail.yandex.net (nwsmtp/Yandex) with ESMTP id xZPLybpHUP-rw1iYMdl; Tue, 27 Aug 2019 11:53:59 +0300 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=flygoat.com; s=mail; t=1566896039; bh=CsoeEKAYNLsfsaC+bfVXBTx78Q1mmSh/vUaSOV3DIxc=; h=In-Reply-To:Subject:To:From:Cc:References:Date:Message-Id; b=P9jT3t2TWIdTeQ2XE4RnEYEzFGR6yRERDQNMpBzQZrSKKLtWd13IprtUKb2C9WSk4 lqoX4DjRjPtt9exVrWjiRQBsp0oy/aQr9COFVHds+aI89idN20Mi6feMwGI6Wz6edq 4Q1JxfOMVQFSnefGiozOxHLzY8LYIJbXywUo0N6s= Authentication-Results: mxback12j.mail.yandex.net; dkim=pass header.i=@flygoat.com Received: by smtp1p.mail.yandex.net (nwsmtp/Yandex) with ESMTPSA id JOqUfE8LDO-rntCjp2L; Tue, 27 Aug 2019 11:53:54 +0300 (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits)) (Client certificate not present) From: Jiaxun Yang To: linux-mips@vger.kernel.org Cc: chenhc@lemote.com, paul.burton@mips.com, tglx@linutronix.de, jason@lakedaemon.net, maz@kernel.org, linux-kernel@vger.kernel.org, robh+dt@kernel.org, mark.rutland@arm.co, devicetree@vger.kernel.org, Jiaxun Yang Subject: [PATCH 02/13] MIPS: Loongson64: Sepreate loongson2ef/loongson64 code Date: Tue, 27 Aug 2019 16:52:51 +0800 Message-Id: <20190827085302.5197-3-jiaxun.yang@flygoat.com> X-Mailer: git-send-email 2.22.0 In-Reply-To: <20190827085302.5197-1-jiaxun.yang@flygoat.com> References: <20190827085302.5197-1-jiaxun.yang@flygoat.com> MIME-Version: 1.0 Sender: linux-mips-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-mips@vger.kernel.org As later model of GSx64 family processors including 2-series-soc have similar design with initial loongson3a while loongson2e/f seems less identical, we seprate loongson2e/f support code out of mach-loongson64 to make our life easier. Signed-off-by: Jiaxun Yang --- arch/mips/Kbuild.platforms | 1 + arch/mips/Kconfig | 51 +++++-- arch/mips/include/asm/bootinfo.h | 1 - .../mach-loongson2ef/cpu-feature-overrides.h | 45 +++++++ .../cs5536/cs5536.h | 0 .../cs5536/cs5536_mfgpt.h | 0 .../cs5536/cs5536_pci.h | 0 .../cs5536/cs5536_vsm.h | 0 .../loongson2ef.h} | 29 +--- .../machine.h | 6 - .../mc146818rtc.h | 5 +- .../mem.h | 6 +- arch/mips/include/asm/mach-loongson2ef/pci.h | 43 ++++++ .../include/asm/mach-loongson2ef/spaces.h | 10 ++ .../mach-loongson64/cpu-feature-overrides.h | 3 - arch/mips/include/asm/mach-loongson64/irq.h | 7 +- .../asm/mach-loongson64/kernel-entry-init.h | 74 ---------- .../include/asm/mach-loongson64/loongson64.h | 48 +++++++ .../mips/include/asm/mach-loongson64/mmzone.h | 16 --- arch/mips/include/asm/mach-loongson64/pci.h | 41 +----- .../include/asm/mach-loongson64/workarounds.h | 4 +- arch/mips/loongson2ef/Kconfig | 93 +++++++++++++ arch/mips/loongson2ef/Makefile | 18 +++ arch/mips/loongson2ef/Platform | 32 +++++ .../common/Makefile | 0 .../common/bonito-irq.c | 2 +- .../common/cmdline.c | 2 +- .../common/cs5536/Makefile | 0 .../common/cs5536/cs5536_acc.c | 0 .../common/cs5536/cs5536_ehci.c | 0 .../common/cs5536/cs5536_ide.c | 0 .../common/cs5536/cs5536_isa.c | 0 .../common/cs5536/cs5536_mfgpt.c | 0 .../common/cs5536/cs5536_ohci.c | 0 .../common/cs5536/cs5536_pci.c | 0 .../common/early_printk.c | 2 +- arch/mips/loongson2ef/common/env.c | 71 ++++++++++ .../{loongson64 => loongson2ef}/common/init.c | 7 +- .../{loongson64 => loongson2ef}/common/irq.c | 2 +- .../common/machtype.c | 3 +- .../{loongson64 => loongson2ef}/common/mem.c | 40 +----- .../{loongson64 => loongson2ef}/common/pci.c | 11 +- .../common/platform.c | 0 .../{loongson64 => loongson2ef}/common/pm.c | 2 +- .../common/reset.c | 23 +--- .../{loongson64 => loongson2ef}/common/rtc.c | 0 .../common/serial.c | 37 +---- .../common/setup.c | 2 +- .../{loongson64 => loongson2ef}/common/time.c | 2 +- .../common/uart_base.c | 10 +- .../fuloong-2e/Makefile | 0 .../fuloong-2e/dma.c | 0 .../fuloong-2e/irq.c | 2 +- .../fuloong-2e/reset.c | 2 +- .../lemote-2f/Makefile | 0 .../lemote-2f/clock.c | 2 +- .../lemote-2f/dma.c | 0 .../lemote-2f/ec_kb3310b.c | 0 .../lemote-2f/ec_kb3310b.h | 0 .../lemote-2f/irq.c | 2 +- .../lemote-2f/machtype.c | 2 +- .../lemote-2f/pm.c | 2 +- .../lemote-2f/reset.c | 2 +- arch/mips/loongson64/Kconfig | 126 +----------------- arch/mips/loongson64/Makefile | 23 +--- arch/mips/loongson64/Platform | 26 +--- .../loongson64/{loongson-3 => }/acpi_init.c | 3 +- .../loongson64/{loongson-3 => }/cop2-ex.c | 5 +- arch/mips/loongson64/{loongson-3 => }/dma.c | 6 +- arch/mips/loongson64/{common => }/env.c | 72 +++------- arch/mips/loongson64/{loongson-3 => }/hpet.c | 0 arch/mips/loongson64/{loongson-3 => }/irq.c | 40 +++++- arch/mips/loongson64/loongson-3/Makefile | 11 -- arch/mips/loongson64/{loongson-3 => }/numa.c | 4 +- arch/mips/loongson64/pci.c | 45 +++++++ .../loongson64/{loongson-3 => }/platform.c | 0 arch/mips/loongson64/reset.c | 58 ++++++++ arch/mips/loongson64/setup.c | 92 +++++++++++++ arch/mips/loongson64/{loongson-3 => }/smp.c | 4 +- arch/mips/loongson64/{loongson-3 => }/smp.h | 0 arch/mips/oprofile/op_model_loongson2.c | 2 +- arch/mips/oprofile/op_model_loongson3.c | 2 +- arch/mips/pci/Makefile | 2 +- arch/mips/pci/fixup-fuloong2e.c | 2 +- arch/mips/pci/fixup-lemote2f.c | 2 +- arch/mips/pci/ops-loongson2.c | 2 +- arch/mips/pci/ops-loongson3.c | 2 +- drivers/cpufreq/loongson2_cpufreq.c | 2 +- drivers/gpio/gpio-loongson.c | 2 +- drivers/platform/mips/cpu_hwmon.c | 2 +- 90 files changed, 720 insertions(+), 578 deletions(-) create mode 100644 arch/mips/include/asm/mach-loongson2ef/cpu-feature-overrides.h rename arch/mips/include/asm/{mach-loongson64 => mach-loongson2ef}/cs5536/cs5536.h (100%) rename arch/mips/include/asm/{mach-loongson64 => mach-loongson2ef}/cs5536/cs5536_mfgpt.h (100%) rename arch/mips/include/asm/{mach-loongson64 => mach-loongson2ef}/cs5536/cs5536_pci.h (100%) rename arch/mips/include/asm/{mach-loongson64 => mach-loongson2ef}/cs5536/cs5536_vsm.h (100%) rename arch/mips/include/asm/{mach-loongson64/loongson.h => mach-loongson2ef/loongson2ef.h} (91%) rename arch/mips/include/asm/{mach-loongson64 => mach-loongson2ef}/machine.h (80%) rename arch/mips/include/asm/{mach-loongson64 => mach-loongson2ef}/mc146818rtc.h (80%) rename arch/mips/include/asm/{mach-loongson64 => mach-loongson2ef}/mem.h (86%) create mode 100644 arch/mips/include/asm/mach-loongson2ef/pci.h create mode 100644 arch/mips/include/asm/mach-loongson2ef/spaces.h delete mode 100644 arch/mips/include/asm/mach-loongson64/kernel-entry-init.h create mode 100644 arch/mips/include/asm/mach-loongson64/loongson64.h create mode 100644 arch/mips/loongson2ef/Kconfig create mode 100644 arch/mips/loongson2ef/Makefile create mode 100644 arch/mips/loongson2ef/Platform rename arch/mips/{loongson64 => loongson2ef}/common/Makefile (100%) rename arch/mips/{loongson64 => loongson2ef}/common/bonito-irq.c (97%) rename arch/mips/{loongson64 => loongson2ef}/common/cmdline.c (97%) rename arch/mips/{loongson64 => loongson2ef}/common/cs5536/Makefile (100%) rename arch/mips/{loongson64 => loongson2ef}/common/cs5536/cs5536_acc.c (100%) rename arch/mips/{loongson64 => loongson2ef}/common/cs5536/cs5536_ehci.c (100%) rename arch/mips/{loongson64 => loongson2ef}/common/cs5536/cs5536_ide.c (100%) rename arch/mips/{loongson64 => loongson2ef}/common/cs5536/cs5536_isa.c (100%) rename arch/mips/{loongson64 => loongson2ef}/common/cs5536/cs5536_mfgpt.c (100%) rename arch/mips/{loongson64 => loongson2ef}/common/cs5536/cs5536_ohci.c (100%) rename arch/mips/{loongson64 => loongson2ef}/common/cs5536/cs5536_pci.c (100%) rename arch/mips/{loongson64 => loongson2ef}/common/early_printk.c (97%) create mode 100644 arch/mips/loongson2ef/common/env.c rename arch/mips/{loongson64 => loongson2ef}/common/init.c (90%) rename arch/mips/{loongson64 => loongson2ef}/common/irq.c (98%) rename arch/mips/{loongson64 => loongson2ef}/common/machtype.c (94%) rename arch/mips/{loongson64 => loongson2ef}/common/mem.c (72%) rename arch/mips/{loongson64 => loongson2ef}/common/pci.c (89%) rename arch/mips/{loongson64 => loongson2ef}/common/platform.c (100%) rename arch/mips/{loongson64 => loongson2ef}/common/pm.c (99%) rename arch/mips/{loongson64 => loongson2ef}/common/reset.c (77%) rename arch/mips/{loongson64 => loongson2ef}/common/rtc.c (100%) rename arch/mips/{loongson64 => loongson2ef}/common/serial.c (63%) rename arch/mips/{loongson64 => loongson2ef}/common/setup.c (97%) rename arch/mips/{loongson64 => loongson2ef}/common/time.c (96%) rename arch/mips/{loongson64 => loongson2ef}/common/uart_base.c (77%) rename arch/mips/{loongson64 => loongson2ef}/fuloong-2e/Makefile (100%) rename arch/mips/{loongson64 => loongson2ef}/fuloong-2e/dma.c (100%) rename arch/mips/{loongson64 => loongson2ef}/fuloong-2e/irq.c (98%) rename arch/mips/{loongson64 => loongson2ef}/fuloong-2e/reset.c (93%) rename arch/mips/{loongson64 => loongson2ef}/lemote-2f/Makefile (100%) rename arch/mips/{loongson64 => loongson2ef}/lemote-2f/clock.c (98%) rename arch/mips/{loongson64 => loongson2ef}/lemote-2f/dma.c (100%) rename arch/mips/{loongson64 => loongson2ef}/lemote-2f/ec_kb3310b.c (100%) rename arch/mips/{loongson64 => loongson2ef}/lemote-2f/ec_kb3310b.h (100%) rename arch/mips/{loongson64 => loongson2ef}/lemote-2f/irq.c (99%) rename arch/mips/{loongson64 => loongson2ef}/lemote-2f/machtype.c (98%) rename arch/mips/{loongson64 => loongson2ef}/lemote-2f/pm.c (99%) rename arch/mips/{loongson64 => loongson2ef}/lemote-2f/reset.c (99%) rename arch/mips/loongson64/{loongson-3 => }/acpi_init.c (99%) rename arch/mips/loongson64/{loongson-3 => }/cop2-ex.c (88%) rename arch/mips/loongson64/{loongson-3 => }/dma.c (82%) rename arch/mips/loongson64/{common => }/env.c (79%) rename arch/mips/loongson64/{loongson-3 => }/hpet.c (100%) rename arch/mips/loongson64/{loongson-3 => }/irq.c (77%) delete mode 100644 arch/mips/loongson64/loongson-3/Makefile rename arch/mips/loongson64/{loongson-3 => }/numa.c (98%) create mode 100644 arch/mips/loongson64/pci.c rename arch/mips/loongson64/{loongson-3 => }/platform.c (100%) create mode 100644 arch/mips/loongson64/reset.c create mode 100644 arch/mips/loongson64/setup.c rename arch/mips/loongson64/{loongson-3 => }/smp.c (99%) rename arch/mips/loongson64/{loongson-3 => }/smp.h (100%) diff --git a/arch/mips/Kbuild.platforms b/arch/mips/Kbuild.platforms index 0de839882106..7c0d461483ef 100644 --- a/arch/mips/Kbuild.platforms +++ b/arch/mips/Kbuild.platforms @@ -17,6 +17,7 @@ platforms += jazz platforms += jz4740 platforms += lantiq platforms += lasat +platforms += loongson2ef platforms += loongson32 platforms += loongson64 platforms += mti-malta diff --git a/arch/mips/Kconfig b/arch/mips/Kconfig index cbc76f00d1fc..92a2ee773a40 100644 --- a/arch/mips/Kconfig +++ b/arch/mips/Kconfig @@ -445,18 +445,52 @@ config MACH_LOONGSON32 the Institute of Computing Technology (ICT), Chinese Academy of Sciences (CAS). +config MACH_LOONGSON2EF + bool "Loongson-2E/F family of machines" + select SYS_SUPPORTS_ZBOOT + help + This enables the support of Loongson-2E/F family of machines. + + Loongson-2E/F is a family of single-core CPUs, They are 64-bit + general-purpose MIPS-III compatible CPUs. Loongson-2E/F are developed + by the Institute of Computing Technology (ICT), Chinese Academy of + Sciences (CAS) in the People's Republic of China. + The chief architect is Professor Weiwu Hu. + config MACH_LOONGSON64 - bool "Loongson-2/3 family of machines" + bool "Loongson GSx64 family of machines" + select ARCH_SPARSEMEM_ENABLE + select ARCH_MIGHT_HAVE_PC_PARPORT + select ARCH_MIGHT_HAVE_PC_SERIO + select GENERIC_ISA_DMA_SUPPORT_BROKEN + select BOOT_ELF32 + select BOARD_SCACHE + select CSRC_R4K + select CEVT_R4K + select CPU_HAS_WB + select FORCE_PCI + select ISA + select I8259 + select IRQ_MIPS_CPU + select NUMA + select NR_CPUS_DEFAULT_32 + select SYS_HAS_CPU_LOONGSON64 + select SYS_HAS_EARLY_PRINTK + select USE_GENERIC_EARLY_PRINTK_8250 + select SYS_SUPPORTS_SMP + select SYS_SUPPORTS_HOTPLUG_CPU + select SYS_SUPPORTS_NUMA + select SYS_SUPPORTS_64BIT_KERNEL + select SYS_SUPPORTS_HIGHMEM + select SYS_SUPPORTS_LITTLE_ENDIAN + select ZONE_DMA32 select SYS_SUPPORTS_ZBOOT help - This enables the support of Loongson-2/3 family of machines. + This enables the support of Loongson-3A/3B/2-series-soc processors - Loongson-2 is a family of single-core CPUs and Loongson-3 is a - family of multi-core CPUs. They are both 64-bit general-purpose - MIPS-compatible CPUs. Loongson-2/3 are developed by the Institute - of Computing Technology (ICT), Chinese Academy of Sciences (CAS) - in the People's Republic of China. The chief architect is Professor - Weiwu Hu. + GSx64 is a family of general-purpose MIPS64R2+ procossor featured + multi-core support. Their firmwares are passing parameters according + to uniformed "Loongson Firmware Kernel Interface Specification". config MACH_PISTACHIO bool "IMG Pistachio SoC based boards" @@ -1033,6 +1067,7 @@ source "arch/mips/sibyte/Kconfig" source "arch/mips/txx9/Kconfig" source "arch/mips/vr41xx/Kconfig" source "arch/mips/cavium-octeon/Kconfig" +source "arch/mips/loongson2ef/Kconfig" source "arch/mips/loongson32/Kconfig" source "arch/mips/loongson64/Kconfig" source "arch/mips/netlogic/Kconfig" diff --git a/arch/mips/include/asm/bootinfo.h b/arch/mips/include/asm/bootinfo.h index f711ccf7bace..6c1602af2bf4 100644 --- a/arch/mips/include/asm/bootinfo.h +++ b/arch/mips/include/asm/bootinfo.h @@ -70,7 +70,6 @@ enum loongson_machine_type { MACH_DEXXON_GDIUM2F10, MACH_LEMOTE_NAS, MACH_LEMOTE_LL2F, - MACH_LOONGSON_GENERIC, MACH_LOONGSON_END }; diff --git a/arch/mips/include/asm/mach-loongson2ef/cpu-feature-overrides.h b/arch/mips/include/asm/mach-loongson2ef/cpu-feature-overrides.h new file mode 100644 index 000000000000..961ce43c6c98 --- /dev/null +++ b/arch/mips/include/asm/mach-loongson2ef/cpu-feature-overrides.h @@ -0,0 +1,45 @@ +// SPDX-License-Identifier: GPL-2.0-or-later +/* + * Copyright (C) 2009 Wu Zhangjin + * Copyright (C) 2009 Philippe Vachon + * Copyright (C) 2009 Zhang Le + * + * reference: /proc/cpuinfo, + * arch/mips/kernel/cpu-probe.c(cpu_probe_legacy), + * arch/mips/kernel/proc.c(show_cpuinfo), + * loongson2f user manual. + */ + +#ifndef __ASM_MACH_LOONGSON2EF_CPU_FEATURE_OVERRIDES_H +#define __ASM_MACH_LOONGSON2EF_CPU_FEATURE_OVERRIDES_H + +#define cpu_has_32fpr 1 +#define cpu_has_3k_cache 0 +#define cpu_has_4k_cache 1 +#define cpu_has_4kex 1 +#define cpu_has_64bits 1 +#define cpu_has_cache_cdex_p 0 +#define cpu_has_cache_cdex_s 0 +#define cpu_has_counter 1 +#define cpu_has_dc_aliases (PAGE_SIZE < 0x4000) +#define cpu_has_divec 0 +#define cpu_has_ejtag 0 +#define cpu_has_inclusive_pcaches 1 +#define cpu_has_llsc 1 +#define cpu_has_mcheck 0 +#define cpu_has_mdmx 0 +#define cpu_has_mips16 0 +#define cpu_has_mips16e2 0 +#define cpu_has_mips3d 0 +#define cpu_has_mipsmt 0 +#define cpu_has_smartmips 0 +#define cpu_has_tlb 1 +#define cpu_has_tx39_cache 0 +#define cpu_has_vce 0 +#define cpu_has_veic 0 +#define cpu_has_vint 0 +#define cpu_has_vtag_icache 0 +#define cpu_has_watch 1 +#define cpu_has_local_ebase 0 + +#endif /* __ASM_MACH_LOONGSON2EF_CPU_FEATURE_OVERRIDES_H */ diff --git a/arch/mips/include/asm/mach-loongson64/cs5536/cs5536.h b/arch/mips/include/asm/mach-loongson2ef/cs5536/cs5536.h similarity index 100% rename from arch/mips/include/asm/mach-loongson64/cs5536/cs5536.h rename to arch/mips/include/asm/mach-loongson2ef/cs5536/cs5536.h diff --git a/arch/mips/include/asm/mach-loongson64/cs5536/cs5536_mfgpt.h b/arch/mips/include/asm/mach-loongson2ef/cs5536/cs5536_mfgpt.h similarity index 100% rename from arch/mips/include/asm/mach-loongson64/cs5536/cs5536_mfgpt.h rename to arch/mips/include/asm/mach-loongson2ef/cs5536/cs5536_mfgpt.h diff --git a/arch/mips/include/asm/mach-loongson64/cs5536/cs5536_pci.h b/arch/mips/include/asm/mach-loongson2ef/cs5536/cs5536_pci.h similarity index 100% rename from arch/mips/include/asm/mach-loongson64/cs5536/cs5536_pci.h rename to arch/mips/include/asm/mach-loongson2ef/cs5536/cs5536_pci.h diff --git a/arch/mips/include/asm/mach-loongson64/cs5536/cs5536_vsm.h b/arch/mips/include/asm/mach-loongson2ef/cs5536/cs5536_vsm.h similarity index 100% rename from arch/mips/include/asm/mach-loongson64/cs5536/cs5536_vsm.h rename to arch/mips/include/asm/mach-loongson2ef/cs5536/cs5536_vsm.h diff --git a/arch/mips/include/asm/mach-loongson64/loongson.h b/arch/mips/include/asm/mach-loongson2ef/loongson2ef.h similarity index 91% rename from arch/mips/include/asm/mach-loongson64/loongson.h rename to arch/mips/include/asm/mach-loongson2ef/loongson2ef.h index 40a24b76b874..b4524937df0e 100644 --- a/arch/mips/include/asm/mach-loongson64/loongson.h +++ b/arch/mips/include/asm/mach-loongson2ef/loongson2ef.h @@ -4,13 +4,12 @@ * Author: Wu Zhangjin */ -#ifndef __ASM_MACH_LOONGSON64_LOONGSON_H -#define __ASM_MACH_LOONGSON64_LOONGSON_H +#ifndef __ASM_MACH_LOONGSON2EF_LOONGSON2EF_H +#define __ASM_MACH_LOONGSON2EF_LOONGSON2EF_H #include #include #include -#include /* loongson internal northbridge initialization */ extern void bonito_irq_init(void); @@ -22,7 +21,6 @@ extern void mach_prepare_shutdown(void); /* environment arguments from bootloader */ extern u32 cpu_clock_freq; extern u32 memsize, highmemsize; -extern const struct plat_smp_ops loongson3_smp_ops; /* loongson-specific command line, env and memory initialization */ extern void __init prom_init_memory(void); @@ -58,11 +56,6 @@ extern int mach_i8259_irq(void); #define LOONGSON_REG(x) \ (*(volatile u32 *)((char *)CKSEG1ADDR(LOONGSON_REG_BASE) + (x))) -#define LOONGSON3_REG8(base, x) \ - (*(volatile u8 *)((char *)TO_UNCAC(base) + (x))) - -#define LOONGSON3_REG32(base, x) \ - (*(volatile u32 *)((char *)TO_UNCAC(base) + (x))) #define LOONGSON_IRQ_BASE 32 #define LOONGSON2_PERFCNT_IRQ (MIPS_CPU_IRQ_BASE + 6) /* cpu perf counter */ @@ -89,10 +82,6 @@ static inline void do_perfcnt_IRQ(void) #define LOONGSON_REG_BASE 0x1fe00000 #define LOONGSON_REG_SIZE 0x00100000 /* 256Bytes + 256Bytes + ??? */ #define LOONGSON_REG_TOP (LOONGSON_REG_BASE+LOONGSON_REG_SIZE-1) -/* Loongson-3 specific registers */ -#define LOONGSON3_REG_BASE 0x3ff00000 -#define LOONGSON3_REG_SIZE 0x00100000 /* 256Bytes + 256Bytes + ??? */ -#define LOONGSON3_REG_TOP (LOONGSON3_REG_BASE+LOONGSON3_REG_SIZE-1) #define LOONGSON_LIO1_BASE 0x1ff00000 #define LOONGSON_LIO1_SIZE 0x00100000 /* 1M */ @@ -247,19 +236,9 @@ static inline void do_perfcnt_IRQ(void) #define MAX_PACKAGES 4 /* Chip Config registor of each physical cpu package, PRid >= Loongson-2F */ -extern u64 loongson_chipcfg[MAX_PACKAGES]; -#define LOONGSON_CHIPCFG(id) (*(volatile u32 *)(loongson_chipcfg[id])) - -/* Chip Temperature registor of each physical cpu package, PRid >= Loongson-3A */ -extern u64 loongson_chiptemp[MAX_PACKAGES]; -#define LOONGSON_CHIPTEMP(id) (*(volatile u32 *)(loongson_chiptemp[id])) - -/* Freq Control register of each physical cpu package, PRid >= Loongson-3B */ -extern u64 loongson_freqctrl[MAX_PACKAGES]; -#define LOONGSON_FREQCTRL(id) (*(volatile u32 *)(loongson_freqctrl[id])) +#define LOONGSON_CHIPCFG(id) (*(volatile u32 *)(0xffffffffbfc00180)) /* pcimap */ - #define LOONGSON_PCIMAP_PCIMAP_LO0 0x0000003f #define LOONGSON_PCIMAP_PCIMAP_LO0_SHIFT 0 #define LOONGSON_PCIMAP_PCIMAP_LO1 0x00000fc0 @@ -352,4 +331,4 @@ extern unsigned long _loongson_addrwincfg_base; #endif /* ! CONFIG_CPU_SUPPORTS_ADDRWINCFG */ -#endif /* __ASM_MACH_LOONGSON64_LOONGSON_H */ +#endif /* __ASM_MACH_LOONGSON2EF_LOONGSON_H */ diff --git a/arch/mips/include/asm/mach-loongson64/machine.h b/arch/mips/include/asm/mach-loongson2ef/machine.h similarity index 80% rename from arch/mips/include/asm/mach-loongson64/machine.h rename to arch/mips/include/asm/mach-loongson2ef/machine.h index 8ef7ea94a26d..2a032259041d 100644 --- a/arch/mips/include/asm/mach-loongson64/machine.h +++ b/arch/mips/include/asm/mach-loongson2ef/machine.h @@ -20,10 +20,4 @@ #endif -#ifdef CONFIG_LOONGSON_MACH3X - -#define LOONGSON_MACHTYPE MACH_LOONGSON_GENERIC - -#endif /* CONFIG_LOONGSON_MACH3X */ - #endif /* __ASM_MACH_LOONGSON64_MACHINE_H */ diff --git a/arch/mips/include/asm/mach-loongson64/mc146818rtc.h b/arch/mips/include/asm/mach-loongson2ef/mc146818rtc.h similarity index 80% rename from arch/mips/include/asm/mach-loongson64/mc146818rtc.h rename to arch/mips/include/asm/mach-loongson2ef/mc146818rtc.h index ebdccfee50be..7b42c9efccc0 100644 --- a/arch/mips/include/asm/mach-loongson64/mc146818rtc.h +++ b/arch/mips/include/asm/mach-loongson2ef/mc146818rtc.h @@ -1,8 +1,5 @@ +// SPDX-License-Identifier: GPL-2.0-or-later /* - * This file is subject to the terms and conditions of the GNU General Public - * License. See the file "COPYING" in the main directory of this archive - * for more details. - * * Copyright (C) 1998, 2001, 03, 07 by Ralf Baechle (ralf@linux-mips.org) * * RTC routines for PC style attached Dallas chip. diff --git a/arch/mips/include/asm/mach-loongson64/mem.h b/arch/mips/include/asm/mach-loongson2ef/mem.h similarity index 86% rename from arch/mips/include/asm/mach-loongson64/mem.h rename to arch/mips/include/asm/mach-loongson2ef/mem.h index ce33c174c04d..d1d759b8974e 100644 --- a/arch/mips/include/asm/mach-loongson64/mem.h +++ b/arch/mips/include/asm/mach-loongson2ef/mem.h @@ -4,8 +4,8 @@ * Author: Wu Zhangjin */ -#ifndef __ASM_MACH_LOONGSON64_MEM_H -#define __ASM_MACH_LOONGSON64_MEM_H +#ifndef __ASM_MACH_LOONGSON2EF_MEM_H +#define __ASM_MACH_LOONGSON2EF_MEM_H /* * high memory space @@ -34,4 +34,4 @@ #define LOONGSON_MMIO_MEM_END 0x80000000 #endif -#endif /* __ASM_MACH_LOONGSON64_MEM_H */ +#endif /* __ASM_MACH_LOONGSON2EF_MEM_H */ diff --git a/arch/mips/include/asm/mach-loongson2ef/pci.h b/arch/mips/include/asm/mach-loongson2ef/pci.h new file mode 100644 index 000000000000..df65d3c14896 --- /dev/null +++ b/arch/mips/include/asm/mach-loongson2ef/pci.h @@ -0,0 +1,43 @@ +/* SPDX-License-Identifier: GPL-2.0-or-later */ +/* + * Copyright (c) 2008 Zhang Le + * Copyright (c) 2009 Wu Zhangjin + */ + +#ifndef __ASM_MACH_LOONGSON2EF_PCI_H_ +#define __ASM_MACH_LOONGSON2EF_PCI_H_ + +extern struct pci_ops loongson_pci_ops; + +/* this is an offset from mips_io_port_base */ +#define LOONGSON_PCI_IO_START 0x00004000UL + +#ifdef CONFIG_CPU_SUPPORTS_ADDRWINCFG + +/* + * we use address window2 to map cpu address space to pci space + * window2: cpu [1G, 2G] -> pci [1G, 2G] + * why not use window 0 & 1? because they are used by cpu when booting. + * window0: cpu [0, 256M] -> ddr [0, 256M] + * window1: cpu [256M, 512M] -> pci [256M, 512M] + */ + +/* the smallest LOONGSON_CPU_MEM_SRC can be 512M */ +#define LOONGSON_CPU_MEM_SRC 0x40000000ul /* 1G */ +#define LOONGSON_PCI_MEM_DST LOONGSON_CPU_MEM_SRC + +#define LOONGSON_PCI_MEM_START LOONGSON_PCI_MEM_DST +#define LOONGSON_PCI_MEM_END (0x80000000ul-1) /* 2G */ + +#define MMAP_CPUTOPCI_SIZE (LOONGSON_PCI_MEM_END - \ + LOONGSON_PCI_MEM_START + 1) + +#else /* loongson2f/32bit & loongson2e */ + +/* this pci memory space is mapped by pcimap in pci.c */ +#define LOONGSON_PCI_MEM_START LOONGSON_PCILO1_BASE +#define LOONGSON_PCI_MEM_END (LOONGSON_PCILO1_BASE + 0x04000000 * 2) + +#endif /* !CONFIG_CPU_SUPPORTS_ADDRWINCFG */ + +#endif /* !__ASM_MACH_LOONGSON2EF_PCI_H_ */ diff --git a/arch/mips/include/asm/mach-loongson2ef/spaces.h b/arch/mips/include/asm/mach-loongson2ef/spaces.h new file mode 100644 index 000000000000..ba4e8e9b618e --- /dev/null +++ b/arch/mips/include/asm/mach-loongson2ef/spaces.h @@ -0,0 +1,10 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +#ifndef __ASM_MACH_LOONGSON2EF_SPACES_H_ +#define __ASM_MACH_LOONGSON2EF_SPACES_H_ + +#if defined(CONFIG_64BIT) +#define CAC_BASE _AC(0x9800000000000000, UL) +#endif /* CONFIG_64BIT */ + +#include +#endif diff --git a/arch/mips/include/asm/mach-loongson64/cpu-feature-overrides.h b/arch/mips/include/asm/mach-loongson64/cpu-feature-overrides.h index 153b6042e174..e70e8abc8348 100644 --- a/arch/mips/include/asm/mach-loongson64/cpu-feature-overrides.h +++ b/arch/mips/include/asm/mach-loongson64/cpu-feature-overrides.h @@ -44,11 +44,8 @@ #define cpu_has_vtag_icache 0 #define cpu_has_watch 1 #define cpu_has_local_ebase 0 - -#ifdef CONFIG_CPU_LOONGSON64 #define cpu_has_wsbh 1 #define cpu_has_ic_fills_f_dc 1 #define cpu_hwrena_impl_bits 0xc0000000 -#endif #endif /* __ASM_MACH_LOONGSON64_CPU_FEATURE_OVERRIDES_H */ diff --git a/arch/mips/include/asm/mach-loongson64/irq.h b/arch/mips/include/asm/mach-loongson64/irq.h index 557e069c400c..baed43285163 100644 --- a/arch/mips/include/asm/mach-loongson64/irq.h +++ b/arch/mips/include/asm/mach-loongson64/irq.h @@ -2,10 +2,9 @@ #ifndef __ASM_MACH_LOONGSON64_IRQ_H_ #define __ASM_MACH_LOONGSON64_IRQ_H_ +#include #include -#ifdef CONFIG_CPU_LOONGSON64 - /* cpu core interrupt numbers */ #define MIPS_CPU_IRQ_BASE 56 @@ -35,10 +34,8 @@ #define LOONGSON_INT_COREx_INTy(x, y) (1<<(x) | 1<<(y+4)) /* route to int y of core x */ -#endif - extern void fixup_irqs(void); -extern void loongson3_ipi_interrupt(struct pt_regs *regs); +extern void loongson3_ipi_interrupt(void); #include_next #endif /* __ASM_MACH_LOONGSON64_IRQ_H_ */ diff --git a/arch/mips/include/asm/mach-loongson64/kernel-entry-init.h b/arch/mips/include/asm/mach-loongson64/kernel-entry-init.h deleted file mode 100644 index 74d94fc1ed53..000000000000 --- a/arch/mips/include/asm/mach-loongson64/kernel-entry-init.h +++ /dev/null @@ -1,74 +0,0 @@ -/* - * This file is subject to the terms and conditions of the GNU General Public - * License. See the file "COPYING" in the main directory of this archive - * for more details. - * - * Copyright (C) 2005 Embedded Alley Solutions, Inc - * Copyright (C) 2005 Ralf Baechle (ralf@linux-mips.org) - * Copyright (C) 2009 Jiajie Chen (chenjiajie@cse.buaa.edu.cn) - * Copyright (C) 2012 Huacai Chen (chenhc@lemote.com) - */ -#ifndef __ASM_MACH_LOONGSON64_KERNEL_ENTRY_H -#define __ASM_MACH_LOONGSON64_KERNEL_ENTRY_H - -#include - -/* - * Override macros used in arch/mips/kernel/head.S. - */ - .macro kernel_entry_setup -#ifdef CONFIG_CPU_LOONGSON64 - .set push - .set mips64 - /* Set LPA on LOONGSON3 config3 */ - mfc0 t0, CP0_CONFIG3 - or t0, (0x1 << 7) - mtc0 t0, CP0_CONFIG3 - /* Set ELPA on LOONGSON3 pagegrain */ - mfc0 t0, CP0_PAGEGRAIN - or t0, (0x1 << 29) - mtc0 t0, CP0_PAGEGRAIN - /* Enable STFill Buffer */ - mfc0 t0, CP0_PRID - andi t0, (PRID_IMP_MASK | PRID_REV_MASK) - slti t0, (PRID_IMP_LOONGSON_64 | PRID_REV_LOONGSON3A_R2_0) - bnez t0, 1f - mfc0 t0, CP0_CONFIG6 - or t0, 0x100 - mtc0 t0, CP0_CONFIG6 -1: - _ehb - .set pop -#endif - .endm - -/* - * Do SMP slave processor setup. - */ - .macro smp_slave_setup -#ifdef CONFIG_CPU_LOONGSON64 - .set push - .set mips64 - /* Set LPA on LOONGSON3 config3 */ - mfc0 t0, CP0_CONFIG3 - or t0, (0x1 << 7) - mtc0 t0, CP0_CONFIG3 - /* Set ELPA on LOONGSON3 pagegrain */ - mfc0 t0, CP0_PAGEGRAIN - or t0, (0x1 << 29) - mtc0 t0, CP0_PAGEGRAIN - /* Enable STFill Buffer */ - mfc0 t0, CP0_PRID - andi t0, (PRID_IMP_MASK | PRID_REV_MASK) - slti t0, (PRID_IMP_LOONGSON_64 | PRID_REV_LOONGSON3A_R2_0) - bnez t0, 1f - mfc0 t0, CP0_CONFIG6 - or t0, 0x100 - mtc0 t0, CP0_CONFIG6 -1: - _ehb - .set pop -#endif - .endm - -#endif /* __ASM_MACH_LOONGSON64_KERNEL_ENTRY_H */ diff --git a/arch/mips/include/asm/mach-loongson64/loongson64.h b/arch/mips/include/asm/mach-loongson64/loongson64.h new file mode 100644 index 000000000000..d877adb99d33 --- /dev/null +++ b/arch/mips/include/asm/mach-loongson64/loongson64.h @@ -0,0 +1,48 @@ +/* SPDX-License-Identifier: GPL-2.0-or-later */ +/* + * Copyright (C) 2019 Jiaxun Yang + * + * Generic definitions for MACH_LOONGSON64 + */ + +#ifndef __ASM_MACH_LOONGSON64_LOONGSON64_H +#define __ASM_MACH_LOONGSON64_LOONGSON64_H + +#include +#include + +#define MAX_PACKAGES 4 + +#define LOONGSON_REG_BASE 0x1fe00000 +#define LOONGSON_REGBASE 0x100 + +#define LOONGSON3_REG_BASE 0x3ff00000 +#define LOONGSON3_REG_SIZE 0x00100000 /* 256Bytes + 256Bytes + ??? */ +#define LOONGSON3_REG_TOP (LOONGSON3_REG_BASE+LOONGSON3_REG_SIZE-1) + +#define LOONGSON_REG(x) \ + (*(volatile u32 *)((char *)CKSEG1ADDR(LOONGSON_REG_BASE) + (x))) + +#define LOONGSON3_REG8(base, x) \ + (*(volatile u8 *)((char *)TO_UNCAC(base) + (x))) + +#define LOONGSON3_REG32(base, x) \ + (*(volatile u32 *)((char *)TO_UNCAC(base) + (x)))/* Loongson-3 specific registers */ + +#define LOONGSON_PCIIO_SIZE 0x00100000 /* 1M */ + +/* Chip Config registor of each physical cpu package, PRid >= Loongson-2F */ +extern u64 loongson_chipcfg[MAX_PACKAGES]; +#define LOONGSON_CHIPCFG(id) (*(volatile u32 *)(loongson_chipcfg[id])) + +/* Chip Temperature registor of each physical cpu package, PRid >= Loongson-3A */ +extern u64 loongson_chiptemp[MAX_PACKAGES]; +#define LOONGSON_CHIPTEMP(id) (*(volatile u32 *)(loongson_chiptemp[id])) + +/* Freq Control register of each physical cpu package, PRid >= Loongson-3B */ +extern u64 loongson_freqctrl[MAX_PACKAGES]; +#define LOONGSON_FREQCTRL(id) (*(volatile u32 *)(loongson_freqctrl[id])) + +extern const struct plat_smp_ops loongson3_smp_ops; +extern void __init prom_init_lefi(void); +#endif diff --git a/arch/mips/include/asm/mach-loongson64/mmzone.h b/arch/mips/include/asm/mach-loongson64/mmzone.h index 62073d60739f..eec8057d3ec9 100644 --- a/arch/mips/include/asm/mach-loongson64/mmzone.h +++ b/arch/mips/include/asm/mach-loongson64/mmzone.h @@ -19,30 +19,14 @@ #define pa_to_nid(addr) (((addr) & 0xf00000000000) >> NODE_ADDRSPACE_SHIFT) #define nid_to_addrbase(nid) ((nid) << NODE_ADDRSPACE_SHIFT) -#define LEVELS_PER_SLICE 128 - -struct slice_data { - unsigned long irq_enable_mask[2]; - int level_to_irq[LEVELS_PER_SLICE]; -}; - -struct hub_data { - cpumask_t h_cpus; - unsigned long slice_map; - unsigned long irq_alloc_mask[2]; - struct slice_data slice[2]; -}; - struct node_data { struct pglist_data pglist; - struct hub_data hub; cpumask_t cpumask; }; extern struct node_data *__node_data[]; #define NODE_DATA(n) (&__node_data[(n)]->pglist) -#define hub_data(n) (&__node_data[(n)]->hub) extern void setup_zero_pages(void); extern void __init prom_init_numa_memory(void); diff --git a/arch/mips/include/asm/mach-loongson64/pci.h b/arch/mips/include/asm/mach-loongson64/pci.h index 05cc9052772f..a30024499590 100644 --- a/arch/mips/include/asm/mach-loongson64/pci.h +++ b/arch/mips/include/asm/mach-loongson64/pci.h @@ -4,47 +4,12 @@ * Copyright (c) 2009 Wu Zhangjin */ -#ifndef __ASM_MACH_LOONGSON64_PCI_H_ -#define __ASM_MACH_LOONGSON64_PCI_H_ +#ifndef __ASM_MACH_LOONGSON2EF_PCI_H_ +#define __ASM_MACH_LOONGSON2EF_PCI_H_ extern struct pci_ops loongson_pci_ops; -/* this is an offset from mips_io_port_base */ -#define LOONGSON_PCI_IO_START 0x00004000UL - -#ifdef CONFIG_CPU_SUPPORTS_ADDRWINCFG - -/* - * we use address window2 to map cpu address space to pci space - * window2: cpu [1G, 2G] -> pci [1G, 2G] - * why not use window 0 & 1? because they are used by cpu when booting. - * window0: cpu [0, 256M] -> ddr [0, 256M] - * window1: cpu [256M, 512M] -> pci [256M, 512M] - */ - -/* the smallest LOONGSON_CPU_MEM_SRC can be 512M */ -#define LOONGSON_CPU_MEM_SRC 0x40000000ul /* 1G */ -#define LOONGSON_PCI_MEM_DST LOONGSON_CPU_MEM_SRC - -#define LOONGSON_PCI_MEM_START LOONGSON_PCI_MEM_DST -#define LOONGSON_PCI_MEM_END (0x80000000ul-1) /* 2G */ - -#define MMAP_CPUTOPCI_SIZE (LOONGSON_PCI_MEM_END - \ - LOONGSON_PCI_MEM_START + 1) - -#else /* loongson2f/32bit & loongson2e */ - -/* this pci memory space is mapped by pcimap in pci.c */ -#ifdef CONFIG_CPU_LOONGSON64 #define LOONGSON_PCI_MEM_START 0x40000000UL #define LOONGSON_PCI_MEM_END 0x7effffffUL -#else -#define LOONGSON_PCI_MEM_START LOONGSON_PCILO1_BASE -#define LOONGSON_PCI_MEM_END (LOONGSON_PCILO1_BASE + 0x04000000 * 2) -#endif -/* this is an offset from mips_io_port_base */ -#define LOONGSON_PCI_IO_START 0x00004000UL - -#endif /* !CONFIG_CPU_SUPPORTS_ADDRWINCFG */ -#endif /* !__ASM_MACH_LOONGSON64_PCI_H_ */ +#endif /* !__ASM_MACH_LOONGSON2EF_PCI_H_ */ diff --git a/arch/mips/include/asm/mach-loongson64/workarounds.h b/arch/mips/include/asm/mach-loongson64/workarounds.h index 17b71172a097..e30415bef7b7 100644 --- a/arch/mips/include/asm/mach-loongson64/workarounds.h +++ b/arch/mips/include/asm/mach-loongson64/workarounds.h @@ -2,7 +2,7 @@ #ifndef __ASM_MACH_LOONGSON64_WORKAROUNDS_H_ #define __ASM_MACH_LOONGSON64_WORKAROUNDS_H_ -#define WORKAROUND_CPUFREQ 0x00000001 -#define WORKAROUND_CPUHOTPLUG 0x00000002 +#define WORKAROUND_CPUFREQ BIT(1) +#define WORKAROUND_CPUHOTPLUG BIT(2) #endif diff --git a/arch/mips/loongson2ef/Kconfig b/arch/mips/loongson2ef/Kconfig new file mode 100644 index 000000000000..cb2f523d9e30 --- /dev/null +++ b/arch/mips/loongson2ef/Kconfig @@ -0,0 +1,93 @@ +# SPDX-License-Identifier: GPL-2.0 +if MACH_LOONGSON2EF + +choice + prompt "Machine Type" + +config LEMOTE_FULOONG2E + bool "Lemote Fuloong(2e) mini-PC" + select ARCH_SPARSEMEM_ENABLE + select ARCH_MIGHT_HAVE_PC_PARPORT + select ARCH_MIGHT_HAVE_PC_SERIO + select CEVT_R4K + select CSRC_R4K + select SYS_HAS_CPU_LOONGSON2E + select DMA_NONCOHERENT + select BOOT_ELF32 + select BOARD_SCACHE + select HAVE_PCI + select I8259 + select ISA + select IRQ_MIPS_CPU + select SYS_SUPPORTS_64BIT_KERNEL + select SYS_SUPPORTS_LITTLE_ENDIAN + select SYS_SUPPORTS_HIGHMEM + select SYS_HAS_EARLY_PRINTK + select GENERIC_ISA_DMA_SUPPORT_BROKEN + select CPU_HAS_WB + select LOONGSON_MC146818 + help + Lemote Fuloong(2e) mini-PC board based on the Chinese Loongson-2E CPU and + an FPGA northbridge + + Lemote Fuloong(2e) mini PC have a VIA686B south bridge. + +config LEMOTE_MACH2F + bool "Lemote Loongson 2F family machines" + select ARCH_SPARSEMEM_ENABLE + select ARCH_MIGHT_HAVE_PC_PARPORT + select ARCH_MIGHT_HAVE_PC_SERIO + select BOARD_SCACHE + select BOOT_ELF32 + select CEVT_R4K if ! MIPS_EXTERNAL_TIMER + select CPU_HAS_WB + select CS5536 + select CSRC_R4K if ! MIPS_EXTERNAL_TIMER + select DMA_NONCOHERENT + select GENERIC_ISA_DMA_SUPPORT_BROKEN + select HAVE_CLK + select HAVE_PCI + select I8259 + select IRQ_MIPS_CPU + select ISA + select SYS_HAS_CPU_LOONGSON2F + select SYS_HAS_EARLY_PRINTK + select SYS_SUPPORTS_64BIT_KERNEL + select SYS_SUPPORTS_HIGHMEM + select SYS_SUPPORTS_LITTLE_ENDIAN + select LOONGSON_MC146818 + help + Lemote Loongson 2F family machines utilize the 2F revision of + Loongson processor and the AMD CS5536 south bridge. + + These family machines include fuloong2f mini PC, yeeloong2f notebook, + LingLoong allinone PC and so forth. + +endchoice + +config CS5536 + bool + +config CS5536_MFGPT + bool "CS5536 MFGPT Timer" + depends on CS5536 && !HIGH_RES_TIMERS + select MIPS_EXTERNAL_TIMER + help + This option enables the mfgpt0 timer of AMD CS5536. With this timer + switched on you can not use high resolution timers. + + If you want to enable the Loongson2 CPUFreq Driver, Please enable + this option at first, otherwise, You will get wrong system time. + + If unsure, say Yes. + +config LOONGSON_UART_BASE + bool + default y + depends on EARLY_PRINTK || SERIAL_8250 + +config LOONGSON_MC146818 + bool + default n + +endif # MACH_LOONGSON2EF diff --git a/arch/mips/loongson2ef/Makefile b/arch/mips/loongson2ef/Makefile new file mode 100644 index 000000000000..0535d244d75b --- /dev/null +++ b/arch/mips/loongson2ef/Makefile @@ -0,0 +1,18 @@ +# SPDX-License-Identifier: GPL-2.0-only +# +# Common code for all Loongson based systems +# + +obj-y += common/ + +# +# Lemote Fuloong mini-PC (Loongson 2E-based) +# + +obj-$(CONFIG_LEMOTE_FULOONG2E) += fuloong-2e/ + +# +# Lemote loongson2f family machines +# + +obj-$(CONFIG_LEMOTE_MACH2F) += lemote-2f/ diff --git a/arch/mips/loongson2ef/Platform b/arch/mips/loongson2ef/Platform new file mode 100644 index 000000000000..3aca42963f35 --- /dev/null +++ b/arch/mips/loongson2ef/Platform @@ -0,0 +1,32 @@ +# +# Loongson Processors' Support +# + +# Only gcc >= 4.4 have Loongson specific support +cflags-$(CONFIG_CPU_LOONGSON2EF) += -Wa,--trap +cflags-$(CONFIG_CPU_LOONGSON2E) += \ + $(call cc-option,-march=loongson2e,-march=r4600) +cflags-$(CONFIG_CPU_LOONGSON2F) += \ + $(call cc-option,-march=loongson2f,-march=r4600) +# Enable the workarounds for Loongson2f +ifdef CONFIG_CPU_LOONGSON2F_WORKAROUNDS + ifeq ($(call as-option,-Wa$(comma)-mfix-loongson2f-nop,),) + $(error only binutils >= 2.20.2 have needed option -mfix-loongson2f-nop) + else + cflags-$(CONFIG_CPU_NOP_WORKAROUNDS) += -Wa$(comma)-mfix-loongson2f-nop + endif + ifeq ($(call as-option,-Wa$(comma)-mfix-loongson2f-jump,),) + $(error only binutils >= 2.20.2 have needed option -mfix-loongson2f-jump) + else + cflags-$(CONFIG_CPU_JUMP_WORKAROUNDS) += -Wa$(comma)-mfix-loongson2f-jump + endif +endif + +# +# Loongson Machines' Support +# + +platform-$(CONFIG_MACH_LOONGSON2EF) += loongson2ef/ +cflags-$(CONFIG_MACH_LOONGSON2EF) += -I$(srctree)/arch/mips/include/asm/mach-loongson2ef -mno-branch-likely +load-$(CONFIG_LEMOTE_FULOONG2E) += 0xffffffff80100000 +load-$(CONFIG_LEMOTE_MACH2F) += 0xffffffff80200000 diff --git a/arch/mips/loongson64/common/Makefile b/arch/mips/loongson2ef/common/Makefile similarity index 100% rename from arch/mips/loongson64/common/Makefile rename to arch/mips/loongson2ef/common/Makefile diff --git a/arch/mips/loongson64/common/bonito-irq.c b/arch/mips/loongson2ef/common/bonito-irq.c similarity index 97% rename from arch/mips/loongson64/common/bonito-irq.c rename to arch/mips/loongson2ef/common/bonito-irq.c index 82352cc25e4c..e59248c53bc5 100644 --- a/arch/mips/loongson64/common/bonito-irq.c +++ b/arch/mips/loongson2ef/common/bonito-irq.c @@ -10,7 +10,7 @@ #include #include -#include +#include static inline void bonito_irq_enable(struct irq_data *d) { diff --git a/arch/mips/loongson64/common/cmdline.c b/arch/mips/loongson2ef/common/cmdline.c similarity index 97% rename from arch/mips/loongson64/common/cmdline.c rename to arch/mips/loongson2ef/common/cmdline.c index a735460682cf..ab126a7cefdc 100644 --- a/arch/mips/loongson64/common/cmdline.c +++ b/arch/mips/loongson2ef/common/cmdline.c @@ -15,7 +15,7 @@ */ #include -#include +#include void __init prom_init_cmdline(void) { diff --git a/arch/mips/loongson64/common/cs5536/Makefile b/arch/mips/loongson2ef/common/cs5536/Makefile similarity index 100% rename from arch/mips/loongson64/common/cs5536/Makefile rename to arch/mips/loongson2ef/common/cs5536/Makefile diff --git a/arch/mips/loongson64/common/cs5536/cs5536_acc.c b/arch/mips/loongson2ef/common/cs5536/cs5536_acc.c similarity index 100% rename from arch/mips/loongson64/common/cs5536/cs5536_acc.c rename to arch/mips/loongson2ef/common/cs5536/cs5536_acc.c diff --git a/arch/mips/loongson64/common/cs5536/cs5536_ehci.c b/arch/mips/loongson2ef/common/cs5536/cs5536_ehci.c similarity index 100% rename from arch/mips/loongson64/common/cs5536/cs5536_ehci.c rename to arch/mips/loongson2ef/common/cs5536/cs5536_ehci.c diff --git a/arch/mips/loongson64/common/cs5536/cs5536_ide.c b/arch/mips/loongson2ef/common/cs5536/cs5536_ide.c similarity index 100% rename from arch/mips/loongson64/common/cs5536/cs5536_ide.c rename to arch/mips/loongson2ef/common/cs5536/cs5536_ide.c diff --git a/arch/mips/loongson64/common/cs5536/cs5536_isa.c b/arch/mips/loongson2ef/common/cs5536/cs5536_isa.c similarity index 100% rename from arch/mips/loongson64/common/cs5536/cs5536_isa.c rename to arch/mips/loongson2ef/common/cs5536/cs5536_isa.c diff --git a/arch/mips/loongson64/common/cs5536/cs5536_mfgpt.c b/arch/mips/loongson2ef/common/cs5536/cs5536_mfgpt.c similarity index 100% rename from arch/mips/loongson64/common/cs5536/cs5536_mfgpt.c rename to arch/mips/loongson2ef/common/cs5536/cs5536_mfgpt.c diff --git a/arch/mips/loongson64/common/cs5536/cs5536_ohci.c b/arch/mips/loongson2ef/common/cs5536/cs5536_ohci.c similarity index 100% rename from arch/mips/loongson64/common/cs5536/cs5536_ohci.c rename to arch/mips/loongson2ef/common/cs5536/cs5536_ohci.c diff --git a/arch/mips/loongson64/common/cs5536/cs5536_pci.c b/arch/mips/loongson2ef/common/cs5536/cs5536_pci.c similarity index 100% rename from arch/mips/loongson64/common/cs5536/cs5536_pci.c rename to arch/mips/loongson2ef/common/cs5536/cs5536_pci.c diff --git a/arch/mips/loongson64/common/early_printk.c b/arch/mips/loongson2ef/common/early_printk.c similarity index 97% rename from arch/mips/loongson64/common/early_printk.c rename to arch/mips/loongson2ef/common/early_printk.c index 5e2a151aa30c..e22d16728e13 100644 --- a/arch/mips/loongson64/common/early_printk.c +++ b/arch/mips/loongson2ef/common/early_printk.c @@ -8,7 +8,7 @@ #include #include -#include +#include #define PORT(base, offset) (u8 *)(base + offset) diff --git a/arch/mips/loongson2ef/common/env.c b/arch/mips/loongson2ef/common/env.c new file mode 100644 index 000000000000..03a8d0165d2e --- /dev/null +++ b/arch/mips/loongson2ef/common/env.c @@ -0,0 +1,71 @@ +// SPDX-License-Identifier: GPL-2.0-or-later +/* + * Based on Ocelot Linux port, which is + * Copyright 2001 MontaVista Software Inc. + * Author: jsun@mvista.com or jsun@junsun.net + * + * Copyright 2003 ICT CAS + * Author: Michael Guo + * + * Copyright (C) 2007 Lemote Inc. & Institute of Computing Technology + * Author: Fuxin Zhang, zhangfx@lemote.com + * + * Copyright (C) 2009 Lemote Inc. + * Author: Wu Zhangjin, wuzhangjin@gmail.com + */ +#include +#include +#include + +u32 cpu_clock_freq; +EXPORT_SYMBOL(cpu_clock_freq); + +unsigned long long smp_group[4]; + +#define parse_even_earlier(res, option, p) \ +do { \ + unsigned int tmp __maybe_unused; \ + \ + if (strncmp(option, (char *)p, strlen(option)) == 0) \ + tmp = kstrtou32((char *)p + strlen(option"="), 10, &res); \ +} while (0) + +void __init prom_init_env(void) +{ + /* pmon passes arguments in 32bit pointers */ + unsigned int processor_id; + int *_prom_envp; + long l; + + /* firmware arguments are initialized in head.S */ + _prom_envp = (int *)fw_arg2; + + l = (long)*_prom_envp; + while (l != 0) { + parse_even_earlier(cpu_clock_freq, "cpuclock", l); + parse_even_earlier(memsize, "memsize", l); + parse_even_earlier(highmemsize, "highmemsize", l); + _prom_envp++; + l = (long)*_prom_envp; + } + if (memsize == 0) + memsize = 256; + + pr_info("memsize=%u, highmemsize=%u\n", memsize, highmemsize); + + if (cpu_clock_freq == 0) { + processor_id = (¤t_cpu_data)->processor_id; + switch (processor_id & PRID_REV_MASK) { + case PRID_REV_LOONGSON2E: + cpu_clock_freq = 533080000; + break; + case PRID_REV_LOONGSON2F: + cpu_clock_freq = 797000000; + break; + default: + cpu_clock_freq = 100000000; + break; + } + } + pr_info("CpuClock = %u\n", cpu_clock_freq); +} diff --git a/arch/mips/loongson64/common/init.c b/arch/mips/loongson2ef/common/init.c similarity index 90% rename from arch/mips/loongson64/common/init.c rename to arch/mips/loongson2ef/common/init.c index 912fe61c4fc7..b65763818911 100644 --- a/arch/mips/loongson64/common/init.c +++ b/arch/mips/loongson2ef/common/init.c @@ -10,7 +10,7 @@ #include #include -#include +#include /* Loongson CPU address windows config space base address */ unsigned long __maybe_unused _loongson_addrwincfg_base; @@ -39,15 +39,10 @@ void __init prom_init(void) set_io_port_base((unsigned long) ioremap(LOONGSON_PCIIO_BASE, LOONGSON_PCIIO_SIZE)); -#ifdef CONFIG_NUMA - prom_init_numa_memory(); -#else prom_init_memory(); -#endif /*init the uart base address */ prom_init_uart_base(); - register_smp_ops(&loongson3_smp_ops); board_nmi_handler_setup = mips_nmi_setup; } diff --git a/arch/mips/loongson64/common/irq.c b/arch/mips/loongson2ef/common/irq.c similarity index 98% rename from arch/mips/loongson64/common/irq.c rename to arch/mips/loongson2ef/common/irq.c index 0ea93c1c0a97..96d492511e41 100644 --- a/arch/mips/loongson64/common/irq.c +++ b/arch/mips/loongson2ef/common/irq.c @@ -6,7 +6,7 @@ #include #include -#include +#include /* * the first level int-handler will jump here if it is a bonito irq */ diff --git a/arch/mips/loongson64/common/machtype.c b/arch/mips/loongson2ef/common/machtype.c similarity index 94% rename from arch/mips/loongson64/common/machtype.c rename to arch/mips/loongson2ef/common/machtype.c index 4e42d929f1c7..d2ea4d25246a 100644 --- a/arch/mips/loongson64/common/machtype.c +++ b/arch/mips/loongson2ef/common/machtype.c @@ -8,7 +8,7 @@ #include #include -#include +#include #include /* please ensure the length of the machtype string is less than 50 */ @@ -23,7 +23,6 @@ static const char *system_types[] = { [MACH_DEXXON_GDIUM2F10] = "dexxon-gdium-2f", [MACH_LEMOTE_NAS] = "lemote-nas-2f", [MACH_LEMOTE_LL2F] = "lemote-lynloong-2f", - [MACH_LOONGSON_GENERIC] = "generic-loongson-machine", [MACH_LOONGSON_END] = NULL, }; diff --git a/arch/mips/loongson64/common/mem.c b/arch/mips/loongson2ef/common/mem.c similarity index 72% rename from arch/mips/loongson64/common/mem.c rename to arch/mips/loongson2ef/common/mem.c index 4abb92e0fc39..c90beb048233 100644 --- a/arch/mips/loongson64/common/mem.c +++ b/arch/mips/loongson2ef/common/mem.c @@ -7,12 +7,10 @@ #include -#include -#include +#include #include #include -#ifndef CONFIG_LEFI_FIRMWARE_INTERFACE u32 memsize, highmemsize; @@ -51,42 +49,6 @@ void __init prom_init_memory(void) #endif /* !CONFIG_64BIT */ } -#else /* CONFIG_LEFI_FIRMWARE_INTERFACE */ - -void __init prom_init_memory(void) -{ - int i; - u32 node_id; - u32 mem_type; - - /* parse memory information */ - for (i = 0; i < loongson_memmap->nr_map; i++) { - node_id = loongson_memmap->map[i].node_id; - mem_type = loongson_memmap->map[i].mem_type; - - if (node_id == 0) { - switch (mem_type) { - case SYSTEM_RAM_LOW: - add_memory_region(loongson_memmap->map[i].mem_start, - (u64)loongson_memmap->map[i].mem_size << 20, - BOOT_MEM_RAM); - break; - case SYSTEM_RAM_HIGH: - add_memory_region(loongson_memmap->map[i].mem_start, - (u64)loongson_memmap->map[i].mem_size << 20, - BOOT_MEM_RAM); - break; - case SYSTEM_RAM_RESERVED: - add_memory_region(loongson_memmap->map[i].mem_start, - (u64)loongson_memmap->map[i].mem_size << 20, - BOOT_MEM_RESERVED); - break; - } - } - } -} - -#endif /* CONFIG_LEFI_FIRMWARE_INTERFACE */ /* override of arch/mips/mm/cache.c: __uncached_access */ int __uncached_access(struct file *file, unsigned long addr) diff --git a/arch/mips/loongson64/common/pci.c b/arch/mips/loongson2ef/common/pci.c similarity index 89% rename from arch/mips/loongson64/common/pci.c rename to arch/mips/loongson2ef/common/pci.c index 2d9755c49524..3df8d1695243 100644 --- a/arch/mips/loongson64/common/pci.c +++ b/arch/mips/loongson2ef/common/pci.c @@ -6,8 +6,7 @@ #include #include -#include -#include +#include static struct resource loongson_pci_mem_resource = { .name = "pci memory space", @@ -81,16 +80,8 @@ static int __init pcibios_init(void) setup_pcimap(); loongson_pci_controller.io_map_base = mips_io_port_base; -#ifdef CONFIG_LEFI_FIRMWARE_INTERFACE - loongson_pci_mem_resource.start = loongson_sysconf.pci_mem_start_addr; - loongson_pci_mem_resource.end = loongson_sysconf.pci_mem_end_addr; -#endif register_pci_controller(&loongson_pci_controller); -#ifdef CONFIG_CPU_LOONGSON64 - sbx00_acpi_init(); -#endif - return 0; } diff --git a/arch/mips/loongson64/common/platform.c b/arch/mips/loongson2ef/common/platform.c similarity index 100% rename from arch/mips/loongson64/common/platform.c rename to arch/mips/loongson2ef/common/platform.c diff --git a/arch/mips/loongson64/common/pm.c b/arch/mips/loongson2ef/common/pm.c similarity index 99% rename from arch/mips/loongson64/common/pm.c rename to arch/mips/loongson2ef/common/pm.c index b8aed878d912..0e3c9f245215 100644 --- a/arch/mips/loongson64/common/pm.c +++ b/arch/mips/loongson2ef/common/pm.c @@ -12,7 +12,7 @@ #include #include -#include +#include static unsigned int __maybe_unused cached_master_mask; /* i8259A */ static unsigned int __maybe_unused cached_slave_mask; diff --git a/arch/mips/loongson64/common/reset.c b/arch/mips/loongson2ef/common/reset.c similarity index 77% rename from arch/mips/loongson64/common/reset.c rename to arch/mips/loongson2ef/common/reset.c index ce39e918e4d5..fc296ac979c6 100644 --- a/arch/mips/loongson64/common/reset.c +++ b/arch/mips/loongson2ef/common/reset.c @@ -12,8 +12,7 @@ #include #include -#include -#include +#include static inline void loongson_reboot(void) { @@ -35,26 +34,15 @@ static inline void loongson_reboot(void) static void loongson_restart(char *command) { -#ifndef CONFIG_LEFI_FIRMWARE_INTERFACE /* do preparation for reboot */ mach_prepare_reboot(); /* reboot via jumping to boot base address */ loongson_reboot(); -#else - void (*fw_restart)(void) = (void *)loongson_sysconf.restart_addr; - - fw_restart(); - while (1) { - if (cpu_wait) - cpu_wait(); - } -#endif } static void loongson_poweroff(void) { -#ifndef CONFIG_LEFI_FIRMWARE_INTERFACE mach_prepare_shutdown(); /* @@ -62,15 +50,6 @@ static void loongson_poweroff(void) * a generic delay loop, machine_hang(), so simply return. */ return; -#else - void (*fw_poweroff)(void) = (void *)loongson_sysconf.poweroff_addr; - - fw_poweroff(); - while (1) { - if (cpu_wait) - cpu_wait(); - } -#endif } static void loongson_halt(void) diff --git a/arch/mips/loongson64/common/rtc.c b/arch/mips/loongson2ef/common/rtc.c similarity index 100% rename from arch/mips/loongson64/common/rtc.c rename to arch/mips/loongson2ef/common/rtc.c diff --git a/arch/mips/loongson64/common/serial.c b/arch/mips/loongson2ef/common/serial.c similarity index 63% rename from arch/mips/loongson64/common/serial.c rename to arch/mips/loongson2ef/common/serial.c index ffefc1cb2612..4203486b1570 100644 --- a/arch/mips/loongson64/common/serial.c +++ b/arch/mips/loongson2ef/common/serial.c @@ -16,7 +16,7 @@ #include -#include +#include #include #define PORT(int, clk) \ @@ -38,7 +38,7 @@ .regshift = 0, \ } -static struct plat_serial8250_port uart8250_data[][MAX_UARTS + 1] = { +static struct plat_serial8250_port uart8250_data[][16] = { [MACH_LOONGSON_UNKNOWN] = {}, [MACH_LEMOTE_FL2E] = {PORT(4, 1843200), {} }, [MACH_LEMOTE_FL2F] = {PORT(3, 1843200), {} }, @@ -47,7 +47,6 @@ static struct plat_serial8250_port uart8250_data[][MAX_UARTS + 1] = { [MACH_DEXXON_GDIUM2F10] = {PORT_M(3, 3686400), {} }, [MACH_LEMOTE_NAS] = {PORT_M(3, 3686400), {} }, [MACH_LEMOTE_LL2F] = {PORT(3, 1843200), {} }, - [MACH_LOONGSON_GENERIC] = {PORT_M(2, 25000000), {} }, [MACH_LOONGSON_END] = {}, }; @@ -58,7 +57,6 @@ static struct platform_device uart8250_device = { static int __init serial_init(void) { - int i; unsigned char iotype; iotype = uart8250_data[mips_machtype][0].iotype; @@ -73,36 +71,7 @@ static int __init serial_init(void) uart8250_data[mips_machtype][0].iobase = loongson_uart_base[0] - LOONGSON_PCIIO_BASE; - if (loongson_sysconf.uarts[0].uartclk) - uart8250_data[mips_machtype][0].uartclk = - loongson_sysconf.uarts[0].uartclk; - - for (i = 1; i < loongson_sysconf.nr_uarts; i++) { - iotype = loongson_sysconf.uarts[i].iotype; - uart8250_data[mips_machtype][i].iotype = iotype; - loongson_uart_base[i] = loongson_sysconf.uarts[i].uart_base; - - if (UPIO_MEM == iotype) { - uart8250_data[mips_machtype][i].irq = - MIPS_CPU_IRQ_BASE + loongson_sysconf.uarts[i].int_offset; - uart8250_data[mips_machtype][i].mapbase = - loongson_uart_base[i]; - uart8250_data[mips_machtype][i].membase = - ioremap_nocache(loongson_uart_base[i], 8); - } else if (UPIO_PORT == iotype) { - uart8250_data[mips_machtype][i].irq = - loongson_sysconf.uarts[i].int_offset; - uart8250_data[mips_machtype][i].iobase = - loongson_uart_base[i] - LOONGSON_PCIIO_BASE; - } - - uart8250_data[mips_machtype][i].uartclk = - loongson_sysconf.uarts[i].uartclk; - uart8250_data[mips_machtype][i].flags = - UPF_BOOT_AUTOCONF | UPF_SKIP_TEST; - } - - memset(&uart8250_data[mips_machtype][loongson_sysconf.nr_uarts], + memset(&uart8250_data[mips_machtype][1], 0, sizeof(struct plat_serial8250_port)); uart8250_device.dev.platform_data = uart8250_data[mips_machtype]; diff --git a/arch/mips/loongson64/common/setup.c b/arch/mips/loongson2ef/common/setup.c similarity index 97% rename from arch/mips/loongson64/common/setup.c rename to arch/mips/loongson2ef/common/setup.c index bc2da4c140c4..278d2b62d9a6 100644 --- a/arch/mips/loongson64/common/setup.c +++ b/arch/mips/loongson2ef/common/setup.c @@ -9,7 +9,7 @@ #include #include -#include +#include #ifdef CONFIG_VT #include diff --git a/arch/mips/loongson64/common/time.c b/arch/mips/loongson2ef/common/time.c similarity index 96% rename from arch/mips/loongson64/common/time.c rename to arch/mips/loongson2ef/common/time.c index e78760ce475b..b29f89a9db8e 100644 --- a/arch/mips/loongson64/common/time.c +++ b/arch/mips/loongson2ef/common/time.c @@ -10,7 +10,7 @@ #include #include -#include +#include #include void __init plat_time_init(void) diff --git a/arch/mips/loongson64/common/uart_base.c b/arch/mips/loongson2ef/common/uart_base.c similarity index 77% rename from arch/mips/loongson64/common/uart_base.c rename to arch/mips/loongson2ef/common/uart_base.c index e88d937f10fe..27d073f1cd48 100644 --- a/arch/mips/loongson64/common/uart_base.c +++ b/arch/mips/loongson2ef/common/uart_base.c @@ -7,12 +7,12 @@ #include #include -#include +#include /* raw */ -unsigned long loongson_uart_base[MAX_UARTS] = {}; +unsigned long loongson_uart_base[16] = {}; /* ioremapped */ -unsigned long _loongson_uart_base[MAX_UARTS] = {}; +unsigned long _loongson_uart_base[16] = {}; EXPORT_SYMBOL(loongson_uart_base); EXPORT_SYMBOL(_loongson_uart_base); @@ -20,10 +20,6 @@ EXPORT_SYMBOL(_loongson_uart_base); void prom_init_loongson_uart_base(void) { switch (mips_machtype) { - case MACH_LOONGSON_GENERIC: - /* The CPU provided serial port (CPU) */ - loongson_uart_base[0] = LOONGSON_REG_BASE + 0x1e0; - break; case MACH_LEMOTE_FL2E: loongson_uart_base[0] = LOONGSON_PCIIO_BASE + 0x3f8; break; diff --git a/arch/mips/loongson64/fuloong-2e/Makefile b/arch/mips/loongson2ef/fuloong-2e/Makefile similarity index 100% rename from arch/mips/loongson64/fuloong-2e/Makefile rename to arch/mips/loongson2ef/fuloong-2e/Makefile diff --git a/arch/mips/loongson64/fuloong-2e/dma.c b/arch/mips/loongson2ef/fuloong-2e/dma.c similarity index 100% rename from arch/mips/loongson64/fuloong-2e/dma.c rename to arch/mips/loongson2ef/fuloong-2e/dma.c diff --git a/arch/mips/loongson64/fuloong-2e/irq.c b/arch/mips/loongson2ef/fuloong-2e/irq.c similarity index 98% rename from arch/mips/loongson64/fuloong-2e/irq.c rename to arch/mips/loongson2ef/fuloong-2e/irq.c index 32278e7bf85c..caaf9e907dd2 100644 --- a/arch/mips/loongson64/fuloong-2e/irq.c +++ b/arch/mips/loongson2ef/fuloong-2e/irq.c @@ -8,7 +8,7 @@ #include #include -#include +#include static void i8259_irqdispatch(void) { diff --git a/arch/mips/loongson64/fuloong-2e/reset.c b/arch/mips/loongson2ef/fuloong-2e/reset.c similarity index 93% rename from arch/mips/loongson64/fuloong-2e/reset.c rename to arch/mips/loongson2ef/fuloong-2e/reset.c index 8273de1cf4bb..df60685d0626 100644 --- a/arch/mips/loongson64/fuloong-2e/reset.c +++ b/arch/mips/loongson2ef/fuloong-2e/reset.c @@ -6,7 +6,7 @@ * Author: Wu Zhangjin, wuzhangjin@gmail.com */ -#include +#include void mach_prepare_reboot(void) { diff --git a/arch/mips/loongson64/lemote-2f/Makefile b/arch/mips/loongson2ef/lemote-2f/Makefile similarity index 100% rename from arch/mips/loongson64/lemote-2f/Makefile rename to arch/mips/loongson2ef/lemote-2f/Makefile diff --git a/arch/mips/loongson64/lemote-2f/clock.c b/arch/mips/loongson2ef/lemote-2f/clock.c similarity index 98% rename from arch/mips/loongson64/lemote-2f/clock.c rename to arch/mips/loongson2ef/lemote-2f/clock.c index 8281334df9c8..83f7b9cabcd1 100644 --- a/arch/mips/loongson64/lemote-2f/clock.c +++ b/arch/mips/loongson2ef/lemote-2f/clock.c @@ -15,7 +15,7 @@ #include #include -#include +#include static LIST_HEAD(clock_list); static DEFINE_SPINLOCK(clock_lock); diff --git a/arch/mips/loongson64/lemote-2f/dma.c b/arch/mips/loongson2ef/lemote-2f/dma.c similarity index 100% rename from arch/mips/loongson64/lemote-2f/dma.c rename to arch/mips/loongson2ef/lemote-2f/dma.c diff --git a/arch/mips/loongson64/lemote-2f/ec_kb3310b.c b/arch/mips/loongson2ef/lemote-2f/ec_kb3310b.c similarity index 100% rename from arch/mips/loongson64/lemote-2f/ec_kb3310b.c rename to arch/mips/loongson2ef/lemote-2f/ec_kb3310b.c diff --git a/arch/mips/loongson64/lemote-2f/ec_kb3310b.h b/arch/mips/loongson2ef/lemote-2f/ec_kb3310b.h similarity index 100% rename from arch/mips/loongson64/lemote-2f/ec_kb3310b.h rename to arch/mips/loongson2ef/lemote-2f/ec_kb3310b.h diff --git a/arch/mips/loongson64/lemote-2f/irq.c b/arch/mips/loongson2ef/lemote-2f/irq.c similarity index 99% rename from arch/mips/loongson64/lemote-2f/irq.c rename to arch/mips/loongson2ef/lemote-2f/irq.c index c58a044c6c07..2906f6fb2243 100644 --- a/arch/mips/loongson64/lemote-2f/irq.c +++ b/arch/mips/loongson2ef/lemote-2f/irq.c @@ -12,7 +12,7 @@ #include #include -#include +#include #include #define LOONGSON_TIMER_IRQ (MIPS_CPU_IRQ_BASE + 7) /* cpu timer */ diff --git a/arch/mips/loongson64/lemote-2f/machtype.c b/arch/mips/loongson2ef/lemote-2f/machtype.c similarity index 98% rename from arch/mips/loongson64/lemote-2f/machtype.c rename to arch/mips/loongson2ef/lemote-2f/machtype.c index 9462a3ab57be..0200e4223771 100644 --- a/arch/mips/loongson64/lemote-2f/machtype.c +++ b/arch/mips/loongson2ef/lemote-2f/machtype.c @@ -5,7 +5,7 @@ */ #include -#include +#include void __init mach_prom_init_machtype(void) { diff --git a/arch/mips/loongson64/lemote-2f/pm.c b/arch/mips/loongson2ef/lemote-2f/pm.c similarity index 99% rename from arch/mips/loongson64/lemote-2f/pm.c rename to arch/mips/loongson2ef/lemote-2f/pm.c index 3d0027229e3c..339601752d40 100644 --- a/arch/mips/loongson64/lemote-2f/pm.c +++ b/arch/mips/loongson2ef/lemote-2f/pm.c @@ -16,7 +16,7 @@ #include #include -#include +#include #include #include "ec_kb3310b.h" diff --git a/arch/mips/loongson64/lemote-2f/reset.c b/arch/mips/loongson2ef/lemote-2f/reset.c similarity index 99% rename from arch/mips/loongson64/lemote-2f/reset.c rename to arch/mips/loongson2ef/lemote-2f/reset.c index 0db0934302ea..faec0d919889 100644 --- a/arch/mips/loongson64/lemote-2f/reset.c +++ b/arch/mips/loongson2ef/lemote-2f/reset.c @@ -13,7 +13,7 @@ #include -#include +#include #include #include "ec_kb3310b.h" diff --git a/arch/mips/loongson64/Kconfig b/arch/mips/loongson64/Kconfig index d08b20ff2b27..025cd274146f 100644 --- a/arch/mips/loongson64/Kconfig +++ b/arch/mips/loongson64/Kconfig @@ -1,119 +1,9 @@ # SPDX-License-Identifier: GPL-2.0 if MACH_LOONGSON64 -choice - prompt "Machine Type" - -config LEMOTE_FULOONG2E - bool "Lemote Fuloong(2e) mini-PC" - select ARCH_SPARSEMEM_ENABLE - select ARCH_MIGHT_HAVE_PC_PARPORT - select ARCH_MIGHT_HAVE_PC_SERIO - select CEVT_R4K - select CSRC_R4K - select SYS_HAS_CPU_LOONGSON2E - select DMA_NONCOHERENT - select BOOT_ELF32 - select BOARD_SCACHE - select HAVE_PCI - select I8259 - select ISA - select IRQ_MIPS_CPU - select SYS_SUPPORTS_64BIT_KERNEL - select SYS_SUPPORTS_LITTLE_ENDIAN - select SYS_SUPPORTS_HIGHMEM - select SYS_HAS_EARLY_PRINTK - select GENERIC_ISA_DMA_SUPPORT_BROKEN - select CPU_HAS_WB - select LOONGSON_MC146818 - help - Lemote Fuloong(2e) mini-PC board based on the Chinese Loongson-2E CPU and - an FPGA northbridge - - Lemote Fuloong(2e) mini PC have a VIA686B south bridge. - -config LEMOTE_MACH2F - bool "Lemote Loongson 2F family machines" - select ARCH_SPARSEMEM_ENABLE - select ARCH_MIGHT_HAVE_PC_PARPORT - select ARCH_MIGHT_HAVE_PC_SERIO - select BOARD_SCACHE - select BOOT_ELF32 - select CEVT_R4K if ! MIPS_EXTERNAL_TIMER - select CPU_HAS_WB - select CS5536 - select CSRC_R4K if ! MIPS_EXTERNAL_TIMER - select DMA_NONCOHERENT - select GENERIC_ISA_DMA_SUPPORT_BROKEN - select HAVE_CLK - select HAVE_PCI - select I8259 - select IRQ_MIPS_CPU - select ISA - select SYS_HAS_CPU_LOONGSON2F - select SYS_HAS_EARLY_PRINTK - select SYS_SUPPORTS_64BIT_KERNEL - select SYS_SUPPORTS_HIGHMEM - select SYS_SUPPORTS_LITTLE_ENDIAN - select LOONGSON_MC146818 - help - Lemote Loongson 2F family machines utilize the 2F revision of - Loongson processor and the AMD CS5536 south bridge. - - These family machines include fuloong2f mini PC, yeeloong2f notebook, - LingLoong allinone PC and so forth. - -config LOONGSON_MACH3X - bool "Generic Loongson 3 family machines" - select ARCH_SPARSEMEM_ENABLE - select ARCH_MIGHT_HAVE_PC_PARPORT - select ARCH_MIGHT_HAVE_PC_SERIO - select GENERIC_ISA_DMA_SUPPORT_BROKEN - select BOOT_ELF32 - select BOARD_SCACHE - select CSRC_R4K - select CEVT_R4K - select CPU_HAS_WB - select FORCE_PCI - select ISA - select I8259 - select IRQ_MIPS_CPU - select NR_CPUS_DEFAULT_4 - select SYS_HAS_CPU_LOONGSON64 - select SYS_HAS_EARLY_PRINTK - select SYS_SUPPORTS_SMP - select SYS_SUPPORTS_HOTPLUG_CPU - select SYS_SUPPORTS_NUMA - select SYS_SUPPORTS_64BIT_KERNEL - select SYS_SUPPORTS_HIGHMEM - select SYS_SUPPORTS_LITTLE_ENDIAN - select LOONGSON_MC146818 - select ZONE_DMA32 - select LEFI_FIRMWARE_INTERFACE - help - Generic Loongson 3 family machines utilize the 3A/3B revision - of Loongson processor and RS780/SBX00 chipset. -endchoice - -config CS5536 - bool - -config CS5536_MFGPT - bool "CS5536 MFGPT Timer" - depends on CS5536 && !HIGH_RES_TIMERS - select MIPS_EXTERNAL_TIMER - help - This option enables the mfgpt0 timer of AMD CS5536. With this timer - switched on you can not use high resolution timers. - - If you want to enable the Loongson2 CPUFreq Driver, Please enable - this option at first, otherwise, You will get wrong system time. - - If unsure, say Yes. - config RS780_HPET bool "RS780/SBX00 HPET Timer" - depends on LOONGSON_MACH3X + depends on MACH_LOONGSON64 select MIPS_EXTERNAL_TIMER help This option enables the hpet timer of AMD RS780/SBX00. @@ -123,16 +13,4 @@ config RS780_HPET If unsure, say Yes. -config LOONGSON_UART_BASE - bool - default y - depends on EARLY_PRINTK || SERIAL_8250 - -config LOONGSON_MC146818 - bool - default n - -config LEFI_FIRMWARE_INTERFACE - bool - -endif # MACH_LOONGSON64 +endif diff --git a/arch/mips/loongson64/Makefile b/arch/mips/loongson64/Makefile index c74bc0251e9d..3c92e04e3827 100644 --- a/arch/mips/loongson64/Makefile +++ b/arch/mips/loongson64/Makefile @@ -1,24 +1,11 @@ # SPDX-License-Identifier: GPL-2.0-only # -# Common code for all Loongson based systems +# Makefile for Loongson64 family machines # +obj-y += irq.o cop2-ex.o platform.o acpi_init.o dma.o env.o platform.o reset.o setup.o pci.o -obj-$(CONFIG_MACH_LOONGSON64) += common/ +obj-$(CONFIG_SMP) += smp.o -# -# Lemote Fuloong mini-PC (Loongson 2E-based) -# - -obj-$(CONFIG_LEMOTE_FULOONG2E) += fuloong-2e/ - -# -# Lemote loongson2f family machines -# - -obj-$(CONFIG_LEMOTE_MACH2F) += lemote-2f/ - -# -# All Loongson-3 family machines -# +obj-$(CONFIG_NUMA) += numa.o -obj-$(CONFIG_CPU_LOONGSON64) += loongson-3/ +obj-$(CONFIG_RS780_HPET) += hpet.o diff --git a/arch/mips/loongson64/Platform b/arch/mips/loongson64/Platform index b4d2582eb1ef..7f4006833fa5 100644 --- a/arch/mips/loongson64/Platform +++ b/arch/mips/loongson64/Platform @@ -1,27 +1,7 @@ # -# Loongson Processors' Support +# Loongson64 Processors' Support # -# Only gcc >= 4.4 have Loongson specific support -cflags-$(CONFIG_CPU_LOONGSON2EF) += -Wa,--trap -cflags-$(CONFIG_CPU_LOONGSON2E) += \ - $(call cc-option,-march=loongson2e,-march=r4600) -cflags-$(CONFIG_CPU_LOONGSON2F) += \ - $(call cc-option,-march=loongson2f,-march=r4600) -# Enable the workarounds for Loongson2f -ifdef CONFIG_CPU_LOONGSON2F_WORKAROUNDS - ifeq ($(call as-option,-Wa$(comma)-mfix-loongson2f-nop,),) - $(error only binutils >= 2.20.2 have needed option -mfix-loongson2f-nop) - else - cflags-$(CONFIG_CPU_NOP_WORKAROUNDS) += -Wa$(comma)-mfix-loongson2f-nop - endif - ifeq ($(call as-option,-Wa$(comma)-mfix-loongson2f-jump,),) - $(error only binutils >= 2.20.2 have needed option -mfix-loongson2f-jump) - else - cflags-$(CONFIG_CPU_JUMP_WORKAROUNDS) += -Wa$(comma)-mfix-loongson2f-jump - endif -endif - cflags-$(CONFIG_CPU_LOONGSON64) += -Wa,--trap # @@ -72,6 +52,4 @@ endif platform-$(CONFIG_MACH_LOONGSON64) += loongson64/ cflags-$(CONFIG_MACH_LOONGSON64) += -I$(srctree)/arch/mips/include/asm/mach-loongson64 -mno-branch-likely -load-$(CONFIG_LEMOTE_FULOONG2E) += 0xffffffff80100000 -load-$(CONFIG_LEMOTE_MACH2F) += 0xffffffff80200000 -load-$(CONFIG_LOONGSON_MACH3X) += 0xffffffff80200000 +load-$(CONFIG_MACH_LOONGSON64) += 0xffffffff80200000 diff --git a/arch/mips/loongson64/loongson-3/acpi_init.c b/arch/mips/loongson64/acpi_init.c similarity index 99% rename from arch/mips/loongson64/loongson-3/acpi_init.c rename to arch/mips/loongson64/acpi_init.c index 8d7c119ddf91..3dd8135d2911 100644 --- a/arch/mips/loongson64/loongson-3/acpi_init.c +++ b/arch/mips/loongson64/acpi_init.c @@ -99,7 +99,8 @@ void acpi_registers_setup(void) pm_iowrite(0x2f, ACPI_END >> 8); /* IO Decode: When AcpiDecodeEnable set, South-Bridge uses the contents - * of the PM registers at index 0x20~0x2B to decode ACPI I/O address. */ + * of the PM registers at index 0x20~0x2B to decode ACPI I/O address. + */ pm_iowrite(0x0e, 1 << 3); /* SCI_EN set */ diff --git a/arch/mips/loongson64/loongson-3/cop2-ex.c b/arch/mips/loongson64/cop2-ex.c similarity index 88% rename from arch/mips/loongson64/loongson-3/cop2-ex.c rename to arch/mips/loongson64/cop2-ex.c index 9efdfe430ff0..508c707627ba 100644 --- a/arch/mips/loongson64/loongson-3/cop2-ex.c +++ b/arch/mips/loongson64/cop2-ex.c @@ -1,8 +1,5 @@ +// SPDX-License-Identifier: GPL-2.0 /* - * This file is subject to the terms and conditions of the GNU General Public - * License. See the file "COPYING" in the main directory of this archive - * for more details. - * * Copyright (C) 2014 Lemote Corporation. * written by Huacai Chen * diff --git a/arch/mips/loongson64/loongson-3/dma.c b/arch/mips/loongson64/dma.c similarity index 82% rename from arch/mips/loongson64/loongson-3/dma.c rename to arch/mips/loongson64/dma.c index 5e86635f71db..e2c3354d1d30 100644 --- a/arch/mips/loongson64/loongson-3/dma.c +++ b/arch/mips/loongson64/dma.c @@ -6,7 +6,8 @@ dma_addr_t __phys_to_dma(struct device *dev, phys_addr_t paddr) { /* We extract 2bit node id (bit 44~47, only bit 44~45 used now) from - * Loongson-3's 48bit address space and embed it into 40bit */ + * Loongson-3's 48bit address space and embed it into 40bit + */ long nid = (paddr >> 44) & 0x3; return ((nid << 44) ^ paddr) | (nid << 37); } @@ -14,7 +15,8 @@ dma_addr_t __phys_to_dma(struct device *dev, phys_addr_t paddr) phys_addr_t __dma_to_phys(struct device *dev, dma_addr_t daddr) { /* We extract 2bit node id (bit 44~47, only bit 44~45 used now) from - * Loongson-3's 48bit address space and embed it into 40bit */ + * Loongson-3's 48bit address space and embed it into 40bit + */ long nid = (daddr >> 37) & 0x3; return ((nid << 37) ^ daddr) | (nid << 44); } diff --git a/arch/mips/loongson64/common/env.c b/arch/mips/loongson64/env.c similarity index 79% rename from arch/mips/loongson64/common/env.c rename to arch/mips/loongson64/env.c index 09d5cf4676ca..93658cfbf3a6 100644 --- a/arch/mips/loongson64/common/env.c +++ b/arch/mips/loongson64/env.c @@ -15,7 +15,10 @@ */ #include #include -#include +#include +#include + +#include #include #include @@ -30,45 +33,17 @@ u64 loongson_freqctrl[MAX_PACKAGES]; unsigned long long smp_group[4]; -#define parse_even_earlier(res, option, p) \ -do { \ - unsigned int tmp __maybe_unused; \ - \ - if (strncmp(option, (char *)p, strlen(option)) == 0) \ - tmp = kstrtou32((char *)p + strlen(option"="), 10, &res); \ -} while (0) -void __init prom_init_env(void) +void __init prom_init_lefi(void) { /* pmon passes arguments in 32bit pointers */ unsigned int processor_id; -#ifndef CONFIG_LEFI_FIRMWARE_INTERFACE - int *_prom_envp; - long l; - - /* firmware arguments are initialized in head.S */ - _prom_envp = (int *)fw_arg2; - - l = (long)*_prom_envp; - while (l != 0) { - parse_even_earlier(cpu_clock_freq, "cpuclock", l); - parse_even_earlier(memsize, "memsize", l); - parse_even_earlier(highmemsize, "highmemsize", l); - _prom_envp++; - l = (long)*_prom_envp; - } - if (memsize == 0) - memsize = 256; - - loongson_sysconf.nr_uarts = 1; - - pr_info("memsize=%u, highmemsize=%u\n", memsize, highmemsize); -#else struct boot_params *boot_p; struct loongson_params *loongson_p; struct system_loongson *esys; struct efi_cpuinfo_loongson *ecpu; + struct board_devices *eboard; struct irq_source_routing_table *eirq_source; /* firmware arguments are initialized in head.S */ @@ -79,12 +54,15 @@ void __init prom_init_env(void) ((u64)loongson_p + loongson_p->system_offset); ecpu = (struct efi_cpuinfo_loongson *) ((u64)loongson_p + loongson_p->cpu_offset); + eboard = (struct board_devices *) + ((u64)loongson_p + loongson_p->boarddev_table_offset); eirq_source = (struct irq_source_routing_table *) ((u64)loongson_p + loongson_p->irq_offset); loongson_memmap = (struct efi_memory_map_loongson *) ((u64)loongson_p + loongson_p->memory_offset); cpu_clock_freq = ecpu->cpu_clock_freq; + mips_hpt_frequency = cpu_clock_freq / 2; loongson_sysconf.cputype = ecpu->cputype; switch (ecpu->cputype) { case Legacy_3A: @@ -151,6 +129,7 @@ void __init prom_init_env(void) loongson_sysconf.pci_mem_start_addr = eirq_source->pci_mem_start_addr; loongson_sysconf.pci_mem_end_addr = eirq_source->pci_mem_end_addr; loongson_sysconf.pci_io_base = eirq_source->pci_io_start_addr; + set_io_port_base(loongson_sysconf.pci_io_base); loongson_sysconf.dma_mask_bits = eirq_source->dma_mask_bits; if (loongson_sysconf.dma_mask_bits < 32 || loongson_sysconf.dma_mask_bits > 64) @@ -165,6 +144,9 @@ void __init prom_init_env(void) loongson_sysconf.poweroff_addr, loongson_sysconf.restart_addr, loongson_sysconf.vgabios_addr); + if (eboard->name) + mips_set_machine_name(eboard->name); + memset(loongson_sysconf.ecname, 0, 32); if (esys->has_ec) memcpy(loongson_sysconf.ecname, esys->ec_name, 32); @@ -182,31 +164,7 @@ void __init prom_init_env(void) if (loongson_sysconf.nr_sensors) memcpy(loongson_sysconf.sensors, esys->sensors, sizeof(struct sensor_device) * loongson_sysconf.nr_sensors); -#endif - if (cpu_clock_freq == 0) { - processor_id = (¤t_cpu_data)->processor_id; - switch (processor_id & PRID_REV_MASK) { - case PRID_REV_LOONGSON2E: - cpu_clock_freq = 533080000; - break; - case PRID_REV_LOONGSON2F: - cpu_clock_freq = 797000000; - break; - case PRID_REV_LOONGSON3A_R1: - case PRID_REV_LOONGSON3A_R2_0: - case PRID_REV_LOONGSON3A_R2_1: - case PRID_REV_LOONGSON3A_R3_0: - case PRID_REV_LOONGSON3A_R3_1: - cpu_clock_freq = 900000000; - break; - case PRID_REV_LOONGSON3B_R1: - case PRID_REV_LOONGSON3B_R2: - cpu_clock_freq = 1000000000; - break; - default: - cpu_clock_freq = 100000000; - break; - } - } + processor_id = (¤t_cpu_data)->processor_id; + pr_info("CpuClock = %u\n", cpu_clock_freq); } diff --git a/arch/mips/loongson64/loongson-3/hpet.c b/arch/mips/loongson64/hpet.c similarity index 100% rename from arch/mips/loongson64/loongson-3/hpet.c rename to arch/mips/loongson64/hpet.c diff --git a/arch/mips/loongson64/loongson-3/irq.c b/arch/mips/loongson64/irq.c similarity index 77% rename from arch/mips/loongson64/loongson-3/irq.c rename to arch/mips/loongson64/irq.c index 5605061f5f98..4d7b80a0ffb9 100644 --- a/arch/mips/loongson64/loongson-3/irq.c +++ b/arch/mips/loongson64/irq.c @@ -1,5 +1,5 @@ // SPDX-License-Identifier: GPL-2.0 -#include +#include #include #include #include @@ -10,6 +10,19 @@ #include "smp.h" +/* ICU Configuration Regs - r/w */ + +#define LOONGSON_INTEDGE LOONGSON_REG(LOONGSON_REGBASE + 0x24) +#define LOONGSON_INTSTEER LOONGSON_REG(LOONGSON_REGBASE + 0x28) +#define LOONGSON_INTPOL LOONGSON_REG(LOONGSON_REGBASE + 0x2c) + +/* ICU Enable Regs - IntEn & IntISR are r/o. */ + +#define LOONGSON_INTENSET LOONGSON_REG(LOONGSON_REGBASE + 0x30) +#define LOONGSON_INTENCLR LOONGSON_REG(LOONGSON_REGBASE + 0x34) +#define LOONGSON_INTEN LOONGSON_REG(LOONGSON_REGBASE + 0x38) +#define LOONGSON_INTISR LOONGSON_REG(LOONGSON_REGBASE + 0x3c) + extern void loongson3_send_irq_by_ipi(int cpu, int irqs); unsigned int irq_cpu[16] = {[0 ... 15] = -1}; @@ -78,13 +91,17 @@ static void ht_irqdispatch(void) #define UNUSED_IPS (CAUSEF_IP5 | CAUSEF_IP4 | CAUSEF_IP1 | CAUSEF_IP0) -void mach_irq_dispatch(unsigned int pending) +asmlinkage void plat_irq_dispatch(void) { + unsigned int pending; + + pending = read_c0_cause() & read_c0_status() & ST0_IM; + if (pending & CAUSEF_IP7) do_IRQ(LOONGSON_TIMER_IRQ); #if defined(CONFIG_SMP) if (pending & CAUSEF_IP6) - loongson3_ipi_interrupt(NULL); + loongson3_ipi_interrupt(); #endif if (pending & CAUSEF_IP3) ht_irqdispatch(); @@ -127,10 +144,25 @@ void irq_router_init(void) LOONGSON_INT_ROUTER_INTEN | (0xffff << 16) | 0x1 << 10; } -void __init mach_init_irq(void) +void __init arch_init_irq(void) { struct irq_chip *chip; + /* + * Clear all of the interrupts while we change the able around a bit. + * int-handler is not on bootstrap + */ + clear_c0_status(ST0_IM | ST0_BEV); + + /* no steer */ + LOONGSON_INTSTEER = 0; + + /* + * Mask out all interrupt by writing "1" to all bit position in + * the interrupt reset reg. + */ + LOONGSON_INTENCLR = ~0; + clear_c0_status(ST0_IM | ST0_BEV); irq_router_init(); diff --git a/arch/mips/loongson64/loongson-3/Makefile b/arch/mips/loongson64/loongson-3/Makefile deleted file mode 100644 index df39598742b2..000000000000 --- a/arch/mips/loongson64/loongson-3/Makefile +++ /dev/null @@ -1,11 +0,0 @@ -# SPDX-License-Identifier: GPL-2.0-only -# -# Makefile for Loongson-3 family machines -# -obj-y += irq.o cop2-ex.o platform.o acpi_init.o dma.o - -obj-$(CONFIG_SMP) += smp.o - -obj-$(CONFIG_NUMA) += numa.o - -obj-$(CONFIG_RS780_HPET) += hpet.o diff --git a/arch/mips/loongson64/loongson-3/numa.c b/arch/mips/loongson64/numa.c similarity index 98% rename from arch/mips/loongson64/loongson-3/numa.c rename to arch/mips/loongson64/numa.c index 414e97de5dc0..de3d3d682694 100644 --- a/arch/mips/loongson64/loongson-3/numa.c +++ b/arch/mips/loongson64/numa.c @@ -98,6 +98,7 @@ static void __init init_topology_matrix(void) static unsigned long nid_to_addroffset(unsigned int nid) { unsigned long result; + switch (nid) { case 0: default: @@ -119,7 +120,7 @@ static unsigned long nid_to_addroffset(unsigned int nid) static void __init szmem(unsigned int node) { u32 i, mem_type; - static unsigned long num_physpages = 0; + static unsigned long num_physpages; u64 node_id, node_psize, start_pfn, end_pfn, mem_start, mem_size; /* Parse memory information and activate */ @@ -276,4 +277,3 @@ void __init prom_init_numa_memory(void) enable_lpa(); prom_meminit(); } -EXPORT_SYMBOL(prom_init_numa_memory); diff --git a/arch/mips/loongson64/pci.c b/arch/mips/loongson64/pci.c new file mode 100644 index 000000000000..4e896817aadc --- /dev/null +++ b/arch/mips/loongson64/pci.c @@ -0,0 +1,45 @@ +// SPDX-License-Identifier: GPL-2.0-or-later +/* + * Copyright (C) 2007 Lemote, Inc. & Institute of Computing Technology + * Author: Fuxin Zhang, zhangfx@lemote.com + */ +#include + +#include +#include + +static struct resource loongson_pci_mem_resource = { + .name = "PCI Memory Space", + .flags = IORESOURCE_MEM, +}; + +static struct resource loongson_pci_io_resource = { + .name = "PCI IO Space", + .end = IO_SPACE_LIMIT, + .flags = IORESOURCE_IO, +}; + +static struct pci_controller loongson_pci_controller = { + .pci_ops = &loongson_pci_ops, + .io_resource = &loongson_pci_io_resource, + .mem_resource = &loongson_pci_mem_resource, + .mem_offset = 0x00000000UL, + .io_offset = 0x00000000UL, +}; + +extern int sbx00_acpi_init(void); + +static int __init pcibios_init(void) +{ + loongson_pci_controller.io_map_base = mips_io_port_base; + loongson_pci_mem_resource.start = loongson_sysconf.pci_mem_start_addr; + loongson_pci_mem_resource.end = loongson_sysconf.pci_mem_end_addr; + + register_pci_controller(&loongson_pci_controller); + + sbx00_acpi_init(); + + return 0; +} + +arch_initcall(pcibios_init); diff --git a/arch/mips/loongson64/loongson-3/platform.c b/arch/mips/loongson64/platform.c similarity index 100% rename from arch/mips/loongson64/loongson-3/platform.c rename to arch/mips/loongson64/platform.c diff --git a/arch/mips/loongson64/reset.c b/arch/mips/loongson64/reset.c new file mode 100644 index 000000000000..0bbd2a38c127 --- /dev/null +++ b/arch/mips/loongson64/reset.c @@ -0,0 +1,58 @@ +// SPDX-License-Identifier: GPL-2.0-or-later +/* + * + * Copyright (C) 2007 Lemote, Inc. & Institute of Computing Technology + * Author: Fuxin Zhang, zhangfx@lemote.com + * Copyright (C) 2009 Lemote, Inc. + * Author: Zhangjin Wu, wuzhangjin@gmail.com + */ +#include +#include + +#include +#include + +#include +#include + +static void loongson_restart(char *command) +{ + void (*fw_restart)(void) = (void *)loongson_sysconf.restart_addr; + + fw_restart(); + while (1) { + if (cpu_wait) + cpu_wait(); + } +} + +static void loongson_poweroff(void) +{ + void (*fw_poweroff)(void) = (void *)loongson_sysconf.poweroff_addr; + + fw_poweroff(); + while (1) { + if (cpu_wait) + cpu_wait(); + } +} + +static void loongson_halt(void) +{ + pr_notice("\n\n** You can safely turn off the power now **\n\n"); + while (1) { + if (cpu_wait) + cpu_wait(); + } +} + +static int __init mips_reboot_setup(void) +{ + _machine_restart = loongson_restart; + _machine_halt = loongson_halt; + pm_power_off = loongson_poweroff; + + return 0; +} + +arch_initcall(mips_reboot_setup); diff --git a/arch/mips/loongson64/setup.c b/arch/mips/loongson64/setup.c new file mode 100644 index 000000000000..24432adc8350 --- /dev/null +++ b/arch/mips/loongson64/setup.c @@ -0,0 +1,92 @@ +// SPDX-License-Identifier: GPL-2.0-or-later +#include +#include +#include +#include +#include +#include +#include +#include + +#include + +static void wbflush_loongson(void) +{ + asm(".set\tpush\n\t" + ".set\tnoreorder\n\t" + ".set mips3\n\t" + "sync\n\t" + "nop\n\t" + ".set\tpop\n\t" + ".set mips0\n\t"); +} + +void (*__wbflush)(void) = wbflush_loongson; +EXPORT_SYMBOL(__wbflush); + +const char *get_system_type(void) +{ + return mips_get_machine_name(); +} + +static void __init mips_nmi_setup(void) +{ + void *base; + extern char except_vec_nmi; + + base = (void *)(CAC_BASE + 0x380); + memcpy(base, &except_vec_nmi, 0x80); + flush_icache_range((unsigned long)base, (unsigned long)base + 0x80); +} + +void __init prom_init_cmdline(void) +{ + int prom_argc; + /* pmon passes arguments in 32bit pointers */ + int *_prom_argv; + int i; + long l; + + /* firmware arguments are initialized in head.S */ + prom_argc = fw_arg0; + _prom_argv = (int *)fw_arg1; + + /* arg[0] is "g", the rest is boot parameters */ + arcs_cmdline[0] = '\0'; + for (i = 1; i < prom_argc; i++) { + l = (long)_prom_argv[i]; + if (strlen(arcs_cmdline) + strlen(((char *)l) + 1) + >= sizeof(arcs_cmdline)) + break; + strcat(arcs_cmdline, ((char *)l)); + strcat(arcs_cmdline, " "); + } +} + +void __init prom_init(void) +{ + prom_init_cmdline(); + setup_8250_early_printk_port(CKSEG1ADDR(LOONGSON_REG_BASE + 0x1e0), 0, 0); + + prom_init_lefi(); + prom_init_numa_memory(); + + register_smp_ops(&loongson3_smp_ops); + board_nmi_handler_setup = mips_nmi_setup; +} + +void __init prom_free_prom_memory(void) +{ +} + +void __init plat_mem_setup(void) +{ +} + +void __init plat_time_init(void) +{ +#ifdef CONFIG_RS780_HPET + setup_hpet_timer(); +#endif +} + diff --git a/arch/mips/loongson64/loongson-3/smp.c b/arch/mips/loongson64/smp.c similarity index 99% rename from arch/mips/loongson64/loongson-3/smp.c rename to arch/mips/loongson64/smp.c index ce68cdaaf33c..8ad845e522fb 100644 --- a/arch/mips/loongson64/loongson-3/smp.c +++ b/arch/mips/loongson64/smp.c @@ -17,7 +17,7 @@ #include #include #include -#include +#include #include #include "smp.h" @@ -252,7 +252,7 @@ void loongson3_send_irq_by_ipi(int cpu, int irqs) loongson3_ipi_write32(irqs << IPI_IRQ_OFFSET, ipi_set0_regs[cpu_logical_map(cpu)]); } -void loongson3_ipi_interrupt(struct pt_regs *regs) +void loongson3_ipi_interrupt() { int i, cpu = smp_processor_id(); unsigned int action, c0count, irqs; diff --git a/arch/mips/loongson64/loongson-3/smp.h b/arch/mips/loongson64/smp.h similarity index 100% rename from arch/mips/loongson64/loongson-3/smp.h rename to arch/mips/loongson64/smp.h diff --git a/arch/mips/oprofile/op_model_loongson2.c b/arch/mips/oprofile/op_model_loongson2.c index b249ec0bebb2..8f739679a5e8 100644 --- a/arch/mips/oprofile/op_model_loongson2.c +++ b/arch/mips/oprofile/op_model_loongson2.c @@ -13,7 +13,7 @@ #include #include -#include /* LOONGSON2_PERFCNT_IRQ */ +#include /* LOONGSON2_PERFCNT_IRQ */ #include "op_impl.h" #define LOONGSON2_CPU_TYPE "mips/loongson2" diff --git a/arch/mips/oprofile/op_model_loongson3.c b/arch/mips/oprofile/op_model_loongson3.c index 436b1fc99f2c..222077e49bc6 100644 --- a/arch/mips/oprofile/op_model_loongson3.c +++ b/arch/mips/oprofile/op_model_loongson3.c @@ -13,7 +13,7 @@ #include #include #include -#include +#include #include "op_impl.h" #define LOONGSON3_PERFCNT_OVERFLOW (1ULL << 63) diff --git a/arch/mips/pci/Makefile b/arch/mips/pci/Makefile index d6de4cb2e31c..342ce10ef593 100644 --- a/arch/mips/pci/Makefile +++ b/arch/mips/pci/Makefile @@ -35,7 +35,7 @@ obj-$(CONFIG_LASAT) += pci-lasat.o obj-$(CONFIG_MIPS_COBALT) += fixup-cobalt.o obj-$(CONFIG_LEMOTE_FULOONG2E) += fixup-fuloong2e.o ops-loongson2.o obj-$(CONFIG_LEMOTE_MACH2F) += fixup-lemote2f.o ops-loongson2.o -obj-$(CONFIG_LOONGSON_MACH3X) += fixup-loongson3.o ops-loongson3.o +obj-$(CONFIG_MACH_LOONGSON64) += fixup-loongson3.o ops-loongson3.o obj-$(CONFIG_MIPS_MALTA) += fixup-malta.o pci-malta.o obj-$(CONFIG_PMC_MSP7120_GW) += fixup-pmcmsp.o ops-pmcmsp.o obj-$(CONFIG_PMC_MSP7120_EVAL) += fixup-pmcmsp.o ops-pmcmsp.o diff --git a/arch/mips/pci/fixup-fuloong2e.c b/arch/mips/pci/fixup-fuloong2e.c index 91aa923234bc..60b6caec02c0 100644 --- a/arch/mips/pci/fixup-fuloong2e.c +++ b/arch/mips/pci/fixup-fuloong2e.c @@ -10,7 +10,7 @@ #include #include -#include +#include /* South bridge slot number is set by the pci probe process */ static u8 sb_slot = 5; diff --git a/arch/mips/pci/fixup-lemote2f.c b/arch/mips/pci/fixup-lemote2f.c index 632ff2daa338..f998ca1555a5 100644 --- a/arch/mips/pci/fixup-lemote2f.c +++ b/arch/mips/pci/fixup-lemote2f.c @@ -10,7 +10,7 @@ #include #include -#include +#include #include #include diff --git a/arch/mips/pci/ops-loongson2.c b/arch/mips/pci/ops-loongson2.c index 0d1b36ba1c21..f5f479252a3a 100644 --- a/arch/mips/pci/ops-loongson2.c +++ b/arch/mips/pci/ops-loongson2.c @@ -13,7 +13,7 @@ #include #include -#include +#include #ifdef CONFIG_CS5536 #include diff --git a/arch/mips/pci/ops-loongson3.c b/arch/mips/pci/ops-loongson3.c index 2f6ad36bdea6..7f66c8cde773 100644 --- a/arch/mips/pci/ops-loongson3.c +++ b/arch/mips/pci/ops-loongson3.c @@ -5,7 +5,7 @@ #include -#include +#include #define PCI_ACCESS_READ 0 #define PCI_ACCESS_WRITE 1 diff --git a/drivers/cpufreq/loongson2_cpufreq.c b/drivers/cpufreq/loongson2_cpufreq.c index 890813e0bb76..a3b6f17e6e0a 100644 --- a/drivers/cpufreq/loongson2_cpufreq.c +++ b/drivers/cpufreq/loongson2_cpufreq.c @@ -23,7 +23,7 @@ #include #include -#include +#include static uint nowait; diff --git a/drivers/gpio/gpio-loongson.c b/drivers/gpio/gpio-loongson.c index a42145873cc9..7b72846a6dc7 100644 --- a/drivers/gpio/gpio-loongson.c +++ b/drivers/gpio/gpio-loongson.c @@ -17,7 +17,7 @@ #include #include #include -#include +#include #define STLS2F_N_GPIO 4 #define STLS3A_N_GPIO 16 diff --git a/drivers/platform/mips/cpu_hwmon.c b/drivers/platform/mips/cpu_hwmon.c index a7f184bb47e0..7b5805b4988c 100644 --- a/drivers/platform/mips/cpu_hwmon.c +++ b/drivers/platform/mips/cpu_hwmon.c @@ -6,7 +6,7 @@ #include #include -#include +#include #include #include From patchwork Tue Aug 27 08:52:52 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Jiaxun Yang X-Patchwork-Id: 11116411 Return-Path: Received: from mail.kernel.org (pdx-korg-mail-1.web.codeaurora.org [172.30.200.123]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id E087614DE for ; Tue, 27 Aug 2019 08:54:10 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.kernel.org (Postfix) with ESMTP id B504B2184D for ; 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t=1566896047; bh=3ncFV5CIf6z1hcaq7XFDclunuP2nn4MnLCLFu4xo8FA=; h=In-Reply-To:Subject:To:From:Cc:References:Date:Message-Id; b=CkZREjclz01e2HUp98KeCCylJk13Lw4po5jZIT4vnXWK8GBFl62uX25Y7F6bIBuwW fGSRjm0c+1W4ni4mdb6xMKjWQrKVs5lIaRGsLsA1UrVXy04a43ietzyTtiV+0GNjEh w5bjBPU3Klu4tb3ojEWOCxVXSUw6NaQUtowLLCCA= Authentication-Results: mxback10j.mail.yandex.net; dkim=pass header.i=@flygoat.com Received: by smtp1p.mail.yandex.net (nwsmtp/Yandex) with ESMTPSA id JOqUfE8LDO-rxtCxnKu; Tue, 27 Aug 2019 11:54:04 +0300 (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits)) (Client certificate not present) From: Jiaxun Yang To: linux-mips@vger.kernel.org Cc: chenhc@lemote.com, paul.burton@mips.com, tglx@linutronix.de, jason@lakedaemon.net, maz@kernel.org, linux-kernel@vger.kernel.org, robh+dt@kernel.org, mark.rutland@arm.co, devicetree@vger.kernel.org, Jiaxun Yang Subject: [PATCH 03/13] MAINTAINERS: Fix entries for new loongson64 path Date: Tue, 27 Aug 2019 16:52:52 +0800 Message-Id: <20190827085302.5197-4-jiaxun.yang@flygoat.com> X-Mailer: git-send-email 2.22.0 In-Reply-To: <20190827085302.5197-1-jiaxun.yang@flygoat.com> References: <20190827085302.5197-1-jiaxun.yang@flygoat.com> MIME-Version: 1.0 Sender: linux-mips-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-mips@vger.kernel.org As we sepreated the code of loongson2ef/loongson3a, they can now have their own entries. Signed-off-by: Jiaxun Yang --- MAINTAINERS | 9 ++++----- 1 file changed, 4 insertions(+), 5 deletions(-) diff --git a/MAINTAINERS b/MAINTAINERS index a2c343ee3b2c..d5d4fed632e6 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -10747,17 +10747,16 @@ F: arch/mips/include/asm/mach-loongson32/ F: drivers/*/*loongson1* F: drivers/*/*/*loongson1* -MIPS/LOONGSON2 ARCHITECTURE +MIPS/LOONGSON2E/F ARCHITECTURE M: Jiaxun Yang L: linux-mips@vger.kernel.org S: Maintained -F: arch/mips/loongson64/fuloong-2e/ -F: arch/mips/loongson64/lemote-2f/ -F: arch/mips/include/asm/mach-loongson64/ +F: arch/mips/loongson2ef/ +F: arch/mips/include/asm/mach-loongson2ef/ F: drivers/*/*loongson2* F: drivers/*/*/*loongson2* -MIPS/LOONGSON3 ARCHITECTURE +MIPS/LOONGSON64 ARCHITECTURE M: Huacai Chen L: linux-mips@vger.kernel.org S: Maintained From patchwork Tue Aug 27 08:52:53 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Jiaxun Yang X-Patchwork-Id: 11116415 Return-Path: Received: from mail.kernel.org (pdx-korg-mail-1.web.codeaurora.org [172.30.200.123]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id 5BD4B14F7 for ; Tue, 27 Aug 2019 08:54:21 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.kernel.org (Postfix) with ESMTP id 315332184D for ; Tue, 27 Aug 2019 08:54:21 +0000 (UTC) Authentication-Results: mail.kernel.org; dkim=pass (1024-bit key) header.d=flygoat.com header.i=@flygoat.com header.b="QCk1lKO6" Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1729843AbfH0IyT (ORCPT ); Tue, 27 Aug 2019 04:54:19 -0400 Received: from forward105o.mail.yandex.net ([37.140.190.183]:50463 "EHLO forward105o.mail.yandex.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1729493AbfH0IyS (ORCPT ); Tue, 27 Aug 2019 04:54:18 -0400 Received: from mxback4o.mail.yandex.net (mxback4o.mail.yandex.net [IPv6:2a02:6b8:0:1a2d::1e]) by forward105o.mail.yandex.net (Yandex) with ESMTP id 5E7274200EE3; Tue, 27 Aug 2019 11:54:14 +0300 (MSK) Received: from smtp1p.mail.yandex.net (smtp1p.mail.yandex.net [2a02:6b8:0:1472:2741:0:8b6:6]) by mxback4o.mail.yandex.net (nwsmtp/Yandex) with ESMTP id UMT5yPq767-sEVuVvkC; Tue, 27 Aug 2019 11:54:14 +0300 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=flygoat.com; s=mail; t=1566896054; bh=ry65v6/TCRoZrNVykYmi6U0q0PkAZQvhlV9P2rFjxqk=; h=In-Reply-To:Subject:To:From:Cc:References:Date:Message-Id; b=QCk1lKO6tpPDXu0FYi0iroiZsKI2cSvmd27cjtxSx0qyFpH7igwvqqlN+76dQQioS UINbaslhSCm8ywi9ucAzBXHEd9OD8uRJFY2pHhAf3eCOV3m4ExufOjbTFvUzZ4u3W5 edco12MZ1VJYOyRhzPTsC/lk8gUOzsQ5KrKMz018= Authentication-Results: mxback4o.mail.yandex.net; dkim=pass header.i=@flygoat.com Received: by smtp1p.mail.yandex.net (nwsmtp/Yandex) with ESMTPSA id JOqUfE8LDO-s7tCT8dN; Tue, 27 Aug 2019 11:54:12 +0300 (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits)) (Client certificate not present) From: Jiaxun Yang To: linux-mips@vger.kernel.org Cc: chenhc@lemote.com, paul.burton@mips.com, tglx@linutronix.de, jason@lakedaemon.net, maz@kernel.org, linux-kernel@vger.kernel.org, robh+dt@kernel.org, mark.rutland@arm.co, devicetree@vger.kernel.org, Jiaxun Yang Subject: [PATCH 04/13] irqchip: Add driver for Loongson-3 I/O interrupt controller Date: Tue, 27 Aug 2019 16:52:53 +0800 Message-Id: <20190827085302.5197-5-jiaxun.yang@flygoat.com> X-Mailer: git-send-email 2.22.0 In-Reply-To: <20190827085302.5197-1-jiaxun.yang@flygoat.com> References: <20190827085302.5197-1-jiaxun.yang@flygoat.com> MIME-Version: 1.0 Sender: linux-mips-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-mips@vger.kernel.org This controller appeared on Loongson-3 family of chips as the primary package interrupt source. Signed-off-by: Jiaxun Yang --- drivers/irqchip/Kconfig | 9 ++ drivers/irqchip/Makefile | 1 + drivers/irqchip/irq-ls3-iointc.c | 216 +++++++++++++++++++++++++++++++ 3 files changed, 226 insertions(+) create mode 100644 drivers/irqchip/irq-ls3-iointc.c diff --git a/drivers/irqchip/Kconfig b/drivers/irqchip/Kconfig index 80e10f4e213a..8d9eac5fd4a7 100644 --- a/drivers/irqchip/Kconfig +++ b/drivers/irqchip/Kconfig @@ -471,6 +471,15 @@ config TI_SCI_INTA_IRQCHIP If you wish to use interrupt aggregator irq resources managed by the TI System Controller, say Y here. Otherwise, say N. +config LS3_IOINTC + bool "Loongson3 I/O Interrupt Controller" + depends on MACH_LOONGSON64 + default y + select IRQ_DOMAIN + select GENERIC_IRQ_CHIP + help + Support for the Loongson-3 I/O Interrupt Controller. + endmenu config SIFIVE_PLIC diff --git a/drivers/irqchip/Makefile b/drivers/irqchip/Makefile index 8d0fcec6ab23..49ecb8d38138 100644 --- a/drivers/irqchip/Makefile +++ b/drivers/irqchip/Makefile @@ -102,3 +102,4 @@ obj-$(CONFIG_MADERA_IRQ) += irq-madera.o obj-$(CONFIG_LS1X_IRQ) += irq-ls1x.o obj-$(CONFIG_TI_SCI_INTR_IRQCHIP) += irq-ti-sci-intr.o obj-$(CONFIG_TI_SCI_INTA_IRQCHIP) += irq-ti-sci-inta.o +obj-$(CONFIG_LS3_IOINTC) += irq-ls3-iointc.o diff --git a/drivers/irqchip/irq-ls3-iointc.c b/drivers/irqchip/irq-ls3-iointc.c new file mode 100644 index 000000000000..1fc3c41c57d9 --- /dev/null +++ b/drivers/irqchip/irq-ls3-iointc.c @@ -0,0 +1,216 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Copyright (C) 2019, Jiaxun Yang + * Loongson-3 IOINTC IRQ support + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + + +#define LS3_CHIP_IRQ 32 + +#define LS3_INTC_CHIP_START 0x20 + +#define LS3_REG_INTC_STATUS 0x00 +#define LS3_REG_INTC_EN_STATUS 0x04 +#define LS3_REG_INTC_ENABLE 0x08 +#define LS3_REG_INTC_DISABLE 0x0c +#define LS3_REG_INTC_POL 0x10 +#define LS3_REG_INTC_EDGE 0x18 + +#define LS3_MAP_CORE_INT(x, y) (u8)(BIT(x) | (BIT(y) << 4)) + + +struct ls3_iointc_priv { + struct irq_domain *domain; + void __iomem *intc_base; +}; + + +static void ls3_io_chained_handle_irq(struct irq_desc *desc) +{ + struct ls3_iointc_priv *priv = irq_desc_get_handler_data(desc); + struct irq_chip *chip = irq_desc_get_chip(desc); + u32 pending; + + chained_irq_enter(chip, desc); + + pending = readl(priv->intc_base + LS3_REG_INTC_EN_STATUS) & + readl(priv->intc_base + LS3_REG_INTC_STATUS); + + if (!pending) + spurious_interrupt(); + + while (pending) { + int bit = __ffs(pending); + + generic_handle_irq(irq_find_mapping(priv->domain, bit)); + pending &= ~BIT(bit); + } + + chained_irq_exit(chip, desc); +} + + +static void ls_intc_set_bit(struct irq_chip_generic *gc, + unsigned int offset, + u32 mask, bool set) +{ + if (set) + writel(readl(gc->reg_base + offset) | mask, + gc->reg_base + offset); + else + writel(readl(gc->reg_base + offset) & ~mask, + gc->reg_base + offset); +} + +static int ls_intc_set_type(struct irq_data *data, unsigned int type) +{ + struct irq_chip_generic *gc = irq_data_get_irq_chip_data(data); + u32 mask = data->mask; + + switch (type) { + case IRQ_TYPE_LEVEL_HIGH: + ls_intc_set_bit(gc, LS3_REG_INTC_EDGE, mask, false); + ls_intc_set_bit(gc, LS3_REG_INTC_POL, mask, true); + break; + case IRQ_TYPE_LEVEL_LOW: + ls_intc_set_bit(gc, LS3_REG_INTC_EDGE, mask, false); + ls_intc_set_bit(gc, LS3_REG_INTC_POL, mask, false); + break; + case IRQ_TYPE_EDGE_RISING: + ls_intc_set_bit(gc, LS3_REG_INTC_EDGE, mask, true); + ls_intc_set_bit(gc, LS3_REG_INTC_POL, mask, true); + break; + case IRQ_TYPE_EDGE_FALLING: + ls_intc_set_bit(gc, LS3_REG_INTC_EDGE, mask, true); + ls_intc_set_bit(gc, LS3_REG_INTC_POL, mask, false); + break; + default: + return -EINVAL; + } + + irqd_set_trigger_type(data, type); + return 0; +} + +int __init ls3_iointc_of_init(struct device_node *node, + struct device_node *parent) +{ + struct irq_chip_generic *gc; + struct irq_chip_type *ct; + struct ls3_iointc_priv *priv; + int parent_irq, err = 0; + int core = cpu_logical_map(smp_processor_id()); + int ip = 0; + int i; + const u32 *map_ip, *map_core; + + priv = kzalloc(sizeof(*priv), GFP_KERNEL); + if (!priv) + return -ENOMEM; + + priv->intc_base = of_iomap(node, 0); + if (!priv->intc_base) { + err = -ENODEV; + goto out_free_priv; + } + + map_ip = of_get_property(node, "loongson,map-ip", NULL); + if (!map_ip) + goto no_ip; + else if ((*map_ip) > 5) + pr_err("* %pOF loongson,map-ip is invalid\n", node); + else + ip = (*map_ip); +no_ip: + + /* If this property does not exist or invalid, + * we map all IRQs to bootcore. + */ + map_core = of_get_property(node, "loongson,map-core", NULL); + if (!map_core) + goto no_core; + else if ((*map_core) > 3) + pr_err("* %pOF loongson,map-core is invalid\n", node); + else + core = (*map_core); +no_core: + + parent_irq = irq_of_parse_and_map(node, 0); + if (!parent_irq) { + pr_err("ls3-iointc: unable to get parent irq\n"); + err = -ENODEV; + goto out_iounmap; + } + /* Set up an IRQ domain */ + priv->domain = irq_domain_add_linear(node, 32, &irq_generic_chip_ops, + NULL); + if (!priv->domain) { + pr_err("ls3-iointc: cannot add IRQ domain\n"); + err = -ENOMEM; + goto out_iounmap; + } + + err = irq_alloc_domain_generic_chips(priv->domain, 32, 1, + node->full_name, handle_level_irq, + IRQ_NOPROBE, 0, 0); + if (err) { + pr_err("ls3-iointc: unable to register IRQ domain\n"); + err = -ENOMEM; + goto out_free_domain; + } + + /* + * Q: Why don't we set IRQ affinity by these registers? + * A: Hardware IRQ delivery is seriously broken, + * so we map all IRQs to a fixed core. + */ + pr_info("ls3-iointc: Mapping All ls3-iointc IRQ to core %d, IP %d\n", core, ip); + for (i = 0; i < LS3_CHIP_IRQ; i++) + writeb(LS3_MAP_CORE_INT(core, ip), priv->intc_base + 0x1 * i); + priv->intc_base += LS3_INTC_CHIP_START; + + /* Disable all IRQs */ + writel(0xffffffff, priv->intc_base + LS3_REG_INTC_DISABLE); + /* Set to level triggered */ + writel(0x0, priv->intc_base + LS3_REG_INTC_EDGE); + + gc = irq_get_domain_generic_chip(priv->domain, 0); + gc->reg_base = priv->intc_base; + gc->domain = priv->domain; + + ct = gc->chip_types; + ct->regs.enable = LS3_REG_INTC_ENABLE; + ct->regs.disable = LS3_REG_INTC_DISABLE; + ct->chip.irq_unmask = irq_gc_unmask_enable_reg; + ct->chip.irq_mask = irq_gc_mask_disable_reg; + ct->chip.irq_mask_ack = irq_gc_mask_disable_reg; + ct->chip.irq_set_type = ls_intc_set_type; + + irq_set_chained_handler_and_data(parent_irq, + ls3_io_chained_handle_irq, priv); + + return 0; + +out_free_domain: + irq_domain_remove(priv->domain); +out_iounmap: + iounmap(priv->intc_base); +out_free_priv: + kfree(priv); + + return err; +} + +IRQCHIP_DECLARE(ls3_iointc, "loongson,ls3-iointc", ls3_iointc_of_init); From patchwork Tue Aug 27 08:52:54 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Jiaxun Yang X-Patchwork-Id: 11116419 Return-Path: Received: from mail.kernel.org (pdx-korg-mail-1.web.codeaurora.org [172.30.200.123]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id 12A2314F7 for ; Tue, 27 Aug 2019 08:54:26 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.kernel.org (Postfix) with ESMTP id E5BB82184D for ; Tue, 27 Aug 2019 08:54:25 +0000 (UTC) Authentication-Results: mail.kernel.org; dkim=pass (1024-bit key) header.d=flygoat.com header.i=@flygoat.com header.b="i5Cfkf1b" Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1729896AbfH0IyZ (ORCPT ); Tue, 27 Aug 2019 04:54:25 -0400 Received: from forward100p.mail.yandex.net ([77.88.28.100]:45072 "EHLO forward100p.mail.yandex.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1729783AbfH0IyY (ORCPT ); Tue, 27 Aug 2019 04:54:24 -0400 Received: from mxback2j.mail.yandex.net (mxback2j.mail.yandex.net [IPv6:2a02:6b8:0:1619::10b]) by forward100p.mail.yandex.net (Yandex) with ESMTP id 918BB5981FA3; Tue, 27 Aug 2019 11:54:21 +0300 (MSK) Received: from smtp1p.mail.yandex.net (smtp1p.mail.yandex.net [2a02:6b8:0:1472:2741:0:8b6:6]) by mxback2j.mail.yandex.net (nwsmtp/Yandex) with ESMTP id 7n65irLtrN-sK9WrAcr; Tue, 27 Aug 2019 11:54:21 +0300 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=flygoat.com; s=mail; t=1566896061; bh=7Gyq+LBu6iHiMYMJuTsTZ0ECsLRbcZFOSDdNe3Heffo=; h=In-Reply-To:Subject:To:From:Cc:References:Date:Message-Id; b=i5Cfkf1b94Rz7e0/qo7TYEPNGrgu0mQC6awkryJJh/k69Ffwe3Ky0TEgEgnomgCKR ErAgY9yt4ODZkZiRZQ2A6d9jspbjgbgYIAtQMmLFUN5U7BLIBt/h9eSs0YLUY+vzlW pKApYZx5/bLKWlSaZy9oi2QmTA3z1hkyh11WwGs4= Authentication-Results: mxback2j.mail.yandex.net; dkim=pass header.i=@flygoat.com Received: by smtp1p.mail.yandex.net (nwsmtp/Yandex) with ESMTPSA id JOqUfE8LDO-sEtCfvQg; Tue, 27 Aug 2019 11:54:19 +0300 (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits)) (Client certificate not present) From: Jiaxun Yang To: linux-mips@vger.kernel.org Cc: chenhc@lemote.com, paul.burton@mips.com, tglx@linutronix.de, jason@lakedaemon.net, maz@kernel.org, linux-kernel@vger.kernel.org, robh+dt@kernel.org, mark.rutland@arm.co, devicetree@vger.kernel.org, Jiaxun Yang Subject: [PATCH 05/13] dt-bindings: interrupt-controller: Add Loongson-3 IOINTC Date: Tue, 27 Aug 2019 16:52:54 +0800 Message-Id: <20190827085302.5197-6-jiaxun.yang@flygoat.com> X-Mailer: git-send-email 2.22.0 In-Reply-To: <20190827085302.5197-1-jiaxun.yang@flygoat.com> References: <20190827085302.5197-1-jiaxun.yang@flygoat.com> MIME-Version: 1.0 Sender: linux-mips-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-mips@vger.kernel.org Document Loongson-3 I/O Interrupt controller. Signed-off-by: Jiaxun Yang --- .../loongson,ls3-iointc.yaml | 61 +++++++++++++++++++ 1 file changed, 61 insertions(+) create mode 100644 Documentation/devicetree/bindings/interrupt-controller/loongson,ls3-iointc.yaml diff --git a/Documentation/devicetree/bindings/interrupt-controller/loongson,ls3-iointc.yaml b/Documentation/devicetree/bindings/interrupt-controller/loongson,ls3-iointc.yaml new file mode 100644 index 000000000000..cc6ac8b2cd7c --- /dev/null +++ b/Documentation/devicetree/bindings/interrupt-controller/loongson,ls3-iointc.yaml @@ -0,0 +1,61 @@ +# SPDX-License-Identifier: GPL-2.0 +%YAML 1.2 +--- +$id: "http://devicetree.org/schemas/interrupt-controller/loongson,ls3-iointc.yaml#" +$schema: "http://devicetree.org/meta-schemas/core.yaml#" + +title: Loongson-3 I/O Interrupt Controller + +maintainers: + - Jiaxun Yang + +description: | + This interrupt controller is found in the Loongson-3 family of chips as the primary + package interrupt source which can route interrupt to interrupt line of cores. + +properties: + compatible: + items: + - enum: + - loongson,ls3-iointc + + reg: + maxItems: 1 + + 'loongson,map-ip': + description: + The interrupt line it's going to map to. + allOf: + - maximum: 5 + minimum: 0 + + 'loongson,map-core': + description: + The core it's going to map to. + allOf: + - maximum: 5 + minimum: 0 + + interrupt-controller: true + + '#interrupt-cells': + const: 2 + +required: + - compatible + - reg + - interrupts + - interrupt-controller + - '#interrupt-cells' + +examples: + - | + iointc: interrupt-controller@3ff01400 { + compatible = "loongson,ls3-io-intc"; + reg = <0x3ff01400 0x60>; + interrupts = <2>; + loongson,map-ip = <0>; + loongson,map-core = <0>; + interrupt-controller; + #interrupt-cells = <2>; + }; From patchwork Tue Aug 27 08:52:55 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Jiaxun Yang X-Patchwork-Id: 11116427 Return-Path: Received: from mail.kernel.org (pdx-korg-mail-1.web.codeaurora.org [172.30.200.123]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id 26B4B14DE for ; Tue, 27 Aug 2019 08:54:34 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.kernel.org (Postfix) with ESMTP id 04FAA2184D for ; Tue, 27 Aug 2019 08:54:34 +0000 (UTC) Authentication-Results: mail.kernel.org; dkim=pass (1024-bit key) header.d=flygoat.com header.i=@flygoat.com header.b="f342uDTt" Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1729494AbfH0Iyd (ORCPT ); Tue, 27 Aug 2019 04:54:33 -0400 Received: from forward100j.mail.yandex.net ([5.45.198.240]:35425 "EHLO forward100j.mail.yandex.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1729895AbfH0Iyd (ORCPT ); Tue, 27 Aug 2019 04:54:33 -0400 Received: from mxback5j.mail.yandex.net (mxback5j.mail.yandex.net [IPv6:2a02:6b8:0:1619::10e]) by forward100j.mail.yandex.net (Yandex) with ESMTP id 35D7250E1B68; Tue, 27 Aug 2019 11:54:28 +0300 (MSK) Received: from smtp1p.mail.yandex.net (smtp1p.mail.yandex.net [2a02:6b8:0:1472:2741:0:8b6:6]) by mxback5j.mail.yandex.net (nwsmtp/Yandex) with ESMTP id HykKnQ8voc-sRIOZ1Ch; Tue, 27 Aug 2019 11:54:28 +0300 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=flygoat.com; s=mail; t=1566896068; bh=G0jHcPXM+OCk44Z0PCwjREln9mLdtxprn1r5zWOEs78=; h=In-Reply-To:Subject:To:From:Cc:References:Date:Message-Id; b=f342uDTtikFulBQKjxq016BGG0gvX9l22Frpnw2Ff3ZPoEbkBeLOCugfPOKsJRa9B imMZKyaZfGRNXnDAboV6RYWMF+gvr7yL8Ih4+5GYR8Q+izjfwag9g8HD4O5DzD4BxM cZhbXg9VyjD7BPj6rznXO6AhLnsyY09XHf5DnQlc= Authentication-Results: mxback5j.mail.yandex.net; dkim=pass header.i=@flygoat.com Received: by smtp1p.mail.yandex.net (nwsmtp/Yandex) with ESMTPSA id JOqUfE8LDO-sLtCjfGP; Tue, 27 Aug 2019 11:54:26 +0300 (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits)) (Client certificate not present) From: Jiaxun Yang To: linux-mips@vger.kernel.org Cc: chenhc@lemote.com, paul.burton@mips.com, tglx@linutronix.de, jason@lakedaemon.net, maz@kernel.org, linux-kernel@vger.kernel.org, robh+dt@kernel.org, mark.rutland@arm.co, devicetree@vger.kernel.org, Jiaxun Yang Subject: [PATCH 06/13] irqchip: Add driver for Loongson-3 HyperTransport interrupt controller Date: Tue, 27 Aug 2019 16:52:55 +0800 Message-Id: <20190827085302.5197-7-jiaxun.yang@flygoat.com> X-Mailer: git-send-email 2.22.0 In-Reply-To: <20190827085302.5197-1-jiaxun.yang@flygoat.com> References: <20190827085302.5197-1-jiaxun.yang@flygoat.com> MIME-Version: 1.0 Sender: linux-mips-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-mips@vger.kernel.org This controller appeared on Loongson-3 family of chips to receive interrupts from PCH chip. Signed-off-by: Jiaxun Yang --- drivers/irqchip/Kconfig | 8 ++ drivers/irqchip/Makefile | 1 + drivers/irqchip/irq-ls3-htintc.c | 145 +++++++++++++++++++++++++++++++ 3 files changed, 154 insertions(+) create mode 100644 drivers/irqchip/irq-ls3-htintc.c diff --git a/drivers/irqchip/Kconfig b/drivers/irqchip/Kconfig index 8d9eac5fd4a7..b3ce0f3e43ae 100644 --- a/drivers/irqchip/Kconfig +++ b/drivers/irqchip/Kconfig @@ -480,6 +480,14 @@ config LS3_IOINTC help Support for the Loongson-3 I/O Interrupt Controller. +config LS3_HTINTC + bool "Loongson3 HyperTransport Interrupt Controller" + depends on MACH_LOONGSON64 + default y + select IRQ_DOMAIN + select GENERIC_IRQ_CHIP + help + Support for the Loongson-3 HyperTransport Interrupt Controller. endmenu config SIFIVE_PLIC diff --git a/drivers/irqchip/Makefile b/drivers/irqchip/Makefile index 49ecb8d38138..0fda94c319e9 100644 --- a/drivers/irqchip/Makefile +++ b/drivers/irqchip/Makefile @@ -103,3 +103,4 @@ obj-$(CONFIG_LS1X_IRQ) += irq-ls1x.o obj-$(CONFIG_TI_SCI_INTR_IRQCHIP) += irq-ti-sci-intr.o obj-$(CONFIG_TI_SCI_INTA_IRQCHIP) += irq-ti-sci-inta.o obj-$(CONFIG_LS3_IOINTC) += irq-ls3-iointc.o +obj-$(CONFIG_LS3_HTINTC) += irq-ls3-htintc.o diff --git a/drivers/irqchip/irq-ls3-htintc.c b/drivers/irqchip/irq-ls3-htintc.c new file mode 100644 index 000000000000..c53bbb0bd78c --- /dev/null +++ b/drivers/irqchip/irq-ls3-htintc.c @@ -0,0 +1,145 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Copyright (C) 2019, Jiaxun Yang + * Loongson-3 HyperTransport IRQ support + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#define HTINTC_NUM_GC 4 +#define HTINTC_GC_SIZE 0x4 +#define HTINTC_NUM_HANDLER 4 +#define HTINTC_HANDLER_SIZE 0x8 +#define HTINTC_HANDLER_IRQ 64 + +#define HTINTC_VECTOR_OFFSET 0x0 +#define HTINTC_EN_OFFSET 0x20 + +struct htintc_handler_priv { + struct irq_domain *domain; + void __iomem *handler_base; +}; + +static void htintc_chained_handle_irq(struct irq_desc *desc) +{ + struct htintc_handler_priv *priv = irq_desc_get_handler_data(desc); + struct irq_chip *chip = irq_desc_get_chip(desc); + int i; + bool handled; + + chained_irq_enter(chip, desc); + + for (i = 0; i < HTINTC_NUM_GC; i++) { + uint32_t irqs = readl(priv->handler_base + HTINTC_GC_SIZE * i); + + while (irqs) { + int bit = __ffs(irqs); + + generic_handle_irq(irq_find_mapping(priv->domain, bit + 32 * i)); + irqs &= ~BIT(bit); + handled = true; + } + } + + if (!handled) + spurious_interrupt(); + + chained_irq_exit(chip, desc); +} + +int __init ls3_htintc_of_init(struct device_node *node, + struct device_node *parent) +{ + struct irq_chip_generic *gc; + struct irq_chip_type *ct; + struct htintc_handler_priv *priv; + struct irq_domain *domain; + void __iomem *base; + int parent_irq[HTINTC_NUM_HANDLER], err = 0; + int i; + + + priv = kzalloc(sizeof(*priv), GFP_KERNEL); + if (!priv) + return -ENOMEM; + + base = of_iomap(node, 0); + if (!base) { + err = -ENODEV; + goto out_free_priv; + } + + for (i = 0; i < HTINTC_NUM_HANDLER; i++) { + parent_irq[i] = irq_of_parse_and_map(node, i); + if (!parent_irq[i]) { + pr_err("ls3-htintc: unable to get parent irq %d\n", i); + err = -ENODEV; + goto out_iounmap; + } + } + /* Set up an IRQ domain */ + domain = irq_domain_add_linear(node, 32 * HTINTC_NUM_GC, + &irq_generic_chip_ops, NULL); + if (!domain) { + pr_err("ls3-htintc: cannot add IRQ domain\n"); + err = -ENOMEM; + goto out_iounmap; + } + + for (i = 0; i < HTINTC_NUM_HANDLER; i++) { + /* Mask all interrupts */ + writeq(0x0, base + HTINTC_EN_OFFSET + HTINTC_HANDLER_SIZE * i); + } + + err = irq_alloc_domain_generic_chips(domain, 32, 1, + node->full_name, handle_fasteoi_irq, + IRQ_NOPROBE, 0, IRQ_GC_INIT_MASK_CACHE); + if (err) { + pr_err("ls3-htintc: unable to register IRQ domain\n"); + err = -ENOMEM; + goto out_free_domain; + } + + for (i = 0; i < HTINTC_NUM_GC; i++) { + gc = irq_get_domain_generic_chip(domain, i * 32); + gc->reg_base = base + HTINTC_GC_SIZE * i; + gc->domain = domain; + + ct = gc->chip_types; + ct->regs.mask = HTINTC_EN_OFFSET; + ct->regs.ack = HTINTC_VECTOR_OFFSET; + ct->chip.irq_unmask = irq_gc_mask_set_bit; + ct->chip.irq_mask = irq_gc_mask_clr_bit; + ct->chip.irq_ack = irq_gc_ack_set_bit; + } + + priv->domain = domain; + priv->handler_base = base + HTINTC_VECTOR_OFFSET; + + for (i = 0; i < HTINTC_NUM_HANDLER; i++) { + irq_set_chained_handler_and_data(parent_irq[i], + htintc_chained_handle_irq, priv); + } + + return 0; + +out_free_domain: + irq_domain_remove(domain); +out_iounmap: + iounmap(base); +out_free_priv: + kfree(priv); + + return err; +} + +IRQCHIP_DECLARE(ls3_htintc, "loongson,ls3-htintc", ls3_htintc_of_init); From patchwork Tue Aug 27 08:52:56 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Jiaxun Yang X-Patchwork-Id: 11116429 Return-Path: Received: from mail.kernel.org (pdx-korg-mail-1.web.codeaurora.org [172.30.200.123]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id 8161B14DE for ; Tue, 27 Aug 2019 08:54:39 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.kernel.org (Postfix) with ESMTP id 6059E2184D for ; Tue, 27 Aug 2019 08:54:39 +0000 (UTC) Authentication-Results: mail.kernel.org; dkim=pass (1024-bit key) header.d=flygoat.com header.i=@flygoat.com header.b="W2u7El7n" Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1729895AbfH0Iyj (ORCPT ); Tue, 27 Aug 2019 04:54:39 -0400 Received: from forward105o.mail.yandex.net ([37.140.190.183]:50879 "EHLO forward105o.mail.yandex.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1729600AbfH0Iyj (ORCPT ); Tue, 27 Aug 2019 04:54:39 -0400 Received: from mxback17j.mail.yandex.net (mxback17j.mail.yandex.net [IPv6:2a02:6b8:0:1619::93]) by forward105o.mail.yandex.net (Yandex) with ESMTP id 9C8734201AE6; Tue, 27 Aug 2019 11:54:35 +0300 (MSK) Received: from smtp1p.mail.yandex.net (smtp1p.mail.yandex.net [2a02:6b8:0:1472:2741:0:8b6:6]) by mxback17j.mail.yandex.net (nwsmtp/Yandex) with ESMTP id eh7vR3ekib-sYB0FNsC; Tue, 27 Aug 2019 11:54:35 +0300 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=flygoat.com; s=mail; t=1566896075; bh=EFyS7rMeUv/1O17IZuGpXYP3C3ZKhieRADD/pMwZx/g=; h=In-Reply-To:Subject:To:From:Cc:References:Date:Message-Id; b=W2u7El7nNMhuqvl3ci41yQaAPFXFFeFne01qo4MDWr57EVVgeaDRNsLBIAbt2/kFe 3ajWpfIcZ1GWjN7oCzNVAhAX3Bg+vlxh5HR1HXxgeiNzqf7bV8ys8uInLnZ3DRkP8q 2fY+VFGJbryHqa7v4rC1BuNIJ5JIOrJtEJKXGQp8= Authentication-Results: mxback17j.mail.yandex.net; dkim=pass header.i=@flygoat.com Received: by smtp1p.mail.yandex.net (nwsmtp/Yandex) with ESMTPSA id JOqUfE8LDO-sStCc4I5; Tue, 27 Aug 2019 11:54:33 +0300 (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits)) (Client certificate not present) From: Jiaxun Yang To: linux-mips@vger.kernel.org Cc: chenhc@lemote.com, paul.burton@mips.com, tglx@linutronix.de, jason@lakedaemon.net, maz@kernel.org, linux-kernel@vger.kernel.org, robh+dt@kernel.org, mark.rutland@arm.co, devicetree@vger.kernel.org, Jiaxun Yang Subject: [PATCH 07/13] dt-bindings: interrupt-controller: Add Loongson-3 HTINTC Date: Tue, 27 Aug 2019 16:52:56 +0800 Message-Id: <20190827085302.5197-8-jiaxun.yang@flygoat.com> X-Mailer: git-send-email 2.22.0 In-Reply-To: <20190827085302.5197-1-jiaxun.yang@flygoat.com> References: <20190827085302.5197-1-jiaxun.yang@flygoat.com> MIME-Version: 1.0 Sender: linux-mips-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-mips@vger.kernel.org Document Loongson-3 HyperTransport Interrupt controller. Signed-off-by: Jiaxun Yang --- .../loongson,ls3-htintc.yaml | 53 +++++++++++++++++++ 1 file changed, 53 insertions(+) create mode 100644 Documentation/devicetree/bindings/interrupt-controller/loongson,ls3-htintc.yaml diff --git a/Documentation/devicetree/bindings/interrupt-controller/loongson,ls3-htintc.yaml b/Documentation/devicetree/bindings/interrupt-controller/loongson,ls3-htintc.yaml new file mode 100644 index 000000000000..c1bc0faca656 --- /dev/null +++ b/Documentation/devicetree/bindings/interrupt-controller/loongson,ls3-htintc.yaml @@ -0,0 +1,53 @@ +# SPDX-License-Identifier: GPL-2.0 +%YAML 1.2 +--- +$id: "http://devicetree.org/schemas/interrupt-controller/loongson,ls3-htintc.yaml#" +$schema: "http://devicetree.org/meta-schemas/core.yaml#" + +title: Loongson-3 HyperTransport Interrupt Controller + +maintainers: + - Jiaxun Yang + +description: | + This interrupt controller is found in the Loongson-3 family of chips to transfer + interrupts from PCH connected on HyperTransport bus. + +properties: + compatible: + items: + - enum: + - loongson,ls3-htintc + + reg: + maxItems: 1 + + interrupts: + maxItems: 4 + + interrupt-controller: true + + '#interrupt-cells': + const: 1 + +required: + - compatible + - reg + - interrupts + - interrupt-controller + - '#interrupt-cells' + +examples: + - | + htintc: interrupt-controller@0xEFDFB000080 { + compatible = "loongson,ls3-htintc"; + reg = <0xEFD 0xFB000080 0x100>; + interrupt-controller; + #interrupt-cells = <1>; + + interrupt-parent = <&iointc>; + interrupts = <24 IRQ_TYPE_LEVEL_HIGH>, + <25 IRQ_TYPE_LEVEL_HIGH>, + <26 IRQ_TYPE_LEVEL_HIGH>, + <27 IRQ_TYPE_LEVEL_HIGH>; + }; From patchwork Tue Aug 27 08:52:57 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Jiaxun Yang X-Patchwork-Id: 11116431 Return-Path: Received: from mail.kernel.org (pdx-korg-mail-1.web.codeaurora.org [172.30.200.123]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id 179071399 for ; Tue, 27 Aug 2019 08:54:50 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.kernel.org (Postfix) with ESMTP id E91492186A for ; Tue, 27 Aug 2019 08:54:49 +0000 (UTC) Authentication-Results: mail.kernel.org; dkim=pass (1024-bit key) header.d=flygoat.com header.i=@flygoat.com header.b="p7a94URR" Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1729945AbfH0Iyt (ORCPT ); Tue, 27 Aug 2019 04:54:49 -0400 Received: from forward104p.mail.yandex.net ([77.88.28.107]:56559 "EHLO forward104p.mail.yandex.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1726091AbfH0Iyt (ORCPT ); Tue, 27 Aug 2019 04:54:49 -0400 Received: from mxback6j.mail.yandex.net (mxback6j.mail.yandex.net [IPv6:2a02:6b8:0:1619::10f]) by forward104p.mail.yandex.net (Yandex) with ESMTP id 8CF404B01AEB; Tue, 27 Aug 2019 11:54:41 +0300 (MSK) Received: from smtp1p.mail.yandex.net (smtp1p.mail.yandex.net [2a02:6b8:0:1472:2741:0:8b6:6]) by mxback6j.mail.yandex.net (nwsmtp/Yandex) with ESMTP id 6wxlYKcOkb-sfpSOoHv; Tue, 27 Aug 2019 11:54:41 +0300 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=flygoat.com; s=mail; t=1566896081; bh=GDPLbh2Za9If16kngBr0Vy91wenOeOyR+BDWVi+j/l8=; h=In-Reply-To:Subject:To:From:Cc:References:Date:Message-Id; b=p7a94URRoHEenFOSNITq6Ze3C0HzxvW8GZnRtZwTvFIsNDFJkfSLJ+l9/18bk0Y6e 7OYtsru6kk19cutO4I1/s3Cp1Ixud/xrX/T0IvTbA3VNvQyGa0yDiA7zJdOeyMFwW6 F67kC95DNSvlYlK5A5AjIzxx4KlB9kZ61R36WT34= Authentication-Results: mxback6j.mail.yandex.net; dkim=pass header.i=@flygoat.com Received: by smtp1p.mail.yandex.net (nwsmtp/Yandex) with ESMTPSA id JOqUfE8LDO-satCj8nx; Tue, 27 Aug 2019 11:54:40 +0300 (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits)) (Client certificate not present) From: Jiaxun Yang To: linux-mips@vger.kernel.org Cc: chenhc@lemote.com, paul.burton@mips.com, tglx@linutronix.de, jason@lakedaemon.net, maz@kernel.org, linux-kernel@vger.kernel.org, robh+dt@kernel.org, mark.rutland@arm.co, devicetree@vger.kernel.org, Jiaxun Yang Subject: [PATCH 08/13] irqchip: i8259: Add plat-poll support Date: Tue, 27 Aug 2019 16:52:57 +0800 Message-Id: <20190827085302.5197-9-jiaxun.yang@flygoat.com> X-Mailer: git-send-email 2.22.0 In-Reply-To: <20190827085302.5197-1-jiaxun.yang@flygoat.com> References: <20190827085302.5197-1-jiaxun.yang@flygoat.com> MIME-Version: 1.0 Sender: linux-mips-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-mips@vger.kernel.org For some platforms (e.g. Loongson-3), platfrom interrupt controller supports polling interrupt vector from i8259 automaticly and generating sepreated interrupt. Thus we add plat-poll OF property for these platforms and setup sepreated chained interrupt handler. Signed-off-by: Jiaxun Yang --- drivers/irqchip/irq-i8259.c | 47 ++++++++++++++++++++++++++++++++----- 1 file changed, 41 insertions(+), 6 deletions(-) diff --git a/drivers/irqchip/irq-i8259.c b/drivers/irqchip/irq-i8259.c index d000870d9b6b..e7a9895f3b2d 100644 --- a/drivers/irqchip/irq-i8259.c +++ b/drivers/irqchip/irq-i8259.c @@ -40,6 +40,12 @@ static void mask_and_ack_8259A(struct irq_data *d); static void init_8259A(int auto_eoi); static int (*i8259_poll)(void) = i8259_irq; +struct plat_poll_priv { + struct irq_domain *domain; + int hwirq; +}; +static struct plat_poll_priv plat_poll_priv[16]; + static struct irq_chip i8259A_chip = { .name = "XT-PIC", .irq_mask = disable_8259A_irq, @@ -346,22 +352,51 @@ static void i8259_irq_dispatch(struct irq_desc *desc) generic_handle_irq(irq); } +static void plat_poll_irq_dispatch(struct irq_desc *desc) +{ + struct plat_poll_priv *priv = irq_desc_get_handler_data(desc); + unsigned int irq; + + irq = irq_linear_revmap(priv->domain, priv->hwirq); + generic_handle_irq(irq); +} + int __init i8259_of_init(struct device_node *node, struct device_node *parent) { struct irq_domain *domain; - unsigned int parent_irq; domain = __init_i8259_irqs(node); - parent_irq = irq_of_parse_and_map(node, 0); - if (!parent_irq) { - pr_err("Failed to map i8259 parent IRQ\n"); - irq_domain_remove(domain); - return -ENODEV; + if (of_find_property(node, "plat-poll", NULL)) { + int i; + + for (i = 0; i < 16; i++) { + int parent_irq = irq_of_parse_and_map(node, i); + + if (!parent_irq) { + pr_err("Failed to map %d plat-poll i8259 parent IRQ\n", i); + irq_domain_remove(domain); + return -ENODEV; + } + plat_poll_priv[i].domain = domain; + plat_poll_priv[i].hwirq = i; + irq_set_chained_handler_and_data(parent_irq, + plat_poll_irq_dispatch, + &plat_poll_priv[i]); + } + } else { + unsigned int parent_irq; + + parent_irq = irq_of_parse_and_map(node, 0); + if (!parent_irq) { + pr_err("Failed to map i8259 parent IRQ\n"); + irq_domain_remove(domain); + return -ENODEV; } irq_set_chained_handler_and_data(parent_irq, i8259_irq_dispatch, domain); + } return 0; } IRQCHIP_DECLARE(i8259, "intel,i8259", i8259_of_init); From patchwork Tue Aug 27 08:52:58 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Jiaxun Yang X-Patchwork-Id: 11116433 Return-Path: Received: from mail.kernel.org (pdx-korg-mail-1.web.codeaurora.org [172.30.200.123]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id 08A961399 for ; Tue, 27 Aug 2019 08:54:51 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.kernel.org (Postfix) with ESMTP id D0FAC21872 for ; Tue, 27 Aug 2019 08:54:50 +0000 (UTC) Authentication-Results: mail.kernel.org; dkim=pass (1024-bit key) header.d=flygoat.com header.i=@flygoat.com header.b="mgxy0CGc" Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1726091AbfH0Iyu (ORCPT ); Tue, 27 Aug 2019 04:54:50 -0400 Received: from forward103p.mail.yandex.net ([77.88.28.106]:47844 "EHLO forward103p.mail.yandex.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1729600AbfH0Iyu (ORCPT ); Tue, 27 Aug 2019 04:54:50 -0400 Received: from mxback5o.mail.yandex.net (mxback5o.mail.yandex.net [IPv6:2a02:6b8:0:1a2d::1f]) by forward103p.mail.yandex.net (Yandex) with ESMTP id E781B18C06D6; Tue, 27 Aug 2019 11:54:47 +0300 (MSK) Received: from smtp1p.mail.yandex.net (smtp1p.mail.yandex.net [2a02:6b8:0:1472:2741:0:8b6:6]) by mxback5o.mail.yandex.net (nwsmtp/Yandex) with ESMTP id bGqLoqeX6o-sliWgxAQ; Tue, 27 Aug 2019 11:54:47 +0300 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=flygoat.com; s=mail; t=1566896087; bh=lGWrm07yEb+iDYbXl6MNXFFYrFAuttvAedBfbL1LKfs=; h=In-Reply-To:Subject:To:From:Cc:References:Date:Message-Id; b=mgxy0CGcJd7PFBjv4r1CFiD/p+bdHfc/oqo43KxX18vsKUIoOIhG1zGKVxIKxZSLt +IoaggXz519wa0CtjxMhDAq71CsXOAlRoK1h2jQWlfXKTacihq9cqqS9UQ2DvtGKOd 2W4ck6Gfw9zFiyCvh2IuwsLsU/IFuXp7EFXIef0M= Authentication-Results: mxback5o.mail.yandex.net; dkim=pass header.i=@flygoat.com Received: by smtp1p.mail.yandex.net (nwsmtp/Yandex) with ESMTPSA id JOqUfE8LDO-sftCBi7A; Tue, 27 Aug 2019 11:54:46 +0300 (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits)) (Client certificate not present) From: Jiaxun Yang To: linux-mips@vger.kernel.org Cc: chenhc@lemote.com, paul.burton@mips.com, tglx@linutronix.de, jason@lakedaemon.net, maz@kernel.org, linux-kernel@vger.kernel.org, robh+dt@kernel.org, mark.rutland@arm.co, devicetree@vger.kernel.org, Jiaxun Yang Subject: [PATCH 09/13] irqchip: mips-cpu: Convert to simple domain Date: Tue, 27 Aug 2019 16:52:58 +0800 Message-Id: <20190827085302.5197-10-jiaxun.yang@flygoat.com> X-Mailer: git-send-email 2.22.0 In-Reply-To: <20190827085302.5197-1-jiaxun.yang@flygoat.com> References: <20190827085302.5197-1-jiaxun.yang@flygoat.com> MIME-Version: 1.0 Sender: linux-mips-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-mips@vger.kernel.org The old code is using legacy domain to setup irq_domain for CPU interrupts which requires irq_desc being preallocated. However, when MIPS_CPU_IRQ_BASE >= 16, irq_desc for CPU IRQs may end up unallocated and lead to incorrect behavior. Thus we convert the legacy domain to simple domain which can allocate irq_desc during initialization. Signed-off-by: Jiaxun Yang --- drivers/irqchip/irq-mips-cpu.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/irqchip/irq-mips-cpu.c b/drivers/irqchip/irq-mips-cpu.c index 95d4fd8f7a96..c3cf7fa76424 100644 --- a/drivers/irqchip/irq-mips-cpu.c +++ b/drivers/irqchip/irq-mips-cpu.c @@ -251,7 +251,7 @@ static void __init __mips_cpu_irq_init(struct device_node *of_node) clear_c0_status(ST0_IM); clear_c0_cause(CAUSEF_IP); - irq_domain = irq_domain_add_legacy(of_node, 8, MIPS_CPU_IRQ_BASE, 0, + irq_domain = irq_domain_add_simple(of_node, 8, MIPS_CPU_IRQ_BASE, &mips_cpu_intc_irq_domain_ops, NULL); if (!irq_domain) From patchwork Tue Aug 27 08:52:59 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Jiaxun Yang X-Patchwork-Id: 11116435 Return-Path: Received: from mail.kernel.org (pdx-korg-mail-1.web.codeaurora.org [172.30.200.123]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id 6EBB714F7 for ; Tue, 27 Aug 2019 08:55:00 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.kernel.org (Postfix) with ESMTP id 4384A2184D for ; Tue, 27 Aug 2019 08:55:00 +0000 (UTC) Authentication-Results: mail.kernel.org; dkim=pass (1024-bit key) header.d=flygoat.com header.i=@flygoat.com header.b="qQlrn8nh" Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1726257AbfH0IzA (ORCPT ); Tue, 27 Aug 2019 04:55:00 -0400 Received: from forward105o.mail.yandex.net ([37.140.190.183]:51330 "EHLO forward105o.mail.yandex.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1725912AbfH0Iy7 (ORCPT ); Tue, 27 Aug 2019 04:54:59 -0400 Received: from mxback18o.mail.yandex.net (mxback18o.mail.yandex.net [IPv6:2a02:6b8:0:1a2d::69]) by forward105o.mail.yandex.net (Yandex) with ESMTP id A0D1142018CE; Tue, 27 Aug 2019 11:54:54 +0300 (MSK) Received: from smtp1p.mail.yandex.net (smtp1p.mail.yandex.net [2a02:6b8:0:1472:2741:0:8b6:6]) by mxback18o.mail.yandex.net (nwsmtp/Yandex) with ESMTP id JAtSOct50N-srhm5duN; Tue, 27 Aug 2019 11:54:54 +0300 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=flygoat.com; s=mail; t=1566896094; bh=tqrCk2lHh7uLbBYfb1q4A+xs3HDXcUI81jcco/99ZUo=; h=In-Reply-To:Subject:To:From:Cc:References:Date:Message-Id; b=qQlrn8nh0uhQu7x5F4meGSuarFZ/WQGcBpLHs2SMXW8ZFcYjU08BrM3g75+t1UPH5 DXmt7f8B9DTgkEwKMQJbXWoG6CPe4Hu1N8yG7wrW+r8BGJKMfX3C3W+kyglym34Oj2 WTPAJPCvtIJbpHNPVnZuRfnKdwHNe/FtqzFFQEZ0= Authentication-Results: mxback18o.mail.yandex.net; dkim=pass header.i=@flygoat.com Received: by smtp1p.mail.yandex.net (nwsmtp/Yandex) with ESMTPSA id JOqUfE8LDO-smtCFZv9; Tue, 27 Aug 2019 11:54:52 +0300 (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits)) (Client certificate not present) From: Jiaxun Yang To: linux-mips@vger.kernel.org Cc: chenhc@lemote.com, paul.burton@mips.com, tglx@linutronix.de, jason@lakedaemon.net, maz@kernel.org, linux-kernel@vger.kernel.org, robh+dt@kernel.org, mark.rutland@arm.co, devicetree@vger.kernel.org, Jiaxun Yang Subject: [PATCH 10/13] MIPS: Loongson64: Drop legacy IRQ code Date: Tue, 27 Aug 2019 16:52:59 +0800 Message-Id: <20190827085302.5197-11-jiaxun.yang@flygoat.com> X-Mailer: git-send-email 2.22.0 In-Reply-To: <20190827085302.5197-1-jiaxun.yang@flygoat.com> References: <20190827085302.5197-1-jiaxun.yang@flygoat.com> MIME-Version: 1.0 Sender: linux-mips-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-mips@vger.kernel.org We've made generic irqchip drivers for Loongson-3 platform, it's time to say goodbye to these legacy code. Signed-off-by: Jiaxun Yang --- arch/mips/include/asm/mach-loongson64/irq.h | 1 - arch/mips/loongson64/irq.c | 167 +------------------- arch/mips/loongson64/smp.c | 26 ++- 3 files changed, 11 insertions(+), 183 deletions(-) diff --git a/arch/mips/include/asm/mach-loongson64/irq.h b/arch/mips/include/asm/mach-loongson64/irq.h index baed43285163..e57a21fc581c 100644 --- a/arch/mips/include/asm/mach-loongson64/irq.h +++ b/arch/mips/include/asm/mach-loongson64/irq.h @@ -35,7 +35,6 @@ #define LOONGSON_INT_COREx_INTy(x, y) (1<<(x) | 1<<(y+4)) /* route to int y of core x */ extern void fixup_irqs(void); -extern void loongson3_ipi_interrupt(void); #include_next #endif /* __ASM_MACH_LOONGSON64_IRQ_H_ */ diff --git a/arch/mips/loongson64/irq.c b/arch/mips/loongson64/irq.c index 4d7b80a0ffb9..78cd824cc84e 100644 --- a/arch/mips/loongson64/irq.c +++ b/arch/mips/loongson64/irq.c @@ -3,180 +3,17 @@ #include #include #include +#include #include -#include #include #include "smp.h" -/* ICU Configuration Regs - r/w */ - -#define LOONGSON_INTEDGE LOONGSON_REG(LOONGSON_REGBASE + 0x24) -#define LOONGSON_INTSTEER LOONGSON_REG(LOONGSON_REGBASE + 0x28) -#define LOONGSON_INTPOL LOONGSON_REG(LOONGSON_REGBASE + 0x2c) - -/* ICU Enable Regs - IntEn & IntISR are r/o. */ - -#define LOONGSON_INTENSET LOONGSON_REG(LOONGSON_REGBASE + 0x30) -#define LOONGSON_INTENCLR LOONGSON_REG(LOONGSON_REGBASE + 0x34) -#define LOONGSON_INTEN LOONGSON_REG(LOONGSON_REGBASE + 0x38) -#define LOONGSON_INTISR LOONGSON_REG(LOONGSON_REGBASE + 0x3c) - -extern void loongson3_send_irq_by_ipi(int cpu, int irqs); - -unsigned int irq_cpu[16] = {[0 ... 15] = -1}; -unsigned int ht_irq[] = {0, 1, 3, 4, 5, 6, 7, 8, 12, 14, 15}; -unsigned int local_irq = 1<<0 | 1<<1 | 1<<2 | 1<<7 | 1<<8 | 1<<12; - -int plat_set_irq_affinity(struct irq_data *d, const struct cpumask *affinity, - bool force) -{ - unsigned int cpu; - struct cpumask new_affinity; - - /* I/O devices are connected on package-0 */ - cpumask_copy(&new_affinity, affinity); - for_each_cpu(cpu, affinity) - if (cpu_data[cpu].package > 0) - cpumask_clear_cpu(cpu, &new_affinity); - - if (cpumask_empty(&new_affinity)) - return -EINVAL; - - cpumask_copy(d->common->affinity, &new_affinity); - - return IRQ_SET_MASK_OK_NOCOPY; -} - -static void ht_irqdispatch(void) -{ - unsigned int i, irq; - struct irq_data *irqd; - struct cpumask affinity; - - irq = LOONGSON_HT1_INT_VECTOR(0); - LOONGSON_HT1_INT_VECTOR(0) = irq; /* Acknowledge the IRQs */ - - for (i = 0; i < ARRAY_SIZE(ht_irq); i++) { - if (!(irq & (0x1 << ht_irq[i]))) - continue; - - /* handled by local core */ - if (local_irq & (0x1 << ht_irq[i])) { - do_IRQ(ht_irq[i]); - continue; - } - - irqd = irq_get_irq_data(ht_irq[i]); - cpumask_and(&affinity, irqd->common->affinity, cpu_active_mask); - if (cpumask_empty(&affinity)) { - do_IRQ(ht_irq[i]); - continue; - } - - irq_cpu[ht_irq[i]] = cpumask_next(irq_cpu[ht_irq[i]], &affinity); - if (irq_cpu[ht_irq[i]] >= nr_cpu_ids) - irq_cpu[ht_irq[i]] = cpumask_first(&affinity); - - if (irq_cpu[ht_irq[i]] == 0) { - do_IRQ(ht_irq[i]); - continue; - } - - /* balanced by other cores */ - loongson3_send_irq_by_ipi(irq_cpu[ht_irq[i]], (0x1 << ht_irq[i])); - } -} - -#define UNUSED_IPS (CAUSEF_IP5 | CAUSEF_IP4 | CAUSEF_IP1 | CAUSEF_IP0) - -asmlinkage void plat_irq_dispatch(void) -{ - unsigned int pending; - - pending = read_c0_cause() & read_c0_status() & ST0_IM; - - if (pending & CAUSEF_IP7) - do_IRQ(LOONGSON_TIMER_IRQ); -#if defined(CONFIG_SMP) - if (pending & CAUSEF_IP6) - loongson3_ipi_interrupt(); -#endif - if (pending & CAUSEF_IP3) - ht_irqdispatch(); - if (pending & CAUSEF_IP2) - do_IRQ(LOONGSON_UART_IRQ); - if (pending & UNUSED_IPS) { - pr_err("%s : spurious interrupt\n", __func__); - spurious_interrupt(); - } -} - -static inline void mask_loongson_irq(struct irq_data *d) { } -static inline void unmask_loongson_irq(struct irq_data *d) { } - - /* For MIPS IRQs which shared by all cores */ -static struct irq_chip loongson_irq_chip = { - .name = "Loongson", - .irq_ack = mask_loongson_irq, - .irq_mask = mask_loongson_irq, - .irq_mask_ack = mask_loongson_irq, - .irq_unmask = unmask_loongson_irq, - .irq_eoi = unmask_loongson_irq, -}; - -void irq_router_init(void) -{ - int i; - - /* route LPC int to cpu core0 int 0 */ - LOONGSON_INT_ROUTER_LPC = - LOONGSON_INT_COREx_INTy(loongson_sysconf.boot_cpu_id, 0); - /* route HT1 int0 ~ int7 to cpu core0 INT1*/ - for (i = 0; i < 8; i++) - LOONGSON_INT_ROUTER_HT1(i) = - LOONGSON_INT_COREx_INTy(loongson_sysconf.boot_cpu_id, 1); - /* enable HT1 interrupt */ - LOONGSON_HT1_INTN_EN(0) = 0xffffffff; - /* enable router interrupt intenset */ - LOONGSON_INT_ROUTER_INTENSET = - LOONGSON_INT_ROUTER_INTEN | (0xffff << 16) | 0x1 << 10; -} void __init arch_init_irq(void) { - struct irq_chip *chip; - - /* - * Clear all of the interrupts while we change the able around a bit. - * int-handler is not on bootstrap - */ - clear_c0_status(ST0_IM | ST0_BEV); - - /* no steer */ - LOONGSON_INTSTEER = 0; - - /* - * Mask out all interrupt by writing "1" to all bit position in - * the interrupt reset reg. - */ - LOONGSON_INTENCLR = ~0; - - clear_c0_status(ST0_IM | ST0_BEV); - - irq_router_init(); - mips_cpu_irq_init(); - init_i8259_irqs(); - chip = irq_get_chip(I8259A_IRQ_BASE); - chip->irq_set_affinity = plat_set_irq_affinity; - - irq_set_chip_and_handler(LOONGSON_UART_IRQ, - &loongson_irq_chip, handle_percpu_irq); - irq_set_chip_and_handler(LOONGSON_BRIDGE_IRQ, - &loongson_irq_chip, handle_percpu_irq); - - set_c0_status(STATUSF_IP2 | STATUSF_IP3 | STATUSF_IP6); + irqchip_init(); } #ifdef CONFIG_HOTPLUG_CPU diff --git a/arch/mips/loongson64/smp.c b/arch/mips/loongson64/smp.c index 8ad845e522fb..d53942c56a16 100644 --- a/arch/mips/loongson64/smp.c +++ b/arch/mips/loongson64/smp.c @@ -4,6 +4,7 @@ * Author: Chen Huacai, chenhc@lemote.com */ +#include #include #include #include @@ -24,6 +25,8 @@ DEFINE_PER_CPU(int, cpu_state); +#define LS_IPI_IRQ (MIPS_CPU_IRQ_BASE + 6) + static void *ipi_set0_regs[16]; static void *ipi_clear0_regs[16]; static void *ipi_status0_regs[16]; @@ -245,21 +248,13 @@ loongson3_send_ipi_mask(const struct cpumask *mask, unsigned int action) loongson3_ipi_write32((u32)action, ipi_set0_regs[cpu_logical_map(i)]); } -#define IPI_IRQ_OFFSET 6 - -void loongson3_send_irq_by_ipi(int cpu, int irqs) -{ - loongson3_ipi_write32(irqs << IPI_IRQ_OFFSET, ipi_set0_regs[cpu_logical_map(cpu)]); -} - -void loongson3_ipi_interrupt() +static irqreturn_t loongson3_ipi_interrupt(int irq, void *dev_id) { int i, cpu = smp_processor_id(); - unsigned int action, c0count, irqs; + unsigned int action, c0count; /* Load the ipi register to figure out what we're supposed to do */ action = loongson3_ipi_read32(ipi_status0_regs[cpu_logical_map(cpu)]); - irqs = action >> IPI_IRQ_OFFSET; /* Clear the ipi register to clear the interrupt */ loongson3_ipi_write32((u32)action, ipi_clear0_regs[cpu_logical_map(cpu)]); @@ -282,13 +277,7 @@ void loongson3_ipi_interrupt() __wbflush(); /* Let others see the result ASAP */ } - if (irqs) { - int irq; - while ((irq = ffs(irqs))) { - do_IRQ(irq-1); - irqs &= ~(1<<(irq-1)); - } - } + return IRQ_HANDLED; } #define MAX_LOOPS 800 @@ -384,6 +373,9 @@ static void __init loongson3_smp_setup(void) static void __init loongson3_prepare_cpus(unsigned int max_cpus) { + if (request_irq(LS_IPI_IRQ, loongson3_ipi_interrupt, + IRQF_PERCPU | IRQF_NO_SUSPEND, "SMP_IPI", NULL)) + pr_err("Failed to request IPI IRQ\n"); init_cpu_present(cpu_possible_mask); per_cpu(cpu_state, smp_processor_id()) = CPU_ONLINE; } From patchwork Tue Aug 27 08:53:00 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Jiaxun Yang X-Patchwork-Id: 11116437 Return-Path: Received: from mail.kernel.org (pdx-korg-mail-1.web.codeaurora.org [172.30.200.123]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id C800514DE for ; Tue, 27 Aug 2019 08:55:06 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.kernel.org (Postfix) with ESMTP id A5E6B2173E for ; Tue, 27 Aug 2019 08:55:06 +0000 (UTC) Authentication-Results: mail.kernel.org; dkim=pass (1024-bit key) header.d=flygoat.com header.i=@flygoat.com header.b="ItpLCNRM" Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1726955AbfH0IzG (ORCPT ); Tue, 27 Aug 2019 04:55:06 -0400 Received: from forward106p.mail.yandex.net ([77.88.28.109]:39006 "EHLO forward106p.mail.yandex.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1725912AbfH0IzG (ORCPT ); Tue, 27 Aug 2019 04:55:06 -0400 Received: from mxback28o.mail.yandex.net (mxback28o.mail.yandex.net [IPv6:2a02:6b8:0:1a2d::79]) by forward106p.mail.yandex.net (Yandex) with ESMTP id E9A541C81A15; Tue, 27 Aug 2019 11:55:00 +0300 (MSK) Received: from smtp1p.mail.yandex.net (smtp1p.mail.yandex.net [2a02:6b8:0:1472:2741:0:8b6:6]) by mxback28o.mail.yandex.net (nwsmtp/Yandex) with ESMTP id Hptl9zhHrY-t08a4aTr; Tue, 27 Aug 2019 11:55:00 +0300 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=flygoat.com; s=mail; t=1566896100; bh=Y6sfZ58nj6HzDrvBbI59ncoDg0LgIEFsSAJSPkb15cQ=; h=In-Reply-To:Subject:To:From:Cc:References:Date:Message-Id; b=ItpLCNRMQorxM6o/rJmNmiJGruMvcws/t4qnRv6ynhTh/uMXaXRHsMYaoYLDtmHNe tzh+VRvOcyqqsoxaqfnTvn49nEVkDbXuJX2k9SGw6awt1LImS2sx90UVGyiNCEos7P 7R8Zw2OpkT6CLzwcS5Q9ZvCUITw2QwY7MkWDbAxw= Authentication-Results: mxback28o.mail.yandex.net; dkim=pass header.i=@flygoat.com Received: by smtp1p.mail.yandex.net (nwsmtp/Yandex) with ESMTPSA id JOqUfE8LDO-sttCsrGB; Tue, 27 Aug 2019 11:54:59 +0300 (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits)) (Client certificate not present) From: Jiaxun Yang To: linux-mips@vger.kernel.org Cc: chenhc@lemote.com, paul.burton@mips.com, tglx@linutronix.de, jason@lakedaemon.net, maz@kernel.org, linux-kernel@vger.kernel.org, robh+dt@kernel.org, mark.rutland@arm.co, devicetree@vger.kernel.org, Jiaxun Yang Subject: [PATCH 11/13] dt-bindings: mips: Add loongson cpus & boards Date: Tue, 27 Aug 2019 16:53:00 +0800 Message-Id: <20190827085302.5197-12-jiaxun.yang@flygoat.com> X-Mailer: git-send-email 2.22.0 In-Reply-To: <20190827085302.5197-1-jiaxun.yang@flygoat.com> References: <20190827085302.5197-1-jiaxun.yang@flygoat.com> MIME-Version: 1.0 Sender: linux-mips-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-mips@vger.kernel.org Prepare for later dts. Signed-off-by: Jiaxun Yang --- .../bindings/mips/loongson/cpus.yaml | 38 +++++++++++ .../bindings/mips/loongson/devices.yaml | 64 +++++++++++++++++++ 2 files changed, 102 insertions(+) create mode 100644 Documentation/devicetree/bindings/mips/loongson/cpus.yaml create mode 100644 Documentation/devicetree/bindings/mips/loongson/devices.yaml diff --git a/Documentation/devicetree/bindings/mips/loongson/cpus.yaml b/Documentation/devicetree/bindings/mips/loongson/cpus.yaml new file mode 100644 index 000000000000..410d896a0078 --- /dev/null +++ b/Documentation/devicetree/bindings/mips/loongson/cpus.yaml @@ -0,0 +1,38 @@ +# SPDX-License-Identifier: GPL-2.0 +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/mips/loongson/cpus.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Loongson CPUs bindings + +maintainers: + - Jiaxun Yang + +description: |+ + The device tree allows to describe the layout of CPUs in a system through + the "cpus" node, which in turn contains a number of subnodes (ie "cpu") + defining properties for every cpu. + + Bindings for CPU nodes follow the Devicetree Specification, available from: + + https://www.devicetree.org/specifications/ + +properties: + reg: + maxItems: 1 + description: | + Physical ID of a CPU, Can be read from CP0 EBase.CPUNum. + + compatible: + enum: + - loongson,gs464 + - loongson,gs464e + - loongson,gs264 + - loongson,gs464v + +required: + - device_type + - reg + - compatible +... diff --git a/Documentation/devicetree/bindings/mips/loongson/devices.yaml b/Documentation/devicetree/bindings/mips/loongson/devices.yaml new file mode 100644 index 000000000000..181881a9f4a9 --- /dev/null +++ b/Documentation/devicetree/bindings/mips/loongson/devices.yaml @@ -0,0 +1,64 @@ +# SPDX-License-Identifier: GPL-2.0 +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/mips/loongson/devices.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: MediaTek SoC based Platforms Device Tree Bindings + +maintainers: + - Jiaxun Yang +description: | + Devices with a Loongson CPU shall have the following properties. + +properties: + $nodename: + const: '/' + compatible: + oneOf: + + - description: Loongson 3A1000 + RS780E 1Way + items: + - const: loongson,ls3a1000-780e-1way + + - description: Loongson 3A1000 + RS780E 2Way + items: + - const: loongson,ls3a1000-780e-2way + + - description: Loongson 3A1000 + RS780E 4Way + items: + - const: loongson,ls3a1000-780e-4way + + - description: Loongson 3B1000/1500 + RS780E 1Way + items: + - const: loongson,ls3b-780e-1way + + - description: Loongson 3B1000/1500 + RS780E 2Way + items: + - const: loongson,ls3b-780e-2way + + - description: Loongson 3A2000 + RS780E 1Way + items: + - const: loongson,ls3a2000-780e-1way + + - description: Loongson 3A2000 + RS780E 2Way + items: + - const: loongson,ls3a2000-780e-2way + + - description: Loongson 3A2000 + RS780E 4Way + items: + - const: loongson,ls3a2000-780e-4way + + - description: Loongson 3A3000 + RS780E 1Way + items: + - const: loongson,ls3a3000-780e-1way + + - description: Loongson 3A3000 + RS780E 2Way + items: + - const: loongson,ls3a3000-780e-2way + + - description: Loongson 3A3000 + RS780E 4Way + items: + - const: loongson,ls3a3000-780e-4way + +... From patchwork Tue Aug 27 08:53:01 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Jiaxun Yang X-Patchwork-Id: 11116439 Return-Path: Received: from mail.kernel.org (pdx-korg-mail-1.web.codeaurora.org [172.30.200.123]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id 213261399 for ; Tue, 27 Aug 2019 08:55:18 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.kernel.org (Postfix) with ESMTP id DF4FC2173E for ; Tue, 27 Aug 2019 08:55:17 +0000 (UTC) Authentication-Results: mail.kernel.org; dkim=pass (1024-bit key) header.d=flygoat.com header.i=@flygoat.com header.b="gynwRJy5" Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1727219AbfH0IzR (ORCPT ); Tue, 27 Aug 2019 04:55:17 -0400 Received: from forward102j.mail.yandex.net ([5.45.198.243]:52428 "EHLO forward102j.mail.yandex.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1725912AbfH0IzR (ORCPT ); Tue, 27 Aug 2019 04:55:17 -0400 Received: from mxback17o.mail.yandex.net (mxback17o.mail.yandex.net [IPv6:2a02:6b8:0:1a2d::68]) by forward102j.mail.yandex.net (Yandex) with ESMTP id 017FCF2199C; Tue, 27 Aug 2019 11:55:09 +0300 (MSK) Received: from smtp1p.mail.yandex.net (smtp1p.mail.yandex.net [2a02:6b8:0:1472:2741:0:8b6:6]) by mxback17o.mail.yandex.net (nwsmtp/Yandex) with ESMTP id yY6L4p7kYF-t8P0nJpJ; Tue, 27 Aug 2019 11:55:08 +0300 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=flygoat.com; s=mail; t=1566896108; bh=owisGGSSSLuAIaTLqmdEsfbg56svw6meWRNkz/o/U7U=; h=In-Reply-To:Subject:To:From:Cc:References:Date:Message-Id; b=gynwRJy5sUPZRXbhhyJZPMH+jakf54awphvNB9p/l75CiF3HD6NTTr+ypUQzjIAkR aiXWaie8ngizQ8+7jPIw1MHMvWFWth5xEfoykbzJ6uv/f6ZuJyqUwAHybsg+eUjftm aVz2VlOgaLTkjqyim568po5IEGgPu1xgW+0YOfuM= Authentication-Results: mxback17o.mail.yandex.net; dkim=pass header.i=@flygoat.com Received: by smtp1p.mail.yandex.net (nwsmtp/Yandex) with ESMTPSA id JOqUfE8LDO-t1tCmVBW; Tue, 27 Aug 2019 11:55:06 +0300 (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits)) (Client certificate not present) From: Jiaxun Yang To: linux-mips@vger.kernel.org Cc: chenhc@lemote.com, paul.burton@mips.com, tglx@linutronix.de, jason@lakedaemon.net, maz@kernel.org, linux-kernel@vger.kernel.org, robh+dt@kernel.org, mark.rutland@arm.co, devicetree@vger.kernel.org, Jiaxun Yang Subject: [PATCH 12/13] MIPS: Loongson64: Add generic dts Date: Tue, 27 Aug 2019 16:53:01 +0800 Message-Id: <20190827085302.5197-13-jiaxun.yang@flygoat.com> X-Mailer: git-send-email 2.22.0 In-Reply-To: <20190827085302.5197-1-jiaxun.yang@flygoat.com> References: <20190827085302.5197-1-jiaxun.yang@flygoat.com> MIME-Version: 1.0 Sender: linux-mips-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-mips@vger.kernel.org Add generic device dts for Loongson-3 devices. They seems identical but will be different later. Signed-off-by: Jiaxun Yang --- arch/mips/Kconfig | 4 +- arch/mips/boot/dts/Makefile | 1 + arch/mips/boot/dts/loongson/Makefile | 8 + arch/mips/boot/dts/loongson/ls3-2nodes.dtsi | 8 + arch/mips/boot/dts/loongson/ls3-4nodes.dtsi | 15 ++ arch/mips/boot/dts/loongson/ls3-cpus.dtsi | 150 ++++++++++++++++++ arch/mips/boot/dts/loongson/ls3-gs464.dtsi | 18 +++ arch/mips/boot/dts/loongson/ls3-gs464e.dtsi | 18 +++ .../boot/dts/loongson/ls3-rs780e-pch.dtsi | 35 ++++ arch/mips/boot/dts/loongson/ls3a-package.dtsi | 59 +++++++ .../boot/dts/loongson/ls3a1000_780e_1way.dts | 12 ++ .../boot/dts/loongson/ls3a1000_780e_2way.dts | 13 ++ .../boot/dts/loongson/ls3a1000_780e_4way.dts | 13 ++ .../boot/dts/loongson/ls3a2000_780e_1way.dts | 12 ++ .../boot/dts/loongson/ls3a2000_780e_2way.dts | 13 ++ .../boot/dts/loongson/ls3a2000_780e_4way.dts | 13 ++ .../boot/dts/loongson/ls3a3000_780e_1way.dts | 12 ++ .../boot/dts/loongson/ls3a3000_780e_2way.dts | 13 ++ .../boot/dts/loongson/ls3a3000_780e_4way.dts | 13 ++ arch/mips/boot/dts/loongson/ls3b-package.dtsi | 59 +++++++ .../mips/boot/dts/loongson/ls3b_780e_1way.dts | 13 ++ .../mips/boot/dts/loongson/ls3b_780e_2way.dts | 13 ++ 22 files changed, 514 insertions(+), 1 deletion(-) create mode 100644 arch/mips/boot/dts/loongson/Makefile create mode 100644 arch/mips/boot/dts/loongson/ls3-2nodes.dtsi create mode 100644 arch/mips/boot/dts/loongson/ls3-4nodes.dtsi create mode 100644 arch/mips/boot/dts/loongson/ls3-cpus.dtsi create mode 100644 arch/mips/boot/dts/loongson/ls3-gs464.dtsi create mode 100644 arch/mips/boot/dts/loongson/ls3-gs464e.dtsi create mode 100644 arch/mips/boot/dts/loongson/ls3-rs780e-pch.dtsi create mode 100644 arch/mips/boot/dts/loongson/ls3a-package.dtsi create mode 100644 arch/mips/boot/dts/loongson/ls3a1000_780e_1way.dts create mode 100644 arch/mips/boot/dts/loongson/ls3a1000_780e_2way.dts create mode 100644 arch/mips/boot/dts/loongson/ls3a1000_780e_4way.dts create mode 100644 arch/mips/boot/dts/loongson/ls3a2000_780e_1way.dts create mode 100644 arch/mips/boot/dts/loongson/ls3a2000_780e_2way.dts create mode 100644 arch/mips/boot/dts/loongson/ls3a2000_780e_4way.dts create mode 100644 arch/mips/boot/dts/loongson/ls3a3000_780e_1way.dts create mode 100644 arch/mips/boot/dts/loongson/ls3a3000_780e_2way.dts create mode 100644 arch/mips/boot/dts/loongson/ls3a3000_780e_4way.dts create mode 100644 arch/mips/boot/dts/loongson/ls3b-package.dtsi create mode 100644 arch/mips/boot/dts/loongson/ls3b_780e_1way.dts create mode 100644 arch/mips/boot/dts/loongson/ls3b_780e_2way.dts diff --git a/arch/mips/Kconfig b/arch/mips/Kconfig index 92a2ee773a40..1c27c3a4e036 100644 --- a/arch/mips/Kconfig +++ b/arch/mips/Kconfig @@ -485,6 +485,8 @@ config MACH_LOONGSON64 select SYS_SUPPORTS_LITTLE_ENDIAN select ZONE_DMA32 select SYS_SUPPORTS_ZBOOT + select USE_OF + select BUILTIN_DTB help This enables the support of Loongson-3A/3B/2-series-soc processors @@ -3074,7 +3076,7 @@ endchoice choice prompt "Kernel command line type" if !CMDLINE_OVERRIDE default MIPS_CMDLINE_FROM_DTB if USE_OF && !ATH79 && !MACH_INGENIC && \ - !MIPS_MALTA && \ + !MACH_LOONGSON64 && !MIPS_MALTA && \ !CAVIUM_OCTEON_SOC default MIPS_CMDLINE_FROM_BOOTLOADER diff --git a/arch/mips/boot/dts/Makefile b/arch/mips/boot/dts/Makefile index 1e79cab8e269..d429a69bfe30 100644 --- a/arch/mips/boot/dts/Makefile +++ b/arch/mips/boot/dts/Makefile @@ -4,6 +4,7 @@ subdir-y += cavium-octeon subdir-y += img subdir-y += ingenic subdir-y += lantiq +subdir-y += loongson subdir-y += mscc subdir-y += mti subdir-y += netlogic diff --git a/arch/mips/boot/dts/loongson/Makefile b/arch/mips/boot/dts/loongson/Makefile new file mode 100644 index 000000000000..25dca8a89d5d --- /dev/null +++ b/arch/mips/boot/dts/loongson/Makefile @@ -0,0 +1,8 @@ +# SPDX_License_Identifier: GPL_2.0 +dtb-$(CONFIG_MACH_LOONGSON64) += ls3a1000_780e_1way.dtb ls3a1000_780e_2way.dtb ls3a1000_780e_4way.dtb \ + ls3b_780e_1way.dtb ls3b_780e_2way.dtb \ + ls3a2000_780e_1way.dtb ls3a2000_780e_2way.dtb ls3a2000_780e_4way.dtb \ + ls3a3000_780e_1way.dtb ls3a3000_780e_2way.dtb ls3a3000_780e_4way.dtb + + +obj-$(CONFIG_BUILTIN_DTB) += $(addsuffix .o, $(dtb-y)) diff --git a/arch/mips/boot/dts/loongson/ls3-2nodes.dtsi b/arch/mips/boot/dts/loongson/ls3-2nodes.dtsi new file mode 100644 index 000000000000..3103a4f96f68 --- /dev/null +++ b/arch/mips/boot/dts/loongson/ls3-2nodes.dtsi @@ -0,0 +1,8 @@ +// SPDX-License-Identifier: GPL-2.0 + +&cpu4 { status = "okay"; }; +&cpu5 { status = "okay"; }; +&cpu6 { status = "okay"; }; +&cpu7 { status = "okay"; }; + +&scache1 { status = "okay"; }; diff --git a/arch/mips/boot/dts/loongson/ls3-4nodes.dtsi b/arch/mips/boot/dts/loongson/ls3-4nodes.dtsi new file mode 100644 index 000000000000..be8cca52c072 --- /dev/null +++ b/arch/mips/boot/dts/loongson/ls3-4nodes.dtsi @@ -0,0 +1,15 @@ +// SPDX-License-Identifier: GPL-2.0 + +/include/ "ls3-2nodes.dtsi" + +&cpu8 { status = "okay"; }; +&cpu9 { status = "okay"; }; +&cpu10 { status = "okay"; }; +&cpu11 { status = "okay"; }; +&cpu12 { status = "okay"; }; +&cpu13 { status = "okay"; }; +&cpu14 { status = "okay"; }; +&cpu15 { status = "okay"; }; + +&scache2 { status = "okay"; }; +&scache3 { status = "okay"; }; diff --git a/arch/mips/boot/dts/loongson/ls3-cpus.dtsi b/arch/mips/boot/dts/loongson/ls3-cpus.dtsi new file mode 100644 index 000000000000..7e4705cd8a7c --- /dev/null +++ b/arch/mips/boot/dts/loongson/ls3-cpus.dtsi @@ -0,0 +1,150 @@ +// SPDX-License-Identifier: GPL-2.0 + +/ { + #address-cells = <2>; + #size-cells = <2>; + + /* + * Loongson-3 may have as many as 4 nodes, each node has 4 cores. + * Each core has its own pcache and cores in the same node share scache. + * CPU 0-3 should always exist in all the systems. + */ + cpus { + #address-cells = <1>; + #size-cells = <0>; + + cpu0: cpu@0 { + device_type = "cpu"; + reg = <0x0>; + next-level-cache = <&scache0>; + }; + + cpu1: cpu@1 { + device_type = "cpu"; + reg = <0x1>; + next-level-cache = <&scache0>; + }; + + cpu2: cpu@2 { + device_type = "cpu"; + reg = <0x2>; + next-level-cache = <&scache0>; + }; + + cpu3: cpu@3 { + device_type = "cpu"; + reg = <0x3>; + next-level-cache = <&scache0>; + }; + + cpu4: cpu@4 { + status = "disabled"; + device_type = "cpu"; + reg = <0x4>; + next-level-cache = <&scache1>; + }; + + cpu5: cpu@5 { + status = "disabled"; + device_type = "cpu"; + reg = <0x5>; + next-level-cache = <&scache1>; + }; + + cpu6: cpu@6 { + status = "disabled"; + device_type = "cpu"; + reg = <0x6>; + next-level-cache = <&scache1>; + }; + + cpu7: cpu@7 { + status = "disabled"; + device_type = "cpu"; + reg = <0x7>; + next-level-cache = <&scache1>; + }; + + cpu8: cpu@8 { + status = "disabled"; + device_type = "cpu"; + reg = <0x8>; + next-level-cache = <&scache2>; + }; + + cpu9: cpu@9 { + status = "disabled"; + device_type = "cpu"; + reg = <0x9>; + next-level-cache = <&scache2>; + }; + + cpu10: cpu@a { + status = "disabled"; + device_type = "cpu"; + reg = <0xa>; + next-level-cache = <&scache2>; + }; + + cpu11: cpu@b { + status = "disabled"; + device_type = "cpu"; + reg = <0xb>; + next-level-cache = <&scache2>; + }; + + cpu12: cpu@c { + status = "disabled"; + device_type = "cpu"; + reg = <0xc>; + next-level-cache = <&scache3>; + }; + + cpu13: cpu@d { + status = "disabled"; + device_type = "cpu"; + reg = <0xd>; + next-level-cache = <&scache3>; + }; + + cpu14: cpu@e { + status = "disabled"; + device_type = "cpu"; + reg = <0xe>; + next-level-cache = <&scache3>; + }; + + cpu15: cpu@f { + status = "disabled"; + device_type = "cpu"; + reg = <0xf>; + next-level-cache = <&scache3>; + }; + + scache0: l2-cache0 { + compatible = "cache"; + }; + + scache1: l2-cache1 { + status = "disabled"; + compatible = "cache"; + }; + + scache2: l2-cache2 { + status = "disabled"; + compatible = "cache"; + }; + + scache3: l2-cache3 { + status = "disabled"; + compatible = "cache"; + }; + }; + + cpuintc: interrupt-controller { + #address-cells = <0>; + #interrupt-cells = <1>; + interrupt-controller; + compatible = "mti,cpu-interrupt-controller"; + }; +}; diff --git a/arch/mips/boot/dts/loongson/ls3-gs464.dtsi b/arch/mips/boot/dts/loongson/ls3-gs464.dtsi new file mode 100644 index 000000000000..54d7be042150 --- /dev/null +++ b/arch/mips/boot/dts/loongson/ls3-gs464.dtsi @@ -0,0 +1,18 @@ +// SPDX-License-Identifier: GPL-2.0 + +&cpu0 { compatible = "loongson,gs464"; }; +&cpu1 { compatible = "loongson,gs464"; }; +&cpu2 { compatible = "loongson,gs464"; }; +&cpu3 { compatible = "loongson,gs464"; }; +&cpu4 { compatible = "loongson,gs464"; }; +&cpu5 { compatible = "loongson,gs464"; }; +&cpu6 { compatible = "loongson,gs464"; }; +&cpu7 { compatible = "loongson,gs464"; }; +&cpu8 { compatible = "loongson,gs464"; }; +&cpu9 { compatible = "loongson,gs464"; }; +&cpu10 { compatible = "loongson,gs464"; }; +&cpu11 { compatible = "loongson,gs464"; }; +&cpu12 { compatible = "loongson,gs464"; }; +&cpu13 { compatible = "loongson,gs464"; }; +&cpu14 { compatible = "loongson,gs464"; }; +&cpu15 { compatible = "loongson,gs464"; }; diff --git a/arch/mips/boot/dts/loongson/ls3-gs464e.dtsi b/arch/mips/boot/dts/loongson/ls3-gs464e.dtsi new file mode 100644 index 000000000000..c5f545ef8d94 --- /dev/null +++ b/arch/mips/boot/dts/loongson/ls3-gs464e.dtsi @@ -0,0 +1,18 @@ +// SPDX-License-Identifier: GPL-2.0 + +&cpu0 { compatible = "loongson,gs464e"; }; +&cpu1 { compatible = "loongson,gs464e"; }; +&cpu2 { compatible = "loongson,gs464e"; }; +&cpu3 { compatible = "loongson,gs464e"; }; +&cpu4 { compatible = "loongson,gs464e"; }; +&cpu5 { compatible = "loongson,gs464e"; }; +&cpu6 { compatible = "loongson,gs464e"; }; +&cpu7 { compatible = "loongson,gs464e"; }; +&cpu8 { compatible = "loongson,gs464e"; }; +&cpu9 { compatible = "loongson,gs464e"; }; +&cpu10 { compatible = "loongson,gs464e"; }; +&cpu11 { compatible = "loongson,gs464e"; }; +&cpu12 { compatible = "loongson,gs464e"; }; +&cpu13 { compatible = "loongson,gs464e"; }; +&cpu14 { compatible = "loongson,gs464e"; }; +&cpu15 { compatible = "loongson,gs464e"; }; diff --git a/arch/mips/boot/dts/loongson/ls3-rs780e-pch.dtsi b/arch/mips/boot/dts/loongson/ls3-rs780e-pch.dtsi new file mode 100644 index 000000000000..e971a44efc56 --- /dev/null +++ b/arch/mips/boot/dts/loongson/ls3-rs780e-pch.dtsi @@ -0,0 +1,35 @@ +// SPDX-License-Identifier: GPL-2.0 + +/ { + pch { + compatible = "simple-bus"; + #address-cells = <2>; + #size-cells = <1>; + ranges = <0x000 0x10000000 0x000 0x10000000 0x10000000 + 0x000 0x40000000 0x000 0x40000000 0x40000000>; + + isa { + compatible = "isa"; + #address-cells = <2>; + #size-cells = <1>; + ranges = <1 0 0 0 0x1000>; + + i8259: interrupt-controller@20 { + compatible = "intel,i8259"; + interrupt-controller; + #interrupt-cells = <1>; + plat-poll; + interrupts = <0>, <1>, <2>, <3>, <4>, <5>, <6>, <7>, + <8>, <9>, <10>, <11>, <12>, <13>, <14>, <15>; + interrupt-parent = <&htintc>; + }; + + rtc0: rtc@70 { + compatible = "motorola,mc146818"; + reg = <1 0x70 0x8>; + interrupts = <8>; + interrupt-parent = <&i8259>; + }; + }; + }; +}; diff --git a/arch/mips/boot/dts/loongson/ls3a-package.dtsi b/arch/mips/boot/dts/loongson/ls3a-package.dtsi new file mode 100644 index 000000000000..23e5c3a6a71e --- /dev/null +++ b/arch/mips/boot/dts/loongson/ls3a-package.dtsi @@ -0,0 +1,59 @@ +// SPDX-License-Identifier: GPL-2.0 + +#include + +/ { + package@0 { + compatible = "simple-bus"; + #address-cells = <2>; + #size-cells = <1>; + ranges = <0 0x1fe00000 0 0x1fe00000 0x100000 + 0 0x3ff00000 0 0x3ff00000 0x100000 + 0xEFD 0xFB000000 0xEFD 0xFB000000 0x10000000 /* 3A HT Config Space */>; + + iointc: interrupt-controller@3ff01400 { + compatible = "loongson,ls3-iointc"; + reg = <0 0x3ff01400 0x64>; + + interrupt-controller; + #interrupt-cells = <2>; + + interrupt-parent = <&cpuintc>; + interrupts = <2>; + }; + + cpu_uart0: serial@1fe001e0 { + device_type = "serial"; + compatible = "ns16550a"; + reg = <0 0x1fe001e0 0x8>; + clock-frequency = <33000000>; + interrupt-parent = <&iointc>; + interrupts = <10 IRQ_TYPE_LEVEL_HIGH>; + no-loopback-test; + }; + + cpu_uart1: serial@1fe001e8 { + status = "disabled"; + device_type = "serial"; + compatible = "ns16550a"; + reg = <0 0x1fe001e8 0x8>; + clock-frequency = <33000000>; + interrupts = <10 IRQ_TYPE_LEVEL_HIGH>; + interrupt-parent = <&iointc>; + no-loopback-test; + }; + + htintc: interrupt-controller@0xEFDFB000080 { + compatible = "loongson,ls3-htintc"; + reg = <0xEFD 0xFB000080 0x100>; + interrupt-controller; + #interrupt-cells = <1>; + + interrupt-parent = <&iointc>; + interrupts = <24 IRQ_TYPE_LEVEL_HIGH>, + <25 IRQ_TYPE_LEVEL_HIGH>, + <26 IRQ_TYPE_LEVEL_HIGH>, + <27 IRQ_TYPE_LEVEL_HIGH>; + }; + }; +}; diff --git a/arch/mips/boot/dts/loongson/ls3a1000_780e_1way.dts b/arch/mips/boot/dts/loongson/ls3a1000_780e_1way.dts new file mode 100644 index 000000000000..6cf90d032cf6 --- /dev/null +++ b/arch/mips/boot/dts/loongson/ls3a1000_780e_1way.dts @@ -0,0 +1,12 @@ +// SPDX-License-Identifier: GPL-2.0 + +/dts-v1/; + +#include "ls3-cpus.dtsi" +#include "ls3-gs464.dtsi" +#include "ls3a-package.dtsi" +#include "ls3-rs780e-pch.dtsi" + +/ { + compatible = "loongson,ls3a1000-780e-1way"; +}; diff --git a/arch/mips/boot/dts/loongson/ls3a1000_780e_2way.dts b/arch/mips/boot/dts/loongson/ls3a1000_780e_2way.dts new file mode 100644 index 000000000000..cb1325a2bd64 --- /dev/null +++ b/arch/mips/boot/dts/loongson/ls3a1000_780e_2way.dts @@ -0,0 +1,13 @@ +// SPDX-License-Identifier: GPL-2.0 + +/dts-v1/; + +#include "ls3-cpus.dtsi" +#include "ls3-gs464.dtsi" +#include "ls3a-package.dtsi" +#include "ls3-2nodes.dtsi" +#include "ls3-rs780e-pch.dtsi" + +/ { + compatible = "loongson,ls3a1000-780e-2way"; +}; diff --git a/arch/mips/boot/dts/loongson/ls3a1000_780e_4way.dts b/arch/mips/boot/dts/loongson/ls3a1000_780e_4way.dts new file mode 100644 index 000000000000..e6fa9859fa4f --- /dev/null +++ b/arch/mips/boot/dts/loongson/ls3a1000_780e_4way.dts @@ -0,0 +1,13 @@ +// SPDX-License-Identifier: GPL-2.0 + +/dts-v1/; + +#include "ls3-cpus.dtsi" +#include "ls3-gs464.dtsi" +#include "ls3a-package.dtsi" +#include "ls3-4nodes.dtsi" +#include "ls3-rs780e-pch.dtsi" + +/ { + compatible = "loongson,ls3a1000-780e-4way"; +}; diff --git a/arch/mips/boot/dts/loongson/ls3a2000_780e_1way.dts b/arch/mips/boot/dts/loongson/ls3a2000_780e_1way.dts new file mode 100644 index 000000000000..a726f0186355 --- /dev/null +++ b/arch/mips/boot/dts/loongson/ls3a2000_780e_1way.dts @@ -0,0 +1,12 @@ +// SPDX-License-Identifier: GPL-2.0 + +/dts-v1/; + +#include "ls3-cpus.dtsi" +#include "ls3-gs464e.dtsi" +#include "ls3a-package.dtsi" +#include "ls3-rs780e-pch.dtsi" + +/ { + compatible = "loongson,ls3a2000-780e-1way"; +}; diff --git a/arch/mips/boot/dts/loongson/ls3a2000_780e_2way.dts b/arch/mips/boot/dts/loongson/ls3a2000_780e_2way.dts new file mode 100644 index 000000000000..19268b640cae --- /dev/null +++ b/arch/mips/boot/dts/loongson/ls3a2000_780e_2way.dts @@ -0,0 +1,13 @@ +// SPDX-License-Identifier: GPL-2.0 + +/dts-v1/; + +#include "ls3-cpus.dtsi" +#include "ls3-gs464e.dtsi" +#include "ls3a-package.dtsi" +#include "ls3-2nodes.dtsi" +#include "ls3-rs780e-pch.dtsi" + +/ { + compatible = "loongson,ls3a2000-780e-2way"; +}; diff --git a/arch/mips/boot/dts/loongson/ls3a2000_780e_4way.dts b/arch/mips/boot/dts/loongson/ls3a2000_780e_4way.dts new file mode 100644 index 000000000000..2b491396225b --- /dev/null +++ b/arch/mips/boot/dts/loongson/ls3a2000_780e_4way.dts @@ -0,0 +1,13 @@ +// SPDX-License-Identifier: GPL-2.0 + +/dts-v1/; + +#include "ls3-cpus.dtsi" +#include "ls3-gs464e.dtsi" +#include "ls3a-package.dtsi" +#include "ls3-4nodes.dtsi" +#include "ls3-rs780e-pch.dtsi" + +/ { + compatible = "loongson,ls3a2000-780e-4way"; +}; diff --git a/arch/mips/boot/dts/loongson/ls3a3000_780e_1way.dts b/arch/mips/boot/dts/loongson/ls3a3000_780e_1way.dts new file mode 100644 index 000000000000..628c5d0a7a25 --- /dev/null +++ b/arch/mips/boot/dts/loongson/ls3a3000_780e_1way.dts @@ -0,0 +1,12 @@ +// SPDX-License-Identifier: GPL-2.0 + +/dts-v1/; + +#include "ls3-cpus.dtsi" +#include "ls3-gs464e.dtsi" +#include "ls3a-package.dtsi" +#include "ls3-rs780e-pch.dtsi" + +/ { + compatible = "loongson,ls3a3000-780e-1way"; +}; diff --git a/arch/mips/boot/dts/loongson/ls3a3000_780e_2way.dts b/arch/mips/boot/dts/loongson/ls3a3000_780e_2way.dts new file mode 100644 index 000000000000..1390767ed462 --- /dev/null +++ b/arch/mips/boot/dts/loongson/ls3a3000_780e_2way.dts @@ -0,0 +1,13 @@ +// SPDX-License-Identifier: GPL-2.0 + +/dts-v1/; + +#include "ls3-cpus.dtsi" +#include "ls3-gs464e.dtsi" +#include "ls3a-package.dtsi" +#include "ls3-2nodes.dtsi" +#include "ls3-rs780e-pch.dtsi" + +/ { + compatible = "loongson,ls3a3000-780e-2way"; +}; diff --git a/arch/mips/boot/dts/loongson/ls3a3000_780e_4way.dts b/arch/mips/boot/dts/loongson/ls3a3000_780e_4way.dts new file mode 100644 index 000000000000..3f94c05e944a --- /dev/null +++ b/arch/mips/boot/dts/loongson/ls3a3000_780e_4way.dts @@ -0,0 +1,13 @@ +// SPDX-License-Identifier: GPL-2.0 + +/dts-v1/; + +#include "ls3-cpus.dtsi" +#include "ls3-gs464e.dtsi" +#include "ls3a-package.dtsi" +#include "ls3-4nodes.dtsi" +#include "ls3-rs780e-pch.dtsi" + +/ { + compatible = "loongson,ls3a3000-780e-4way"; +}; diff --git a/arch/mips/boot/dts/loongson/ls3b-package.dtsi b/arch/mips/boot/dts/loongson/ls3b-package.dtsi new file mode 100644 index 000000000000..f7e71cd5ba5b --- /dev/null +++ b/arch/mips/boot/dts/loongson/ls3b-package.dtsi @@ -0,0 +1,59 @@ +// SPDX-License-Identifier: GPL-2.0 + +#include + +/ { + package@0 { + compatible = "simple-bus"; + #address-cells = <2>; + #size-cells = <1>; + ranges = <0 0x1fe00000 0 0x1fe00000 0x100000 + 0 0x3ff00000 0 0x3ff00000 0x100000 + 0x1EFD 0xFB000000 0x1EFD 0xFB000000 0x10000000 /* 3B HT Config Space */>; + + iointc: interrupt-controller@3ff01400 { + compatible = "loongson,ls3-iointc"; + reg = <0 0x3ff01400 0x64>; + + interrupt-controller; + #interrupt-cells = <2>; + + interrupt-parent = <&cpuintc>; + interrupts = <2>; + }; + + cpu_uart0: serial@1fe001e0 { + device_type = "serial"; + compatible = "ns16550a"; + reg = <0 0x1fe001e0 0x8>; + clock-frequency = <33000000>; + interrupts = <10 IRQ_TYPE_LEVEL_HIGH>; + interrupt-parent = <&iointc>; + no-loopback-test; + }; + + cpu_uart1: serial@1fe001e8 { + status = "disabled"; + device_type = "serial"; + compatible = "ns16550a"; + reg = <0 0x1fe001e8 0x8>; + clock-frequency = <33000000>; + interrupts = <10 IRQ_TYPE_LEVEL_HIGH>; + interrupt-parent = <&iointc>; + no-loopback-test; + }; + + htintc: interrupt-controller@0x1EFDFB000080 { + compatible = "loongson,ls3-htintc"; + reg = <0x1EFD 0xFB000080 0x100>; + interrupt-controller; + #interrupt-cells = <1>; + + interrupt-parent = <&iointc>; + interrupts = <24 IRQ_TYPE_LEVEL_HIGH>, + <25 IRQ_TYPE_LEVEL_HIGH>, + <26 IRQ_TYPE_LEVEL_HIGH>, + <27 IRQ_TYPE_LEVEL_HIGH>; + }; + }; +}; diff --git a/arch/mips/boot/dts/loongson/ls3b_780e_1way.dts b/arch/mips/boot/dts/loongson/ls3b_780e_1way.dts new file mode 100644 index 000000000000..9b73e0e49408 --- /dev/null +++ b/arch/mips/boot/dts/loongson/ls3b_780e_1way.dts @@ -0,0 +1,13 @@ +// SPDX-License-Identifier: GPL-2.0 + +/dts-v1/; + +#include "ls3-cpus.dtsi" +#include "ls3-gs464.dtsi" +#include "ls3b-package.dtsi" +#include "ls3-2nodes.dtsi" /* Yes, ls3b have 2 nodes per way */ +#include "ls3-rs780e-pch.dtsi" + +/ { + compatible = "loongson,ls3b-780e-1way"; +}; diff --git a/arch/mips/boot/dts/loongson/ls3b_780e_2way.dts b/arch/mips/boot/dts/loongson/ls3b_780e_2way.dts new file mode 100644 index 000000000000..6090de8a32d3 --- /dev/null +++ b/arch/mips/boot/dts/loongson/ls3b_780e_2way.dts @@ -0,0 +1,13 @@ +// SPDX-License-Identifier: GPL-2.0 + +/dts-v1/; + +#include "ls3-cpus.dtsi" +#include "ls3-gs464.dtsi" +#include "ls3b-package.dtsi" +#include "ls3-4nodes.dtsi" /* Yes, ls3b have 2 nodes per way */ +#include "ls3-rs780e-pch.dtsi" + +/ { + compatible = "loongson,ls3b-780e-2way"; +}; From patchwork Tue Aug 27 08:53:02 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Jiaxun Yang X-Patchwork-Id: 11116441 Return-Path: Received: from mail.kernel.org (pdx-korg-mail-1.web.codeaurora.org [172.30.200.123]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id 72ACE14DE for ; Tue, 27 Aug 2019 08:55:21 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.kernel.org (Postfix) with ESMTP id 511342184D for ; Tue, 27 Aug 2019 08:55:21 +0000 (UTC) Authentication-Results: mail.kernel.org; dkim=pass (1024-bit key) header.d=flygoat.com header.i=@flygoat.com header.b="NashDxeo" Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1725912AbfH0IzU (ORCPT ); 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dkim=pass header.i=@flygoat.com Received: by smtp1p.mail.yandex.net (nwsmtp/Yandex) with ESMTPSA id JOqUfE8LDO-t9tClHm7; Tue, 27 Aug 2019 11:55:13 +0300 (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits)) (Client certificate not present) From: Jiaxun Yang To: linux-mips@vger.kernel.org Cc: chenhc@lemote.com, paul.burton@mips.com, tglx@linutronix.de, jason@lakedaemon.net, maz@kernel.org, linux-kernel@vger.kernel.org, robh+dt@kernel.org, mark.rutland@arm.co, devicetree@vger.kernel.org, Jiaxun Yang Subject: [PATCH 13/13] MIPS: Loongson64: Load built-in dtbs Date: Tue, 27 Aug 2019 16:53:02 +0800 Message-Id: <20190827085302.5197-14-jiaxun.yang@flygoat.com> X-Mailer: git-send-email 2.22.0 In-Reply-To: <20190827085302.5197-1-jiaxun.yang@flygoat.com> References: <20190827085302.5197-1-jiaxun.yang@flygoat.com> MIME-Version: 1.0 Sender: linux-mips-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-mips@vger.kernel.org Load proper dtb according to firmware passed parameters and CPU PRID. Signed-off-by: Jiaxun Yang --- .../asm/mach-loongson64/builtin_dtbs.h | 26 +++++++ .../include/asm/mach-loongson64/loongson64.h | 2 + arch/mips/loongson64/env.c | 67 +++++++++++++++++++ arch/mips/loongson64/setup.c | 15 +++++ 4 files changed, 110 insertions(+) create mode 100644 arch/mips/include/asm/mach-loongson64/builtin_dtbs.h diff --git a/arch/mips/include/asm/mach-loongson64/builtin_dtbs.h b/arch/mips/include/asm/mach-loongson64/builtin_dtbs.h new file mode 100644 index 000000000000..234803ba9d82 --- /dev/null +++ b/arch/mips/include/asm/mach-loongson64/builtin_dtbs.h @@ -0,0 +1,26 @@ +/* SPDX-License-Identifier: GPL-2.0-or-later */ +/* + * Copyright (C) 2019 Jiaxun Yang + * + * Built-in Generic dtbs for MACH_LOONGSON64 + */ + +#ifndef __ASM_MACH_LOONGSON64_BUILTIN_DTBS_H_ +#define __ASM_MACH_LOONGSON64_BUILTIN_DTBS_H_ + +extern u32 __dtb_ls3a1000_780e_1way_begin[]; +extern u32 __dtb_ls3a1000_780e_2way_begin[]; +extern u32 __dtb_ls3a1000_780e_4way_begin[]; + +extern u32 __dtb_ls3b_780e_1way_begin[]; +extern u32 __dtb_ls3b_780e_2way_begin[]; + +extern u32 __dtb_ls3a2000_780e_1way_begin[]; +extern u32 __dtb_ls3a2000_780e_2way_begin[]; +extern u32 __dtb_ls3a2000_780e_4way_begin[]; + +extern u32 __dtb_ls3a3000_780e_1way_begin[]; +extern u32 __dtb_ls3a3000_780e_2way_begin[]; +extern u32 __dtb_ls3a3000_780e_4way_begin[]; + +#endif diff --git a/arch/mips/include/asm/mach-loongson64/loongson64.h b/arch/mips/include/asm/mach-loongson64/loongson64.h index d877adb99d33..78daa3fb3fa7 100644 --- a/arch/mips/include/asm/mach-loongson64/loongson64.h +++ b/arch/mips/include/asm/mach-loongson64/loongson64.h @@ -45,4 +45,6 @@ extern u64 loongson_freqctrl[MAX_PACKAGES]; extern const struct plat_smp_ops loongson3_smp_ops; extern void __init prom_init_lefi(void); +extern void *loongson_fdt_blob; + #endif diff --git a/arch/mips/loongson64/env.c b/arch/mips/loongson64/env.c index 93658cfbf3a6..4336bd7c1b94 100644 --- a/arch/mips/loongson64/env.c +++ b/arch/mips/loongson64/env.c @@ -20,6 +20,7 @@ #include #include +#include #include u32 cpu_clock_freq; @@ -126,6 +127,72 @@ void __init prom_init_lefi(void) loongson_sysconf.cores_per_node - 1) / loongson_sysconf.cores_per_node; + if ((read_c0_prid() & PRID_IMP_MASK) == PRID_IMP_LOONGSON_64) { + switch (read_c0_prid() & PRID_REV_MASK) { + case PRID_REV_LOONGSON3A_R1: + switch (loongson_sysconf.nr_nodes) { + case 4: + loongson_fdt_blob = __dtb_ls3a1000_780e_4way_begin; + break; + case 2: + loongson_fdt_blob = __dtb_ls3a1000_780e_2way_begin; + break; + case 1: + default: + loongson_fdt_blob = __dtb_ls3a1000_780e_1way_begin; + break; + } + break; + case PRID_REV_LOONGSON3A_R2_0: + case PRID_REV_LOONGSON3A_R2_1: + switch (loongson_sysconf.nr_nodes) { + case 4: + loongson_fdt_blob = __dtb_ls3a2000_780e_4way_begin; + break; + case 2: + loongson_fdt_blob = __dtb_ls3a2000_780e_2way_begin; + break; + case 1: + default: + loongson_fdt_blob = __dtb_ls3a2000_780e_1way_begin; + break; + } + break; + case PRID_REV_LOONGSON3A_R3_0: + case PRID_REV_LOONGSON3A_R3_1: + switch (loongson_sysconf.nr_nodes) { + case 4: + loongson_fdt_blob = __dtb_ls3a3000_780e_4way_begin; + break; + case 2: + loongson_fdt_blob = __dtb_ls3a3000_780e_2way_begin; + break; + case 1: + default: + loongson_fdt_blob = __dtb_ls3a3000_780e_1way_begin; + break; + } + break; + case PRID_REV_LOONGSON3B_R1: + case PRID_REV_LOONGSON3B_R2: + switch (loongson_sysconf.nr_nodes) { + case 4: + loongson_fdt_blob = __dtb_ls3b_780e_2way_begin; + break; + case 2: + default: + loongson_fdt_blob = __dtb_ls3b_780e_1way_begin; + break; + } + break; + default: + break; + } + } + + if(!loongson_fdt_blob) + pr_err("Failed to determine built-in Loongson64 dtb\n"); + loongson_sysconf.pci_mem_start_addr = eirq_source->pci_mem_start_addr; loongson_sysconf.pci_mem_end_addr = eirq_source->pci_mem_end_addr; loongson_sysconf.pci_io_base = eirq_source->pci_io_start_addr; diff --git a/arch/mips/loongson64/setup.c b/arch/mips/loongson64/setup.c index 24432adc8350..3b850b3128ea 100644 --- a/arch/mips/loongson64/setup.c +++ b/arch/mips/loongson64/setup.c @@ -7,9 +7,15 @@ #include #include #include +#include +#include + +#include #include +void *loongson_fdt_blob; + static void wbflush_loongson(void) { asm(".set\tpush\n\t" @@ -81,6 +87,8 @@ void __init prom_free_prom_memory(void) void __init plat_mem_setup(void) { + if (loongson_fdt_blob) + __dt_setup_arch(loongson_fdt_blob); } void __init plat_time_init(void) @@ -90,3 +98,10 @@ void __init plat_time_init(void) #endif } +void __init device_tree_init(void) +{ + if (!initial_boot_params) + return; + + unflatten_and_copy_device_tree(); +}