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X-Received-From: 216.71.153.144 Subject: [Qemu-devel] [PATCH v1 1/4] target/riscv: Rename mbadaddr and sbadaddr X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: alistair23@gmail.com, alistair.francis@wdc.com Errors-To: qemu-devel-bounces+patchwork-qemu-devel=patchwork.kernel.org@nongnu.org Sender: "Qemu-devel" X-Virus-Scanned: ClamAV using ClamSMTP Update to the latest spec (v1.10.0) and rename mbadaddr and sbadaddr to mtval and stval. Signed-off-by: Alistair Francis --- target/riscv/cpu.h | 3 +-- target/riscv/cpu_bits.h | 4 ++-- target/riscv/helper.c | 8 ++++---- target/riscv/op_helper.c | 16 ++++++++-------- 4 files changed, 15 insertions(+), 16 deletions(-) diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h index 34abc383e3..0243f73129 100644 --- a/target/riscv/cpu.h +++ b/target/riscv/cpu.h @@ -138,8 +138,6 @@ struct CPURISCVState { target_ulong sptbr; /* until: priv-1.9.1 */ target_ulong satp; /* since: priv-1.10.0 */ - target_ulong sbadaddr; - target_ulong mbadaddr; target_ulong medeleg; target_ulong stvec; @@ -150,6 +148,7 @@ struct CPURISCVState { target_ulong mepc; target_ulong mcause; target_ulong mtval; /* since: priv-1.10.0 */ + target_ulong stval; /* since: priv-1.10.0 */ target_ulong scounteren; target_ulong mcounteren; diff --git a/target/riscv/cpu_bits.h b/target/riscv/cpu_bits.h index 64aa097181..135202c359 100644 --- a/target/riscv/cpu_bits.h +++ b/target/riscv/cpu_bits.h @@ -68,7 +68,7 @@ #define CSR_SSCRATCH 0x140 #define CSR_SEPC 0x141 #define CSR_SCAUSE 0x142 -#define CSR_SBADADDR 0x143 +#define CSR_STVAL 0x143 #define CSR_SIP 0x144 #define CSR_SPTBR 0x180 #define CSR_SATP 0x180 @@ -82,7 +82,7 @@ #define CSR_MSCRATCH 0x340 #define CSR_MEPC 0x341 #define CSR_MCAUSE 0x342 -#define CSR_MBADADDR 0x343 +#define CSR_MTVAL 0x343 #define CSR_MIP 0x344 #define CSR_PMPCFG0 0x3a0 #define CSR_PMPCFG1 0x3a1 diff --git a/target/riscv/helper.c b/target/riscv/helper.c index 29e1a603dc..b4a3f80872 100644 --- a/target/riscv/helper.c +++ b/target/riscv/helper.c @@ -465,11 +465,11 @@ void riscv_cpu_do_interrupt(CPUState *cs) qemu_log_mask(LOG_TRACE, "core " TARGET_FMT_ld ": badaddr 0x" TARGET_FMT_lx, env->mhartid, env->badaddr); } - env->sbadaddr = env->badaddr; + env->stval = env->badaddr; } else { /* otherwise we must clear sbadaddr/stval * todo: support populating stval on illegal instructions */ - env->sbadaddr = 0; + env->stval = 0; } target_ulong s = env->mstatus; @@ -490,11 +490,11 @@ void riscv_cpu_do_interrupt(CPUState *cs) qemu_log_mask(LOG_TRACE, "core " TARGET_FMT_ld ": badaddr 0x" TARGET_FMT_lx, env->mhartid, env->badaddr); } - env->mbadaddr = env->badaddr; + env->mtval = env->badaddr; } else { /* otherwise we must clear mbadaddr/mtval * todo: support populating mtval on illegal instructions */ - env->mbadaddr = 0; + env->mtval = 0; } target_ulong s = env->mstatus; diff --git a/target/riscv/op_helper.c b/target/riscv/op_helper.c index aec7558e1b..d2ec078765 100644 --- a/target/riscv/op_helper.c +++ b/target/riscv/op_helper.c @@ -310,8 +310,8 @@ void csr_write_helper(CPURISCVState *env, target_ulong val_to_write, case CSR_SCAUSE: env->scause = val_to_write; break; - case CSR_SBADADDR: - env->sbadaddr = val_to_write; + case CSR_STVAL: + env->stval = val_to_write; break; case CSR_MEPC: env->mepc = val_to_write; @@ -338,8 +338,8 @@ void csr_write_helper(CPURISCVState *env, target_ulong val_to_write, case CSR_MCAUSE: env->mcause = val_to_write; break; - case CSR_MBADADDR: - env->mbadaddr = val_to_write; + case CSR_MTVAL: + env->mtval = val_to_write; break; case CSR_MISA: /* misa is WARL so unsupported writes are ignored */ @@ -515,8 +515,8 @@ target_ulong csr_read_helper(CPURISCVState *env, target_ulong csrno) return env->mie & env->mideleg; case CSR_SEPC: return env->sepc; - case CSR_SBADADDR: - return env->sbadaddr; + case CSR_STVAL: + return env->stval; case CSR_STVEC: return env->stvec; case CSR_SCOUNTEREN: @@ -554,8 +554,8 @@ target_ulong csr_read_helper(CPURISCVState *env, target_ulong csrno) return env->mscratch; case CSR_MCAUSE: return env->mcause; - case CSR_MBADADDR: - return env->mbadaddr; + case CSR_MTVAL: + return env->mtval; case CSR_MISA: return env->misa; case CSR_MARCHID: From patchwork Wed Jul 25 23:04:00 2018 Content-Type: text/plain; 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X-Received-From: 216.71.153.144 Subject: [Qemu-devel] [PATCH v1 2/4] target/riscv: Implement the mtval illegal instruction X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: alistair23@gmail.com, alistair.francis@wdc.com Errors-To: qemu-devel-bounces+patchwork-qemu-devel=patchwork.kernel.org@nongnu.org Sender: "Qemu-devel" X-Virus-Scanned: ClamAV using ClamSMTP The mtval register can optionally contain the faulting instruction on an illegal instruction exception. This patch adds support for setting the mtval register based on the CPU feature. Signed-off-by: Alistair Francis --- target/riscv/cpu.h | 4 +++- target/riscv/helper.c | 13 +++++++++++-- target/riscv/translate.c | 12 ++++++++++++ 3 files changed, 26 insertions(+), 3 deletions(-) diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h index 0243f73129..1bc46aa952 100644 --- a/target/riscv/cpu.h +++ b/target/riscv/cpu.h @@ -85,7 +85,8 @@ is currently no bit in misa to indicate whether an MMU exists or not so a cpu features bitfield is required */ enum { - RISCV_FEATURE_MMU + RISCV_FEATURE_MMU, + RISCV_FEATURE_MTVAL_INST }; #define USER_VERSION_2_02_0 0x00020200 @@ -113,6 +114,7 @@ struct CPURISCVState { target_ulong frm; target_ulong badaddr; + target_ulong bins; target_ulong user_ver; target_ulong priv_ver; diff --git a/target/riscv/helper.c b/target/riscv/helper.c index b4a3f80872..bd78bcff28 100644 --- a/target/riscv/helper.c +++ b/target/riscv/helper.c @@ -491,9 +491,18 @@ void riscv_cpu_do_interrupt(CPUState *cs) ": badaddr 0x" TARGET_FMT_lx, env->mhartid, env->badaddr); } env->mtval = env->badaddr; + } else if (cs->exception_index & RISCV_EXCP_ILLEGAL_INST) { + if (riscv_feature(env, RISCV_FEATURE_MTVAL_INST)) { + /* The mtval register can optionally also be used to + * return the faulting instruction bits on an illegal + * instruction exception. + */ + env->mtval = env->bins; + } else { + env->mtval = 0; + } } else { - /* otherwise we must clear mbadaddr/mtval - * todo: support populating mtval on illegal instructions */ + /* Otherwise we must clear mbadaddr/mtval */ env->mtval = 0; } diff --git a/target/riscv/translate.c b/target/riscv/translate.c index 0b6be74f2d..1fe8b9c982 100644 --- a/target/riscv/translate.c +++ b/target/riscv/translate.c @@ -102,6 +102,15 @@ static void gen_exception_debug(void) static void gen_exception_illegal(DisasContext *ctx) { +#if defined(TARGET_RISCV64) + TCGv_i64 helper_tmp = tcg_const_i64(ctx->opcode); + tcg_gen_st_tl(helper_tmp, cpu_env, offsetof(CPURISCVState, bins)); + tcg_temp_free_i64(helper_tmp); +#else + TCGv_i32 helper_tmp = tcg_const_i32(ctx->opcode); + tcg_gen_st_tl(helper_tmp, cpu_env, offsetof(CPURISCVState, bins)); + tcg_temp_free_i32(helper_tmp); +#endif generate_exception(ctx, RISCV_EXCP_ILLEGAL_INST); } @@ -1287,6 +1296,9 @@ static void gen_system(CPURISCVState *env, DisasContext *ctx, uint32_t opc, tcg_gen_movi_tl(rs1_pass, rs1); tcg_gen_movi_tl(csr_store, csr); /* copy into temp reg to feed to helper */ + /* Store the opcode code incase we need it for mtval/stval. */ + env->bins = ctx->opcode; + #ifndef CONFIG_USER_ONLY /* Extract funct7 value and check whether it matches SFENCE.VMA */ if ((opc == OPC_RISC_ECALL) && ((csr >> 5) == 9)) { From patchwork Wed Jul 25 23:04:13 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Alistair Francis X-Patchwork-Id: 10544905 Return-Path: Received: from mail.wl.linuxfoundation.org (pdx-wl-mail.web.codeaurora.org [172.30.200.125]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id 270D4139A for ; Wed, 25 Jul 2018 23:07:43 +0000 (UTC) Received: from mail.wl.linuxfoundation.org (localhost [127.0.0.1]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id 081342A671 for ; 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X-Received-From: 68.232.141.245 Subject: [Qemu-devel] [PATCH v1 3/4] target/riscv: Implement the stval illegal instruction X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: alistair23@gmail.com, alistair.francis@wdc.com Errors-To: qemu-devel-bounces+patchwork-qemu-devel=patchwork.kernel.org@nongnu.org Sender: "Qemu-devel" X-Virus-Scanned: ClamAV using ClamSMTP The stval register can optionally contain the faulting instruction on an illegal instruction exception. This patch adds support for setting the stval register based on the CPU feature. Signed-off-by: Alistair Francis --- target/riscv/cpu.h | 3 ++- target/riscv/helper.c | 13 +++++++++++-- 2 files changed, 13 insertions(+), 3 deletions(-) diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h index 1bc46aa952..b797850816 100644 --- a/target/riscv/cpu.h +++ b/target/riscv/cpu.h @@ -86,7 +86,8 @@ so a cpu features bitfield is required */ enum { RISCV_FEATURE_MMU, - RISCV_FEATURE_MTVAL_INST + RISCV_FEATURE_MTVAL_INST, + RISCV_FEATURE_STVAL_INST }; #define USER_VERSION_2_02_0 0x00020200 diff --git a/target/riscv/helper.c b/target/riscv/helper.c index bd78bcff28..924a49d06f 100644 --- a/target/riscv/helper.c +++ b/target/riscv/helper.c @@ -466,9 +466,18 @@ void riscv_cpu_do_interrupt(CPUState *cs) ": badaddr 0x" TARGET_FMT_lx, env->mhartid, env->badaddr); } env->stval = env->badaddr; + } else if (cs->exception_index & RISCV_EXCP_ILLEGAL_INST) { + if (riscv_feature(env, RISCV_FEATURE_STVAL_INST)) { + /* The stval register can optionally also be used to + * return the faulting instruction bits on an illegal + * instruction exception. + */ + env->stval = env->bins; + } else { + env->stval = 0; + } } else { - /* otherwise we must clear sbadaddr/stval - * todo: support populating stval on illegal instructions */ + /* Otherwise we must clear mbadaddr/stval */ env->stval = 0; } From patchwork Wed Jul 25 23:04:25 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Alistair Francis X-Patchwork-Id: 10544907 Return-Path: Received: from mail.wl.linuxfoundation.org (pdx-wl-mail.web.codeaurora.org [172.30.200.125]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id 50E66112E for ; Wed, 25 Jul 2018 23:07:51 +0000 (UTC) Received: from mail.wl.linuxfoundation.org (localhost [127.0.0.1]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id 3E8392A674 for ; Wed, 25 Jul 2018 23:07:51 +0000 (UTC) Received: by mail.wl.linuxfoundation.org (Postfix, from userid 486) id 32E062A680; Wed, 25 Jul 2018 23:07:51 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on pdx-wl-mail.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-7.8 required=2.0 tests=BAD_ENC_HEADER,BAYES_00, DKIM_SIGNED,MAILING_LIST_MULTI,RCVD_IN_DNSWL_HI,T_DKIM_INVALID autolearn=ham version=3.3.1 Received: from lists.gnu.org (lists.gnu.org [208.118.235.17]) (using TLSv1 with cipher AES256-SHA (256/256 bits)) (No client certificate requested) by mail.wl.linuxfoundation.org (Postfix) with ESMTPS id BA3E02A674 for ; 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X-Received-From: 216.71.154.45 Subject: [Qemu-devel] [PATCH v1 4/4] target/riscv: set mtval and stval support X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: alistair23@gmail.com, alistair.francis@wdc.com Errors-To: qemu-devel-bounces+patchwork-qemu-devel=patchwork.kernel.org@nongnu.org Sender: "Qemu-devel" X-Virus-Scanned: ClamAV using ClamSMTP Signed-off-by: Alistair Francis --- target/riscv/cpu.c | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c index d630e8fd6c..b33950a2d4 100644 --- a/target/riscv/cpu.c +++ b/target/riscv/cpu.c @@ -133,6 +133,8 @@ static void rv32gcsu_priv1_10_0_cpu_init(Object *obj) set_versions(env, USER_VERSION_2_02_0, PRIV_VERSION_1_10_0); set_resetvec(env, DEFAULT_RSTVEC); set_feature(env, RISCV_FEATURE_MMU); + set_feature(env, RISCV_FEATURE_MTVAL_INST); + set_feature(env, RISCV_FEATURE_STVAL_INST); } static void rv32imacu_nommu_cpu_init(Object *obj) @@ -161,6 +163,8 @@ static void rv64gcsu_priv1_10_0_cpu_init(Object *obj) set_versions(env, USER_VERSION_2_02_0, PRIV_VERSION_1_10_0); set_resetvec(env, DEFAULT_RSTVEC); set_feature(env, RISCV_FEATURE_MMU); + set_feature(env, RISCV_FEATURE_MTVAL_INST); + set_feature(env, RISCV_FEATURE_STVAL_INST); } static void rv64imacu_nommu_cpu_init(Object *obj)