From patchwork Wed Aug 28 07:19:31 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Tero Kristo X-Patchwork-Id: 11117947 Return-Path: Received: from mail.kernel.org (pdx-korg-mail-1.web.codeaurora.org [172.30.200.123]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id F324D184E for ; Wed, 28 Aug 2019 07:20:05 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.kernel.org (Postfix) with ESMTP id D22D3217F5 for ; Wed, 28 Aug 2019 07:20:05 +0000 (UTC) Authentication-Results: mail.kernel.org; dkim=pass (1024-bit key) header.d=ti.com header.i=@ti.com header.b="LraKS8Tz" Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1726301AbfH1HUF (ORCPT ); Wed, 28 Aug 2019 03:20:05 -0400 Received: from lelv0142.ext.ti.com ([198.47.23.249]:33448 "EHLO lelv0142.ext.ti.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1726232AbfH1HUF (ORCPT ); Wed, 28 Aug 2019 03:20:05 -0400 Received: from fllv0034.itg.ti.com ([10.64.40.246]) by lelv0142.ext.ti.com (8.15.2/8.15.2) with ESMTP id x7S7JsW1126646; Wed, 28 Aug 2019 02:19:54 -0500 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=ti.com; s=ti-com-17Q1; t=1566976794; bh=4/vn3nShvBSwpELcXgs5bhAcnH64+34+9f0PSBWUDWs=; h=From:To:CC:Subject:Date:In-Reply-To:References; b=LraKS8TzgEzeYPHL4snMeE1o84L1wckgIsDr7E6wpgeU5JfDuCio95vxBJ+W4EcHp uHfalLNWZHAaRjdkaub4waGf9pv9M8ZaaQiMFO1vVP+d17PfmzDODyFRup8BrF2JKi wo2Cz+w2REE1unixyoxLKytENSJoyyrLIZr6xtmo= Received: from DFLE111.ent.ti.com (dfle111.ent.ti.com [10.64.6.32]) by fllv0034.itg.ti.com (8.15.2/8.15.2) with ESMTPS id x7S7Js4E025032 (version=TLSv1.2 cipher=AES256-GCM-SHA384 bits=256 verify=FAIL); Wed, 28 Aug 2019 02:19:54 -0500 Received: from DFLE102.ent.ti.com (10.64.6.23) by DFLE111.ent.ti.com (10.64.6.32) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.1713.5; Wed, 28 Aug 2019 02:19:53 -0500 Received: from lelv0327.itg.ti.com (10.180.67.183) by DFLE102.ent.ti.com (10.64.6.23) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.1713.5 via Frontend Transport; Wed, 28 Aug 2019 02:19:53 -0500 Received: from sokoban.bb.dnainternet.fi (ileax41-snat.itg.ti.com [10.172.224.153]) by lelv0327.itg.ti.com (8.15.2/8.15.2) with ESMTP id x7S7JmfD052201; Wed, 28 Aug 2019 02:19:51 -0500 From: Tero Kristo To: , , , , CC: , , Subject: [PATCHv2 01/11] dt-bindings: omap: add new binding for PRM instances Date: Wed, 28 Aug 2019 10:19:31 +0300 Message-ID: <20190828071941.32378-2-t-kristo@ti.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20190828071941.32378-1-t-kristo@ti.com> References: <20190828071941.32378-1-t-kristo@ti.com> MIME-Version: 1.0 X-EXCLAIMER-MD-CONFIG: e1e8a2fd-e40a-4ac6-ac9b-f7e9cc9ee180 Sender: linux-omap-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-omap@vger.kernel.org Add new binding for OMAP PRM (Power and Reset Manager) instances. Each of these will act as a power domain controller and potentially as a reset provider. Signed-off-by: Tero Kristo --- .../devicetree/bindings/arm/omap/prm-inst.txt | 31 +++++++++++++++++++ 1 file changed, 31 insertions(+) create mode 100644 Documentation/devicetree/bindings/arm/omap/prm-inst.txt diff --git a/Documentation/devicetree/bindings/arm/omap/prm-inst.txt b/Documentation/devicetree/bindings/arm/omap/prm-inst.txt new file mode 100644 index 000000000000..7c7527c37734 --- /dev/null +++ b/Documentation/devicetree/bindings/arm/omap/prm-inst.txt @@ -0,0 +1,31 @@ +OMAP PRM instance bindings + +Power and Reset Manager is an IP block on OMAP family of devices which +handle the power domains and their current state, and provide reset +handling for the domains and/or separate IP blocks under the power domain +hierarchy. + +Required properties: +- compatible: Must be one of: + "ti,am3-prm-inst" + "ti,am4-prm-inst" + "ti,omap4-prm-inst" + "ti,omap5-prm-inst" + "ti,dra7-prm-inst" +- reg: Contains PRM instance register address range + (base address and length) + +Optional properties: +- #reset-cells: Should be 1 if the PRM instance in question supports resets. +- clocks: Associated clocks for the reset signals if any. Certain reset + signals can't be toggled properly without functional clock + being active for them. + +Example: + +prm_dsp2: prm@1b00 { + compatible = "ti,dra7-prm-inst"; + reg = <0x1b00 0x40>; + #reset-cells = <1>; + clocks = <&dsp2_clkctrl DRA7_DSP2_MMU0_DSP2_CLKCTRL 0>; +}; From patchwork Wed Aug 28 07:19:32 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Tero Kristo X-Patchwork-Id: 11117953 Return-Path: Received: from mail.kernel.org (pdx-korg-mail-1.web.codeaurora.org [172.30.200.123]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id 588A514F7 for ; Wed, 28 Aug 2019 07:20:08 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.kernel.org (Postfix) with ESMTP id 3053222DA7 for ; Wed, 28 Aug 2019 07:20:08 +0000 (UTC) Authentication-Results: mail.kernel.org; dkim=pass (1024-bit key) header.d=ti.com header.i=@ti.com header.b="Ejjw0t3X" Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1726440AbfH1HUH (ORCPT ); Wed, 28 Aug 2019 03:20:07 -0400 Received: from lelv0143.ext.ti.com ([198.47.23.248]:59400 "EHLO lelv0143.ext.ti.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1726253AbfH1HUH (ORCPT ); Wed, 28 Aug 2019 03:20:07 -0400 Received: from fllv0035.itg.ti.com ([10.64.41.0]) by lelv0143.ext.ti.com (8.15.2/8.15.2) with ESMTP id x7S7JtKI116086; Wed, 28 Aug 2019 02:19:55 -0500 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=ti.com; s=ti-com-17Q1; t=1566976795; bh=fikmTZhZFrmAeiEznJxUUl2+wbhEDuDam0XUgWBgSxU=; h=From:To:CC:Subject:Date:In-Reply-To:References; b=Ejjw0t3XXbrKB/2FYpxB1drS8a8VN6CcHq/pI695lEN2Whj7yozw4hJ2qADywJyOM rE2rXxk1PSEPPImbX1Hswf1ee5av0JASrDxwkeUotckaVJgjUQjn7q73inx3IPSLZr W1zlkHkGHyvqGJ116RJtJes+Rj7dO7qgwnsYB2jY= Received: from DFLE111.ent.ti.com (dfle111.ent.ti.com [10.64.6.32]) by fllv0035.itg.ti.com (8.15.2/8.15.2) with ESMTPS id x7S7JtRm078024 (version=TLSv1.2 cipher=AES256-GCM-SHA384 bits=256 verify=FAIL); Wed, 28 Aug 2019 02:19:55 -0500 Received: from DFLE107.ent.ti.com (10.64.6.28) by DFLE111.ent.ti.com (10.64.6.32) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.1713.5; Wed, 28 Aug 2019 02:19:55 -0500 Received: from lelv0327.itg.ti.com (10.180.67.183) by DFLE107.ent.ti.com (10.64.6.28) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.1713.5 via Frontend Transport; Wed, 28 Aug 2019 02:19:55 -0500 Received: from sokoban.bb.dnainternet.fi (ileax41-snat.itg.ti.com [10.172.224.153]) by lelv0327.itg.ti.com (8.15.2/8.15.2) with ESMTP id x7S7JmfE052201; Wed, 28 Aug 2019 02:19:53 -0500 From: Tero Kristo To: , , , , CC: , , Subject: [PATCHv2 02/11] soc: ti: add initial PRM driver with reset control support Date: Wed, 28 Aug 2019 10:19:32 +0300 Message-ID: <20190828071941.32378-3-t-kristo@ti.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20190828071941.32378-1-t-kristo@ti.com> References: <20190828071941.32378-1-t-kristo@ti.com> MIME-Version: 1.0 X-EXCLAIMER-MD-CONFIG: e1e8a2fd-e40a-4ac6-ac9b-f7e9cc9ee180 Sender: linux-omap-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-omap@vger.kernel.org Add initial PRM (Power and Reset Management) driver for TI OMAP class SoCs. Initially this driver only supports reset control, but can be extended to support rest of the functionality, like powerdomain control, PRCM irq support etc. Signed-off-by: Tero Kristo --- arch/arm/mach-omap2/Kconfig | 1 + drivers/soc/ti/Makefile | 1 + drivers/soc/ti/omap_prm.c | 235 ++++++++++++++++++++++++++++++++++++ 3 files changed, 237 insertions(+) create mode 100644 drivers/soc/ti/omap_prm.c diff --git a/arch/arm/mach-omap2/Kconfig b/arch/arm/mach-omap2/Kconfig index fdb6743760a2..ad08d470a2ca 100644 --- a/arch/arm/mach-omap2/Kconfig +++ b/arch/arm/mach-omap2/Kconfig @@ -109,6 +109,7 @@ config ARCH_OMAP2PLUS select TI_SYSC select OMAP_IRQCHIP select CLKSRC_TI_32K + select ARCH_HAS_RESET_CONTROLLER help Systems based on OMAP2, OMAP3, OMAP4 or OMAP5 diff --git a/drivers/soc/ti/Makefile b/drivers/soc/ti/Makefile index b3868d392d4f..788b5cd1e180 100644 --- a/drivers/soc/ti/Makefile +++ b/drivers/soc/ti/Makefile @@ -6,6 +6,7 @@ obj-$(CONFIG_KEYSTONE_NAVIGATOR_QMSS) += knav_qmss.o knav_qmss-y := knav_qmss_queue.o knav_qmss_acc.o obj-$(CONFIG_KEYSTONE_NAVIGATOR_DMA) += knav_dma.o obj-$(CONFIG_AMX3_PM) += pm33xx.o +obj-$(CONFIG_ARCH_OMAP2PLUS) += omap_prm.o obj-$(CONFIG_WKUP_M3_IPC) += wkup_m3_ipc.o obj-$(CONFIG_TI_SCI_PM_DOMAINS) += ti_sci_pm_domains.o obj-$(CONFIG_TI_SCI_INTA_MSI_DOMAIN) += ti_sci_inta_msi.o diff --git a/drivers/soc/ti/omap_prm.c b/drivers/soc/ti/omap_prm.c new file mode 100644 index 000000000000..fd5c431f8736 --- /dev/null +++ b/drivers/soc/ti/omap_prm.c @@ -0,0 +1,235 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * OMAP2+ PRM driver + * + * Copyright (C) 2019 Texas Instruments Incorporated - http://www.ti.com/ + * Tero Kristo + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include + +struct omap_rst_map { + s8 rst; + s8 st; +}; + +struct omap_prm_data { + u32 base; + const char *name; + u16 rstctrl; + u16 rstst; + const struct omap_rst_map *rstmap; + u8 flags; +}; + +struct omap_prm { + const struct omap_prm_data *data; + void __iomem *base; +}; + +struct omap_reset_data { + struct reset_controller_dev rcdev; + struct omap_prm *prm; +}; + +#define to_omap_reset_data(p) container_of((p), struct omap_reset_data, rcdev) + +#define OMAP_MAX_RESETS 8 +#define OMAP_RESET_MAX_WAIT 10000 + +#define OMAP_PRM_HAS_RSTCTRL BIT(0) +#define OMAP_PRM_HAS_RSTST BIT(1) + +#define OMAP_PRM_HAS_RESETS (OMAP_PRM_HAS_RSTCTRL | OMAP_PRM_HAS_RSTST) + +static const struct of_device_id omap_prm_id_table[] = { + { }, +}; + +static bool _is_valid_reset(struct omap_reset_data *reset, unsigned long id) +{ + const struct omap_rst_map *map = reset->prm->data->rstmap; + + while (map && map->rst >= 0) { + if (map->rst == id) + return true; + map++; + } + + return false; +} + +static int omap_reset_status(struct reset_controller_dev *rcdev, + unsigned long id) +{ + struct omap_reset_data *reset = to_omap_reset_data(rcdev); + u32 v; + + if (!_is_valid_reset(reset, id)) + return -EINVAL; + + v = readl_relaxed(reset->prm->base + reset->prm->data->rstst); + v &= 1 << id; + v >>= id; + + return v; +} + +static int omap_reset_assert(struct reset_controller_dev *rcdev, + unsigned long id) +{ + struct omap_reset_data *reset = to_omap_reset_data(rcdev); + u32 v; + + if (!_is_valid_reset(reset, id)) + return -EINVAL; + + /* assert the reset control line */ + v = readl_relaxed(reset->prm->base + reset->prm->data->rstctrl); + v |= 1 << id; + writel_relaxed(v, reset->prm->base + reset->prm->data->rstctrl); + + return 0; +} + +static int omap_reset_get_st_bit(struct omap_reset_data *reset, + unsigned long id) +{ + const struct omap_rst_map *map = reset->prm->data->rstmap; + + while (map && map->rst >= 0) { + if (map->rst == id) + return map->st; + + map++; + } + + return id; +} + +/* + * Note that status will not change until clocks are on, and clocks cannot be + * enabled until reset is deasserted. Consumer drivers must check status + * separately after enabling clocks. + */ +static int omap_reset_deassert(struct reset_controller_dev *rcdev, + unsigned long id) +{ + struct omap_reset_data *reset = to_omap_reset_data(rcdev); + u32 v; + int st_bit; + bool has_rstst; + + if (!_is_valid_reset(reset, id)) + return -EINVAL; + + /* check the current status to avoid de-asserting the line twice */ + v = readl_relaxed(reset->prm->base + reset->prm->data->rstctrl); + if (!(v & BIT(id))) + return -EEXIST; + + has_rstst = reset->prm->data->rstst || + (reset->prm->data->flags & OMAP_PRM_HAS_RSTST); + + if (has_rstst) { + st_bit = omap_reset_get_st_bit(reset, id); + + /* Clear the reset status by writing 1 to the status bit */ + v = readl_relaxed(reset->prm->base + reset->prm->data->rstst); + v |= 1 << st_bit; + writel_relaxed(v, reset->prm->base + reset->prm->data->rstst); + } + + /* de-assert the reset control line */ + v = readl_relaxed(reset->prm->base + reset->prm->data->rstctrl); + v &= ~(1 << id); + writel_relaxed(v, reset->prm->base + reset->prm->data->rstctrl); + + return 0; +} + +static const struct reset_control_ops omap_reset_ops = { + .assert = omap_reset_assert, + .deassert = omap_reset_deassert, + .status = omap_reset_status, +}; + +static int omap_prm_reset_init(struct platform_device *pdev, + struct omap_prm *prm) +{ + struct omap_reset_data *reset; + + /* + * Check if we have controllable resets. If either rstctrl is non-zero + * or OMAP_PRM_HAS_RSTCTRL flag is set, we have reset control register + * for the domain. + */ + if (!prm->data->rstctrl && !(prm->data->flags & OMAP_PRM_HAS_RSTCTRL)) + return 0; + + reset = devm_kzalloc(&pdev->dev, sizeof(*reset), GFP_KERNEL); + if (!reset) + return -ENOMEM; + + reset->rcdev.owner = THIS_MODULE; + reset->rcdev.ops = &omap_reset_ops; + reset->rcdev.of_node = pdev->dev.of_node; + reset->rcdev.nr_resets = OMAP_MAX_RESETS; + + reset->prm = prm; + + return devm_reset_controller_register(&pdev->dev, &reset->rcdev); +} + +static int omap_prm_probe(struct platform_device *pdev) +{ + struct resource *res; + const struct omap_prm_data *data; + struct omap_prm *prm; + const struct of_device_id *match; + + res = platform_get_resource(pdev, IORESOURCE_MEM, 0); + if (!res) + return -ENODEV; + + match = of_match_device(omap_prm_id_table, &pdev->dev); + if (!match) + return -ENOTSUPP; + + prm = devm_kzalloc(&pdev->dev, sizeof(*prm), GFP_KERNEL); + if (!prm) + return -ENOMEM; + + data = match->data; + + while (data->base != res->start) { + if (!data->base) + return -EINVAL; + data++; + } + + prm->data = data; + + prm->base = devm_ioremap_resource(&pdev->dev, res); + if (!prm->base) + return -ENOMEM; + + return omap_prm_reset_init(pdev, prm); +} + +static struct platform_driver omap_prm_driver = { + .probe = omap_prm_probe, + .driver = { + .name = KBUILD_MODNAME, + .of_match_table = omap_prm_id_table, + }, +}; +builtin_platform_driver(omap_prm_driver); From patchwork Wed Aug 28 07:19:33 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Tero Kristo X-Patchwork-Id: 11117951 Return-Path: Received: from mail.kernel.org (pdx-korg-mail-1.web.codeaurora.org [172.30.200.123]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id 8568014F7 for ; Wed, 28 Aug 2019 07:20:07 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.kernel.org (Postfix) with ESMTP id 62AF922DA7 for ; Wed, 28 Aug 2019 07:20:07 +0000 (UTC) Authentication-Results: mail.kernel.org; dkim=pass (1024-bit key) header.d=ti.com header.i=@ti.com header.b="sE5yNRtk" Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1726408AbfH1HUG (ORCPT ); Wed, 28 Aug 2019 03:20:06 -0400 Received: from lelv0143.ext.ti.com ([198.47.23.248]:59396 "EHLO lelv0143.ext.ti.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1726252AbfH1HUG (ORCPT ); Wed, 28 Aug 2019 03:20:06 -0400 Received: from fllv0035.itg.ti.com ([10.64.41.0]) by lelv0143.ext.ti.com (8.15.2/8.15.2) with ESMTP id x7S7JxAl116149; Wed, 28 Aug 2019 02:19:59 -0500 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=ti.com; s=ti-com-17Q1; t=1566976799; bh=lun/IihhVZD0SSuBuE72idtwD4SSrSW8blVhgZgqk2U=; h=From:To:CC:Subject:Date:In-Reply-To:References; b=sE5yNRtkvGyAPqmNv20ep8YkcF+5JLPMY4UC7vGG9gyEVOtYrxe3ZN0AU5DmyGY6/ jqSEMF1M0TASDP6kp4ALgZV6Ov++akIxnWCuuC/MoHaIBbxQ1iqskeaJUYqHoHP9VC XtWuhxZg1vfdeNP0W+tjXKfRDMKSUHBgzvKNoTRg= Received: from DLEE110.ent.ti.com (dlee110.ent.ti.com [157.170.170.21]) by fllv0035.itg.ti.com (8.15.2/8.15.2) with ESMTPS id x7S7Jxsw078153 (version=TLSv1.2 cipher=AES256-GCM-SHA384 bits=256 verify=FAIL); Wed, 28 Aug 2019 02:19:59 -0500 Received: from DLEE113.ent.ti.com (157.170.170.24) by DLEE110.ent.ti.com (157.170.170.21) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.1713.5; Wed, 28 Aug 2019 02:19:57 -0500 Received: from lelv0327.itg.ti.com (10.180.67.183) by DLEE113.ent.ti.com (157.170.170.24) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.1713.5 via Frontend Transport; Wed, 28 Aug 2019 02:19:57 -0500 Received: from sokoban.bb.dnainternet.fi (ileax41-snat.itg.ti.com [10.172.224.153]) by lelv0327.itg.ti.com (8.15.2/8.15.2) with ESMTP id x7S7JmfF052201; Wed, 28 Aug 2019 02:19:55 -0500 From: Tero Kristo To: , , , , CC: , , Subject: [PATCHv2 03/11] soc: ti: omap-prm: poll for reset complete during de-assert Date: Wed, 28 Aug 2019 10:19:33 +0300 Message-ID: <20190828071941.32378-4-t-kristo@ti.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20190828071941.32378-1-t-kristo@ti.com> References: <20190828071941.32378-1-t-kristo@ti.com> MIME-Version: 1.0 X-EXCLAIMER-MD-CONFIG: e1e8a2fd-e40a-4ac6-ac9b-f7e9cc9ee180 Sender: linux-omap-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-omap@vger.kernel.org Poll for reset completion status during de-assertion of reset, otherwise the IP in question might be accessed before it has left reset properly. Signed-off-by: Tero Kristo --- drivers/soc/ti/omap_prm.c | 20 ++++++++++++++++++++ 1 file changed, 20 insertions(+) diff --git a/drivers/soc/ti/omap_prm.c b/drivers/soc/ti/omap_prm.c index fd5c431f8736..afeb70761b27 100644 --- a/drivers/soc/ti/omap_prm.c +++ b/drivers/soc/ti/omap_prm.c @@ -127,6 +127,7 @@ static int omap_reset_deassert(struct reset_controller_dev *rcdev, u32 v; int st_bit; bool has_rstst; + int timeout = 0; if (!_is_valid_reset(reset, id)) return -EINVAL; @@ -153,6 +154,25 @@ static int omap_reset_deassert(struct reset_controller_dev *rcdev, v &= ~(1 << id); writel_relaxed(v, reset->prm->base + reset->prm->data->rstctrl); + if (!has_rstst) + return 0; + + /* wait for the status to be set */ + while (1) { + v = readl_relaxed(reset->prm->base + reset->prm->data->rstst); + v &= 1 << st_bit; + if (v) + break; + timeout++; + if (timeout > OMAP_RESET_MAX_WAIT) { + pr_err("%s: timedout waiting for %s:%lu\n", __func__, + dev_name(rcdev->dev), id); + return -EBUSY; + } + + udelay(1); + } + return 0; } From patchwork Wed Aug 28 07:19:34 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Tero Kristo X-Patchwork-Id: 11117955 Return-Path: Received: from mail.kernel.org (pdx-korg-mail-1.web.codeaurora.org [172.30.200.123]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id 340FE184E for ; Wed, 28 Aug 2019 07:20:09 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.kernel.org (Postfix) with ESMTP id 14C79217F5 for ; Wed, 28 Aug 2019 07:20:09 +0000 (UTC) Authentication-Results: mail.kernel.org; dkim=pass (1024-bit key) header.d=ti.com header.i=@ti.com header.b="TKgJcyum" Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1726253AbfH1HUI (ORCPT ); Wed, 28 Aug 2019 03:20:08 -0400 Received: from fllv0016.ext.ti.com ([198.47.19.142]:52982 "EHLO fllv0016.ext.ti.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1726252AbfH1HUI (ORCPT ); Wed, 28 Aug 2019 03:20:08 -0400 Received: from lelv0266.itg.ti.com ([10.180.67.225]) by fllv0016.ext.ti.com (8.15.2/8.15.2) with ESMTP id x7S7Jxwa112292; Wed, 28 Aug 2019 02:19:59 -0500 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=ti.com; s=ti-com-17Q1; t=1566976799; bh=MaJKqEmPi2ARgN2dmtUrxd+FuRc6LkB83YP9HuVdTr8=; h=From:To:CC:Subject:Date:In-Reply-To:References; b=TKgJcyumN+Uh48ci5bfK/qWgiynhCaRHxNXvrefoTDyGRNN4Bp01ddpml62kxyZFt 6ycXiTl9BSFNjZSdAHx/W/o6kAYn7EkAFJdrOp9zbUfgNbxqIK83qWT2cO+O7KLeM0 D7+sn99CefCR7PoeW19GC2oD6bOz8zfvSBNpqHDY= Received: from DLEE113.ent.ti.com (dlee113.ent.ti.com [157.170.170.24]) by lelv0266.itg.ti.com (8.15.2/8.15.2) with ESMTPS id x7S7Jxoe082890 (version=TLSv1.2 cipher=AES256-GCM-SHA384 bits=256 verify=FAIL); Wed, 28 Aug 2019 02:19:59 -0500 Received: from DLEE106.ent.ti.com (157.170.170.36) by DLEE113.ent.ti.com (157.170.170.24) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.1713.5; Wed, 28 Aug 2019 02:19:59 -0500 Received: from lelv0327.itg.ti.com (10.180.67.183) by DLEE106.ent.ti.com (157.170.170.36) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.1713.5 via Frontend Transport; Wed, 28 Aug 2019 02:19:59 -0500 Received: from sokoban.bb.dnainternet.fi (ileax41-snat.itg.ti.com [10.172.224.153]) by lelv0327.itg.ti.com (8.15.2/8.15.2) with ESMTP id x7S7JmfG052201; Wed, 28 Aug 2019 02:19:57 -0500 From: Tero Kristo To: , , , , CC: , , Subject: [PATCHv2 04/11] soc: ti: omap-prm: add support for denying idle for reset clockdomain Date: Wed, 28 Aug 2019 10:19:34 +0300 Message-ID: <20190828071941.32378-5-t-kristo@ti.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20190828071941.32378-1-t-kristo@ti.com> References: <20190828071941.32378-1-t-kristo@ti.com> MIME-Version: 1.0 X-EXCLAIMER-MD-CONFIG: e1e8a2fd-e40a-4ac6-ac9b-f7e9cc9ee180 Sender: linux-omap-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-omap@vger.kernel.org TI SoCs hardware reset signals require the parent clockdomain to be in force wakeup mode while de-asserting the reset, otherwise it may never complete. To support this, add pdata hooks to control the clockdomain directly. Signed-off-by: Tero Kristo --- drivers/soc/ti/omap_prm.c | 34 +++++++++++++++++++++++++--- include/linux/platform_data/ti-prm.h | 21 +++++++++++++++++ 2 files changed, 52 insertions(+), 3 deletions(-) create mode 100644 include/linux/platform_data/ti-prm.h diff --git a/drivers/soc/ti/omap_prm.c b/drivers/soc/ti/omap_prm.c index afeb70761b27..38998ce19c71 100644 --- a/drivers/soc/ti/omap_prm.c +++ b/drivers/soc/ti/omap_prm.c @@ -16,6 +16,8 @@ #include #include +#include + struct omap_rst_map { s8 rst; s8 st; @@ -24,6 +26,7 @@ struct omap_rst_map { struct omap_prm_data { u32 base; const char *name; + const char *clkdm_name; u16 rstctrl; u16 rstst; const struct omap_rst_map *rstmap; @@ -38,6 +41,8 @@ struct omap_prm { struct omap_reset_data { struct reset_controller_dev rcdev; struct omap_prm *prm; + struct clockdomain *clkdm; + struct device *dev; }; #define to_omap_reset_data(p) container_of((p), struct omap_reset_data, rcdev) @@ -128,6 +133,8 @@ static int omap_reset_deassert(struct reset_controller_dev *rcdev, int st_bit; bool has_rstst; int timeout = 0; + struct ti_prm_platform_data *pdata = dev_get_platdata(reset->dev); + int ret = 0; if (!_is_valid_reset(reset, id)) return -EINVAL; @@ -149,13 +156,15 @@ static int omap_reset_deassert(struct reset_controller_dev *rcdev, writel_relaxed(v, reset->prm->base + reset->prm->data->rstst); } + pdata->clkdm_deny_idle(reset->clkdm); + /* de-assert the reset control line */ v = readl_relaxed(reset->prm->base + reset->prm->data->rstctrl); v &= ~(1 << id); writel_relaxed(v, reset->prm->base + reset->prm->data->rstctrl); if (!has_rstst) - return 0; + goto exit; /* wait for the status to be set */ while (1) { @@ -167,13 +176,17 @@ static int omap_reset_deassert(struct reset_controller_dev *rcdev, if (timeout > OMAP_RESET_MAX_WAIT) { pr_err("%s: timedout waiting for %s:%lu\n", __func__, dev_name(rcdev->dev), id); - return -EBUSY; + ret = -EBUSY; + goto exit; } udelay(1); } - return 0; +exit: + pdata->clkdm_allow_idle(reset->clkdm); + + return ret; } static const struct reset_control_ops omap_reset_ops = { @@ -186,6 +199,8 @@ static int omap_prm_reset_init(struct platform_device *pdev, struct omap_prm *prm) { struct omap_reset_data *reset; + struct ti_prm_platform_data *pdata = dev_get_platdata(&pdev->dev); + char buf[32]; /* * Check if we have controllable resets. If either rstctrl is non-zero @@ -195,6 +210,11 @@ static int omap_prm_reset_init(struct platform_device *pdev, if (!prm->data->rstctrl && !(prm->data->flags & OMAP_PRM_HAS_RSTCTRL)) return 0; + /* Check if we have the pdata callbacks in place */ + if (!pdata->clkdm_lookup || !pdata->clkdm_deny_idle || + !pdata->clkdm_allow_idle) + return -EINVAL; + reset = devm_kzalloc(&pdev->dev, sizeof(*reset), GFP_KERNEL); if (!reset) return -ENOMEM; @@ -203,9 +223,17 @@ static int omap_prm_reset_init(struct platform_device *pdev, reset->rcdev.ops = &omap_reset_ops; reset->rcdev.of_node = pdev->dev.of_node; reset->rcdev.nr_resets = OMAP_MAX_RESETS; + reset->dev = &pdev->dev; reset->prm = prm; + sprintf(buf, "%s_clkdm", prm->data->clkdm_name ? prm->data->clkdm_name : + prm->data->name); + + reset->clkdm = pdata->clkdm_lookup(buf); + if (!reset->clkdm) + return -EINVAL; + return devm_reset_controller_register(&pdev->dev, &reset->rcdev); } diff --git a/include/linux/platform_data/ti-prm.h b/include/linux/platform_data/ti-prm.h new file mode 100644 index 000000000000..28154c3226c2 --- /dev/null +++ b/include/linux/platform_data/ti-prm.h @@ -0,0 +1,21 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* + * TI PRM (Power & Reset Manager) platform data + * + * Copyright (C) 2019 Texas Instruments, Inc. + * + * Tero Kristo + */ + +#ifndef _LINUX_PLATFORM_DATA_TI_PRM_H +#define _LINUX_PLATFORM_DATA_TI_PRM_H + +struct clockdomain; + +struct ti_prm_platform_data { + void (*clkdm_deny_idle)(struct clockdomain *clkdm); + void (*clkdm_allow_idle)(struct clockdomain *clkdm); + struct clockdomain * (*clkdm_lookup)(const char *name); +}; + +#endif /* _LINUX_PLATFORM_DATA_TI_PRM_H */ From patchwork Wed Aug 28 07:19:35 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Tero Kristo X-Patchwork-Id: 11117959 Return-Path: Received: from mail.kernel.org (pdx-korg-mail-1.web.codeaurora.org [172.30.200.123]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id 7F4C414F7 for ; Wed, 28 Aug 2019 07:20:10 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.kernel.org (Postfix) with ESMTP id 5F647217F5 for ; Wed, 28 Aug 2019 07:20:10 +0000 (UTC) Authentication-Results: mail.kernel.org; dkim=pass (1024-bit key) header.d=ti.com header.i=@ti.com header.b="pR+wdsTO" Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1726339AbfH1HUJ (ORCPT ); Wed, 28 Aug 2019 03:20:09 -0400 Received: from lelv0142.ext.ti.com ([198.47.23.249]:33462 "EHLO lelv0142.ext.ti.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1726252AbfH1HUJ (ORCPT ); Wed, 28 Aug 2019 03:20:09 -0400 Received: from lelv0265.itg.ti.com ([10.180.67.224]) by lelv0142.ext.ti.com (8.15.2/8.15.2) with ESMTP id x7S7K2Wd126743; Wed, 28 Aug 2019 02:20:02 -0500 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=ti.com; s=ti-com-17Q1; t=1566976802; bh=+t+/Qiw1iCU7XUNdlc5BaxCXhjDYvL050wWa31KgFc0=; h=From:To:CC:Subject:Date:In-Reply-To:References; b=pR+wdsTOST4GukDQCINVeAcrz2zTzejQrJd9AQ2G9iO5rwcQB2CFPxQ36jpiT+7WW zSOrf5v6nnoAKY3I7gmxI1cB3Z+ebhOTbDB/NHXRCXt1nxrsmSU/pVFsB0epeBHDk5 eRN2O4lil2W3s25+Z2pc9z5sxIm8LeJzidrvWpZY= Received: from DLEE114.ent.ti.com (dlee114.ent.ti.com [157.170.170.25]) by lelv0265.itg.ti.com (8.15.2/8.15.2) with ESMTPS id x7S7K1ch081901 (version=TLSv1.2 cipher=AES256-GCM-SHA384 bits=256 verify=FAIL); Wed, 28 Aug 2019 02:20:02 -0500 Received: from DLEE104.ent.ti.com (157.170.170.34) by DLEE114.ent.ti.com (157.170.170.25) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.1713.5; Wed, 28 Aug 2019 02:20:01 -0500 Received: from lelv0327.itg.ti.com (10.180.67.183) by DLEE104.ent.ti.com (157.170.170.34) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.1713.5 via Frontend Transport; Wed, 28 Aug 2019 02:20:01 -0500 Received: from sokoban.bb.dnainternet.fi (ileax41-snat.itg.ti.com [10.172.224.153]) by lelv0327.itg.ti.com (8.15.2/8.15.2) with ESMTP id x7S7JmfH052201; Wed, 28 Aug 2019 02:19:59 -0500 From: Tero Kristo To: , , , , CC: , , Subject: [PATCHv2 05/11] soc: ti: omap-prm: sync func clock status with resets Date: Wed, 28 Aug 2019 10:19:35 +0300 Message-ID: <20190828071941.32378-6-t-kristo@ti.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20190828071941.32378-1-t-kristo@ti.com> References: <20190828071941.32378-1-t-kristo@ti.com> MIME-Version: 1.0 X-EXCLAIMER-MD-CONFIG: e1e8a2fd-e40a-4ac6-ac9b-f7e9cc9ee180 Sender: linux-omap-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-omap@vger.kernel.org Hardware reset signals are tightly coupled with associated clocks, and basically de-asserting a reset won't succeed properly if the clock is not enabled, and vice-versa. Also, disabling a clock won't fully succeed if the associated hardware resets are not asserted. Add status sync functionality between these two for TI drivers so that the situations can be handled properly without generating any timeouts. Signed-off-by: Tero Kristo --- drivers/soc/ti/omap_prm.c | 36 ++++++++++++++++++++++++++++++++++++ 1 file changed, 36 insertions(+) diff --git a/drivers/soc/ti/omap_prm.c b/drivers/soc/ti/omap_prm.c index 38998ce19c71..e876bad8f8d5 100644 --- a/drivers/soc/ti/omap_prm.c +++ b/drivers/soc/ti/omap_prm.c @@ -15,6 +15,8 @@ #include #include #include +#include +#include #include @@ -42,7 +44,9 @@ struct omap_reset_data { struct reset_controller_dev rcdev; struct omap_prm *prm; struct clockdomain *clkdm; + struct clk *clk; struct device *dev; + u32 mask; }; #define to_omap_reset_data(p) container_of((p), struct omap_reset_data, rcdev) @@ -102,6 +106,8 @@ static int omap_reset_assert(struct reset_controller_dev *rcdev, v |= 1 << id; writel_relaxed(v, reset->prm->base + reset->prm->data->rstctrl); + ti_clk_notify_resets(reset->clk, v == reset->mask); + return 0; } @@ -163,9 +169,19 @@ static int omap_reset_deassert(struct reset_controller_dev *rcdev, v &= ~(1 << id); writel_relaxed(v, reset->prm->base + reset->prm->data->rstctrl); + ti_clk_notify_resets(reset->clk, v == reset->mask); + if (!has_rstst) goto exit; + /* If associated clock is disabled, we can't poll completion status */ + if (reset->clk) { + struct clk_hw *hw = __clk_get_hw(reset->clk); + + if (!clk_hw_is_enabled(hw)) + return ret; + } + /* wait for the status to be set */ while (1) { v = readl_relaxed(reset->prm->base + reset->prm->data->rstst); @@ -199,8 +215,10 @@ static int omap_prm_reset_init(struct platform_device *pdev, struct omap_prm *prm) { struct omap_reset_data *reset; + const struct omap_rst_map *map; struct ti_prm_platform_data *pdata = dev_get_platdata(&pdev->dev); char buf[32]; + u32 v; /* * Check if we have controllable resets. If either rstctrl is non-zero @@ -215,6 +233,10 @@ static int omap_prm_reset_init(struct platform_device *pdev, !pdata->clkdm_allow_idle) return -EINVAL; + map = prm->data->rstmap; + if (!map) + return -EINVAL; + reset = devm_kzalloc(&pdev->dev, sizeof(*reset), GFP_KERNEL); if (!reset) return -ENOMEM; @@ -224,6 +246,10 @@ static int omap_prm_reset_init(struct platform_device *pdev, reset->rcdev.of_node = pdev->dev.of_node; reset->rcdev.nr_resets = OMAP_MAX_RESETS; reset->dev = &pdev->dev; + reset->clk = of_clk_get(pdev->dev.of_node, 0); + + if (IS_ERR(reset->clk)) + reset->clk = NULL; reset->prm = prm; @@ -234,6 +260,16 @@ static int omap_prm_reset_init(struct platform_device *pdev, if (!reset->clkdm) return -EINVAL; + while (map->rst >= 0) { + reset->mask |= BIT(map->rst); + map++; + } + + if (reset->clk) { + v = readl_relaxed(reset->prm->base + reset->prm->data->rstctrl); + ti_clk_notify_resets(reset->clk, v == reset->mask); + } + return devm_reset_controller_register(&pdev->dev, &reset->rcdev); } From patchwork Wed Aug 28 07:19:36 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Tero Kristo X-Patchwork-Id: 11117961 Return-Path: Received: from mail.kernel.org (pdx-korg-mail-1.web.codeaurora.org [172.30.200.123]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id 1DBE814F7 for ; Wed, 28 Aug 2019 07:20:12 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.kernel.org (Postfix) with ESMTP id F233F22CF8 for ; Wed, 28 Aug 2019 07:20:11 +0000 (UTC) Authentication-Results: mail.kernel.org; dkim=pass (1024-bit key) header.d=ti.com header.i=@ti.com header.b="CQcK8JDZ" Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1726399AbfH1HUL (ORCPT ); Wed, 28 Aug 2019 03:20:11 -0400 Received: from lelv0143.ext.ti.com ([198.47.23.248]:59428 "EHLO lelv0143.ext.ti.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1726252AbfH1HUL (ORCPT ); Wed, 28 Aug 2019 03:20:11 -0400 Received: from lelv0266.itg.ti.com ([10.180.67.225]) by lelv0143.ext.ti.com (8.15.2/8.15.2) with ESMTP id x7S7K4O5116190; Wed, 28 Aug 2019 02:20:04 -0500 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=ti.com; s=ti-com-17Q1; t=1566976804; bh=haaNeLbrXohBveS7uejJKhMKitMSpHxT1HJ3TV94XO8=; h=From:To:CC:Subject:Date:In-Reply-To:References; b=CQcK8JDZ6gfr2c/MsWlW0toLXL7U/02zMv/yE2ceznAc9siz99nvKNv2Fcgx13/KJ IWBW2T4ZbqMGXoi1FoZQdglad/a3JfpYt59GBb9ri0Ipao9txqjd0WTnkHyEc5MZ+O 9qfgN33QDGOYISMn9WZcWsV4OZhAXfW7ULA43//A= Received: from DLEE110.ent.ti.com (dlee110.ent.ti.com [157.170.170.21]) by lelv0266.itg.ti.com (8.15.2/8.15.2) with ESMTPS id x7S7K4VK083176 (version=TLSv1.2 cipher=AES256-GCM-SHA384 bits=256 verify=FAIL); Wed, 28 Aug 2019 02:20:04 -0500 Received: from DLEE100.ent.ti.com (157.170.170.30) by DLEE110.ent.ti.com (157.170.170.21) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.1713.5; Wed, 28 Aug 2019 02:20:04 -0500 Received: from lelv0327.itg.ti.com (10.180.67.183) by DLEE100.ent.ti.com (157.170.170.30) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.1713.5 via Frontend Transport; Wed, 28 Aug 2019 02:20:03 -0500 Received: from sokoban.bb.dnainternet.fi (ileax41-snat.itg.ti.com [10.172.224.153]) by lelv0327.itg.ti.com (8.15.2/8.15.2) with ESMTP id x7S7JmfI052201; Wed, 28 Aug 2019 02:20:02 -0500 From: Tero Kristo To: , , , , CC: , , Subject: [PATCHv2 06/11] soc: ti: omap-prm: support resets with no associated clockdomain Date: Wed, 28 Aug 2019 10:19:36 +0300 Message-ID: <20190828071941.32378-7-t-kristo@ti.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20190828071941.32378-1-t-kristo@ti.com> References: <20190828071941.32378-1-t-kristo@ti.com> MIME-Version: 1.0 X-EXCLAIMER-MD-CONFIG: e1e8a2fd-e40a-4ac6-ac9b-f7e9cc9ee180 Sender: linux-omap-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-omap@vger.kernel.org Typically hardware resets on TI SoCs are associated with a clockdomain which must be forced to be active while the reset is being de-asserted. Otherwise the reset may not de-assert properly leaving the IP in some weird metastate. However, some hardware reset lines don't have this association in place, so add support for a new PRM flag for this purpose. Signed-off-by: Tero Kristo --- drivers/soc/ti/omap_prm.c | 17 +++++++++++------ 1 file changed, 11 insertions(+), 6 deletions(-) diff --git a/drivers/soc/ti/omap_prm.c b/drivers/soc/ti/omap_prm.c index e876bad8f8d5..d7a29e282788 100644 --- a/drivers/soc/ti/omap_prm.c +++ b/drivers/soc/ti/omap_prm.c @@ -56,6 +56,7 @@ struct omap_reset_data { #define OMAP_PRM_HAS_RSTCTRL BIT(0) #define OMAP_PRM_HAS_RSTST BIT(1) +#define OMAP_PRM_HAS_NO_CLKDM BIT(2) #define OMAP_PRM_HAS_RESETS (OMAP_PRM_HAS_RSTCTRL | OMAP_PRM_HAS_RSTST) @@ -162,7 +163,8 @@ static int omap_reset_deassert(struct reset_controller_dev *rcdev, writel_relaxed(v, reset->prm->base + reset->prm->data->rstst); } - pdata->clkdm_deny_idle(reset->clkdm); + if (reset->clkdm) + pdata->clkdm_deny_idle(reset->clkdm); /* de-assert the reset control line */ v = readl_relaxed(reset->prm->base + reset->prm->data->rstctrl); @@ -200,7 +202,8 @@ static int omap_reset_deassert(struct reset_controller_dev *rcdev, } exit: - pdata->clkdm_allow_idle(reset->clkdm); + if (reset->clkdm) + pdata->clkdm_allow_idle(reset->clkdm); return ret; } @@ -229,7 +232,7 @@ static int omap_prm_reset_init(struct platform_device *pdev, return 0; /* Check if we have the pdata callbacks in place */ - if (!pdata->clkdm_lookup || !pdata->clkdm_deny_idle || + if (!pdata || !pdata->clkdm_lookup || !pdata->clkdm_deny_idle || !pdata->clkdm_allow_idle) return -EINVAL; @@ -256,9 +259,11 @@ static int omap_prm_reset_init(struct platform_device *pdev, sprintf(buf, "%s_clkdm", prm->data->clkdm_name ? prm->data->clkdm_name : prm->data->name); - reset->clkdm = pdata->clkdm_lookup(buf); - if (!reset->clkdm) - return -EINVAL; + if (!(prm->data->flags & OMAP_PRM_HAS_NO_CLKDM)) { + reset->clkdm = pdata->clkdm_lookup(buf); + if (!reset->clkdm) + return -EINVAL; + } while (map->rst >= 0) { reset->mask |= BIT(map->rst); From patchwork Wed Aug 28 07:19:37 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Tero Kristo X-Patchwork-Id: 11117963 Return-Path: Received: from mail.kernel.org (pdx-korg-mail-1.web.codeaurora.org [172.30.200.123]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id B93A2184E for ; Wed, 28 Aug 2019 07:20:15 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.kernel.org (Postfix) with ESMTP id 99DDD22DA7 for ; Wed, 28 Aug 2019 07:20:15 +0000 (UTC) Authentication-Results: mail.kernel.org; dkim=pass (1024-bit key) header.d=ti.com header.i=@ti.com header.b="NwWwH8X6" Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1726396AbfH1HUP (ORCPT ); Wed, 28 Aug 2019 03:20:15 -0400 Received: from fllv0016.ext.ti.com ([198.47.19.142]:53012 "EHLO fllv0016.ext.ti.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1726252AbfH1HUO (ORCPT ); Wed, 28 Aug 2019 03:20:14 -0400 Received: from fllv0034.itg.ti.com ([10.64.40.246]) by fllv0016.ext.ti.com (8.15.2/8.15.2) with ESMTP id x7S7K7Fa112330; Wed, 28 Aug 2019 02:20:07 -0500 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=ti.com; s=ti-com-17Q1; t=1566976807; bh=H3gWYOUu1IxnMBzQnYaDY16nQ5OnXii/NZ37NGeparY=; h=From:To:CC:Subject:Date:In-Reply-To:References; b=NwWwH8X6fdafxhbYabOne0KA2m/hIeo08jmufbeZxc9MZf0QniL3ReGp36mbXZKKH 4tc+7aawy6sG8LaCTV+xXILmX7xkABmRbCXbsVVT2DmtUAF07EMd268QLoxFc2fDho Xd8ieKmjFnY1iKwJUlQrAFSBQ1k+R2Q2iSkYo/Mc= Received: from DLEE112.ent.ti.com (dlee112.ent.ti.com [157.170.170.23]) by fllv0034.itg.ti.com (8.15.2/8.15.2) with ESMTPS id x7S7K7Ow025590 (version=TLSv1.2 cipher=AES256-GCM-SHA384 bits=256 verify=FAIL); Wed, 28 Aug 2019 02:20:07 -0500 Received: from DLEE113.ent.ti.com (157.170.170.24) by DLEE112.ent.ti.com (157.170.170.23) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.1713.5; Wed, 28 Aug 2019 02:20:06 -0500 Received: from lelv0327.itg.ti.com (10.180.67.183) by DLEE113.ent.ti.com (157.170.170.24) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.1713.5 via Frontend Transport; Wed, 28 Aug 2019 02:20:05 -0500 Received: from sokoban.bb.dnainternet.fi (ileax41-snat.itg.ti.com [10.172.224.153]) by lelv0327.itg.ti.com (8.15.2/8.15.2) with ESMTP id x7S7JmfJ052201; Wed, 28 Aug 2019 02:20:04 -0500 From: Tero Kristo To: , , , , CC: , , Subject: [PATCHv2 07/11] soc: ti: omap-prm: add omap4 PRM data Date: Wed, 28 Aug 2019 10:19:37 +0300 Message-ID: <20190828071941.32378-8-t-kristo@ti.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20190828071941.32378-1-t-kristo@ti.com> References: <20190828071941.32378-1-t-kristo@ti.com> MIME-Version: 1.0 X-EXCLAIMER-MD-CONFIG: e1e8a2fd-e40a-4ac6-ac9b-f7e9cc9ee180 Sender: linux-omap-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-omap@vger.kernel.org Add PRM data for omap4 family of SoCs. Initially this is just used to provide reset support. Signed-off-by: Tero Kristo --- drivers/soc/ti/omap_prm.c | 22 ++++++++++++++++++++++ 1 file changed, 22 insertions(+) diff --git a/drivers/soc/ti/omap_prm.c b/drivers/soc/ti/omap_prm.c index d7a29e282788..192eeae67dfc 100644 --- a/drivers/soc/ti/omap_prm.c +++ b/drivers/soc/ti/omap_prm.c @@ -60,7 +60,29 @@ struct omap_reset_data { #define OMAP_PRM_HAS_RESETS (OMAP_PRM_HAS_RSTCTRL | OMAP_PRM_HAS_RSTST) +static const struct omap_rst_map rst_map_01[] = { + { .rst = 0, .st = 0 }, + { .rst = 1, .st = 1 }, + { .rst = -1 }, +}; + +static const struct omap_rst_map rst_map_012[] = { + { .rst = 0, .st = 0 }, + { .rst = 1, .st = 1 }, + { .rst = 2, .st = 2 }, + { .rst = -1 }, +}; + +static const struct omap_prm_data omap4_prm_data[] = { + { .name = "tesla", .base = 0x4a306400, .rstctrl = 0x10, .rstst = 0x14, .rstmap = rst_map_01 }, + { .name = "core", .base = 0x4a306700, .rstctrl = 0x210, .rstst = 0x214, .clkdm_name = "ducati", .rstmap = rst_map_012 }, + { .name = "ivahd", .base = 0x4a306f00, .rstctrl = 0x10, .rstst = 0x14, .rstmap = rst_map_012 }, + { .name = "device", .base = 0x4a307b00, .rstctrl = 0x0, .rstst = 0x4, .rstmap = rst_map_01, .flags = OMAP_PRM_HAS_RSTCTRL | OMAP_PRM_HAS_NO_CLKDM }, + { }, +}; + static const struct of_device_id omap_prm_id_table[] = { + { .compatible = "ti,omap4-prm-inst", .data = omap4_prm_data }, { }, }; From patchwork Wed Aug 28 07:19:38 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Tero Kristo X-Patchwork-Id: 11117965 Return-Path: Received: from mail.kernel.org (pdx-korg-mail-1.web.codeaurora.org [172.30.200.123]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id E4C38184E for ; Wed, 28 Aug 2019 07:20:16 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.kernel.org (Postfix) with ESMTP id C5D4C22CF8 for ; Wed, 28 Aug 2019 07:20:16 +0000 (UTC) Authentication-Results: mail.kernel.org; dkim=pass (1024-bit key) header.d=ti.com header.i=@ti.com header.b="UjZ65xWt" Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1726252AbfH1HUQ (ORCPT ); Wed, 28 Aug 2019 03:20:16 -0400 Received: from lelv0143.ext.ti.com ([198.47.23.248]:59438 "EHLO lelv0143.ext.ti.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1726449AbfH1HUQ (ORCPT ); Wed, 28 Aug 2019 03:20:16 -0400 Received: from fllv0035.itg.ti.com ([10.64.41.0]) by lelv0143.ext.ti.com (8.15.2/8.15.2) with ESMTP id x7S7K8fg116225; Wed, 28 Aug 2019 02:20:08 -0500 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=ti.com; s=ti-com-17Q1; t=1566976808; bh=YN1mTOuLTNP+kJXj7vQ1LNJarTAWZ6U/EhWx8gi2dsM=; h=From:To:CC:Subject:Date:In-Reply-To:References; b=UjZ65xWt6Rz98jas+kJDH3+GqkYlEf6G15KbGynvIwHo3Yjr+Sf5PGfHytlrTLD3M TDjxUbYtzSkc7Nm36CbGFiXnGm4WYJpT5L4Y8FYVynSqlga+oMjRPT3Yi9osmKHsby DB6hu7DFoSHOErn7hNlMsYoBeHbAYRaDkUDu/B4c= Received: from DLEE113.ent.ti.com (dlee113.ent.ti.com [157.170.170.24]) by fllv0035.itg.ti.com (8.15.2/8.15.2) with ESMTPS id x7S7K8Be078691 (version=TLSv1.2 cipher=AES256-GCM-SHA384 bits=256 verify=FAIL); Wed, 28 Aug 2019 02:20:08 -0500 Received: from DLEE106.ent.ti.com (157.170.170.36) by DLEE113.ent.ti.com (157.170.170.24) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.1713.5; Wed, 28 Aug 2019 02:20:08 -0500 Received: from lelv0327.itg.ti.com (10.180.67.183) by DLEE106.ent.ti.com (157.170.170.36) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.1713.5 via Frontend Transport; Wed, 28 Aug 2019 02:20:08 -0500 Received: from sokoban.bb.dnainternet.fi (ileax41-snat.itg.ti.com [10.172.224.153]) by lelv0327.itg.ti.com (8.15.2/8.15.2) with ESMTP id x7S7JmfK052201; Wed, 28 Aug 2019 02:20:06 -0500 From: Tero Kristo To: , , , , CC: , , Subject: [PATCHv2 08/11] soc: ti: omap-prm: add data for am33xx Date: Wed, 28 Aug 2019 10:19:38 +0300 Message-ID: <20190828071941.32378-9-t-kristo@ti.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20190828071941.32378-1-t-kristo@ti.com> References: <20190828071941.32378-1-t-kristo@ti.com> MIME-Version: 1.0 X-EXCLAIMER-MD-CONFIG: e1e8a2fd-e40a-4ac6-ac9b-f7e9cc9ee180 Sender: linux-omap-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-omap@vger.kernel.org Add PRM instance data for AM33xx SoC. Includes some basic register definitions and reset data for now. Signed-off-by: Tero Kristo --- drivers/soc/ti/omap_prm.c | 24 ++++++++++++++++++++++++ 1 file changed, 24 insertions(+) diff --git a/drivers/soc/ti/omap_prm.c b/drivers/soc/ti/omap_prm.c index 192eeae67dfc..c4b33214bce1 100644 --- a/drivers/soc/ti/omap_prm.c +++ b/drivers/soc/ti/omap_prm.c @@ -60,6 +60,11 @@ struct omap_reset_data { #define OMAP_PRM_HAS_RESETS (OMAP_PRM_HAS_RSTCTRL | OMAP_PRM_HAS_RSTST) +static const struct omap_rst_map rst_map_0[] = { + { .rst = 0, .st = 0 }, + { .rst = -1 }, +}; + static const struct omap_rst_map rst_map_01[] = { { .rst = 0, .st = 0 }, { .rst = 1, .st = 1 }, @@ -81,8 +86,27 @@ static const struct omap_prm_data omap4_prm_data[] = { { }, }; +static const struct omap_rst_map am3_per_rst_map[] = { + { .rst = 1 }, + { .rst = -1 }, +}; + +static const struct omap_rst_map am3_wkup_rst_map[] = { + { .rst = 3, .st = 5 }, + { .rst = -1 }, +}; + +static const struct omap_prm_data am3_prm_data[] = { + { .name = "per", .base = 0x44e00c00, .rstctrl = 0x0, .rstmap = am3_per_rst_map, .flags = OMAP_PRM_HAS_RSTCTRL, .clkdm_name = "pruss_ocp" }, + { .name = "wkup", .base = 0x44e00d00, .rstctrl = 0x0, .rstst = 0xc, .rstmap = am3_wkup_rst_map, .flags = OMAP_PRM_HAS_RSTCTRL | OMAP_PRM_HAS_NO_CLKDM }, + { .name = "device", .base = 0x44e00f00, .rstctrl = 0x0, .rstst = 0x8, .rstmap = rst_map_01, .flags = OMAP_PRM_HAS_RSTCTRL | OMAP_PRM_HAS_NO_CLKDM }, + { .name = "gfx", .base = 0x44e01100, .rstctrl = 0x4, .rstst = 0x14, .rstmap = rst_map_0, .clkdm_name = "gfx_l3" }, + { }, +}; + static const struct of_device_id omap_prm_id_table[] = { { .compatible = "ti,omap4-prm-inst", .data = omap4_prm_data }, + { .compatible = "ti,am3-prm-inst", .data = am3_prm_data }, { }, }; From patchwork Wed Aug 28 07:19:39 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Tero Kristo X-Patchwork-Id: 11117967 Return-Path: Received: from mail.kernel.org (pdx-korg-mail-1.web.codeaurora.org [172.30.200.123]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id A90D814F7 for ; Wed, 28 Aug 2019 07:20:18 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.kernel.org (Postfix) with ESMTP id 8947422CF8 for ; Wed, 28 Aug 2019 07:20:18 +0000 (UTC) Authentication-Results: mail.kernel.org; dkim=pass (1024-bit key) header.d=ti.com header.i=@ti.com header.b="aVC1ZoaB" Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1726449AbfH1HUS (ORCPT ); Wed, 28 Aug 2019 03:20:18 -0400 Received: from lelv0143.ext.ti.com ([198.47.23.248]:59446 "EHLO lelv0143.ext.ti.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1726328AbfH1HUS (ORCPT ); Wed, 28 Aug 2019 03:20:18 -0400 Received: from fllv0035.itg.ti.com ([10.64.41.0]) by lelv0143.ext.ti.com (8.15.2/8.15.2) with ESMTP id x7S7KAH2116241; Wed, 28 Aug 2019 02:20:10 -0500 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=ti.com; s=ti-com-17Q1; t=1566976810; bh=LG7XOMd3X8KORp948KL5SdMjDvzk087XF2Wob74XRRY=; h=From:To:CC:Subject:Date:In-Reply-To:References; b=aVC1ZoaByZga+guWqMWK7wAIJbW4CdYlXHR75pJwULA0VmUl+nJw6bb3JWTfmWX/D gWtFMDATQ7HzcMWDL1ZTWthsRnu58PKRLKtKNg25hk/YDilFpHGnttvPDLwktzg/0M 3byxO6ODIrC43EtuE/rkSVLnedBTZ9pNmhqEorQU= Received: from DFLE112.ent.ti.com (dfle112.ent.ti.com [10.64.6.33]) by fllv0035.itg.ti.com (8.15.2/8.15.2) with ESMTPS id x7S7KAje078708 (version=TLSv1.2 cipher=AES256-GCM-SHA384 bits=256 verify=FAIL); Wed, 28 Aug 2019 02:20:10 -0500 Received: from DFLE109.ent.ti.com (10.64.6.30) by DFLE112.ent.ti.com (10.64.6.33) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.1713.5; Wed, 28 Aug 2019 02:20:10 -0500 Received: from lelv0327.itg.ti.com (10.180.67.183) by DFLE109.ent.ti.com (10.64.6.30) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.1713.5 via Frontend Transport; Wed, 28 Aug 2019 02:20:10 -0500 Received: from sokoban.bb.dnainternet.fi (ileax41-snat.itg.ti.com [10.172.224.153]) by lelv0327.itg.ti.com (8.15.2/8.15.2) with ESMTP id x7S7JmfL052201; Wed, 28 Aug 2019 02:20:08 -0500 From: Tero Kristo To: , , , , CC: , , Subject: [PATCHv2 09/11] soc: ti: omap-prm: add dra7 PRM data Date: Wed, 28 Aug 2019 10:19:39 +0300 Message-ID: <20190828071941.32378-10-t-kristo@ti.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20190828071941.32378-1-t-kristo@ti.com> References: <20190828071941.32378-1-t-kristo@ti.com> MIME-Version: 1.0 X-EXCLAIMER-MD-CONFIG: e1e8a2fd-e40a-4ac6-ac9b-f7e9cc9ee180 Sender: linux-omap-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-omap@vger.kernel.org Add PRM instance data for dra7 family of SoCs. Initially this is just used to provide reset support. Signed-off-by: Tero Kristo --- drivers/soc/ti/omap_prm.c | 14 ++++++++++++++ 1 file changed, 14 insertions(+) diff --git a/drivers/soc/ti/omap_prm.c b/drivers/soc/ti/omap_prm.c index c4b33214bce1..a54c2e556b7a 100644 --- a/drivers/soc/ti/omap_prm.c +++ b/drivers/soc/ti/omap_prm.c @@ -86,6 +86,19 @@ static const struct omap_prm_data omap4_prm_data[] = { { }, }; +static const struct omap_prm_data dra7_prm_data[] = { + { .name = "dsp1", .base = 0x4ae06400, .rstctrl = 0x10, .rstst = 0x14, .rstmap = rst_map_01 }, + { .name = "ipu", .base = 0x4ae06500, .rstctrl = 0x10, .rstst = 0x14, .clkdm_name = "ipu1", .rstmap = rst_map_012 }, + { .name = "core", .base = 0x4ae06700, .rstctrl = 0x210, .rstst = 0x214, .clkdm_name = "ipu2", .rstmap = rst_map_012 }, + { .name = "iva", .base = 0x4ae06f00, .rstctrl = 0x10, .rstst = 0x14, .rstmap = rst_map_012 }, + { .name = "dsp2", .base = 0x4ae07b00, .rstctrl = 0x10, .rstst = 0x14, .rstmap = rst_map_01 }, + { .name = "eve1", .base = 0x4ae07b40, .rstctrl = 0x10, .rstst = 0x14, .rstmap = rst_map_01 }, + { .name = "eve2", .base = 0x4ae07b80, .rstctrl = 0x10, .rstst = 0x14, .rstmap = rst_map_01 }, + { .name = "eve3", .base = 0x4ae07bc0, .rstctrl = 0x10, .rstst = 0x14, .rstmap = rst_map_01 }, + { .name = "eve4", .base = 0x4ae07c00, .rstctrl = 0x10, .rstst = 0x14, .rstmap = rst_map_01 }, + { }, +}; + static const struct omap_rst_map am3_per_rst_map[] = { { .rst = 1 }, { .rst = -1 }, @@ -106,6 +119,7 @@ static const struct omap_prm_data am3_prm_data[] = { static const struct of_device_id omap_prm_id_table[] = { { .compatible = "ti,omap4-prm-inst", .data = omap4_prm_data }, + { .compatible = "ti,dra7-prm-inst", .data = dra7_prm_data }, { .compatible = "ti,am3-prm-inst", .data = am3_prm_data }, { }, }; From patchwork Wed Aug 28 07:19:40 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Tero Kristo X-Patchwork-Id: 11117969 Return-Path: Received: from mail.kernel.org (pdx-korg-mail-1.web.codeaurora.org [172.30.200.123]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id 61D27184E for ; Wed, 28 Aug 2019 07:20:20 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.kernel.org (Postfix) with ESMTP id 426E622CF8 for ; Wed, 28 Aug 2019 07:20:20 +0000 (UTC) Authentication-Results: mail.kernel.org; dkim=pass (1024-bit key) header.d=ti.com header.i=@ti.com header.b="K+ZnL1gI" Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1726455AbfH1HUT (ORCPT ); Wed, 28 Aug 2019 03:20:19 -0400 Received: from fllv0016.ext.ti.com ([198.47.19.142]:53020 "EHLO fllv0016.ext.ti.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1726328AbfH1HUT (ORCPT ); Wed, 28 Aug 2019 03:20:19 -0400 Received: from lelv0266.itg.ti.com ([10.180.67.225]) by fllv0016.ext.ti.com (8.15.2/8.15.2) with ESMTP id x7S7KC2Z112354; Wed, 28 Aug 2019 02:20:12 -0500 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=ti.com; s=ti-com-17Q1; t=1566976812; bh=afuz//7UnNzwVZVMwo/xYo1kuWhXq1NbpeAZpr9BBT0=; h=From:To:CC:Subject:Date:In-Reply-To:References; b=K+ZnL1gIFj9jeX5sHseRH7zdRdJETd2Tvrx12JwRcNd3MxajRRIN6pEoIENLvzfqq +iO+vUUdd7jIpZXNsM1+PGZpZ6J6FLgrXMBU2s2dyjHF68hs56h7bsfQQw7RFEWnCv n7WgqpXKsTlUUf+0WJ+gM1E8htrekrMKAcZHCnU4= Received: from DFLE114.ent.ti.com (dfle114.ent.ti.com [10.64.6.35]) by lelv0266.itg.ti.com (8.15.2/8.15.2) with ESMTPS id x7S7KCgi083430 (version=TLSv1.2 cipher=AES256-GCM-SHA384 bits=256 verify=FAIL); Wed, 28 Aug 2019 02:20:12 -0500 Received: from DFLE101.ent.ti.com (10.64.6.22) by DFLE114.ent.ti.com (10.64.6.35) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.1713.5; Wed, 28 Aug 2019 02:20:12 -0500 Received: from lelv0327.itg.ti.com (10.180.67.183) by DFLE101.ent.ti.com (10.64.6.22) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.1713.5 via Frontend Transport; Wed, 28 Aug 2019 02:20:12 -0500 Received: from sokoban.bb.dnainternet.fi (ileax41-snat.itg.ti.com [10.172.224.153]) by lelv0327.itg.ti.com (8.15.2/8.15.2) with ESMTP id x7S7JmfM052201; Wed, 28 Aug 2019 02:20:10 -0500 From: Tero Kristo To: , , , , CC: , , Subject: [PATCHv2 10/11] soc: ti: omap-prm: add am4 PRM data Date: Wed, 28 Aug 2019 10:19:40 +0300 Message-ID: <20190828071941.32378-11-t-kristo@ti.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20190828071941.32378-1-t-kristo@ti.com> References: <20190828071941.32378-1-t-kristo@ti.com> MIME-Version: 1.0 X-EXCLAIMER-MD-CONFIG: e1e8a2fd-e40a-4ac6-ac9b-f7e9cc9ee180 Sender: linux-omap-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-omap@vger.kernel.org Add PRM instance data for am4 family of SoCs. Initially this is just used to provide reset support. Signed-off-by: Tero Kristo --- drivers/soc/ti/omap_prm.c | 20 ++++++++++++++++++++ 1 file changed, 20 insertions(+) diff --git a/drivers/soc/ti/omap_prm.c b/drivers/soc/ti/omap_prm.c index a54c2e556b7a..fd11785637ff 100644 --- a/drivers/soc/ti/omap_prm.c +++ b/drivers/soc/ti/omap_prm.c @@ -117,10 +117,30 @@ static const struct omap_prm_data am3_prm_data[] = { { }, }; +static const struct omap_rst_map am4_per_rst_map[] = { + { .rst = 1, .st = 0 }, + { .rst = -1 }, +}; + +static const struct omap_rst_map am4_device_rst_map[] = { + { .rst = 0, .st = 1 }, + { .rst = 1, .st = 0 }, + { .rst = -1 }, +}; + +static const struct omap_prm_data am4_prm_data[] = { + { .name = "gfx", .base = 0x44df0400, .rstctrl = 0x10, .rstst = 0x14, .rstmap = rst_map_0, .clkdm_name = "gfx_l3" }, + { .name = "per", .base = 0x44df0800, .rstctrl = 0x10, .rstst = 0x14, .rstmap = am4_per_rst_map, .clkdm_name = "pruss_ocp" }, + { .name = "wkup", .base = 0x44df2000, .rstctrl = 0x10, .rstst = 0x14, .rstmap = am3_wkup_rst_map, .flags = OMAP_PRM_HAS_NO_CLKDM }, + { .name = "device", .base = 0x44df4000, .rstctrl = 0x0, .rstst = 0x4, .rstmap = am4_device_rst_map, .flags = OMAP_PRM_HAS_RSTCTRL | OMAP_PRM_HAS_NO_CLKDM }, + { }, +}; + static const struct of_device_id omap_prm_id_table[] = { { .compatible = "ti,omap4-prm-inst", .data = omap4_prm_data }, { .compatible = "ti,dra7-prm-inst", .data = dra7_prm_data }, { .compatible = "ti,am3-prm-inst", .data = am3_prm_data }, + { .compatible = "ti,am4-prm-inst", .data = am4_prm_data }, { }, }; From patchwork Wed Aug 28 07:19:41 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Tero Kristo X-Patchwork-Id: 11117973 Return-Path: Received: from mail.kernel.org (pdx-korg-mail-1.web.codeaurora.org [172.30.200.123]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id 1170A14F7 for ; Wed, 28 Aug 2019 07:20:29 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.kernel.org (Postfix) with ESMTP id E6653217F5 for ; Wed, 28 Aug 2019 07:20:28 +0000 (UTC) Authentication-Results: mail.kernel.org; dkim=pass (1024-bit key) header.d=ti.com header.i=@ti.com header.b="LA7RHGfH" Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1726462AbfH1HU2 (ORCPT ); Wed, 28 Aug 2019 03:20:28 -0400 Received: from fllv0016.ext.ti.com ([198.47.19.142]:53060 "EHLO fllv0016.ext.ti.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1726328AbfH1HU2 (ORCPT ); Wed, 28 Aug 2019 03:20:28 -0400 Received: from fllv0034.itg.ti.com ([10.64.40.246]) by fllv0016.ext.ti.com (8.15.2/8.15.2) with ESMTP id x7S7KKG4112382; Wed, 28 Aug 2019 02:20:20 -0500 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=ti.com; s=ti-com-17Q1; t=1566976821; bh=dGrMgeUi6wflxIOZ9TLPa+y2wgWQNeSeZXll2Q1ypN8=; h=From:To:CC:Subject:Date:In-Reply-To:References; b=LA7RHGfHHWPKg1RLI17yfbYWVpXg1RU3JUvaAt79aXRfoyq+tfl95bm6lZfmvApRn NaoPn9ry9yrPaftjaSzzRyIPKtKLkegS4EdzCdrVl4TiOCXXnjleX50Q1Sq5a2ViTl D2q2ImWl/caFL0skz6G7J2KTjb44CSDVht2xOM4M= Received: from DFLE113.ent.ti.com (dfle113.ent.ti.com [10.64.6.34]) by fllv0034.itg.ti.com (8.15.2/8.15.2) with ESMTPS id x7S7KKbZ025853 (version=TLSv1.2 cipher=AES256-GCM-SHA384 bits=256 verify=FAIL); Wed, 28 Aug 2019 02:20:20 -0500 Received: from DFLE112.ent.ti.com (10.64.6.33) by DFLE113.ent.ti.com (10.64.6.34) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.1713.5; Wed, 28 Aug 2019 02:20:14 -0500 Received: from lelv0327.itg.ti.com (10.180.67.183) by DFLE112.ent.ti.com (10.64.6.33) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.1713.5 via Frontend Transport; Wed, 28 Aug 2019 02:20:14 -0500 Received: from sokoban.bb.dnainternet.fi (ileax41-snat.itg.ti.com [10.172.224.153]) by lelv0327.itg.ti.com (8.15.2/8.15.2) with ESMTP id x7S7JmfN052201; Wed, 28 Aug 2019 02:20:12 -0500 From: Tero Kristo To: , , , , CC: , , Subject: [PATCHv2 11/11] soc: ti: omap-prm: add omap5 PRM data Date: Wed, 28 Aug 2019 10:19:41 +0300 Message-ID: <20190828071941.32378-12-t-kristo@ti.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20190828071941.32378-1-t-kristo@ti.com> References: <20190828071941.32378-1-t-kristo@ti.com> MIME-Version: 1.0 X-EXCLAIMER-MD-CONFIG: e1e8a2fd-e40a-4ac6-ac9b-f7e9cc9ee180 Sender: linux-omap-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-omap@vger.kernel.org Add PRM instance data for omap5 family of SoCs. Initially this is just used to provide reset support. Signed-off-by: Tero Kristo --- drivers/soc/ti/omap_prm.c | 9 +++++++++ 1 file changed, 9 insertions(+) diff --git a/drivers/soc/ti/omap_prm.c b/drivers/soc/ti/omap_prm.c index fd11785637ff..1a02e319fc63 100644 --- a/drivers/soc/ti/omap_prm.c +++ b/drivers/soc/ti/omap_prm.c @@ -86,6 +86,14 @@ static const struct omap_prm_data omap4_prm_data[] = { { }, }; +static const struct omap_prm_data omap5_prm_data[] = { + { .name = "dsp", .base = 0x4ae06400, .rstctrl = 0x10, .rstst = 0x14, .rstmap = rst_map_01 }, + { .name = "core", .base = 0x4ae06700, .rstctrl = 0x210, .rstst = 0x214, .clkdm_name = "ipu", .rstmap = rst_map_012 }, + { .name = "iva", .base = 0x4ae07200, .rstctrl = 0x10, .rstst = 0x14, .rstmap = rst_map_012 }, + { .name = "device", .base = 0x4ae07c00, .rstctrl = 0x0, .rstst = 0x4, .rstmap = rst_map_01, .flags = OMAP_PRM_HAS_RSTCTRL | OMAP_PRM_HAS_NO_CLKDM }, + { }, +}; + static const struct omap_prm_data dra7_prm_data[] = { { .name = "dsp1", .base = 0x4ae06400, .rstctrl = 0x10, .rstst = 0x14, .rstmap = rst_map_01 }, { .name = "ipu", .base = 0x4ae06500, .rstctrl = 0x10, .rstst = 0x14, .clkdm_name = "ipu1", .rstmap = rst_map_012 }, @@ -138,6 +146,7 @@ static const struct omap_prm_data am4_prm_data[] = { static const struct of_device_id omap_prm_id_table[] = { { .compatible = "ti,omap4-prm-inst", .data = omap4_prm_data }, + { .compatible = "ti,omap5-prm-inst", .data = omap5_prm_data }, { .compatible = "ti,dra7-prm-inst", .data = dra7_prm_data }, { .compatible = "ti,am3-prm-inst", .data = am3_prm_data }, { .compatible = "ti,am4-prm-inst", .data = am4_prm_data },