From patchwork Wed Aug 28 07:56:35 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Tero Kristo X-Patchwork-Id: 11118101 Return-Path: Received: from mail.kernel.org (pdx-korg-mail-1.web.codeaurora.org [172.30.200.123]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id 9D5361398 for ; Wed, 28 Aug 2019 07:57:03 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.kernel.org (Postfix) with ESMTP id 7309722CF5 for ; Wed, 28 Aug 2019 07:57:03 +0000 (UTC) Authentication-Results: mail.kernel.org; dkim=pass (1024-bit key) header.d=ti.com header.i=@ti.com header.b="JvmWmEIF" Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1726382AbfH1H5D (ORCPT ); Wed, 28 Aug 2019 03:57:03 -0400 Received: from fllv0016.ext.ti.com ([198.47.19.142]:58684 "EHLO fllv0016.ext.ti.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1726339AbfH1H5C (ORCPT ); Wed, 28 Aug 2019 03:57:02 -0400 Received: from fllv0034.itg.ti.com ([10.64.40.246]) by fllv0016.ext.ti.com (8.15.2/8.15.2) with ESMTP id x7S7uxJF123121; Wed, 28 Aug 2019 02:56:59 -0500 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=ti.com; s=ti-com-17Q1; t=1566979019; bh=u5tysN0SZOq/tSuyufNeM9PorN2KHwQ83/BegyqbgjI=; h=From:To:CC:Subject:Date:In-Reply-To:References; b=JvmWmEIFfFauU/RYUeBDx/hWp4iBOZ5NHIPqqF1LoRkYn9PTGhqtyeL9UAIUpxqnL FjoFJfvthz+qTiu3JmrPyy/Xu0TAOqU2oB7kxDkWjNfty1fycn9HuKtxVDJpE4oVl5 i3kx7Q/KDmPjEGr1wbiF69zwetJSmR6qGWz+VBts= Received: from DFLE110.ent.ti.com (dfle110.ent.ti.com [10.64.6.31]) by fllv0034.itg.ti.com (8.15.2/8.15.2) with ESMTPS id x7S7ux4H072041 (version=TLSv1.2 cipher=AES256-GCM-SHA384 bits=256 verify=FAIL); Wed, 28 Aug 2019 02:56:59 -0500 Received: from DFLE102.ent.ti.com (10.64.6.23) by DFLE110.ent.ti.com (10.64.6.31) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.1713.5; Wed, 28 Aug 2019 02:56:59 -0500 Received: from lelv0327.itg.ti.com (10.180.67.183) by DFLE102.ent.ti.com (10.64.6.23) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.1713.5 via Frontend Transport; Wed, 28 Aug 2019 02:56:59 -0500 Received: from sokoban.bb.dnainternet.fi (ileax41-snat.itg.ti.com [10.172.224.153]) by lelv0327.itg.ti.com (8.15.2/8.15.2) with ESMTP id x7S7uuFk107124; Wed, 28 Aug 2019 02:56:58 -0500 From: Tero Kristo To: , CC: , Subject: [PATCH 01/10] ARM: dts: omap5: add IVA clkctrl nodes Date: Wed, 28 Aug 2019 10:56:35 +0300 Message-ID: <20190828075644.4493-2-t-kristo@ti.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20190828075644.4493-1-t-kristo@ti.com> References: <20190828075644.4493-1-t-kristo@ti.com> MIME-Version: 1.0 X-EXCLAIMER-MD-CONFIG: e1e8a2fd-e40a-4ac6-ac9b-f7e9cc9ee180 Sender: linux-omap-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-omap@vger.kernel.org Add clkctrtl nodes for Image and Video Accelerator subsystem for omap5. Signed-off-by: Tero Kristo --- arch/arm/boot/dts/omap54xx-clocks.dtsi | 14 ++++++++++++++ 1 file changed, 14 insertions(+) diff --git a/arch/arm/boot/dts/omap54xx-clocks.dtsi b/arch/arm/boot/dts/omap54xx-clocks.dtsi index 33e8dd905bff..f1ab2777e33e 100644 --- a/arch/arm/boot/dts/omap54xx-clocks.dtsi +++ b/arch/arm/boot/dts/omap54xx-clocks.dtsi @@ -1132,6 +1132,20 @@ }; }; + iva_cm: iva_cm@1200 { + compatible = "ti,omap4-cm"; + reg = <0x1200 0x100>; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0 0x1200 0x100>; + + iva_clkctrl: clk@20 { + compatible = "ti,clkctrl"; + reg = <0x20 0xc>; + #clock-cells = <2>; + }; + }; + dss_cm: dss_cm@1400 { compatible = "ti,omap4-cm"; reg = <0x1400 0x100>; From patchwork Wed Aug 28 07:56:36 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Tero Kristo X-Patchwork-Id: 11118105 Return-Path: Received: from mail.kernel.org (pdx-korg-mail-1.web.codeaurora.org [172.30.200.123]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id 3CC091398 for ; Wed, 28 Aug 2019 07:57:05 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.kernel.org (Postfix) with ESMTP id 1E69822CF5 for ; Wed, 28 Aug 2019 07:57:05 +0000 (UTC) Authentication-Results: mail.kernel.org; dkim=pass (1024-bit key) header.d=ti.com header.i=@ti.com header.b="fn8qFFe/" Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1726394AbfH1H5E (ORCPT ); Wed, 28 Aug 2019 03:57:04 -0400 Received: from fllv0016.ext.ti.com ([198.47.19.142]:58694 "EHLO fllv0016.ext.ti.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1726290AbfH1H5E (ORCPT ); Wed, 28 Aug 2019 03:57:04 -0400 Received: from fllv0035.itg.ti.com ([10.64.41.0]) by fllv0016.ext.ti.com (8.15.2/8.15.2) with ESMTP id x7S7v0T1123126; Wed, 28 Aug 2019 02:57:00 -0500 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=ti.com; s=ti-com-17Q1; t=1566979020; bh=uXEzRmZ8z51c3KPk6HSXAw3k87purAqVMHp+qIFsIyU=; h=From:To:CC:Subject:Date:In-Reply-To:References; b=fn8qFFe/hwbwjccB2ES+C1PtMuLaz/Mn6HnJCxBQqhQfHUxt7Av3rDMF0/omntq/G mH1biLT5jOw8ZJfi/oYOKGlpbZ7DhXkYpqCjbL4QFDaRSBPN3ZIhg6C4RgndIUk8mL IaRayL34CGDqnrrpAw0Piu7e0Bmdg8JJNLL0mW1U= Received: from DLEE112.ent.ti.com (dlee112.ent.ti.com [157.170.170.23]) by fllv0035.itg.ti.com (8.15.2/8.15.2) with ESMTPS id x7S7v0jr123876 (version=TLSv1.2 cipher=AES256-GCM-SHA384 bits=256 verify=FAIL); Wed, 28 Aug 2019 02:57:00 -0500 Received: from DLEE114.ent.ti.com (157.170.170.25) by DLEE112.ent.ti.com (157.170.170.23) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.1713.5; Wed, 28 Aug 2019 02:57:00 -0500 Received: from lelv0327.itg.ti.com (10.180.67.183) by DLEE114.ent.ti.com (157.170.170.25) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.1713.5 via Frontend Transport; Wed, 28 Aug 2019 02:57:00 -0500 Received: from sokoban.bb.dnainternet.fi (ileax41-snat.itg.ti.com [10.172.224.153]) by lelv0327.itg.ti.com (8.15.2/8.15.2) with ESMTP id x7S7uuFl107124; Wed, 28 Aug 2019 02:56:59 -0500 From: Tero Kristo To: , CC: , Subject: [PATCH 02/10] ARM: dts: dra7: add PRM nodes Date: Wed, 28 Aug 2019 10:56:36 +0300 Message-ID: <20190828075644.4493-3-t-kristo@ti.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20190828075644.4493-1-t-kristo@ti.com> References: <20190828075644.4493-1-t-kristo@ti.com> MIME-Version: 1.0 X-EXCLAIMER-MD-CONFIG: e1e8a2fd-e40a-4ac6-ac9b-f7e9cc9ee180 Sender: linux-omap-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-omap@vger.kernel.org Add PRM nodes for dra7 series of SoCs. These are initially used to support reset control for some of the nodes, but will be extended later to add powerdomain control and support for PRCM irqs among other things. Signed-off-by: Tero Kristo --- arch/arm/boot/dts/dra7.dtsi | 55 +++++++++++++++++++++++++++++++++++++ 1 file changed, 55 insertions(+) diff --git a/arch/arm/boot/dts/dra7.dtsi b/arch/arm/boot/dts/dra7.dtsi index 953f0ffce2a9..95147289be9c 100644 --- a/arch/arm/boot/dts/dra7.dtsi +++ b/arch/arm/boot/dts/dra7.dtsi @@ -763,3 +763,58 @@ #include "dra7-l4.dtsi" #include "dra7xx-clocks.dtsi" + +&prm { + prm_dsp1: prm@400 { + compatible = "ti,dra7-prm-inst"; + reg = <0x400 0x100>; + #reset-cells = <1>; + clocks = <&dsp1_clkctrl DRA7_DSP1_MMU0_DSP1_CLKCTRL 0>; + }; + + prm_ipu: prm@500 { + compatible = "ti,dra7-prm-inst"; + reg = <0x500 0x100>; + #reset-cells = <1>; + clocks = <&ipu1_clkctrl DRA7_IPU1_MMU_IPU1_CLKCTRL 0>; + }; + + prm_core: prm@700 { + compatible = "ti,dra7-prm-inst"; + reg = <0x700 0x100>; + #reset-cells = <1>; + clocks = <&ipu2_clkctrl DRA7_IPU2_MMU_IPU2_CLKCTRL 0>; + }; + + prm_iva: prm@f00 { + compatible = "ti,dra7-prm-inst"; + reg = <0xf00 0x100>; + }; + + prm_dsp2: prm@1b00 { + compatible = "ti,dra7-prm-inst"; + reg = <0x1b00 0x40>; + #reset-cells = <1>; + clocks = <&dsp2_clkctrl DRA7_DSP2_MMU0_DSP2_CLKCTRL 0>; + }; + + prm_eve1: prm@1b40 { + compatible = "ti,dra7-prm-inst"; + reg = <0x1b40 0x40>; + }; + + prm_eve2: prm@1b80 { + compatible = "ti,dra7-prm-inst"; + reg = <0x1b80 0x40>; + }; + + prm_eve3: prm@1bc0 { + compatible = "ti,dra7-prm-inst"; + reg = <0x1bc0 0x40>; + }; + + prm_eve4: prm@1c00 { + compatible = "ti,dra7-prm-inst"; + reg = <0x1c00 0x60>; + }; +}; From patchwork Wed Aug 28 07:56:37 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Tero Kristo X-Patchwork-Id: 11118109 Return-Path: Received: from mail.kernel.org (pdx-korg-mail-1.web.codeaurora.org [172.30.200.123]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id 151C41395 for ; Wed, 28 Aug 2019 07:57:08 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.kernel.org (Postfix) with ESMTP id EA4A7217F5 for ; Wed, 28 Aug 2019 07:57:07 +0000 (UTC) Authentication-Results: mail.kernel.org; dkim=pass (1024-bit key) header.d=ti.com header.i=@ti.com header.b="eVWVv26k" Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1726326AbfH1H5H (ORCPT ); Wed, 28 Aug 2019 03:57:07 -0400 Received: from lelv0143.ext.ti.com ([198.47.23.248]:37160 "EHLO lelv0143.ext.ti.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1726290AbfH1H5H (ORCPT ); Wed, 28 Aug 2019 03:57:07 -0400 Received: from fllv0034.itg.ti.com ([10.64.40.246]) by lelv0143.ext.ti.com (8.15.2/8.15.2) with ESMTP id x7S7v2eU127649; Wed, 28 Aug 2019 02:57:02 -0500 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=ti.com; s=ti-com-17Q1; t=1566979022; bh=usezFA71rznpN9ia/t+wJ4qi7Gg7ULvpWM8RBhJKtf8=; h=From:To:CC:Subject:Date:In-Reply-To:References; b=eVWVv26kx/ZLkUP2KsIMU9gkIDrDd+eOXNiLPGCXJafrU2Pdny9cfOlO4vk722rTG BEs9xW0LRjRKnl/LkMU66Iiq7LOqXmmLnjk3m0jrhFH+yv9xk/PSEumuCbv4bGxUhf hUBYf9FPfgw5jxTZ+CTluPyy4o+3fz0Cr03pf/AE= Received: from DFLE112.ent.ti.com (dfle112.ent.ti.com [10.64.6.33]) by fllv0034.itg.ti.com (8.15.2/8.15.2) with ESMTPS id x7S7v2Nc072155 (version=TLSv1.2 cipher=AES256-GCM-SHA384 bits=256 verify=FAIL); Wed, 28 Aug 2019 02:57:02 -0500 Received: from DFLE107.ent.ti.com (10.64.6.28) by DFLE112.ent.ti.com (10.64.6.33) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.1713.5; Wed, 28 Aug 2019 02:57:02 -0500 Received: from lelv0327.itg.ti.com (10.180.67.183) by DFLE107.ent.ti.com (10.64.6.28) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.1713.5 via Frontend Transport; Wed, 28 Aug 2019 02:57:01 -0500 Received: from sokoban.bb.dnainternet.fi (ileax41-snat.itg.ti.com [10.172.224.153]) by lelv0327.itg.ti.com (8.15.2/8.15.2) with ESMTP id x7S7uuFm107124; Wed, 28 Aug 2019 02:57:00 -0500 From: Tero Kristo To: , CC: , Subject: [PATCH 03/10] ARM: dts: omap4: add PRM nodes Date: Wed, 28 Aug 2019 10:56:37 +0300 Message-ID: <20190828075644.4493-4-t-kristo@ti.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20190828075644.4493-1-t-kristo@ti.com> References: <20190828075644.4493-1-t-kristo@ti.com> MIME-Version: 1.0 X-EXCLAIMER-MD-CONFIG: e1e8a2fd-e40a-4ac6-ac9b-f7e9cc9ee180 Sender: linux-omap-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-omap@vger.kernel.org Add PRM nodes for omap4 series of SoCs. These are initially used to support reset control for some of the nodes, but will be extended later to add powerdomain control and support for PRCM irqs among other things. Signed-off-by: Tero Kristo --- arch/arm/boot/dts/omap4-l4.dtsi | 2 +- arch/arm/boot/dts/omap4.dtsi | 29 +++++++++++++++++++++++++++++ 2 files changed, 30 insertions(+), 1 deletion(-) diff --git a/arch/arm/boot/dts/omap4-l4.dtsi b/arch/arm/boot/dts/omap4-l4.dtsi index bea05dc4ef0f..0977bc39955b 100644 --- a/arch/arm/boot/dts/omap4-l4.dtsi +++ b/arch/arm/boot/dts/omap4-l4.dtsi @@ -981,7 +981,7 @@ ranges = <0x0 0x6000 0x2000>; prm: prm@0 { - compatible = "ti,omap4-prm"; + compatible = "ti,omap4-prm", "simple-bus"; reg = <0x0 0x2000>; interrupts = ; #address-cells = <1>; diff --git a/arch/arm/boot/dts/omap4.dtsi b/arch/arm/boot/dts/omap4.dtsi index c43e52fd5f65..e377f66fc322 100644 --- a/arch/arm/boot/dts/omap4.dtsi +++ b/arch/arm/boot/dts/omap4.dtsi @@ -443,3 +443,32 @@ #include "omap4-l4.dtsi" #include "omap4-l4-abe.dtsi" #include "omap44xx-clocks.dtsi" + +&prm { + prm_tesla: prm@400 { + compatible = "ti,omap4-prm-inst"; + reg = <0x400 0x100>; + #reset-cells = <1>; + clocks = <&tesla_clkctrl OMAP4_DSP_CLKCTRL 0>; + }; + + prm_core: prm@700 { + compatible = "ti,omap4-prm-inst"; + reg = <0x700 0x100>; + #reset-cells = <1>; + clocks = <&ducati_clkctrl OMAP4_IPU_CLKCTRL 0>; + }; + + prm_ivahd: prm@f00 { + compatible = "ti,omap4-prm-inst"; + reg = <0xf00 0x100>; + #reset-cells = <1>; + clocks = <&ivahd_clkctrl OMAP4_IVA_CLKCTRL 0>; + }; + + prm_device: prm@1b00 { + compatible = "ti,omap4-prm-inst"; + reg = <0x1b00 0x40>; + #reset-cells = <1>; + }; +}; From patchwork Wed Aug 28 07:56:38 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Tero Kristo X-Patchwork-Id: 11118111 Return-Path: Received: from mail.kernel.org (pdx-korg-mail-1.web.codeaurora.org [172.30.200.123]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id 072E71395 for ; Wed, 28 Aug 2019 07:57:09 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.kernel.org (Postfix) with ESMTP id DD55C22CF8 for ; Wed, 28 Aug 2019 07:57:08 +0000 (UTC) Authentication-Results: mail.kernel.org; dkim=pass (1024-bit key) header.d=ti.com header.i=@ti.com header.b="xELkV4Nv" Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1726399AbfH1H5I (ORCPT ); Wed, 28 Aug 2019 03:57:08 -0400 Received: from lelv0143.ext.ti.com ([198.47.23.248]:37166 "EHLO lelv0143.ext.ti.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1726422AbfH1H5I (ORCPT ); Wed, 28 Aug 2019 03:57:08 -0400 Received: from fllv0035.itg.ti.com ([10.64.41.0]) by lelv0143.ext.ti.com (8.15.2/8.15.2) with ESMTP id x7S7v3kS127658; Wed, 28 Aug 2019 02:57:03 -0500 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=ti.com; s=ti-com-17Q1; t=1566979023; bh=kh0XqWPOVpwPZwZq3NDgP1PINZHnA6n9NcYoIfo7Ms8=; h=From:To:CC:Subject:Date:In-Reply-To:References; b=xELkV4NvKsUmAKWgdTz8PyPcHUwUK9sCG1T27KPYW9bKxygVrN1x0LqKTOWMsI3zd 7Me+zMWTkrCrDkm5NHid4PubiN7mgtoU3wiiSEWkh6lDdD/CsniydC5GoZ0Ta7WuHv 2jdNDbHslir1Ee4VI3ia7h3Xk5QpLUIaaWE91X8s= Received: from DLEE114.ent.ti.com (dlee114.ent.ti.com [157.170.170.25]) by fllv0035.itg.ti.com (8.15.2/8.15.2) with ESMTPS id x7S7v3II124014 (version=TLSv1.2 cipher=AES256-GCM-SHA384 bits=256 verify=FAIL); Wed, 28 Aug 2019 02:57:03 -0500 Received: from DLEE111.ent.ti.com (157.170.170.22) by DLEE114.ent.ti.com (157.170.170.25) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.1713.5; Wed, 28 Aug 2019 02:57:03 -0500 Received: from lelv0327.itg.ti.com (10.180.67.183) by DLEE111.ent.ti.com (157.170.170.22) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.1713.5 via Frontend Transport; Wed, 28 Aug 2019 02:57:03 -0500 Received: from sokoban.bb.dnainternet.fi (ileax41-snat.itg.ti.com [10.172.224.153]) by lelv0327.itg.ti.com (8.15.2/8.15.2) with ESMTP id x7S7uuFn107124; Wed, 28 Aug 2019 02:57:02 -0500 From: Tero Kristo To: , CC: , Subject: [PATCH 04/10] ARM: dts: am33xx: Add PRM data Date: Wed, 28 Aug 2019 10:56:38 +0300 Message-ID: <20190828075644.4493-5-t-kristo@ti.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20190828075644.4493-1-t-kristo@ti.com> References: <20190828075644.4493-1-t-kristo@ti.com> MIME-Version: 1.0 X-EXCLAIMER-MD-CONFIG: e1e8a2fd-e40a-4ac6-ac9b-f7e9cc9ee180 Sender: linux-omap-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-omap@vger.kernel.org Add PRM data for AM33xx SoC. Initially this is used to provide reset support, but will be expanded later to support also powerdomain control. Signed-off-by: Tero Kristo --- arch/arm/boot/dts/am33xx.dtsi | 29 +++++++++++++++++++++++++++++ 1 file changed, 29 insertions(+) diff --git a/arch/arm/boot/dts/am33xx.dtsi b/arch/arm/boot/dts/am33xx.dtsi index e5c2f71a7c77..7448400a119e 100644 --- a/arch/arm/boot/dts/am33xx.dtsi +++ b/arch/arm/boot/dts/am33xx.dtsi @@ -445,3 +445,32 @@ #include "am33xx-l4.dtsi" #include "am33xx-clocks.dtsi" + +&prcm { + prm_per: prm@c00 { + compatible = "ti,am3-prm-inst"; + reg = <0xc00 0x100>; + #reset-cells = <1>; + clocks = <&pruss_ocp_clkctrl AM3_PRUSS_OCP_PRUSS_CLKCTRL 0>; + }; + + prm_wkup: prm@d00 { + compatible = "ti,am3-prm-inst"; + reg = <0xd00 0x100>; + #reset-cells = <1>; + clocks = <&l4_wkup_clkctrl AM3_WKUP_M3_CLKCTRL 0>; + }; + + prm_device: prm@f00 { + compatible = "ti,am3-prm-inst"; + reg = <0xf00 0x100>; + #reset-cells = <1>; + }; + + prm_gfx: prm@1100 { + compatible = "ti,am3-prm-inst"; + reg = <0x1100 0x100>; + #reset-cells = <1>; + clocks = <&gfx_l3_clkctrl AM3_GFX_CLKCTRL 0>; + }; +}; From patchwork Wed Aug 28 07:56:39 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Tero Kristo X-Patchwork-Id: 11118113 Return-Path: Received: from mail.kernel.org (pdx-korg-mail-1.web.codeaurora.org [172.30.200.123]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id EA4B51398 for ; Wed, 28 Aug 2019 07:57:09 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.kernel.org (Postfix) with ESMTP id CB95D22CF8 for ; Wed, 28 Aug 2019 07:57:09 +0000 (UTC) Authentication-Results: mail.kernel.org; dkim=pass (1024-bit key) header.d=ti.com header.i=@ti.com header.b="fpx+YKcp" Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1726290AbfH1H5J (ORCPT ); Wed, 28 Aug 2019 03:57:09 -0400 Received: from lelv0143.ext.ti.com ([198.47.23.248]:37170 "EHLO lelv0143.ext.ti.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1726422AbfH1H5J (ORCPT ); Wed, 28 Aug 2019 03:57:09 -0400 Received: from lelv0265.itg.ti.com ([10.180.67.224]) by lelv0143.ext.ti.com (8.15.2/8.15.2) with ESMTP id x7S7v5ms127667; Wed, 28 Aug 2019 02:57:05 -0500 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=ti.com; s=ti-com-17Q1; t=1566979025; bh=bV7v6jpzGIFR9zq5s75cVQi0wC5i+NfYYrnSlvWqJrY=; h=From:To:CC:Subject:Date:In-Reply-To:References; b=fpx+YKcpik5O8NsYVVQvNBBcj20qZLch66ErL87bPypPTB/oqDBgy1OL2ByrUmy1i Te8W7NMdmak1u5aFyVkYqiW4GUeGjdbD9QGnUM+LFKGatBpcJxkHgViGoIdOrMimdi qlp/l7MCOg5a+f4kJdu+w06HuDehryacpQbV8/aY= Received: from DLEE113.ent.ti.com (dlee113.ent.ti.com [157.170.170.24]) by lelv0265.itg.ti.com (8.15.2/8.15.2) with ESMTPS id x7S7v5c7127606 (version=TLSv1.2 cipher=AES256-GCM-SHA384 bits=256 verify=FAIL); Wed, 28 Aug 2019 02:57:05 -0500 Received: from DLEE103.ent.ti.com (157.170.170.33) by DLEE113.ent.ti.com (157.170.170.24) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.1713.5; Wed, 28 Aug 2019 02:57:04 -0500 Received: from lelv0327.itg.ti.com (10.180.67.183) by DLEE103.ent.ti.com (157.170.170.33) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.1713.5 via Frontend Transport; Wed, 28 Aug 2019 02:57:04 -0500 Received: from sokoban.bb.dnainternet.fi (ileax41-snat.itg.ti.com [10.172.224.153]) by lelv0327.itg.ti.com (8.15.2/8.15.2) with ESMTP id x7S7uuFo107124; Wed, 28 Aug 2019 02:57:03 -0500 From: Tero Kristo To: , CC: , Subject: [PATCH 05/10] ARM: dts: am43xx: Add PRM data Date: Wed, 28 Aug 2019 10:56:39 +0300 Message-ID: <20190828075644.4493-6-t-kristo@ti.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20190828075644.4493-1-t-kristo@ti.com> References: <20190828075644.4493-1-t-kristo@ti.com> MIME-Version: 1.0 X-EXCLAIMER-MD-CONFIG: e1e8a2fd-e40a-4ac6-ac9b-f7e9cc9ee180 Sender: linux-omap-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-omap@vger.kernel.org Add PRM data for AM43xx SoC. Initially this is used to provide reset support, but will be expanded later to support also powerdomain control. Signed-off-by: Tero Kristo --- arch/arm/boot/dts/am4372.dtsi | 29 +++++++++++++++++++++++++++++ 1 file changed, 29 insertions(+) diff --git a/arch/arm/boot/dts/am4372.dtsi b/arch/arm/boot/dts/am4372.dtsi index 55aff4db9c7c..4bd22c6ba3ff 100644 --- a/arch/arm/boot/dts/am4372.dtsi +++ b/arch/arm/boot/dts/am4372.dtsi @@ -353,3 +353,32 @@ #include "am437x-l4.dtsi" #include "am43xx-clocks.dtsi" + +&prcm { + prm_gfx: prm@400 { + compatible = "ti,am4-prm-inst"; + reg = <0x400 0x100>; + #reset-cells = <1>; + clocks = <&gfx_l3_clkctrl AM4_GFX_L3_GFX_CLKCTRL 0>; + }; + + prm_per: prm@800 { + compatible = "ti,am4-prm-inst"; + reg = <0x800 0x100>; + #reset-cells = <1>; + clocks = <&pruss_ocp_clkctrl AM4_PRUSS_OCP_PRUSS_CLKCTRL 0>; + }; + + prm_wkup: prm@2000 { + compatible = "ti,am4-prm-inst"; + reg = <0x2000 0x100>; + #reset-cells = <1>; + clocks = <&l4_wkup_aon_clkctrl AM4_L4_WKUP_AON_WKUP_M3_CLKCTRL 0>; + }; + + prm_device: prm@4000 { + compatible = "ti,am4-prm-inst"; + reg = <0x4000 0x100>; + #reset-cells = <1>; + }; +}; From patchwork Wed Aug 28 07:56:40 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Tero Kristo X-Patchwork-Id: 11118115 Return-Path: Received: from mail.kernel.org (pdx-korg-mail-1.web.codeaurora.org [172.30.200.123]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id 208D91398 for ; Wed, 28 Aug 2019 07:57:11 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.kernel.org (Postfix) with ESMTP id 00F4B217F5 for ; Wed, 28 Aug 2019 07:57:11 +0000 (UTC) Authentication-Results: mail.kernel.org; dkim=pass (1024-bit key) header.d=ti.com header.i=@ti.com header.b="dLpyv4z1" Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1726422AbfH1H5K (ORCPT ); Wed, 28 Aug 2019 03:57:10 -0400 Received: from fllv0016.ext.ti.com ([198.47.19.142]:58720 "EHLO fllv0016.ext.ti.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1726396AbfH1H5K (ORCPT ); Wed, 28 Aug 2019 03:57:10 -0400 Received: from fllv0035.itg.ti.com ([10.64.41.0]) by fllv0016.ext.ti.com (8.15.2/8.15.2) with ESMTP id x7S7v6Ar123169; Wed, 28 Aug 2019 02:57:06 -0500 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=ti.com; s=ti-com-17Q1; t=1566979026; bh=hxpUWyPrR3KIUmCy4NBe4h8DLkiKMukqt5xjoDbP8T4=; h=From:To:CC:Subject:Date:In-Reply-To:References; b=dLpyv4z1izWujIj6V5XauobGguNoQtJ8rpHSYuo7NkMcNT0FkLzEBonMKT8G9Am+j XAhVPYHkSu9LcV16wdTDlupqzDhZLJegOsRH9DRpcIqoo2UudEr8wfdBhQRrZz9JZe 5rhw4T4DbGp2/wDkWeGo+cxOd1gmixiohmbQ72bY= Received: from DLEE113.ent.ti.com (dlee113.ent.ti.com [157.170.170.24]) by fllv0035.itg.ti.com (8.15.2/8.15.2) with ESMTPS id x7S7v6ND124268 (version=TLSv1.2 cipher=AES256-GCM-SHA384 bits=256 verify=FAIL); Wed, 28 Aug 2019 02:57:06 -0500 Received: from DLEE101.ent.ti.com (157.170.170.31) by DLEE113.ent.ti.com (157.170.170.24) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.1713.5; Wed, 28 Aug 2019 02:57:06 -0500 Received: from lelv0327.itg.ti.com (10.180.67.183) by DLEE101.ent.ti.com (157.170.170.31) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.1713.5 via Frontend Transport; Wed, 28 Aug 2019 02:57:06 -0500 Received: from sokoban.bb.dnainternet.fi (ileax41-snat.itg.ti.com [10.172.224.153]) by lelv0327.itg.ti.com (8.15.2/8.15.2) with ESMTP id x7S7uuFp107124; Wed, 28 Aug 2019 02:57:05 -0500 From: Tero Kristo To: , CC: , Subject: [PATCH 06/10] ARM: dts: omap5: Add PRM data Date: Wed, 28 Aug 2019 10:56:40 +0300 Message-ID: <20190828075644.4493-7-t-kristo@ti.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20190828075644.4493-1-t-kristo@ti.com> References: <20190828075644.4493-1-t-kristo@ti.com> MIME-Version: 1.0 X-EXCLAIMER-MD-CONFIG: e1e8a2fd-e40a-4ac6-ac9b-f7e9cc9ee180 Sender: linux-omap-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-omap@vger.kernel.org Add PRM data for OMAP54xx SoC. Initially this is used to provide reset support, but will be expanded later to support also powerdomain control. Signed-off-by: Tero Kristo --- arch/arm/boot/dts/omap5.dtsi | 30 ++++++++++++++++++++++++++++++ 1 file changed, 30 insertions(+) diff --git a/arch/arm/boot/dts/omap5.dtsi b/arch/arm/boot/dts/omap5.dtsi index edfd26c03462..c8bde171a949 100644 --- a/arch/arm/boot/dts/omap5.dtsi +++ b/arch/arm/boot/dts/omap5.dtsi @@ -412,3 +412,33 @@ #include "omap5-l4-abe.dtsi" #include "omap54xx-clocks.dtsi" + +&prm { + prm_dsp: prm@400 { + compatible = "ti,omap5-prm-inst"; + reg = <0x400 0x100>; + #reset-cells = <1>; + clocks = <&dsp_clkctrl OMAP5_MMU_DSP_CLKCTRL 0>; + + }; + + prm_core: prm@700 { + compatible = "ti,omap5-prm-inst"; + reg = <0x700 0x100>; + #reset-cells = <1>; + clocks = <&ipu_clkctrl OMAP5_MMU_IPU_CLKCTRL 0>; + }; + + prm_iva: prm@1200 { + compatible = "ti,omap5-prm-inst"; + reg = <0x1200 0x100>; + #reset-cells = <1>; + clocks = <&iva_clkctrl OMAP5_IVA_CLKCTRL 0>; + }; + + prm_device: prm@1c00 { + compatible = "ti,omap5-prm-inst"; + reg = <0x1c00 0x100>; + #reset-cells = <1>; + }; +}; From patchwork Wed Aug 28 07:56:41 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Tero Kristo X-Patchwork-Id: 11118119 Return-Path: Received: from mail.kernel.org (pdx-korg-mail-1.web.codeaurora.org [172.30.200.123]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id 877231800 for ; Wed, 28 Aug 2019 07:57:15 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.kernel.org (Postfix) with ESMTP id 6789922CF5 for ; Wed, 28 Aug 2019 07:57:15 +0000 (UTC) Authentication-Results: mail.kernel.org; dkim=pass (1024-bit key) header.d=ti.com header.i=@ti.com header.b="blR8ntm3" Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1726340AbfH1H5O (ORCPT ); Wed, 28 Aug 2019 03:57:14 -0400 Received: from lelv0142.ext.ti.com ([198.47.23.249]:39464 "EHLO lelv0142.ext.ti.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1726432AbfH1H5N (ORCPT ); Wed, 28 Aug 2019 03:57:13 -0400 Received: from fllv0035.itg.ti.com ([10.64.41.0]) by lelv0142.ext.ti.com (8.15.2/8.15.2) with ESMTP id x7S7v9do007401; Wed, 28 Aug 2019 02:57:09 -0500 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=ti.com; s=ti-com-17Q1; t=1566979029; bh=PdU5LgP9Hg6QKlaio0Oi7x2kiAEJReGQeaYlIom23cw=; h=From:To:CC:Subject:Date:In-Reply-To:References; b=blR8ntm3kKo8JbcKDkKA8bkXjdLUKAyeQZvRhAlcUpe1/nwJ0K4TmtQlIEEV0yKyk ovrA5MtVExT07O3XKAFUMTM0ug9QqCrQqG/ZnBFWrBhArd/ioXw0Mxux1aQXfvEp/4 lcBpMFe/c2BExo5ALcV67OkSXEBbJDFCsMAxI8NQ= Received: from DLEE111.ent.ti.com (dlee111.ent.ti.com [157.170.170.22]) by fllv0035.itg.ti.com (8.15.2/8.15.2) with ESMTPS id x7S7v9Dm124352 (version=TLSv1.2 cipher=AES256-GCM-SHA384 bits=256 verify=FAIL); Wed, 28 Aug 2019 02:57:09 -0500 Received: from DLEE115.ent.ti.com (157.170.170.26) by DLEE111.ent.ti.com (157.170.170.22) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.1713.5; Wed, 28 Aug 2019 02:57:07 -0500 Received: from lelv0327.itg.ti.com (10.180.67.183) by DLEE115.ent.ti.com (157.170.170.26) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.1713.5 via Frontend Transport; Wed, 28 Aug 2019 02:57:07 -0500 Received: from sokoban.bb.dnainternet.fi (ileax41-snat.itg.ti.com [10.172.224.153]) by lelv0327.itg.ti.com (8.15.2/8.15.2) with ESMTP id x7S7uuFq107124; Wed, 28 Aug 2019 02:57:06 -0500 From: Tero Kristo To: , CC: , Subject: [PATCH 07/10] ARM: dts: dra7: convert IOMMUs to use ti-sysc Date: Wed, 28 Aug 2019 10:56:41 +0300 Message-ID: <20190828075644.4493-8-t-kristo@ti.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20190828075644.4493-1-t-kristo@ti.com> References: <20190828075644.4493-1-t-kristo@ti.com> MIME-Version: 1.0 X-EXCLAIMER-MD-CONFIG: e1e8a2fd-e40a-4ac6-ac9b-f7e9cc9ee180 Sender: linux-omap-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-omap@vger.kernel.org Convert dra7 IOMMUs to use ti-sysc instead of legacy omap-hwmod based implementation. Enable the IOMMUs also while doing this. Signed-off-by: Tero Kristo --- arch/arm/boot/dts/dra7.dtsi | 140 +++++++++++++++++++++++++++--------- 1 file changed, 108 insertions(+), 32 deletions(-) diff --git a/arch/arm/boot/dts/dra7.dtsi b/arch/arm/boot/dts/dra7.dtsi index 95147289be9c..98c01f204a1a 100644 --- a/arch/arm/boot/dts/dra7.dtsi +++ b/arch/arm/boot/dts/dra7.dtsi @@ -377,44 +377,120 @@ ti,hwmods = "dmm"; }; - mmu0_dsp1: mmu@40d01000 { - compatible = "ti,dra7-dsp-iommu"; - reg = <0x40d01000 0x100>; - interrupts = ; - ti,hwmods = "mmu0_dsp1"; - #iommu-cells = <0>; - ti,syscon-mmuconfig = <&dsp1_system 0x0>; - status = "disabled"; + target-module@40d01000 { + compatible = "ti,sysc-omap2", "ti,sysc"; + reg = <0x40d01000 0x4>, + <0x40d01010 0x4>, + <0x40d01014 0x4>; + reg-names = "rev", "sysc", "syss"; + ti,sysc-sidle = , + , + ; + ti,sysc-mask = <(SYSC_OMAP2_CLOCKACTIVITY | + SYSC_OMAP2_SOFTRESET | + SYSC_OMAP2_AUTOIDLE)>; + clocks = <&dsp1_clkctrl DRA7_DSP1_MMU0_DSP1_CLKCTRL 0>; + clock-names = "fck"; + resets = <&prm_dsp1 1>; + reset-names = "rstctrl"; + ranges = <0x0 0x40d01000 0x1000>; + #size-cells = <1>; + #address-cells = <1>; + + mmu0_dsp1: mmu@0 { + compatible = "ti,dra7-dsp-iommu"; + reg = <0x0 0x100>; + interrupts = ; + #iommu-cells = <0>; + ti,syscon-mmuconfig = <&dsp1_system 0x0>; + }; }; - mmu1_dsp1: mmu@40d02000 { - compatible = "ti,dra7-dsp-iommu"; - reg = <0x40d02000 0x100>; - interrupts = ; - ti,hwmods = "mmu1_dsp1"; - #iommu-cells = <0>; - ti,syscon-mmuconfig = <&dsp1_system 0x1>; - status = "disabled"; + target-module@40d02000 { + compatible = "ti,sysc-omap2", "ti,sysc"; + reg = <0x40d02000 0x4>, + <0x40d02010 0x4>, + <0x40d02014 0x4>; + reg-names = "rev", "sysc", "syss"; + ti,sysc-sidle = , + , + ; + ti,sysc-mask = <(SYSC_OMAP2_CLOCKACTIVITY | + SYSC_OMAP2_SOFTRESET | + SYSC_OMAP2_AUTOIDLE)>; + clocks = <&dsp1_clkctrl DRA7_DSP1_MMU0_DSP1_CLKCTRL 0>; + clock-names = "fck"; + resets = <&prm_dsp1 1>; + reset-names = "rstctrl"; + ranges = <0x0 0x40d02000 0x1000>; + #size-cells = <1>; + #address-cells = <1>; + + mmu1_dsp1: mmu@0 { + compatible = "ti,dra7-dsp-iommu"; + reg = <0x0 0x100>; + interrupts = ; + #iommu-cells = <0>; + ti,syscon-mmuconfig = <&dsp1_system 0x1>; + }; }; - mmu_ipu1: mmu@58882000 { - compatible = "ti,dra7-iommu"; - reg = <0x58882000 0x100>; - interrupts = ; - ti,hwmods = "mmu_ipu1"; - #iommu-cells = <0>; - ti,iommu-bus-err-back; - status = "disabled"; + target-module@58882000 { + compatible = "ti,sysc-omap2", "ti,sysc"; + reg = <0x58882000 0x4>, + <0x58882010 0x4>, + <0x58882014 0x4>; + reg-names = "rev", "sysc", "syss"; + ti,sysc-sidle = , + , + ; + ti,sysc-mask = <(SYSC_OMAP2_CLOCKACTIVITY | + SYSC_OMAP2_SOFTRESET | + SYSC_OMAP2_AUTOIDLE)>; + clocks = <&ipu1_clkctrl DRA7_IPU1_MMU_IPU1_CLKCTRL 0>; + clock-names = "fck"; + resets = <&prm_ipu 2>; + reset-names = "rstctrl"; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0x0 0x58882000 0x100>; + + mmu_ipu1: mmu@0 { + compatible = "ti,dra7-iommu"; + reg = <0x0 0x100>; + interrupts = ; + #iommu-cells = <0>; + ti,iommu-bus-err-back; + }; }; - mmu_ipu2: mmu@55082000 { - compatible = "ti,dra7-iommu"; - reg = <0x55082000 0x100>; - interrupts = ; - ti,hwmods = "mmu_ipu2"; - #iommu-cells = <0>; - ti,iommu-bus-err-back; - status = "disabled"; + target-module@55082000 { + compatible = "ti,sysc-omap2", "ti,sysc"; + reg = <0x55082000 0x4>, + <0x55082010 0x4>, + <0x55082014 0x4>; + reg-names = "rev", "sysc", "syss"; + ti,sysc-sidle = , + , + ; + ti,sysc-mask = <(SYSC_OMAP2_CLOCKACTIVITY | + SYSC_OMAP2_SOFTRESET | + SYSC_OMAP2_AUTOIDLE)>; + clocks = <&ipu2_clkctrl DRA7_IPU2_MMU_IPU2_CLKCTRL 0>; + clock-names = "fck"; + resets = <&prm_core 2>; + reset-names = "rstctrl"; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0x0 0x55082000 0x100>; + + mmu_ipu2: mmu@0 { + compatible = "ti,dra7-iommu"; + reg = <0x0 0x100>; + interrupts = ; + #iommu-cells = <0>; + ti,iommu-bus-err-back; + }; }; abb_mpu: regulator-abb-mpu { From patchwork Wed Aug 28 07:56:42 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Tero Kristo X-Patchwork-Id: 11118117 Return-Path: Received: from mail.kernel.org (pdx-korg-mail-1.web.codeaurora.org [172.30.200.123]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id F2EDB1398 for ; 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Wed, 28 Aug 2019 02:57:08 -0500 From: Tero Kristo To: , CC: , Subject: [PATCH 08/10] ARM: dts: dra74x: convert IOMMUs to use ti-sysc Date: Wed, 28 Aug 2019 10:56:42 +0300 Message-ID: <20190828075644.4493-9-t-kristo@ti.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20190828075644.4493-1-t-kristo@ti.com> References: <20190828075644.4493-1-t-kristo@ti.com> MIME-Version: 1.0 X-EXCLAIMER-MD-CONFIG: e1e8a2fd-e40a-4ac6-ac9b-f7e9cc9ee180 Sender: linux-omap-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-omap@vger.kernel.org Convert dra74x IOMMUs to use ti-sysc instead of legacy omap-hwmod based implementation. Enable the IOMMUs also while doing this. Signed-off-by: Tero Kristo --- arch/arm/boot/dts/dra74x.dtsi | 71 +++++++++++++++++++++++++++-------- 1 file changed, 55 insertions(+), 16 deletions(-) diff --git a/arch/arm/boot/dts/dra74x.dtsi b/arch/arm/boot/dts/dra74x.dtsi index d1b5b76bc5a8..c5abc436ca1f 100644 --- a/arch/arm/boot/dts/dra74x.dtsi +++ b/arch/arm/boot/dts/dra74x.dtsi @@ -66,24 +66,63 @@ }; }; - mmu0_dsp2: mmu@41501000 { - compatible = "ti,dra7-dsp-iommu"; - reg = <0x41501000 0x100>; - interrupts = ; - ti,hwmods = "mmu0_dsp2"; - #iommu-cells = <0>; - ti,syscon-mmuconfig = <&dsp2_system 0x0>; - status = "disabled"; + target-module@41501000 { + compatible = "ti,sysc-omap2", "ti,sysc"; + reg = <0x41501000 0x4>, + <0x41501010 0x4>, + <0x41501014 0x4>; + reg-names = "rev", "sysc", "syss"; + ti,sysc-sidle = , + , + ; + ti,sysc-mask = <(SYSC_OMAP2_CLOCKACTIVITY | + SYSC_OMAP2_SOFTRESET | + SYSC_OMAP2_AUTOIDLE)>; + clocks = <&dsp2_clkctrl DRA7_DSP2_MMU0_DSP2_CLKCTRL 0>; + clock-names = "fck"; + resets = <&prm_dsp2 1>; + reset-names = "rstctrl"; + ranges = <0x0 0x41501000 0x1000>; + #size-cells = <1>; + #address-cells = <1>; + + mmu0_dsp2: mmu@0 { + compatible = "ti,dra7-dsp-iommu"; + reg = <0x0 0x100>; + interrupts = ; + #iommu-cells = <0>; + ti,syscon-mmuconfig = <&dsp2_system 0x0>; + }; }; - mmu1_dsp2: mmu@41502000 { - compatible = "ti,dra7-dsp-iommu"; - reg = <0x41502000 0x100>; - interrupts = ; - ti,hwmods = "mmu1_dsp2"; - #iommu-cells = <0>; - ti,syscon-mmuconfig = <&dsp2_system 0x1>; - status = "disabled"; + target-module@41502000 { + compatible = "ti,sysc-omap2", "ti,sysc"; + reg = <0x41502000 0x4>, + <0x41502010 0x4>, + <0x41502014 0x4>; + reg-names = "rev", "sysc", "syss"; + ti,sysc-sidle = , + , + ; + ti,sysc-mask = <(SYSC_OMAP2_CLOCKACTIVITY | + SYSC_OMAP2_SOFTRESET | + SYSC_OMAP2_AUTOIDLE)>; + + clocks = <&dsp2_clkctrl DRA7_DSP2_MMU0_DSP2_CLKCTRL 0>; + clock-names = "fck"; + resets = <&prm_dsp2 1>; + reset-names = "rstctrl"; + ranges = <0x0 0x41502000 0x1000>; + #size-cells = <1>; + #address-cells = <1>; + + mmu1_dsp2: mmu@0 { + compatible = "ti,dra7-dsp-iommu"; + reg = <0x0 0x100>; + interrupts = ; + #iommu-cells = <0>; + ti,syscon-mmuconfig = <&dsp2_system 0x1>; + }; }; }; }; From patchwork Wed Aug 28 07:56:43 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Tero Kristo X-Patchwork-Id: 11118121 Return-Path: Received: from mail.kernel.org (pdx-korg-mail-1.web.codeaurora.org [172.30.200.123]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id AAC8C1395 for ; Wed, 28 Aug 2019 07:57:16 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.kernel.org (Postfix) with ESMTP id 8C1CB22CF5 for ; Wed, 28 Aug 2019 07:57:16 +0000 (UTC) Authentication-Results: mail.kernel.org; dkim=pass (1024-bit key) header.d=ti.com header.i=@ti.com header.b="WTjatuQZ" Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1726437AbfH1H5Q (ORCPT ); Wed, 28 Aug 2019 03:57:16 -0400 Received: from lelv0143.ext.ti.com ([198.47.23.248]:37178 "EHLO lelv0143.ext.ti.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1726432AbfH1H5P (ORCPT ); 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Wed, 28 Aug 2019 02:57:10 -0500 Received: from sokoban.bb.dnainternet.fi (ileax41-snat.itg.ti.com [10.172.224.153]) by lelv0327.itg.ti.com (8.15.2/8.15.2) with ESMTP id x7S7uuFs107124; Wed, 28 Aug 2019 02:57:09 -0500 From: Tero Kristo To: , CC: , Subject: [PATCH 09/10] ARM: dts: omap4: convert IOMMUs to use ti-sysc Date: Wed, 28 Aug 2019 10:56:43 +0300 Message-ID: <20190828075644.4493-10-t-kristo@ti.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20190828075644.4493-1-t-kristo@ti.com> References: <20190828075644.4493-1-t-kristo@ti.com> MIME-Version: 1.0 X-EXCLAIMER-MD-CONFIG: e1e8a2fd-e40a-4ac6-ac9b-f7e9cc9ee180 Sender: linux-omap-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-omap@vger.kernel.org Convert omap4 IOMMUs to use ti-sysc instead of legacy omap-hwmod based implementation. Enable the IOMMUs also while doing this. Signed-off-by: Tero Kristo --- arch/arm/boot/dts/omap4-l4.dtsi | 11 ++++++--- arch/arm/boot/dts/omap4.dtsi | 43 +++++++++++++++++++++------------ 2 files changed, 36 insertions(+), 18 deletions(-) diff --git a/arch/arm/boot/dts/omap4-l4.dtsi b/arch/arm/boot/dts/omap4-l4.dtsi index 0977bc39955b..7eca6cdbbdd9 100644 --- a/arch/arm/boot/dts/omap4-l4.dtsi +++ b/arch/arm/boot/dts/omap4-l4.dtsi @@ -321,7 +321,6 @@ target-module@66000 { /* 0x4a066000, ap 25 26.0 */ compatible = "ti,sysc-omap2", "ti,sysc"; - ti,hwmods = "mmu_dsp"; reg = <0x66000 0x4>, <0x66010 0x4>, <0x66014 0x4>; @@ -335,12 +334,18 @@ /* Domains (V, P, C): iva, tesla_pwrdm, tesla_clkdm */ clocks = <&tesla_clkctrl OMAP4_DSP_CLKCTRL 0>; clock-names = "fck"; + resets = <&prm_tesla 1>; + reset-names = "rstctrl"; #address-cells = <1>; #size-cells = <1>; ranges = <0x0 0x66000 0x1000>; - /* mmu_dsp cannot be moved before reset driver */ - status = "disabled"; + mmu_dsp: mmu@0 { + compatible = "ti,omap4-iommu"; + reg = <0x0 0x100>; + interrupts = ; + #iommu-cells = <0>; + }; }; }; diff --git a/arch/arm/boot/dts/omap4.dtsi b/arch/arm/boot/dts/omap4.dtsi index e377f66fc322..f28fe1c36b0c 100644 --- a/arch/arm/boot/dts/omap4.dtsi +++ b/arch/arm/boot/dts/omap4.dtsi @@ -173,14 +173,6 @@ #gpio-cells = <2>; }; - mmu_dsp: mmu@4a066000 { - compatible = "ti,omap4-iommu"; - reg = <0x4a066000 0x100>; - interrupts = ; - ti,hwmods = "mmu_dsp"; - #iommu-cells = <0>; - }; - target-module@52000000 { compatible = "ti,sysc-omap4", "ti,sysc"; ti,hwmods = "iss"; @@ -206,14 +198,35 @@ /* No child device binding, driver in staging */ }; - mmu_ipu: mmu@55082000 { - compatible = "ti,omap4-iommu"; - reg = <0x55082000 0x100>; - interrupts = ; - ti,hwmods = "mmu_ipu"; - #iommu-cells = <0>; - ti,iommu-bus-err-back; + target-module@55082000 { + compatible = "ti,sysc-omap2", "ti,sysc"; + reg = <0x55082000 0x4>, + <0x55082010 0x4>, + <0x55082014 0x4>; + reg-names = "rev", "sysc", "syss"; + ti,sysc-sidle = , + , + ; + ti,sysc-mask = <(SYSC_OMAP2_CLOCKACTIVITY | + SYSC_OMAP2_SOFTRESET | + SYSC_OMAP2_AUTOIDLE)>; + clocks = <&ducati_clkctrl OMAP4_IPU_CLKCTRL 0>; + clock-names = "fck"; + resets = <&prm_core 2>; + reset-names = "rstctrl"; + ranges = <0x0 0x55082000 0x100>; + #size-cells = <1>; + #address-cells = <1>; + + mmu_ipu: mmu@0 { + compatible = "ti,omap4-iommu"; + reg = <0x0 0x100>; + interrupts = ; + #iommu-cells = <0>; + ti,iommu-bus-err-back; + }; }; + target-module@4012c000 { compatible = "ti,sysc-omap4", "ti,sysc"; ti,hwmods = "slimbus1"; From patchwork Wed Aug 28 07:56:44 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Tero Kristo X-Patchwork-Id: 11118125 Return-Path: Received: from mail.kernel.org (pdx-korg-mail-1.web.codeaurora.org [172.30.200.123]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id 063A41398 for ; Wed, 28 Aug 2019 07:57:32 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.kernel.org (Postfix) with ESMTP id D9623217F5 for ; Wed, 28 Aug 2019 07:57:31 +0000 (UTC) Authentication-Results: mail.kernel.org; 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Wed, 28 Aug 2019 02:57:27 -0500 Received: from DLEE105.ent.ti.com (157.170.170.35) by DLEE113.ent.ti.com (157.170.170.24) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.1713.5; Wed, 28 Aug 2019 02:57:26 -0500 Received: from lelv0327.itg.ti.com (10.180.67.183) by DLEE105.ent.ti.com (157.170.170.35) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.1713.5 via Frontend Transport; Wed, 28 Aug 2019 02:57:27 -0500 Received: from sokoban.bb.dnainternet.fi (ileax41-snat.itg.ti.com [10.172.224.153]) by lelv0327.itg.ti.com (8.15.2/8.15.2) with ESMTP id x7S7uuFt107124; Wed, 28 Aug 2019 02:57:10 -0500 From: Tero Kristo To: , CC: , Subject: [PATCH 10/10] ARM: dts: omap5: convert IOMMUs to use ti-sysc Date: Wed, 28 Aug 2019 10:56:44 +0300 Message-ID: <20190828075644.4493-11-t-kristo@ti.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20190828075644.4493-1-t-kristo@ti.com> References: <20190828075644.4493-1-t-kristo@ti.com> MIME-Version: 1.0 X-EXCLAIMER-MD-CONFIG: e1e8a2fd-e40a-4ac6-ac9b-f7e9cc9ee180 Sender: linux-omap-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-omap@vger.kernel.org Convert omap5 IOMMUs to use ti-sysc instead of legacy omap-hwmod based implementation. Enable the IOMMUs also while doing this. Signed-off-by: Tero Kristo --- arch/arm/boot/dts/omap5-l4.dtsi | 11 ++++++--- arch/arm/boot/dts/omap5.dtsi | 40 +++++++++++++++++++++------------ 2 files changed, 34 insertions(+), 17 deletions(-) diff --git a/arch/arm/boot/dts/omap5-l4.dtsi b/arch/arm/boot/dts/omap5-l4.dtsi index 0960348002ad..80c2d2fcc03b 100644 --- a/arch/arm/boot/dts/omap5-l4.dtsi +++ b/arch/arm/boot/dts/omap5-l4.dtsi @@ -349,7 +349,6 @@ target-module@66000 { /* 0x4a066000, ap 23 0a.0 */ compatible = "ti,sysc-omap2", "ti,sysc"; - ti,hwmods = "mmu_dsp"; reg = <0x66000 0x4>, <0x66010 0x4>, <0x66014 0x4>; @@ -364,12 +363,18 @@ /* Domains (V, P, C): mm, dsp_pwrdm, dsp_clkdm */ clocks = <&dsp_clkctrl OMAP5_MMU_DSP_CLKCTRL 0>; clock-names = "fck"; + resets = <&prm_dsp 1>; + reset-names = "rstctrl"; #address-cells = <1>; #size-cells = <1>; ranges = <0x0 0x66000 0x1000>; - /* mmu_dsp cannot be moved before reset driver */ - status = "disabled"; + mmu_dsp: mmu@0 { + compatible = "ti,omap4-iommu"; + reg = <0x0 0x100>; + interrupts = ; + #iommu-cells = <0>; + }; }; target-module@70000 { /* 0x4a070000, ap 79 2e.0 */ diff --git a/arch/arm/boot/dts/omap5.dtsi b/arch/arm/boot/dts/omap5.dtsi index c8bde171a949..05929d59b0af 100644 --- a/arch/arm/boot/dts/omap5.dtsi +++ b/arch/arm/boot/dts/omap5.dtsi @@ -186,21 +186,33 @@ #gpio-cells = <2>; }; - mmu_dsp: mmu@4a066000 { - compatible = "ti,omap4-iommu"; - reg = <0x4a066000 0x100>; - interrupts = ; - ti,hwmods = "mmu_dsp"; - #iommu-cells = <0>; - }; + target-module@55082000 { + compatible = "ti,sysc-omap2", "ti,sysc"; + reg = <0x55082000 0x4>, + <0x55082010 0x4>, + <0x55082014 0x4>; + reg-names = "rev", "sysc", "syss"; + ti,sysc-sidle = , + , + ; + ti,sysc-mask = <(SYSC_OMAP2_CLOCKACTIVITY | + SYSC_OMAP2_SOFTRESET | + SYSC_OMAP2_AUTOIDLE)>; + clocks = <&ipu_clkctrl OMAP5_MMU_IPU_CLKCTRL 0>; + clock-names = "fck"; + resets = <&prm_core 2>; + reset-names = "rstctrl"; + ranges = <0x0 0x55082000 0x100>; + #size-cells = <1>; + #address-cells = <1>; - mmu_ipu: mmu@55082000 { - compatible = "ti,omap4-iommu"; - reg = <0x55082000 0x100>; - interrupts = ; - ti,hwmods = "mmu_ipu"; - #iommu-cells = <0>; - ti,iommu-bus-err-back; + mmu_ipu: mmu@0 { + compatible = "ti,omap4-iommu"; + reg = <0x0 0x100>; + interrupts = ; + #iommu-cells = <0>; + ti,iommu-bus-err-back; + }; }; dmm@4e000000 {