From patchwork Thu Aug 29 18:11:50 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Lina Iyer X-Patchwork-Id: 11122359 Return-Path: Received: from mail.kernel.org (pdx-korg-mail-1.web.codeaurora.org [172.30.200.123]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id 0EA5C1399 for ; Thu, 29 Aug 2019 18:47:36 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.kernel.org (Postfix) with ESMTP id DE8EA21874 for ; Thu, 29 Aug 2019 18:47:35 +0000 (UTC) Authentication-Results: mail.kernel.org; dkim=fail reason="key not found in DNS" (0-bit key) header.d=codeaurora.org header.i=@codeaurora.org header.b="ov21A1G4"; dkim=fail reason="key not found in DNS" (0-bit key) header.d=codeaurora.org header.i=@codeaurora.org header.b="E/u4IlOj" Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1727146AbfH2Sre (ORCPT ); Thu, 29 Aug 2019 14:47:34 -0400 Received: from smtp.codeaurora.org ([198.145.29.96]:35714 "EHLO smtp.codeaurora.org" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1727073AbfH2Sre (ORCPT ); Thu, 29 Aug 2019 14:47:34 -0400 Received: by smtp.codeaurora.org (Postfix, from userid 1000) id E556A694B2; Thu, 29 Aug 2019 18:12:14 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=codeaurora.org; s=default; t=1567104453; bh=aZZpAgEtM8Id45U6CuX5S0qyC0RSjoNEmA5BfPWcAGg=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=ov21A1G42E7QKGF9E4OUvXkh3mhX1MPH0SYwpdYsL2djJExm/+HczxiBWNsKcaSEU YJ3SYl8950Esrr2pVzADwlmyK3E20csr/ih4xF4XdTTx/A+isJywHRbEpbx3Zc4zgI FKMVlyFWRBbBBg+/2/hNKsmTxAnzDjMeHwc+Zwmg= X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on pdx-caf-mail.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-2.7 required=2.0 tests=ALL_TRUSTED,BAYES_00, DKIM_INVALID,DKIM_SIGNED,SPF_NONE autolearn=no autolearn_force=no version=3.4.0 Received: from codeaurora.org (i-global254.qualcomm.com [199.106.103.254]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-SHA256 (128/128 bits)) (No client certificate requested) (Authenticated sender: ilina@smtp.codeaurora.org) by smtp.codeaurora.org (Postfix) with ESMTPSA id D47C0687FA; Thu, 29 Aug 2019 18:12:11 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=codeaurora.org; s=default; t=1567102333; bh=aZZpAgEtM8Id45U6CuX5S0qyC0RSjoNEmA5BfPWcAGg=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=E/u4IlOjRFXMG+Q6scsxflg2M9dogTX+2cs3a2prPwC7a0sHKvKASBxYqzgWs6ZZB oGy5VLDwJSqyPoPTWzb5cpt1CpgAfctgiPb/lsz8NMJ7S9urhyTwulshdDw4fvgllX votNpEZk5O1ZeemKz1gEq+LPOAkv5s+F6+zgQOH0= DMARC-Filter: OpenDMARC Filter v1.3.2 smtp.codeaurora.org D47C0687FA Authentication-Results: pdx-caf-mail.web.codeaurora.org; dmarc=none (p=none dis=none) header.from=codeaurora.org Authentication-Results: pdx-caf-mail.web.codeaurora.org; spf=none smtp.mailfrom=ilina@codeaurora.org From: Lina Iyer To: swboyd@chromium.org, evgreen@chromium.org, marc.zyngier@arm.com, linus.walleij@linaro.org Cc: linux-kernel@vger.kernel.org, linux-arm-msm@vger.kernel.org, bjorn.andersson@linaro.org, mkshah@codeaurora.org, linux-gpio@vger.kernel.org, rnayak@codeaurora.org, Lina Iyer Subject: [PATCH RFC 01/14] irqdomain: add bus token DOMAIN_BUS_WAKEUP Date: Thu, 29 Aug 2019 12:11:50 -0600 Message-Id: <20190829181203.2660-2-ilina@codeaurora.org> X-Mailer: git-send-email 2.22.0 In-Reply-To: <20190829181203.2660-1-ilina@codeaurora.org> References: <20190829181203.2660-1-ilina@codeaurora.org> MIME-Version: 1.0 Sender: linux-arm-msm-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-arm-msm@vger.kernel.org A single controller can handle normal interrupts and wake-up interrupts independently, with a different numbering space. It is thus crucial to allow the driver for such a controller discriminate between the two. A simple way to do so is to tag the wake-up irqdomain with a "bus token" that indicates the wake-up domain. This slightly abuses the notion of bus, but also radically simplifies the design of such a driver. Between two evils, we choose the least damaging. Suggested-by: Stephen Boyd Signed-off-by: Lina Iyer --- include/linux/irqdomain.h | 1 + 1 file changed, 1 insertion(+) diff --git a/include/linux/irqdomain.h b/include/linux/irqdomain.h index 07ec8b390161..cc846abeff28 100644 --- a/include/linux/irqdomain.h +++ b/include/linux/irqdomain.h @@ -83,6 +83,7 @@ enum irq_domain_bus_token { DOMAIN_BUS_IPI, DOMAIN_BUS_FSL_MC_MSI, DOMAIN_BUS_TI_SCI_INTA_MSI, + DOMAIN_BUS_WAKEUP, }; /** From patchwork Thu Aug 29 18:11:51 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Lina Iyer X-Patchwork-Id: 11122203 Return-Path: Received: from mail.kernel.org (pdx-korg-mail-1.web.codeaurora.org [172.30.200.123]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id 0431714D5 for ; Thu, 29 Aug 2019 18:22:54 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.kernel.org (Postfix) with ESMTP id D42DB21726 for ; Thu, 29 Aug 2019 18:22:53 +0000 (UTC) Authentication-Results: mail.kernel.org; dkim=fail reason="key not found in DNS" (0-bit key) header.d=codeaurora.org header.i=@codeaurora.org header.b="VtycVrSA"; dkim=fail reason="key not found in DNS" (0-bit key) header.d=codeaurora.org header.i=@codeaurora.org header.b="RPMpETOq" Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1729669AbfH2SWs (ORCPT ); Thu, 29 Aug 2019 14:22:48 -0400 Received: from smtp.codeaurora.org ([198.145.29.96]:53514 "EHLO smtp.codeaurora.org" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1728700AbfH2SWq (ORCPT ); Thu, 29 Aug 2019 14:22:46 -0400 Received: by smtp.codeaurora.org (Postfix, from userid 1000) id 328F267898; Thu, 29 Aug 2019 18:12:16 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=codeaurora.org; s=default; t=1567102965; bh=FeFaJUoDeHdLOh2OaUz0TWmkbjPXVH4svhWA764YwBA=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=VtycVrSAdkukL9EXA/Nj5URdtARJbT4f2tnn+5EZUFMr7WSmXL+rlzSDC7/jZnW6q PmWt/aQspvB6mKZzr31y7ErivhOdwkR7I56EWnlrgWsnZsomBoI5zd1EM3HFSzJTHu f0PgxHacny5Q09voOOsLnIBMP3UelpPagJ5nT1FU= X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on pdx-caf-mail.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-2.7 required=2.0 tests=ALL_TRUSTED,BAYES_00, DKIM_INVALID,DKIM_SIGNED,SPF_NONE autolearn=no autolearn_force=no version=3.4.0 Received: from codeaurora.org (i-global254.qualcomm.com [199.106.103.254]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-SHA256 (128/128 bits)) (No client certificate requested) (Authenticated sender: ilina@smtp.codeaurora.org) by smtp.codeaurora.org (Postfix) with ESMTPSA id 74C0C6883B; Thu, 29 Aug 2019 18:12:13 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=codeaurora.org; s=default; t=1567102334; bh=FeFaJUoDeHdLOh2OaUz0TWmkbjPXVH4svhWA764YwBA=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=RPMpETOqN+zUgVJ54I7e6zv9LkccOW3ztM6OOrzzC/Te80+y/+TfMkno7u2x1u+eW 9yszoW44Ac6fym1pyMb3Kih+1Q9m07v+wgxqjqTMOrnmOAUN37/L63zmhihJPgyE1g WgnM+oaXtWXMPeroZXKYlb2UcWn2urpwfCUkBwQA= DMARC-Filter: OpenDMARC Filter v1.3.2 smtp.codeaurora.org 74C0C6883B Authentication-Results: pdx-caf-mail.web.codeaurora.org; dmarc=none (p=none dis=none) header.from=codeaurora.org Authentication-Results: pdx-caf-mail.web.codeaurora.org; spf=none smtp.mailfrom=ilina@codeaurora.org From: Lina Iyer To: swboyd@chromium.org, evgreen@chromium.org, marc.zyngier@arm.com, linus.walleij@linaro.org Cc: linux-kernel@vger.kernel.org, linux-arm-msm@vger.kernel.org, bjorn.andersson@linaro.org, mkshah@codeaurora.org, linux-gpio@vger.kernel.org, rnayak@codeaurora.org, Lina Iyer Subject: [PATCH RFC 02/14] drivers: irqchip: pdc: Do not toggle IRQ_ENABLE during mask/unmask Date: Thu, 29 Aug 2019 12:11:51 -0600 Message-Id: <20190829181203.2660-3-ilina@codeaurora.org> X-Mailer: git-send-email 2.22.0 In-Reply-To: <20190829181203.2660-1-ilina@codeaurora.org> References: <20190829181203.2660-1-ilina@codeaurora.org> MIME-Version: 1.0 Sender: linux-arm-msm-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-arm-msm@vger.kernel.org When an interrupt is to be serviced, the convention is to mask the interrupt at the chip and unmask after servicing the interrupt. Enabling and disabling the interrupt at the PDC irqchip causes an interrupt storm due to the way dual edge interrupts are handled in hardware. Skip configuring the PDC when the IRQ is masked and unmasked, instead use the irq_enable/irq_disable callbacks to toggle the IRQ_ENABLE register at the PDC. The PDC's IRQ_ENABLE register is only used during the monitoring mode when the system is asleep and is not needed for active mode detection. Signed-off-by: Lina Iyer --- drivers/irqchip/qcom-pdc.c | 16 ++++++++++++++-- 1 file changed, 14 insertions(+), 2 deletions(-) diff --git a/drivers/irqchip/qcom-pdc.c b/drivers/irqchip/qcom-pdc.c index faa7d61b9d6c..338fae604af5 100644 --- a/drivers/irqchip/qcom-pdc.c +++ b/drivers/irqchip/qcom-pdc.c @@ -63,15 +63,25 @@ static void pdc_enable_intr(struct irq_data *d, bool on) raw_spin_unlock(&pdc_lock); } -static void qcom_pdc_gic_mask(struct irq_data *d) +static void qcom_pdc_gic_disable(struct irq_data *d) { pdc_enable_intr(d, false); + irq_chip_disable_parent(d); +} + +static void qcom_pdc_gic_enable(struct irq_data *d) +{ + pdc_enable_intr(d, true); + irq_chip_enable_parent(d); +} + +static void qcom_pdc_gic_mask(struct irq_data *d) +{ irq_chip_mask_parent(d); } static void qcom_pdc_gic_unmask(struct irq_data *d) { - pdc_enable_intr(d, true); irq_chip_unmask_parent(d); } @@ -148,6 +158,8 @@ static struct irq_chip qcom_pdc_gic_chip = { .irq_eoi = irq_chip_eoi_parent, .irq_mask = qcom_pdc_gic_mask, .irq_unmask = qcom_pdc_gic_unmask, + .irq_disable = qcom_pdc_gic_disable, + .irq_enable = qcom_pdc_gic_enable, .irq_retrigger = irq_chip_retrigger_hierarchy, .irq_set_type = qcom_pdc_gic_set_type, .flags = IRQCHIP_MASK_ON_SUSPEND | From patchwork Thu Aug 29 18:11:52 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Lina Iyer X-Patchwork-Id: 11122319 Return-Path: Received: from mail.kernel.org (pdx-korg-mail-1.web.codeaurora.org [172.30.200.123]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id 747C41398 for ; Thu, 29 Aug 2019 18:31:43 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.kernel.org (Postfix) with ESMTP id 486D521726 for ; Thu, 29 Aug 2019 18:31:43 +0000 (UTC) Authentication-Results: mail.kernel.org; dkim=fail reason="key not found in DNS" (0-bit key) header.d=codeaurora.org header.i=@codeaurora.org header.b="mbPBUhs7"; dkim=fail reason="key not found in DNS" (0-bit key) header.d=codeaurora.org header.i=@codeaurora.org header.b="aMOVPZYk" Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1728826AbfH2SaI (ORCPT ); Thu, 29 Aug 2019 14:30:08 -0400 Received: from smtp.codeaurora.org ([198.145.29.96]:45574 "EHLO smtp.codeaurora.org" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1727673AbfH2SaI (ORCPT ); Thu, 29 Aug 2019 14:30:08 -0400 Received: by smtp.codeaurora.org (Postfix, from userid 1000) id 312EC681CA; Thu, 29 Aug 2019 18:12:18 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=codeaurora.org; s=default; t=1567103407; bh=PuRxldOBN+wEmnBAMw0JNVPaMahVZnx4ztwUFy/rSuM=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=mbPBUhs7fko5DmEDXeobtJDxqpRkMLTpBj+2pp2AaSH2q2/x/O2zy2YQ+kybYCePe 6/MOPorC+mEEvfAK+08vf2VkBjMO6DQi16vqZVsSiWd4l/rDoenS20hTT7BShF+v/N gylKW46LJHaCiM5iBRMi0a1ysNd7xaSjvSotMcjU= X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on pdx-caf-mail.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-2.7 required=2.0 tests=ALL_TRUSTED,BAYES_00, DKIM_INVALID,DKIM_SIGNED,SPF_NONE autolearn=no autolearn_force=no version=3.4.0 Received: from codeaurora.org (i-global254.qualcomm.com [199.106.103.254]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-SHA256 (128/128 bits)) (No client certificate requested) (Authenticated sender: ilina@smtp.codeaurora.org) by smtp.codeaurora.org (Postfix) with ESMTPSA id 3726568867; Thu, 29 Aug 2019 18:12:15 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=codeaurora.org; s=default; t=1567102336; bh=PuRxldOBN+wEmnBAMw0JNVPaMahVZnx4ztwUFy/rSuM=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=aMOVPZYkhWyJP3HYnxpyCW50jxxsg+s3Mk4ipgWM7vSKJF+wBZWkLSyXf5ID/rwuO rjxRqP2vmwPc5J8NwelznsDHL7a6vaNi4/u6v3S+JZZaHl3cIhlvwZSLHvIbUJGtSY 5kZy3SqG/Rair3s+2L38A/HdBLGGt8O8DHXli0WM= DMARC-Filter: OpenDMARC Filter v1.3.2 smtp.codeaurora.org 3726568867 Authentication-Results: pdx-caf-mail.web.codeaurora.org; dmarc=none (p=none dis=none) header.from=codeaurora.org Authentication-Results: pdx-caf-mail.web.codeaurora.org; spf=none smtp.mailfrom=ilina@codeaurora.org From: Lina Iyer To: swboyd@chromium.org, evgreen@chromium.org, marc.zyngier@arm.com, linus.walleij@linaro.org Cc: linux-kernel@vger.kernel.org, linux-arm-msm@vger.kernel.org, bjorn.andersson@linaro.org, mkshah@codeaurora.org, linux-gpio@vger.kernel.org, rnayak@codeaurora.org, Lina Iyer Subject: [PATCH RFC 03/14] drivers: irqchip: add PDC irqdomain for wakeup capable GPIOs Date: Thu, 29 Aug 2019 12:11:52 -0600 Message-Id: <20190829181203.2660-4-ilina@codeaurora.org> X-Mailer: git-send-email 2.22.0 In-Reply-To: <20190829181203.2660-1-ilina@codeaurora.org> References: <20190829181203.2660-1-ilina@codeaurora.org> MIME-Version: 1.0 Sender: linux-arm-msm-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-arm-msm@vger.kernel.org Introduce a new domain for wakeup capable GPIOs. The domain can be requested using the bus token DOMAIN_BUS_WAKEUP. In the following patches, we will specify PDC as the wakeup-parent for the TLMM GPIO irqchip. Requesting a wakeup GPIO will setup the GPIO and the corresponding PDC interrupt as its parent. Co-developed-by: Stephen Boyd Signed-off-by: Lina Iyer Signed-off-by: Stephen Boyd --- drivers/irqchip/qcom-pdc.c | 104 ++++++++++++++++++++++++++++++++--- include/linux/soc/qcom/irq.h | 34 ++++++++++++ 2 files changed, 129 insertions(+), 9 deletions(-) create mode 100644 include/linux/soc/qcom/irq.h diff --git a/drivers/irqchip/qcom-pdc.c b/drivers/irqchip/qcom-pdc.c index 338fae604af5..ad1faf634bcf 100644 --- a/drivers/irqchip/qcom-pdc.c +++ b/drivers/irqchip/qcom-pdc.c @@ -13,12 +13,13 @@ #include #include #include +#include #include -#include #include #include #define PDC_MAX_IRQS 126 +#define PDC_MAX_GPIO_IRQS 256 #define CLEAR_INTR(reg, intr) (reg & ~(1 << intr)) #define ENABLE_INTR(reg, intr) (reg | (1 << intr)) @@ -26,6 +27,8 @@ #define IRQ_ENABLE_BANK 0x10 #define IRQ_i_CFG 0x110 +#define PDC_NO_PARENT_IRQ ~0UL + struct pdc_pin_region { u32 pin_base; u32 parent_base; @@ -65,23 +68,35 @@ static void pdc_enable_intr(struct irq_data *d, bool on) static void qcom_pdc_gic_disable(struct irq_data *d) { + if (d->hwirq == GPIO_NO_WAKE_IRQ) + return; + pdc_enable_intr(d, false); irq_chip_disable_parent(d); } static void qcom_pdc_gic_enable(struct irq_data *d) { + if (d->hwirq == GPIO_NO_WAKE_IRQ) + return; + pdc_enable_intr(d, true); irq_chip_enable_parent(d); } static void qcom_pdc_gic_mask(struct irq_data *d) { + if (d->hwirq == GPIO_NO_WAKE_IRQ) + return; + irq_chip_mask_parent(d); } static void qcom_pdc_gic_unmask(struct irq_data *d) { + if (d->hwirq == GPIO_NO_WAKE_IRQ) + return; + irq_chip_unmask_parent(d); } @@ -124,6 +139,9 @@ static int qcom_pdc_gic_set_type(struct irq_data *d, unsigned int type) int pin_out = d->hwirq; enum pdc_irq_config_bits pdc_type; + if (pin_out == GPIO_NO_WAKE_IRQ) + return 0; + switch (type) { case IRQ_TYPE_EDGE_RISING: pdc_type = PDC_EDGE_RISING; @@ -181,8 +199,7 @@ static irq_hw_number_t get_parent_hwirq(int pin) return (region->parent_base + pin - region->pin_base); } - WARN_ON(1); - return ~0UL; + return PDC_NO_PARENT_IRQ; } static int qcom_pdc_translate(struct irq_domain *d, struct irq_fwspec *fwspec, @@ -211,17 +228,17 @@ static int qcom_pdc_alloc(struct irq_domain *domain, unsigned int virq, ret = qcom_pdc_translate(domain, fwspec, &hwirq, &type); if (ret) - return -EINVAL; - - parent_hwirq = get_parent_hwirq(hwirq); - if (parent_hwirq == ~0UL) - return -EINVAL; + return ret; ret = irq_domain_set_hwirq_and_chip(domain, virq, hwirq, &qcom_pdc_gic_chip, NULL); if (ret) return ret; + parent_hwirq = get_parent_hwirq(hwirq); + if (parent_hwirq == PDC_NO_PARENT_IRQ) + return 0; + if (type & IRQ_TYPE_EDGE_BOTH) type = IRQ_TYPE_EDGE_RISING; @@ -244,6 +261,60 @@ static const struct irq_domain_ops qcom_pdc_ops = { .free = irq_domain_free_irqs_common, }; +static int qcom_pdc_gpio_alloc(struct irq_domain *domain, unsigned int virq, + unsigned int nr_irqs, void *data) +{ + struct irq_fwspec *fwspec = data; + struct irq_fwspec parent_fwspec; + irq_hw_number_t hwirq, parent_hwirq; + unsigned int type; + int ret; + + ret = qcom_pdc_translate(domain, fwspec, &hwirq, &type); + if (ret) + return ret; + + ret = irq_domain_set_hwirq_and_chip(domain, virq, hwirq, + &qcom_pdc_gic_chip, NULL); + if (ret) + return ret; + + if (hwirq == GPIO_NO_WAKE_IRQ) + return 0; + + parent_hwirq = get_parent_hwirq(hwirq); + if (parent_hwirq == PDC_NO_PARENT_IRQ) + return 0; + + if (type & IRQ_TYPE_EDGE_BOTH) + type = IRQ_TYPE_EDGE_RISING; + + if (type & IRQ_TYPE_LEVEL_MASK) + type = IRQ_TYPE_LEVEL_HIGH; + + parent_fwspec.fwnode = domain->parent->fwnode; + parent_fwspec.param_count = 3; + parent_fwspec.param[0] = 0; + parent_fwspec.param[1] = parent_hwirq; + parent_fwspec.param[2] = type; + + return irq_domain_alloc_irqs_parent(domain, virq, nr_irqs, + &parent_fwspec); +} + +static int qcom_pdc_gpio_domain_select(struct irq_domain *d, + struct irq_fwspec *fwspec, + enum irq_domain_bus_token bus_token) +{ + return (bus_token == DOMAIN_BUS_WAKEUP); +} + +static const struct irq_domain_ops qcom_pdc_gpio_ops = { + .select = qcom_pdc_gpio_domain_select, + .alloc = qcom_pdc_gpio_alloc, + .free = irq_domain_free_irqs_common, +}; + static int pdc_setup_pin_mapping(struct device_node *np) { int ret, n; @@ -282,7 +353,7 @@ static int pdc_setup_pin_mapping(struct device_node *np) static int qcom_pdc_init(struct device_node *node, struct device_node *parent) { - struct irq_domain *parent_domain, *pdc_domain; + struct irq_domain *parent_domain, *pdc_domain, *pdc_gpio_domain; int ret; pdc_base = of_iomap(node, 0); @@ -313,8 +384,23 @@ static int qcom_pdc_init(struct device_node *node, struct device_node *parent) goto fail; } + pdc_gpio_domain = irq_domain_create_hierarchy(parent_domain, + IRQ_DOMAIN_FLAG_QCOM_PDC_WAKEUP, + PDC_MAX_GPIO_IRQS, + of_fwnode_handle(node), + &qcom_pdc_gpio_ops, NULL); + if (!pdc_gpio_domain) { + pr_err("%pOF: GIC domain add failed for GPIO domain\n", node); + ret = -ENOMEM; + goto remove; + } + + irq_domain_update_bus_token(pdc_gpio_domain, DOMAIN_BUS_WAKEUP); + return 0; +remove: + irq_domain_remove(pdc_domain); fail: kfree(pdc_region); iounmap(pdc_base); diff --git a/include/linux/soc/qcom/irq.h b/include/linux/soc/qcom/irq.h new file mode 100644 index 000000000000..73239917dc38 --- /dev/null +++ b/include/linux/soc/qcom/irq.h @@ -0,0 +1,34 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#ifndef __QCOM_IRQ_H +#define __QCOM_IRQ_H + +#include + +#define GPIO_NO_WAKE_IRQ ~0U + +/** + * QCOM specific IRQ domain flags that distinguishes the handling of wakeup + * capable interrupts by different interrupt controllers. + * + * IRQ_DOMAIN_FLAG_QCOM_PDC_WAKEUP: Line must be masked at TLMM and the + * interrupt configuration is done at PDC + * IRQ_DOMAIN_FLAG_QCOM_MPM_WAKEUP: Interrupt configuration is handled at TLMM + */ +#define IRQ_DOMAIN_FLAG_QCOM_PDC_WAKEUP (1 << 17) +#define IRQ_DOMAIN_FLAG_QCOM_MPM_WAKEUP (1 << 18) + +/** + * irq_domain_qcom_handle_wakeup: Return if the domain handles interrupt + * configuration + * @parent: irq domain + * + * This QCOM specific irq domain call returns if the interrupt controller + * requires the interrupt be masked at the child interrupt controller. + */ +static inline bool irq_domain_qcom_handle_wakeup(struct irq_domain *parent) +{ + return (parent->flags & IRQ_DOMAIN_FLAG_QCOM_PDC_WAKEUP); +} + +#endif From patchwork Thu Aug 29 18:11:53 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Lina Iyer X-Patchwork-Id: 11122347 Return-Path: Received: from mail.kernel.org (pdx-korg-mail-1.web.codeaurora.org [172.30.200.123]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id CA8071398 for ; Thu, 29 Aug 2019 18:41:52 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.kernel.org (Postfix) with ESMTP id A788421726 for ; Thu, 29 Aug 2019 18:41:52 +0000 (UTC) Authentication-Results: mail.kernel.org; dkim=fail reason="key not found in DNS" (0-bit key) header.d=codeaurora.org header.i=@codeaurora.org header.b="W+9l33i7"; dkim=fail reason="key not found in DNS" (0-bit key) header.d=codeaurora.org header.i=@codeaurora.org header.b="I/Lv8e+5" Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1727935AbfH2Slw (ORCPT ); Thu, 29 Aug 2019 14:41:52 -0400 Received: from smtp.codeaurora.org ([198.145.29.96]:49204 "EHLO smtp.codeaurora.org" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1727867AbfH2Slw (ORCPT ); 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Thu, 29 Aug 2019 18:12:16 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=codeaurora.org; s=default; t=1567102338; bh=idSCDDdET3/7wJntdfWeAGtzPidjabyISQCbpIXoF3g=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=I/Lv8e+5c+rWTsSEDw0Bdjk7jvYOk7c1fmLdoN0csf5ltHQlOWjNmK7Yt8cTRquSA TLdQdG1hZ67HLjAgM/ZFnhxlmx6mHMZoLUuyba8vTcGb5+dMw3WV17HXHnTo8Lyv7C gxvv0wyRY3WYmnZrCAmpDTj8m/huaiFtSLLX/Bhk= DMARC-Filter: OpenDMARC Filter v1.3.2 smtp.codeaurora.org CD8EB688BF Authentication-Results: pdx-caf-mail.web.codeaurora.org; dmarc=none (p=none dis=none) header.from=codeaurora.org Authentication-Results: pdx-caf-mail.web.codeaurora.org; spf=none smtp.mailfrom=ilina@codeaurora.org From: Lina Iyer To: swboyd@chromium.org, evgreen@chromium.org, marc.zyngier@arm.com, linus.walleij@linaro.org Cc: linux-kernel@vger.kernel.org, linux-arm-msm@vger.kernel.org, bjorn.andersson@linaro.org, mkshah@codeaurora.org, linux-gpio@vger.kernel.org, rnayak@codeaurora.org, Lina Iyer , devicetree@vger.kernel.org Subject: [PATCH RFC 04/14] of: irq: document properties for wakeup interrupt parent Date: Thu, 29 Aug 2019 12:11:53 -0600 Message-Id: <20190829181203.2660-5-ilina@codeaurora.org> X-Mailer: git-send-email 2.22.0 In-Reply-To: <20190829181203.2660-1-ilina@codeaurora.org> References: <20190829181203.2660-1-ilina@codeaurora.org> MIME-Version: 1.0 Sender: linux-arm-msm-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-arm-msm@vger.kernel.org Some interrupt controllers in a SoC, are always powered on and have a select interrupts routed to them, so that they can wakeup the SoC from suspend. Add wakeup-parent DT property to refer to these interrupt controllers. Cc: devicetree@vger.kernel.org Signed-off-by: Lina Iyer Reviewed-by: Rob Herring --- .../bindings/interrupt-controller/interrupts.txt | 13 +++++++++++++ 1 file changed, 13 insertions(+) diff --git a/Documentation/devicetree/bindings/interrupt-controller/interrupts.txt b/Documentation/devicetree/bindings/interrupt-controller/interrupts.txt index 8a3c40829899..c10e31050dd2 100644 --- a/Documentation/devicetree/bindings/interrupt-controller/interrupts.txt +++ b/Documentation/devicetree/bindings/interrupt-controller/interrupts.txt @@ -108,3 +108,16 @@ commonly used: sensitivity = <7>; }; }; + +3) Interrupt wakeup parent +-------------------------- + +Some interrupt controllers in a SoC, are always powered on and have a select +interrupts routed to them, so that they can wakeup the SoC from suspend. These +interrupt controllers do not fall into the category of a parent interrupt +controller and can be specified by the "wakeup-parent" property and contain a +single phandle referring to the wakeup capable interrupt controller. + + Example: + wakeup-parent = <&pdc_intc>; + From patchwork Thu Aug 29 18:11:54 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Lina Iyer X-Patchwork-Id: 11122357 Return-Path: Received: from mail.kernel.org (pdx-korg-mail-1.web.codeaurora.org [172.30.200.123]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id C273C18EC for ; Thu, 29 Aug 2019 18:47:29 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.kernel.org (Postfix) with ESMTP id 9DA262189D for ; Thu, 29 Aug 2019 18:47:29 +0000 (UTC) Authentication-Results: mail.kernel.org; dkim=fail reason="key not found in DNS" (0-bit key) header.d=codeaurora.org header.i=@codeaurora.org header.b="O9hf/MTl"; dkim=fail reason="key not found in DNS" (0-bit key) header.d=codeaurora.org header.i=@codeaurora.org header.b="o9wmELH7" Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1728124AbfH2SrZ (ORCPT ); Thu, 29 Aug 2019 14:47:25 -0400 Received: from smtp.codeaurora.org ([198.145.29.96]:35324 "EHLO smtp.codeaurora.org" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1726518AbfH2SrZ (ORCPT ); Thu, 29 Aug 2019 14:47:25 -0400 Received: by smtp.codeaurora.org (Postfix, from userid 1000) id 662F668B12; Thu, 29 Aug 2019 18:12:21 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=codeaurora.org; s=default; t=1567104439; bh=UrH1sAFAb1z9oIzC3C7zIhB+/ZJIJDhRvFYRG0P+AAo=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=O9hf/MTlKD3LwL1oqjIJYG+EVIhZ1YfMeKrtCohMSMHXbRWmomBBAcW9HCwbHmph3 8nJ9TYpmiPxGzZfhynFzA2CI98v1X9e4JdJsVJ0VeRJmkNuhR7JUuKfCnH5gUJPTpO 7deBcmHtmPJXW+buKhdNsTVubYY/BWur35FvodUw= X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on pdx-caf-mail.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-2.7 required=2.0 tests=ALL_TRUSTED,BAYES_00, DKIM_INVALID,DKIM_SIGNED,SPF_NONE autolearn=no autolearn_force=no version=3.4.0 Received: from codeaurora.org (i-global254.qualcomm.com [199.106.103.254]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-SHA256 (128/128 bits)) (No client certificate requested) (Authenticated sender: ilina@smtp.codeaurora.org) by smtp.codeaurora.org (Postfix) with ESMTPSA id 93B1568891; Thu, 29 Aug 2019 18:12:18 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=codeaurora.org; s=default; t=1567102340; bh=UrH1sAFAb1z9oIzC3C7zIhB+/ZJIJDhRvFYRG0P+AAo=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=o9wmELH7qzTvMQkbu04AsjCoy5NjTGqsFtQ1lSjvKSxK7QAEI1J3ajb8cbjIcbOz3 o36Qrl0sJDIobSaS6OqEO7wsvr2Gs+T+OzJl60TGlXIOlTC2Q0+iT2v3PpR5EQ6cRk K6ryPuX+WfYgPdrgZxUrwGG/sI5//AOoDQoXLG6E= DMARC-Filter: OpenDMARC Filter v1.3.2 smtp.codeaurora.org 93B1568891 Authentication-Results: pdx-caf-mail.web.codeaurora.org; dmarc=none (p=none dis=none) header.from=codeaurora.org Authentication-Results: pdx-caf-mail.web.codeaurora.org; spf=none smtp.mailfrom=ilina@codeaurora.org From: Lina Iyer To: swboyd@chromium.org, evgreen@chromium.org, marc.zyngier@arm.com, linus.walleij@linaro.org Cc: linux-kernel@vger.kernel.org, linux-arm-msm@vger.kernel.org, bjorn.andersson@linaro.org, mkshah@codeaurora.org, linux-gpio@vger.kernel.org, rnayak@codeaurora.org, Lina Iyer , devicetree@vger.kernel.org Subject: [PATCH RFC 05/14] dt-bindings/interrupt-controller: pdc: add SPI config register Date: Thu, 29 Aug 2019 12:11:54 -0600 Message-Id: <20190829181203.2660-6-ilina@codeaurora.org> X-Mailer: git-send-email 2.22.0 In-Reply-To: <20190829181203.2660-1-ilina@codeaurora.org> References: <20190829181203.2660-1-ilina@codeaurora.org> MIME-Version: 1.0 Sender: linux-arm-msm-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-arm-msm@vger.kernel.org In addition to configuring the PDC, additional registers that interface the GIC have to be configured to match the GPIO type. The registers on some QCOM SoCs are access restricted, while on other SoCs are not. They SoCs with access restriction to these SPI registers need to be written from the firmware using the SCM interface. Add a flag to indicate if the register is to be written using SCM interface. Cc: devicetree@vger.kernel.org Signed-off-by: Lina Iyer --- .../bindings/interrupt-controller/qcom,pdc.txt | 9 ++++++++- 1 file changed, 8 insertions(+), 1 deletion(-) diff --git a/Documentation/devicetree/bindings/interrupt-controller/qcom,pdc.txt b/Documentation/devicetree/bindings/interrupt-controller/qcom,pdc.txt index 8e0797cb1487..852fcba98ea6 100644 --- a/Documentation/devicetree/bindings/interrupt-controller/qcom,pdc.txt +++ b/Documentation/devicetree/bindings/interrupt-controller/qcom,pdc.txt @@ -50,15 +50,22 @@ Properties: The second element is the GIC hwirq number for the PDC port. The third element is the number of interrupts in sequence. +- qcom,scm-spi-cfg: + Usage: optional + Value type: + Definition: Specifies if the SPI configuration registers have to be + written from the firmware. + Example: pdc: interrupt-controller@b220000 { compatible = "qcom,sdm845-pdc"; - reg = <0xb220000 0x30000>; + reg = <0xb220000 0x30000>, <0x179900f0 0x60>; qcom,pdc-ranges = <0 512 94>, <94 641 15>, <115 662 7>; #interrupt-cells = <2>; interrupt-parent = <&intc>; interrupt-controller; + qcom,scm-spi-cfg; }; DT binding of a device that wants to use the GIC SPI 514 as a wakeup From patchwork Thu Aug 29 18:11:55 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Lina Iyer X-Patchwork-Id: 11122355 Return-Path: Received: from mail.kernel.org (pdx-korg-mail-1.web.codeaurora.org [172.30.200.123]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id E08F614D5 for ; Thu, 29 Aug 2019 18:46:04 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.kernel.org (Postfix) with ESMTP id B44D82189D for ; Thu, 29 Aug 2019 18:46:04 +0000 (UTC) Authentication-Results: mail.kernel.org; dkim=fail reason="key not found in DNS" (0-bit key) header.d=codeaurora.org header.i=@codeaurora.org header.b="dh9Kt024"; dkim=fail reason="key not found in DNS" (0-bit key) header.d=codeaurora.org header.i=@codeaurora.org header.b="W1Xr7uKc" Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1728239AbfH2SqE (ORCPT ); Thu, 29 Aug 2019 14:46:04 -0400 Received: from smtp.codeaurora.org ([198.145.29.96]:60572 "EHLO smtp.codeaurora.org" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1727867AbfH2SqE (ORCPT ); Thu, 29 Aug 2019 14:46:04 -0400 Received: by smtp.codeaurora.org (Postfix, from userid 1000) id 5AE2269729; Thu, 29 Aug 2019 18:12:24 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=codeaurora.org; s=default; t=1567104362; bh=NeN4E6ZDwRBCdLKC0wxNI3H/ZmA0gyTLRM9b/Pm81zE=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=dh9Kt024EryacgO8qnE+9gVquDx+DFricK+M6P/3vzhkfVxNDqxf+59z6dr9X74A3 zfe3qN/r31VAzey3zoklmmtJm+RYl7kz0hAf0WnFY+bVneu3ACA9LHlngNRyMovHsL hePBKtFsrdID7SX/2h6ydKEbFYB3sRpQUJgDPFIQ= X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on pdx-caf-mail.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-2.7 required=2.0 tests=ALL_TRUSTED,BAYES_00, DKIM_INVALID,DKIM_SIGNED,SPF_NONE autolearn=no autolearn_force=no version=3.4.0 Received: from codeaurora.org (i-global254.qualcomm.com [199.106.103.254]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-SHA256 (128/128 bits)) (No client certificate requested) (Authenticated sender: ilina@smtp.codeaurora.org) by smtp.codeaurora.org (Postfix) with ESMTPSA id 97DC86895F; Thu, 29 Aug 2019 18:12:20 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=codeaurora.org; s=default; t=1567102341; bh=NeN4E6ZDwRBCdLKC0wxNI3H/ZmA0gyTLRM9b/Pm81zE=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=W1Xr7uKcxlsqNNIRblfR6+gWo8oIU6UQdeGiiVsn0afNghUlNl98SbU+tSJlNXlOr a87kHbC8jBnFS8ofI9wgMlF+3NPRyTY3nH+a0NXxc3TEHR/wTmJrMzjc9+LurBPD4K tcHBF4WEpXDYSnQiynyxvsDlbX51eR3zvE1sPJG0= DMARC-Filter: OpenDMARC Filter v1.3.2 smtp.codeaurora.org 97DC86895F Authentication-Results: pdx-caf-mail.web.codeaurora.org; dmarc=none (p=none dis=none) header.from=codeaurora.org Authentication-Results: pdx-caf-mail.web.codeaurora.org; spf=none smtp.mailfrom=ilina@codeaurora.org From: Lina Iyer To: swboyd@chromium.org, evgreen@chromium.org, marc.zyngier@arm.com, linus.walleij@linaro.org Cc: linux-kernel@vger.kernel.org, linux-arm-msm@vger.kernel.org, bjorn.andersson@linaro.org, mkshah@codeaurora.org, linux-gpio@vger.kernel.org, rnayak@codeaurora.org, Lina Iyer Subject: [PATCH RFC 06/14] drivers: irqchip: pdc: additionally set type in SPI config registers Date: Thu, 29 Aug 2019 12:11:55 -0600 Message-Id: <20190829181203.2660-7-ilina@codeaurora.org> X-Mailer: git-send-email 2.22.0 In-Reply-To: <20190829181203.2660-1-ilina@codeaurora.org> References: <20190829181203.2660-1-ilina@codeaurora.org> MIME-Version: 1.0 Sender: linux-arm-msm-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-arm-msm@vger.kernel.org GPIOs that can be configured as wakeup are routed to the PDC wakeup interrupt controller and from there to the GIC interrupt controller. On some QCOM SoCs, the interface to the GIC for wakeup capable GPIOs have additional hardware registers that need to be configured as well to match the trigger type of the GPIO. This register interfaces the PDC to the GIC and therefore updated from the PDC driver. Typically, the firmware intializes the interface registers for the wakeup capable GPIOs with commonly used GPIO trigger type, but it is possible that a platform may want to use the GPIO differently. So, in addition to configuring the PDC, configure the interface registers as well. Signed-off-by: Lina Iyer --- drivers/irqchip/qcom-pdc.c | 93 ++++++++++++++++++++++++++++++++++++++ 1 file changed, 93 insertions(+) diff --git a/drivers/irqchip/qcom-pdc.c b/drivers/irqchip/qcom-pdc.c index ad1faf634bcf..bf5f98bb4d2b 100644 --- a/drivers/irqchip/qcom-pdc.c +++ b/drivers/irqchip/qcom-pdc.c @@ -18,6 +18,8 @@ #include #include +#include + #define PDC_MAX_IRQS 126 #define PDC_MAX_GPIO_IRQS 256 @@ -35,10 +37,20 @@ struct pdc_pin_region { u32 cnt; }; +struct spi_cfg_regs { + union { + u64 start; + void __iomem *base; + }; + resource_size_t size; + bool scm_io; +}; + static DEFINE_RAW_SPINLOCK(pdc_lock); static void __iomem *pdc_base; static struct pdc_pin_region *pdc_region; static int pdc_region_cnt; +static struct spi_cfg_regs *spi_cfg; static void pdc_reg_write(int reg, u32 i, u32 val) { @@ -100,6 +112,57 @@ static void qcom_pdc_gic_unmask(struct irq_data *d) irq_chip_unmask_parent(d); } +static u32 __spi_pin_read(unsigned int pin) +{ + void __iomem *cfg_reg = spi_cfg->base + pin * 4; + u64 scm_cfg_reg = spi_cfg->start + pin * 4; + + if (spi_cfg->scm_io) { + unsigned int val; + + qcom_scm_io_readl(scm_cfg_reg, &val); + return val; + } else { + return readl(cfg_reg); + } +} + +static void __spi_pin_write(unsigned int pin, unsigned int val) +{ + void __iomem *cfg_reg = spi_cfg->base + pin * 4; + u64 scm_cfg_reg = spi_cfg->start + pin * 4; + + if (spi_cfg->scm_io) + qcom_scm_io_writel(scm_cfg_reg, val); + else + writel(val, cfg_reg); +} + +static int spi_configure_type(irq_hw_number_t hwirq, unsigned int type) +{ + int spi = hwirq - 32; + u32 pin = spi / 32; + u32 mask = BIT(spi % 32); + u32 val; + unsigned long flags; + + if (!spi_cfg) + return 0; + + if (pin * 4 > spi_cfg->size) + return -EFAULT; + + raw_spin_lock_irqsave(&pdc_lock, flags); + val = __spi_pin_read(pin); + val &= ~mask; + if (type & IRQ_TYPE_LEVEL_MASK) + val |= mask; + __spi_pin_write(pin, val); + raw_spin_unlock_irqrestore(&pdc_lock, flags); + + return 0; +} + /* * GIC does not handle falling edge or active low. To allow falling edge and * active low interrupts to be handled at GIC, PDC has an inverter that inverts @@ -137,7 +200,9 @@ enum pdc_irq_config_bits { static int qcom_pdc_gic_set_type(struct irq_data *d, unsigned int type) { int pin_out = d->hwirq; + int parent_hwirq = d->parent_data->hwirq; enum pdc_irq_config_bits pdc_type; + int ret; if (pin_out == GPIO_NO_WAKE_IRQ) return 0; @@ -168,6 +233,11 @@ static int qcom_pdc_gic_set_type(struct irq_data *d, unsigned int type) pdc_reg_write(IRQ_i_CFG, pin_out, pdc_type); + /* Additionally, configure (only) the GPIO in the f/w */ + ret = spi_configure_type(parent_hwirq, type); + if (ret) + return ret; + return irq_chip_set_type_parent(d, type); } @@ -354,6 +424,7 @@ static int pdc_setup_pin_mapping(struct device_node *np) static int qcom_pdc_init(struct device_node *node, struct device_node *parent) { struct irq_domain *parent_domain, *pdc_domain, *pdc_gpio_domain; + struct resource res; int ret; pdc_base = of_iomap(node, 0); @@ -384,6 +455,27 @@ static int qcom_pdc_init(struct device_node *node, struct device_node *parent) goto fail; } + ret = of_address_to_resource(node, 1, &res); + if (!ret) { + spi_cfg = kcalloc(1, sizeof(*spi_cfg), GFP_KERNEL); + if (!spi_cfg) { + ret = -ENOMEM; + goto remove; + } + spi_cfg->scm_io = of_find_property(node, + "qcom,scm-spi-cfg", NULL); + spi_cfg->size = resource_size(&res); + if (spi_cfg->scm_io) { + spi_cfg->start = res.start; + } else { + spi_cfg->base = ioremap(res.start, spi_cfg->size); + if (!spi_cfg->base) { + ret = -ENOMEM; + goto remove; + } + } + } + pdc_gpio_domain = irq_domain_create_hierarchy(parent_domain, IRQ_DOMAIN_FLAG_QCOM_PDC_WAKEUP, PDC_MAX_GPIO_IRQS, @@ -401,6 +493,7 @@ static int qcom_pdc_init(struct device_node *node, struct device_node *parent) remove: irq_domain_remove(pdc_domain); + kfree(spi_cfg); fail: kfree(pdc_region); iounmap(pdc_base); From patchwork Thu Aug 29 18:11:56 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Lina Iyer X-Patchwork-Id: 11122341 Return-Path: Received: from mail.kernel.org (pdx-korg-mail-1.web.codeaurora.org [172.30.200.123]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id 57C621398 for ; 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h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=ONmK8JYiPgFpRzLr6v1t48svp5CLbD6iVIJE7nbQEMVc6GsQA0Jn76GnNnP9CX2Fv 77Tt4a+QS5qKLwGXGRNcv6LKke5h93nBQkvR5XvtygBn+Zl9fOF4v6j6UGlmeJ9LF/ EKcHw4i1QX5J9ESTQ4NsCq4k/QqhhwwogxeuljEU= DMARC-Filter: OpenDMARC Filter v1.3.2 smtp.codeaurora.org C399D68974 Authentication-Results: pdx-caf-mail.web.codeaurora.org; dmarc=none (p=none dis=none) header.from=codeaurora.org Authentication-Results: pdx-caf-mail.web.codeaurora.org; spf=none smtp.mailfrom=ilina@codeaurora.org From: Lina Iyer To: swboyd@chromium.org, evgreen@chromium.org, marc.zyngier@arm.com, linus.walleij@linaro.org Cc: linux-kernel@vger.kernel.org, linux-arm-msm@vger.kernel.org, bjorn.andersson@linaro.org, mkshah@codeaurora.org, linux-gpio@vger.kernel.org, rnayak@codeaurora.org Subject: [PATCH RFC 07/14] genirq: Introduce irq_chip_get/set_parent_state calls Date: Thu, 29 Aug 2019 12:11:56 -0600 Message-Id: <20190829181203.2660-8-ilina@codeaurora.org> X-Mailer: git-send-email 2.22.0 In-Reply-To: <20190829181203.2660-1-ilina@codeaurora.org> References: <20190829181203.2660-1-ilina@codeaurora.org> MIME-Version: 1.0 Sender: linux-arm-msm-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-arm-msm@vger.kernel.org From: Maulik Shah On certain QTI chipsets some GPIOs are direct-connect interrupts to the GIC. Even when GPIOs are not used for interrupt generation and interrupt line is disabled, it does not prevent interrupt to get pending at GIC_ISPEND. When drivers call enable_irq unwanted interrupt occures. Introduce irq_chip_get/set_parent_state calls to clear pending irq which can get called within irq_enable of child irq chip to clear any pending irq before enabling. Signed-off-by: Maulik Shah --- include/linux/irq.h | 6 ++++++ kernel/irq/chip.c | 44 ++++++++++++++++++++++++++++++++++++++++++++ 2 files changed, 50 insertions(+) diff --git a/include/linux/irq.h b/include/linux/irq.h index fb301cf29148..7853eb9301f2 100644 --- a/include/linux/irq.h +++ b/include/linux/irq.h @@ -610,6 +610,12 @@ extern int irq_chip_pm_put(struct irq_data *data); #ifdef CONFIG_IRQ_DOMAIN_HIERARCHY extern void handle_fasteoi_ack_irq(struct irq_desc *desc); extern void handle_fasteoi_mask_irq(struct irq_desc *desc); +extern int irq_chip_set_parent_state(struct irq_data *data, + enum irqchip_irq_state which, + bool val); +extern int irq_chip_get_parent_state(struct irq_data *data, + enum irqchip_irq_state which, + bool *state); extern void irq_chip_enable_parent(struct irq_data *data); extern void irq_chip_disable_parent(struct irq_data *data); extern void irq_chip_ack_parent(struct irq_data *data); diff --git a/kernel/irq/chip.c b/kernel/irq/chip.c index b76703b2c0af..6bb5b22bb0a7 100644 --- a/kernel/irq/chip.c +++ b/kernel/irq/chip.c @@ -1297,6 +1297,50 @@ EXPORT_SYMBOL_GPL(handle_fasteoi_mask_irq); #endif /* CONFIG_IRQ_FASTEOI_HIERARCHY_HANDLERS */ +/** + * irq_chip_set_parent_state - set the state of a parent interrupt. + * @data: Pointer to interrupt specific data + * @which: State to be restored (one of IRQCHIP_STATE_*) + * @val: Value corresponding to @which + * + */ +int irq_chip_set_parent_state(struct irq_data *data, + enum irqchip_irq_state which, + bool val) +{ + data = data->parent_data; + if (!data) + return 0; + + if (data->chip->irq_set_irqchip_state) + return data->chip->irq_set_irqchip_state(data, which, val); + + return 0; +} +EXPORT_SYMBOL(irq_chip_set_parent_state); + +/** + * irq_chip_get_parent_state - get the state of a parent interrupt. + * @data: Pointer to interrupt specific data + * @which: one of IRQCHIP_STATE_* the caller wants to know + * @state: a pointer to a boolean where the state is to be stored + * + */ +int irq_chip_get_parent_state(struct irq_data *data, + enum irqchip_irq_state which, + bool *state) +{ + data = data->parent_data; + if (!data) + return 0; + + if (data->chip->irq_get_irqchip_state) + return data->chip->irq_get_irqchip_state(data, which, state); + + return 0; +} +EXPORT_SYMBOL(irq_chip_get_parent_state); + /** * irq_chip_enable_parent - Enable the parent interrupt (defaults to unmask if * NULL) From patchwork Thu Aug 29 18:11:57 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Lina Iyer X-Patchwork-Id: 11122345 Return-Path: Received: from mail.kernel.org (pdx-korg-mail-1.web.codeaurora.org [172.30.200.123]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id 26EDD14DE for ; Thu, 29 Aug 2019 18:40:06 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.kernel.org (Postfix) with ESMTP id 03C2D215EA for ; Thu, 29 Aug 2019 18:40:06 +0000 (UTC) Authentication-Results: mail.kernel.org; dkim=fail reason="key not found in DNS" (0-bit key) header.d=codeaurora.org header.i=@codeaurora.org header.b="bYvqXYjD"; dkim=fail reason="key not found in DNS" (0-bit key) header.d=codeaurora.org header.i=@codeaurora.org header.b="lu6zKN1S" Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1728124AbfH2SkF (ORCPT ); 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Thu, 29 Aug 2019 18:12:24 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=codeaurora.org; s=default; t=1567102345; bh=C76NL2lI9WtV1EgLa6yoNbnozvP8sgbuLm9WRaLvPvg=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=lu6zKN1SuhMG+doaOMmCq7+3vjTDBuC7tsKHtYSC5kG2dUwAxm6oaxH8cbFdYQW5j +4GxMKczPvorDyraVRcgltHA1hhH/6uOssutpV5OcS83V3JBDc9aBmEnmakbGEqla6 a/FY0LjoJwUnMCTeMU4XJcVsJZ5Uv5YTtKjs3lDk= DMARC-Filter: OpenDMARC Filter v1.3.2 smtp.codeaurora.org 608BD689AE Authentication-Results: pdx-caf-mail.web.codeaurora.org; dmarc=none (p=none dis=none) header.from=codeaurora.org Authentication-Results: pdx-caf-mail.web.codeaurora.org; spf=none smtp.mailfrom=ilina@codeaurora.org From: Lina Iyer To: swboyd@chromium.org, evgreen@chromium.org, marc.zyngier@arm.com, linus.walleij@linaro.org Cc: linux-kernel@vger.kernel.org, linux-arm-msm@vger.kernel.org, bjorn.andersson@linaro.org, mkshah@codeaurora.org, linux-gpio@vger.kernel.org, rnayak@codeaurora.org Subject: [PATCH RFC 08/14] drivers: irqchip: pdc: Add irqchip set/get state calls Date: Thu, 29 Aug 2019 12:11:57 -0600 Message-Id: <20190829181203.2660-9-ilina@codeaurora.org> X-Mailer: git-send-email 2.22.0 In-Reply-To: <20190829181203.2660-1-ilina@codeaurora.org> References: <20190829181203.2660-1-ilina@codeaurora.org> MIME-Version: 1.0 Sender: linux-arm-msm-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-arm-msm@vger.kernel.org From: Maulik Shah Add irqchip calls to set/get interrupt status from the parent interrupt controller. Signed-off-by: Maulik Shah --- drivers/irqchip/qcom-pdc.c | 21 +++++++++++++++++++++ 1 file changed, 21 insertions(+) diff --git a/drivers/irqchip/qcom-pdc.c b/drivers/irqchip/qcom-pdc.c index bf5f98bb4d2b..ffd5f83d1023 100644 --- a/drivers/irqchip/qcom-pdc.c +++ b/drivers/irqchip/qcom-pdc.c @@ -5,6 +5,7 @@ #include #include +#include #include #include #include @@ -87,6 +88,24 @@ static void qcom_pdc_gic_disable(struct irq_data *d) irq_chip_disable_parent(d); } +static int qcom_pdc_gic_get_irqchip_state(struct irq_data *d, + enum irqchip_irq_state which, bool *state) +{ + if (d->hwirq == GPIO_NO_WAKE_IRQ) + return 0; + + return irq_chip_get_parent_state(d, which, state); +} + +static int qcom_pdc_gic_set_irqchip_state(struct irq_data *d, + enum irqchip_irq_state which, bool value) +{ + if (d->hwirq == GPIO_NO_WAKE_IRQ) + return 0; + + return irq_chip_set_parent_state(d, which, value); +} + static void qcom_pdc_gic_enable(struct irq_data *d) { if (d->hwirq == GPIO_NO_WAKE_IRQ) @@ -248,6 +267,8 @@ static struct irq_chip qcom_pdc_gic_chip = { .irq_unmask = qcom_pdc_gic_unmask, .irq_disable = qcom_pdc_gic_disable, .irq_enable = qcom_pdc_gic_enable, + .irq_get_irqchip_state = qcom_pdc_gic_get_irqchip_state, + .irq_set_irqchip_state = qcom_pdc_gic_set_irqchip_state, .irq_retrigger = irq_chip_retrigger_hierarchy, .irq_set_type = qcom_pdc_gic_set_type, .flags = IRQCHIP_MASK_ON_SUSPEND | From patchwork Thu Aug 29 18:11:58 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Lina Iyer X-Patchwork-Id: 11122325 Return-Path: Received: from mail.kernel.org (pdx-korg-mail-1.web.codeaurora.org [172.30.200.123]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id 1557214DE for ; Thu, 29 Aug 2019 18:35:02 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.kernel.org (Postfix) with ESMTP id E756121874 for ; Thu, 29 Aug 2019 18:35:01 +0000 (UTC) Authentication-Results: mail.kernel.org; dkim=fail reason="key not found in DNS" (0-bit key) header.d=codeaurora.org header.i=@codeaurora.org header.b="KIgEPVQp"; dkim=fail reason="key not found in DNS" (0-bit key) header.d=codeaurora.org header.i=@codeaurora.org header.b="Nyzgyb8c" Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1727437AbfH2SfB (ORCPT ); Thu, 29 Aug 2019 14:35:01 -0400 Received: from smtp.codeaurora.org ([198.145.29.96]:59502 "EHLO smtp.codeaurora.org" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1726518AbfH2SfB (ORCPT ); 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Thu, 29 Aug 2019 18:12:25 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=codeaurora.org; s=default; t=1567102347; bh=rS68WLR481l1COMdQ2jk/qCVOqr85DyICDhl53r3iQE=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=Nyzgyb8c62V8KHiqGWcqXJsfpL1vdt1tW7PnmZou0JbmKQjBHnp62ZrCDdtqj2IEA Np6D7cjv8U7RSZyHLXtWsDuNyOVKmdldOclcfUiZgFMJmFFXI8j5P5eos4CH/92fYf HuCM5eC1yOz4ftXxDl0BHN0nE5lciYqRV4VwP6ak= DMARC-Filter: OpenDMARC Filter v1.3.2 smtp.codeaurora.org B8EB468997 Authentication-Results: pdx-caf-mail.web.codeaurora.org; dmarc=none (p=none dis=none) header.from=codeaurora.org Authentication-Results: pdx-caf-mail.web.codeaurora.org; spf=none smtp.mailfrom=ilina@codeaurora.org From: Lina Iyer To: swboyd@chromium.org, evgreen@chromium.org, marc.zyngier@arm.com, linus.walleij@linaro.org Cc: linux-kernel@vger.kernel.org, linux-arm-msm@vger.kernel.org, bjorn.andersson@linaro.org, mkshah@codeaurora.org, linux-gpio@vger.kernel.org, rnayak@codeaurora.org, Lina Iyer Subject: [PATCH RFC 09/14] drivers: pinctrl: msm: fix use of deprecated gpiolib APIs Date: Thu, 29 Aug 2019 12:11:58 -0600 Message-Id: <20190829181203.2660-10-ilina@codeaurora.org> X-Mailer: git-send-email 2.22.0 In-Reply-To: <20190829181203.2660-1-ilina@codeaurora.org> References: <20190829181203.2660-1-ilina@codeaurora.org> MIME-Version: 1.0 Sender: linux-arm-msm-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-arm-msm@vger.kernel.org Replace gpiochip_irqchip_add() and gpiochip_set_chained_irqchip() calls by populating the gpio_irq_chip data structures instead. Signed-off-by: Lina Iyer --- drivers/pinctrl/qcom/pinctrl-msm.c | 28 +++++++++++++--------------- 1 file changed, 13 insertions(+), 15 deletions(-) diff --git a/drivers/pinctrl/qcom/pinctrl-msm.c b/drivers/pinctrl/qcom/pinctrl-msm.c index 7f35c196bb3e..76e8528e4d0a 100644 --- a/drivers/pinctrl/qcom/pinctrl-msm.c +++ b/drivers/pinctrl/qcom/pinctrl-msm.c @@ -1027,7 +1027,19 @@ static int msm_gpio_init(struct msm_pinctrl *pctrl) pctrl->irq_chip.irq_request_resources = msm_gpio_irq_reqres; pctrl->irq_chip.irq_release_resources = msm_gpio_irq_relres; - ret = gpiochip_add_data(&pctrl->chip, pctrl); + chip->irq.chip = &pctrl->irq_chip; + chip->irq.default_type = IRQ_TYPE_NONE; + chip->irq.handler = handle_bad_irq; + chip->irq.fwnode = pctrl->dev->fwnode; + chip->irq.parent_handler = msm_gpio_irq_handler; + chip->irq.num_parents = 1; + chip->irq.parents = devm_kcalloc(pctrl->dev, 1, + sizeof(*chip->irq.parents), + GFP_KERNEL); + if (!chip->irq.parents) + return -ENOMEM; + + ret = devm_gpiochip_add_data(pctrl->dev, chip, pctrl); if (ret) { dev_err(pctrl->dev, "Failed register gpiochip\n"); return ret; @@ -1053,20 +1065,6 @@ static int msm_gpio_init(struct msm_pinctrl *pctrl) } } - ret = gpiochip_irqchip_add(chip, - &pctrl->irq_chip, - 0, - handle_edge_irq, - IRQ_TYPE_NONE); - if (ret) { - dev_err(pctrl->dev, "Failed to add irqchip to gpiochip\n"); - gpiochip_remove(&pctrl->chip); - return -ENOSYS; - } - - gpiochip_set_chained_irqchip(chip, &pctrl->irq_chip, pctrl->irq, - msm_gpio_irq_handler); - return 0; } From patchwork Thu Aug 29 18:11:59 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Lina Iyer X-Patchwork-Id: 11122353 Return-Path: Received: from mail.kernel.org (pdx-korg-mail-1.web.codeaurora.org [172.30.200.123]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id 798D814D5 for ; Thu, 29 Aug 2019 18:45:47 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.kernel.org (Postfix) with ESMTP id 436B721726 for ; Thu, 29 Aug 2019 18:45:47 +0000 (UTC) Authentication-Results: mail.kernel.org; dkim=fail reason="key not found in DNS" (0-bit key) header.d=codeaurora.org header.i=@codeaurora.org header.b="MctWhjTS"; dkim=fail reason="key not found in DNS" (0-bit key) header.d=codeaurora.org header.i=@codeaurora.org header.b="br2N+vrA" Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1727876AbfH2Spq (ORCPT ); Thu, 29 Aug 2019 14:45:46 -0400 Received: from smtp.codeaurora.org ([198.145.29.96]:59514 "EHLO smtp.codeaurora.org" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1727867AbfH2Spq (ORCPT ); Thu, 29 Aug 2019 14:45:46 -0400 Received: by smtp.codeaurora.org (Postfix, from userid 1000) id BCD7C696F4; Thu, 29 Aug 2019 18:12:32 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=codeaurora.org; s=default; t=1567104345; bh=UEhIiuKN6lZvFJkHN8qytkrYecwNLjuVzsDfPq+Y0Ig=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=MctWhjTSS/HmTH8w/aOmUeGpBTWXXyIt95FG8eODHy+SZq4LMFgiYv449ZBaxYgUV 7lmYvZuvujJQoeeH14UcrCPJa90yIlPea5J6jGdFvSTZKgmvetJm3JlYxKIFTnxAsH V8bLKFii2qrGQfXPlt4/BYoM7Lf5fBQNqXYdOVgo= X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on pdx-caf-mail.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-2.7 required=2.0 tests=ALL_TRUSTED,BAYES_00, DKIM_INVALID,DKIM_SIGNED,SPF_NONE autolearn=no autolearn_force=no version=3.4.0 Received: from codeaurora.org (i-global254.qualcomm.com [199.106.103.254]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-SHA256 (128/128 bits)) (No client certificate requested) (Authenticated sender: ilina@smtp.codeaurora.org) by smtp.codeaurora.org (Postfix) with ESMTPSA id 8770B68A27; Thu, 29 Aug 2019 18:12:27 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=codeaurora.org; s=default; t=1567102349; bh=UEhIiuKN6lZvFJkHN8qytkrYecwNLjuVzsDfPq+Y0Ig=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=br2N+vrAi6Y/F/3/BlazvqHODLCzqzUgz5gCmcDQ3Xt2jVqSoQ4gz6Wg6FErarw9k j+O7VPK+tiKJ7Men2kj7UJ1MqsXspouaOLMfKyjwz9lZkR2MuldU4UXyZL4vmFjsUs /ZCRH+DTv8MSPNYuINuWV/hrZ/kcOCF7fV+Mz7ds= DMARC-Filter: OpenDMARC Filter v1.3.2 smtp.codeaurora.org 8770B68A27 Authentication-Results: pdx-caf-mail.web.codeaurora.org; dmarc=none (p=none dis=none) header.from=codeaurora.org Authentication-Results: pdx-caf-mail.web.codeaurora.org; spf=none smtp.mailfrom=ilina@codeaurora.org From: Lina Iyer To: swboyd@chromium.org, evgreen@chromium.org, marc.zyngier@arm.com, linus.walleij@linaro.org Cc: linux-kernel@vger.kernel.org, linux-arm-msm@vger.kernel.org, bjorn.andersson@linaro.org, mkshah@codeaurora.org, linux-gpio@vger.kernel.org, rnayak@codeaurora.org, Lina Iyer Subject: [PATCH RFC 10/14] drivers: pinctrl: msm: setup GPIO chip in hierarchy Date: Thu, 29 Aug 2019 12:11:59 -0600 Message-Id: <20190829181203.2660-11-ilina@codeaurora.org> X-Mailer: git-send-email 2.22.0 In-Reply-To: <20190829181203.2660-1-ilina@codeaurora.org> References: <20190829181203.2660-1-ilina@codeaurora.org> MIME-Version: 1.0 Sender: linux-arm-msm-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-arm-msm@vger.kernel.org Some GPIOs are marked as wakeup capable and are routed to another interrupt controller that is an always-domain and can detect interrupts even most of the SoC is powered off. The wakeup interrupt controller wakes up the GIC and replays the interrupt at the GIC. Setup the TLMM irqchip in hierarchy with the wakeup interrupt controller and ensure the wakeup GPIOs are handled correctly. Signed-off-by: Maulik Shah Signed-off-by: Lina Iyer --- drivers/pinctrl/qcom/pinctrl-msm.c | 114 +++++++++++++++++++++++++++++ drivers/pinctrl/qcom/pinctrl-msm.h | 16 ++++ 2 files changed, 130 insertions(+) diff --git a/drivers/pinctrl/qcom/pinctrl-msm.c b/drivers/pinctrl/qcom/pinctrl-msm.c index 76e8528e4d0a..d626264fe678 100644 --- a/drivers/pinctrl/qcom/pinctrl-msm.c +++ b/drivers/pinctrl/qcom/pinctrl-msm.c @@ -23,6 +23,8 @@ #include #include +#include + #include "../core.h" #include "../pinconf.h" #include "pinctrl-msm.h" @@ -44,6 +46,7 @@ * @enabled_irqs: Bitmap of currently enabled irqs. * @dual_edge_irqs: Bitmap of irqs that need sw emulated dual edge * detection. + * @skip_wake_irqs: Skip IRQs that are handled by wakeup interrupt contrroller * @soc; Reference to soc_data of platform specific data. * @regs: Base addresses for the TLMM tiles. */ @@ -61,6 +64,7 @@ struct msm_pinctrl { DECLARE_BITMAP(dual_edge_irqs, MAX_NR_GPIO); DECLARE_BITMAP(enabled_irqs, MAX_NR_GPIO); + DECLARE_BITMAP(skip_wake_irqs, MAX_NR_GPIO); const struct msm_pinctrl_soc_data *soc; void __iomem *regs[MAX_NR_TILES]; @@ -708,6 +712,12 @@ static void msm_gpio_irq_mask(struct irq_data *d) unsigned long flags; u32 val; + if (d->parent_data) + irq_chip_mask_parent(d); + + if (test_bit(d->hwirq, pctrl->skip_wake_irqs)) + return; + g = &pctrl->soc->groups[d->hwirq]; raw_spin_lock_irqsave(&pctrl->lock, flags); @@ -752,6 +762,12 @@ static void msm_gpio_irq_clear_unmask(struct irq_data *d, bool status_clear) unsigned long flags; u32 val; + if (d->parent_data) + irq_chip_unmask_parent(d); + + if (test_bit(d->hwirq, pctrl->skip_wake_irqs)) + return; + g = &pctrl->soc->groups[d->hwirq]; raw_spin_lock_irqsave(&pctrl->lock, flags); @@ -779,10 +795,43 @@ static void msm_gpio_irq_clear_unmask(struct irq_data *d, bool status_clear) static void msm_gpio_irq_enable(struct irq_data *d) { + struct gpio_chip *gc = irq_data_get_irq_chip_data(d); + struct msm_pinctrl *pctrl = gpiochip_get_data(gc); + + /* + * Clear the interrupt that may be pending before we enable + * the line. + * This is especially a problem with the GPIOs routed to the + * PDC. These GPIOs are direct-connect interrupts to the GIC. + * Disabling the interrupt line at the PDC does not prevent + * the interrupt from being latched at the GIC. The state at + * GIC needs to be cleared before enabling. + */ + if (d->parent_data) { + irq_chip_set_parent_state(d, IRQCHIP_STATE_PENDING, 0); + irq_chip_enable_parent(d); + } + + if (test_bit(d->hwirq, pctrl->skip_wake_irqs)) + return; msm_gpio_irq_clear_unmask(d, true); } +static void msm_gpio_irq_disable(struct irq_data *d) +{ + struct gpio_chip *gc = irq_data_get_irq_chip_data(d); + struct msm_pinctrl *pctrl = gpiochip_get_data(gc); + + if (d->parent_data) + irq_chip_disable_parent(d); + + if (test_bit(d->hwirq, pctrl->skip_wake_irqs)) + return; + + msm_gpio_irq_mask(d); +} + static void msm_gpio_irq_unmask(struct irq_data *d) { msm_gpio_irq_clear_unmask(d, false); @@ -796,6 +845,9 @@ static void msm_gpio_irq_ack(struct irq_data *d) unsigned long flags; u32 val; + if (test_bit(d->hwirq, pctrl->skip_wake_irqs)) + return; + g = &pctrl->soc->groups[d->hwirq]; raw_spin_lock_irqsave(&pctrl->lock, flags); @@ -821,6 +873,12 @@ static int msm_gpio_irq_set_type(struct irq_data *d, unsigned int type) unsigned long flags; u32 val; + if (d->parent_data) + irq_chip_set_type_parent(d, type); + + if (test_bit(d->hwirq, pctrl->skip_wake_irqs)) + return 0; + g = &pctrl->soc->groups[d->hwirq]; raw_spin_lock_irqsave(&pctrl->lock, flags); @@ -913,6 +971,15 @@ static int msm_gpio_irq_set_wake(struct irq_data *d, unsigned int on) struct msm_pinctrl *pctrl = gpiochip_get_data(gc); unsigned long flags; + if (d->parent_data) + irq_chip_set_wake_parent(d, on); + + /* + * While they may not wake up when the TLMM is powered off, + * some GPIOs would like to wakeup the system from suspend + * when TLMM is powered on. To allow that, enable the GPIO + * summary line to be wakeup capable at GIC. + */ raw_spin_lock_irqsave(&pctrl->lock, flags); irq_set_irq_wake(pctrl->irq, on); @@ -991,6 +1058,30 @@ static void msm_gpio_irq_handler(struct irq_desc *desc) chained_irq_exit(chip, desc); } +static int msm_gpio_wakeirq(struct gpio_chip *gc, + unsigned int child, + unsigned int child_type, + unsigned int *parent, + unsigned int *parent_type) +{ + struct msm_pinctrl *pctrl = gpiochip_get_data(gc); + const struct msm_gpio_wakeirq_map *map; + int i; + + *parent = GPIO_NO_WAKE_IRQ; + *parent_type = IRQ_TYPE_EDGE_RISING; + + for (i = 0; i < pctrl->soc->nwakeirq_map; i++) { + map = &pctrl->soc->wakeirq_map[i]; + if (map->gpio == child) { + *parent = map->wakeirq; + break; + } + } + + return 0; +} + static bool msm_gpio_needs_valid_mask(struct msm_pinctrl *pctrl) { if (pctrl->soc->reserved_gpios) @@ -1004,6 +1095,7 @@ static int msm_gpio_init(struct msm_pinctrl *pctrl) struct gpio_chip *chip; int ret; unsigned ngpio = pctrl->soc->ngpios; + struct device_node *dn; if (WARN_ON(ngpio > MAX_NR_GPIO)) return -EINVAL; @@ -1019,14 +1111,36 @@ static int msm_gpio_init(struct msm_pinctrl *pctrl) pctrl->irq_chip.name = "msmgpio"; pctrl->irq_chip.irq_enable = msm_gpio_irq_enable; + pctrl->irq_chip.irq_disable = msm_gpio_irq_disable; pctrl->irq_chip.irq_mask = msm_gpio_irq_mask; pctrl->irq_chip.irq_unmask = msm_gpio_irq_unmask; pctrl->irq_chip.irq_ack = msm_gpio_irq_ack; + pctrl->irq_chip.irq_eoi = irq_chip_eoi_parent; pctrl->irq_chip.irq_set_type = msm_gpio_irq_set_type; pctrl->irq_chip.irq_set_wake = msm_gpio_irq_set_wake; pctrl->irq_chip.irq_request_resources = msm_gpio_irq_reqres; pctrl->irq_chip.irq_release_resources = msm_gpio_irq_relres; + dn = of_parse_phandle(pctrl->dev->of_node, "wakeup-parent", 0); + if (dn) { + int i; + bool skip; + unsigned int gpio; + + chip->irq.parent_domain = irq_find_matching_host(dn, + DOMAIN_BUS_WAKEUP); + of_node_put(dn); + if (!chip->irq.parent_domain) + return -EPROBE_DEFER; + chip->irq.child_to_parent_hwirq = msm_gpio_wakeirq; + + skip = irq_domain_qcom_handle_wakeup(chip->irq.parent_domain); + for (i = 0; skip && i < pctrl->soc->nwakeirq_map; i++) { + gpio = pctrl->soc->wakeirq_map[i].gpio; + set_bit(gpio, pctrl->skip_wake_irqs); + } + } + chip->irq.chip = &pctrl->irq_chip; chip->irq.default_type = IRQ_TYPE_NONE; chip->irq.handler = handle_bad_irq; diff --git a/drivers/pinctrl/qcom/pinctrl-msm.h b/drivers/pinctrl/qcom/pinctrl-msm.h index 48569cda8471..15470203b446 100644 --- a/drivers/pinctrl/qcom/pinctrl-msm.h +++ b/drivers/pinctrl/qcom/pinctrl-msm.h @@ -5,6 +5,8 @@ #ifndef __PINCTRL_MSM_H__ #define __PINCTRL_MSM_H__ +#include + struct pinctrl_pin_desc; /** @@ -91,6 +93,16 @@ struct msm_pingroup { unsigned intr_detection_width:5; }; +/** + * struct msm_gpio_wakeirq_map - Map of GPIOs and their wakeup pins + * @gpio: The GPIOs that are wakeup capable + * @wakeirq: The interrupt at the always-on interrupt controller + */ +struct msm_gpio_wakeirq_map { + unsigned int gpio; + unsigned int wakeirq; +}; + /** * struct msm_pinctrl_soc_data - Qualcomm pin controller driver configuration * @pins: An array describing all pins the pin controller affects. @@ -101,6 +113,8 @@ struct msm_pingroup { * @ngroups: The numbmer of entries in @groups. * @ngpio: The number of pingroups the driver should expose as GPIOs. * @pull_no_keeper: The SoC does not support keeper bias. + * @wakeirq_map: The map of wakeup capable GPIOs and the pin at PDC/MPM + * @nwakeirq_map: The number of entries in @hierarchy_map */ struct msm_pinctrl_soc_data { const struct pinctrl_pin_desc *pins; @@ -114,6 +128,8 @@ struct msm_pinctrl_soc_data { const char *const *tiles; unsigned int ntiles; const int *reserved_gpios; + const struct msm_gpio_wakeirq_map *wakeirq_map; + unsigned int nwakeirq_map; }; extern const struct dev_pm_ops msm_pinctrl_dev_pm_ops; From patchwork Thu Aug 29 18:12:00 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Lina Iyer X-Patchwork-Id: 11122221 Return-Path: Received: from mail.kernel.org (pdx-korg-mail-1.web.codeaurora.org [172.30.200.123]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id 557941395 for ; Thu, 29 Aug 2019 18:28:51 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.kernel.org (Postfix) with ESMTP id 32A4C205C9 for ; Thu, 29 Aug 2019 18:28:51 +0000 (UTC) Authentication-Results: mail.kernel.org; dkim=fail reason="key not found in DNS" (0-bit key) header.d=codeaurora.org header.i=@codeaurora.org header.b="hnGcdSvC"; dkim=fail reason="key not found in DNS" (0-bit key) header.d=codeaurora.org header.i=@codeaurora.org header.b="MmrHriln" Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1729353AbfH2S2f (ORCPT ); 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Thu, 29 Aug 2019 18:12:30 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=codeaurora.org; s=default; t=1567102351; bh=KRYbwxgKTx0pR8Tqhajtg5Ur7vEwP9WSyPmjMrZBHXw=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=MmrHrilnyHUHaYN4DJEQd+ldJQ3LIfwLHvfXQdJNkGHkO3PVjMEEqGB20uBdQ1awO vQGLC1BmIZuEWcwldfti6dex6n6lTNkCb/wU9ZjH7c89p081ABfJzQf6ykbVtOqCWP uUQQ8aamVcyufnyPyQXo0auGiU0pc4D6kGEDw+8A= DMARC-Filter: OpenDMARC Filter v1.3.2 smtp.codeaurora.org 425D068A3E Authentication-Results: pdx-caf-mail.web.codeaurora.org; dmarc=none (p=none dis=none) header.from=codeaurora.org Authentication-Results: pdx-caf-mail.web.codeaurora.org; spf=none smtp.mailfrom=ilina@codeaurora.org From: Lina Iyer To: swboyd@chromium.org, evgreen@chromium.org, marc.zyngier@arm.com, linus.walleij@linaro.org Cc: linux-kernel@vger.kernel.org, linux-arm-msm@vger.kernel.org, bjorn.andersson@linaro.org, mkshah@codeaurora.org, linux-gpio@vger.kernel.org, rnayak@codeaurora.org, Lina Iyer Subject: [PATCH RFC 11/14] drivers: pinctrl: sdm845: add PDC wakeup interrupt map for GPIOs Date: Thu, 29 Aug 2019 12:12:00 -0600 Message-Id: <20190829181203.2660-12-ilina@codeaurora.org> X-Mailer: git-send-email 2.22.0 In-Reply-To: <20190829181203.2660-1-ilina@codeaurora.org> References: <20190829181203.2660-1-ilina@codeaurora.org> MIME-Version: 1.0 Sender: linux-arm-msm-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-arm-msm@vger.kernel.org Add interrupt parents for wakeup capable GPIOs for Qualcomm SDM845 SoC. Signed-off-by: Lina Iyer --- drivers/pinctrl/qcom/pinctrl-sdm845.c | 83 ++++++++++++++++++++++++++- 1 file changed, 82 insertions(+), 1 deletion(-) diff --git a/drivers/pinctrl/qcom/pinctrl-sdm845.c b/drivers/pinctrl/qcom/pinctrl-sdm845.c index 39f498c09906..5f43dabcd8eb 100644 --- a/drivers/pinctrl/qcom/pinctrl-sdm845.c +++ b/drivers/pinctrl/qcom/pinctrl-sdm845.c @@ -1,6 +1,6 @@ // SPDX-License-Identifier: GPL-2.0 /* - * Copyright (c) 2016-2018, The Linux Foundation. All rights reserved. + * Copyright (c) 2016-2019, The Linux Foundation. All rights reserved. */ #include @@ -1282,6 +1282,84 @@ static const int sdm845_acpi_reserved_gpios[] = { 0, 1, 2, 3, 81, 82, 83, 84, -1 }; +static const struct msm_gpio_wakeirq_map sdm845_pdc_map[] = { + {1, 30}, + {3, 31}, + {5, 32}, + {10, 33}, + {11, 34}, + {20, 35}, + {22, 36}, + {24, 37}, + {26, 38}, + {30, 39}, + {31, 117}, + {32, 41}, + {34, 42}, + {36, 43}, + {37, 44}, + {38, 45}, + {39, 46}, + {40, 47}, + {41, 115}, + {43, 49}, + {44, 50}, + {46, 51}, + {48, 52}, + {49, 118}, + {52, 54}, + {53, 55}, + {54, 56}, + {56, 57}, + {57, 58}, + {58, 59}, + {59, 60}, + {60, 61}, + {61, 62}, + {62, 63}, + {63, 64}, + {64, 65}, + {66, 66}, + {68, 67}, + {71, 68}, + {73, 69}, + {77, 70}, + {78, 71}, + {79, 72}, + {80, 73}, + {84, 74}, + {85, 75}, + {86, 76}, + {88, 77}, + {89, 116}, + {91, 79}, + {92, 80}, + {95, 81}, + {96, 82}, + {97, 83}, + {101, 84}, + {103, 85}, + {104, 86}, + {115, 90}, + {116, 91}, + {117, 92}, + {118, 93}, + {119, 94}, + {120, 95}, + {121, 96}, + {122, 97}, + {123, 98}, + {124, 99}, + {125, 100}, + {127, 102}, + {128, 103}, + {129, 104}, + {130, 105}, + {132, 106}, + {133, 107}, + {145, 108}, +}; + static const struct msm_pinctrl_soc_data sdm845_pinctrl = { .pins = sdm845_pins, .npins = ARRAY_SIZE(sdm845_pins), @@ -1290,6 +1368,9 @@ static const struct msm_pinctrl_soc_data sdm845_pinctrl = { .groups = sdm845_groups, .ngroups = ARRAY_SIZE(sdm845_groups), .ngpios = 151, + .wakeirq_map = sdm845_pdc_map, + .nwakeirq_map = ARRAY_SIZE(sdm845_pdc_map), + }; static const struct msm_pinctrl_soc_data sdm845_acpi_pinctrl = { From patchwork Thu Aug 29 18:12:01 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Lina Iyer X-Patchwork-Id: 11122211 Return-Path: Received: from mail.kernel.org (pdx-korg-mail-1.web.codeaurora.org [172.30.200.123]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id AD3CB14D5 for ; Thu, 29 Aug 2019 18:26:20 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.kernel.org (Postfix) with ESMTP id 8B2172339E for ; Thu, 29 Aug 2019 18:26:20 +0000 (UTC) Authentication-Results: mail.kernel.org; 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Thu, 29 Aug 2019 18:12:31 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=codeaurora.org; s=default; t=1567102353; bh=BLLEmixfGGtKTMt3kN2ZQV5lnoo8OcCb4fQaHMm4IdU=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=eOlBBdXM8HbGfBS28FOVWykOj/WhXUte0t5oR+Ma8p+9p7oUnqGEbxaOxl/3GgHZu 3yrMfiZZBO/C1dYOSfs5AKOkro3LW92VcZ1KbXrYRM9qM4hitd68S0uDHw0uF0h0z0 YIKyF8n3aKhpMc/sM4RYxpfzVW/0osYJrFRoJppI= DMARC-Filter: OpenDMARC Filter v1.3.2 smtp.codeaurora.org D016168A65 Authentication-Results: pdx-caf-mail.web.codeaurora.org; dmarc=none (p=none dis=none) header.from=codeaurora.org Authentication-Results: pdx-caf-mail.web.codeaurora.org; spf=none smtp.mailfrom=ilina@codeaurora.org From: Lina Iyer To: swboyd@chromium.org, evgreen@chromium.org, marc.zyngier@arm.com, linus.walleij@linaro.org Cc: linux-kernel@vger.kernel.org, linux-arm-msm@vger.kernel.org, bjorn.andersson@linaro.org, mkshah@codeaurora.org, linux-gpio@vger.kernel.org, rnayak@codeaurora.org, Lina Iyer Subject: [PATCH RFC 12/14] arm64: dts: qcom: add PDC interrupt controller for SDM845 Date: Thu, 29 Aug 2019 12:12:01 -0600 Message-Id: <20190829181203.2660-13-ilina@codeaurora.org> X-Mailer: git-send-email 2.22.0 In-Reply-To: <20190829181203.2660-1-ilina@codeaurora.org> References: <20190829181203.2660-1-ilina@codeaurora.org> MIME-Version: 1.0 Sender: linux-arm-msm-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-arm-msm@vger.kernel.org Add PDC interrupt controller device bindings for SDM845. Signed-off-by: Lina Iyer --- arch/arm64/boot/dts/qcom/sdm845.dtsi | 10 ++++++++++ 1 file changed, 10 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/sdm845.dtsi b/arch/arm64/boot/dts/qcom/sdm845.dtsi index be0022e09465..ffe28b3e41d8 100644 --- a/arch/arm64/boot/dts/qcom/sdm845.dtsi +++ b/arch/arm64/boot/dts/qcom/sdm845.dtsi @@ -2375,6 +2375,16 @@ #power-domain-cells = <1>; }; + pdc_intc: interrupt-controller@b220000 { + compatible = "qcom,sdm845-pdc"; + reg = <0 0x0b220000 0 0x30000>, <0x179900f0 0x60>; + qcom,pdc-ranges = <0 480 94>, <94 609 15>, <115 630 7>; + #interrupt-cells = <2>; + interrupt-parent = <&intc>; + interrupt-controller; + qcom,scm-spi-cfg; + }; + pdc_reset: reset-controller@b2e0000 { compatible = "qcom,sdm845-pdc-global"; reg = <0 0x0b2e0000 0 0x20000>; From patchwork Thu Aug 29 18:12:02 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Lina Iyer X-Patchwork-Id: 11122349 Return-Path: Received: from mail.kernel.org (pdx-korg-mail-1.web.codeaurora.org [172.30.200.123]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id 722501398 for ; Thu, 29 Aug 2019 18:43:44 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.kernel.org (Postfix) with ESMTP id 4E3B221726 for ; Thu, 29 Aug 2019 18:43:44 +0000 (UTC) Authentication-Results: mail.kernel.org; dkim=fail reason="key not found in DNS" (0-bit key) header.d=codeaurora.org header.i=@codeaurora.org header.b="aqxWGZfO"; dkim=fail reason="key not found in DNS" (0-bit key) header.d=codeaurora.org header.i=@codeaurora.org header.b="hZG8Qr4f" Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1728061AbfH2Snn (ORCPT ); Thu, 29 Aug 2019 14:43:43 -0400 Received: from smtp.codeaurora.org ([198.145.29.96]:53652 "EHLO smtp.codeaurora.org" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1727779AbfH2Snn (ORCPT ); Thu, 29 Aug 2019 14:43:43 -0400 Received: by smtp.codeaurora.org (Postfix, from userid 1000) id 7F956675E1; Thu, 29 Aug 2019 18:12:35 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=codeaurora.org; s=default; t=1567104222; bh=/sOoz74UPGyBboFaMGdZyPO+sOZ6PBTKdK3o6MAKGHA=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=aqxWGZfOvSzqn1LDCrvQXCsmpBkvl7aODdeYzgVyt7oXFG7QHPDMIc3m7CTJPIYt1 AdtmabNN6B6TRhpHw6qyTzrQAI9gQLLCNEcrj/WtHF+Y1b7vzMbcTrzVLoIxQI+T6v QPU5p1Updd9bkWoJVLo86epvl0l2N8VyY+PsJ8Nc= X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on pdx-caf-mail.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-2.7 required=2.0 tests=ALL_TRUSTED,BAYES_00, DKIM_INVALID,DKIM_SIGNED,SPF_NONE autolearn=no autolearn_force=no version=3.4.0 Received: from codeaurora.org (i-global254.qualcomm.com [199.106.103.254]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-SHA256 (128/128 bits)) (No client certificate requested) (Authenticated sender: ilina@smtp.codeaurora.org) by smtp.codeaurora.org (Postfix) with ESMTPSA id 7BA8768A9D; Thu, 29 Aug 2019 18:12:33 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=codeaurora.org; s=default; t=1567102354; bh=/sOoz74UPGyBboFaMGdZyPO+sOZ6PBTKdK3o6MAKGHA=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=hZG8Qr4fdVY+rC2UORwJh1tT1eBgNorNNMKsb0LwZN6Kv94b2LFyz7Ks0vBvphc4o wEKncnbv0mlFwJ+MaWzUcZqUXpLm/jiasJvoI9ae+eJfdd4GfIYVXPuwt/onobtKNN /P80GowTsvHU6NV66jirRZIrPA1U+C8Ok6GU1AZ8= DMARC-Filter: OpenDMARC Filter v1.3.2 smtp.codeaurora.org 7BA8768A9D Authentication-Results: pdx-caf-mail.web.codeaurora.org; dmarc=none (p=none dis=none) header.from=codeaurora.org Authentication-Results: pdx-caf-mail.web.codeaurora.org; spf=none smtp.mailfrom=ilina@codeaurora.org From: Lina Iyer To: swboyd@chromium.org, evgreen@chromium.org, marc.zyngier@arm.com, linus.walleij@linaro.org Cc: linux-kernel@vger.kernel.org, linux-arm-msm@vger.kernel.org, bjorn.andersson@linaro.org, mkshah@codeaurora.org, linux-gpio@vger.kernel.org, rnayak@codeaurora.org, Lina Iyer Subject: [PATCH RFC 13/14] arm64: dts: qcom: setup PDC as the wakeup parent for TLMM on SDM845 Date: Thu, 29 Aug 2019 12:12:02 -0600 Message-Id: <20190829181203.2660-14-ilina@codeaurora.org> X-Mailer: git-send-email 2.22.0 In-Reply-To: <20190829181203.2660-1-ilina@codeaurora.org> References: <20190829181203.2660-1-ilina@codeaurora.org> MIME-Version: 1.0 Sender: linux-arm-msm-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-arm-msm@vger.kernel.org PDC always-on interrupt controller can detect certain GPIOs even when the TLMM interrupt controller is powered off. Link the PDC as TLMM's wakeup parent. Signed-off-by: Lina Iyer --- arch/arm64/boot/dts/qcom/sdm845.dtsi | 1 + 1 file changed, 1 insertion(+) diff --git a/arch/arm64/boot/dts/qcom/sdm845.dtsi b/arch/arm64/boot/dts/qcom/sdm845.dtsi index ffe28b3e41d8..3002793ee688 100644 --- a/arch/arm64/boot/dts/qcom/sdm845.dtsi +++ b/arch/arm64/boot/dts/qcom/sdm845.dtsi @@ -1358,6 +1358,7 @@ interrupt-controller; #interrupt-cells = <2>; gpio-ranges = <&tlmm 0 0 150>; + wakeup-parent = <&pdc_intc>; qspi_clk: qspi-clk { pinmux { From patchwork Thu Aug 29 18:12:03 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Lina Iyer X-Patchwork-Id: 11122323 Return-Path: Received: from mail.kernel.org (pdx-korg-mail-1.web.codeaurora.org [172.30.200.123]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id 650EA14DE for ; Thu, 29 Aug 2019 18:33:27 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.kernel.org (Postfix) with ESMTP id 3F8D62339E for ; Thu, 29 Aug 2019 18:33:27 +0000 (UTC) Authentication-Results: mail.kernel.org; dkim=fail reason="key not found in DNS" (0-bit key) header.d=codeaurora.org header.i=@codeaurora.org header.b="ejFquLtQ"; dkim=fail reason="key not found in DNS" (0-bit key) header.d=codeaurora.org header.i=@codeaurora.org header.b="COkHEyYb" Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1729341AbfH2SdT (ORCPT ); Thu, 29 Aug 2019 14:33:19 -0400 Received: from smtp.codeaurora.org ([198.145.29.96]:54764 "EHLO smtp.codeaurora.org" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1728460AbfH2SdT (ORCPT ); Thu, 29 Aug 2019 14:33:19 -0400 Received: by smtp.codeaurora.org (Postfix, from userid 1000) id 54E1C675E8; Thu, 29 Aug 2019 18:12:37 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=codeaurora.org; s=default; t=1567103598; bh=VsK0OWT4NrTuulRjb3e+y0lwEFWmdZz0LJdwLaeX5m8=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=ejFquLtQhxvoaLkFyTBOPDf2aHwbiabfhzMxIJjCa2QUGTBw5V+NNzhT7+B88xXNh WvhAGcx3o5AV9JD3WNw+8GTA0559qRsi40sNmQBIpRcmxKMtei221TSU8lcdMi9MJj r/5SBVZ+jpi9mHSe4RRAYBVc6YD/XcvFpQmOooTw= X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on pdx-caf-mail.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-2.7 required=2.0 tests=ALL_TRUSTED,BAYES_00, DKIM_INVALID,DKIM_SIGNED,SPF_NONE autolearn=no autolearn_force=no version=3.4.0 Received: from codeaurora.org (i-global254.qualcomm.com [199.106.103.254]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-SHA256 (128/128 bits)) (No client certificate requested) (Authenticated sender: ilina@smtp.codeaurora.org) by smtp.codeaurora.org (Postfix) with ESMTPSA id 2B1CB686B7; Thu, 29 Aug 2019 18:12:35 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=codeaurora.org; s=default; t=1567102356; bh=VsK0OWT4NrTuulRjb3e+y0lwEFWmdZz0LJdwLaeX5m8=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=COkHEyYbgqarmuN0Zt5gpdNFOQq5sGO5AUQwqSo5TY2zr8p3RUVC70IVq4yMSFlon YHiXCVcgVsgmxi92xn0RnpqPoEu9Mkg30jL5LnKGnZXSEVcZeB/dpaqRSbqI7j0s6u D1Ga0+ftGLMnRmszB4PaH1PY55ZRZ8xU3laV9aN0= DMARC-Filter: OpenDMARC Filter v1.3.2 smtp.codeaurora.org 2B1CB686B7 Authentication-Results: pdx-caf-mail.web.codeaurora.org; dmarc=none (p=none dis=none) header.from=codeaurora.org Authentication-Results: pdx-caf-mail.web.codeaurora.org; spf=none smtp.mailfrom=ilina@codeaurora.org From: Lina Iyer To: swboyd@chromium.org, evgreen@chromium.org, marc.zyngier@arm.com, linus.walleij@linaro.org Cc: linux-kernel@vger.kernel.org, linux-arm-msm@vger.kernel.org, bjorn.andersson@linaro.org, mkshah@codeaurora.org, linux-gpio@vger.kernel.org, rnayak@codeaurora.org, Lina Iyer Subject: [PATCH RFC 14/14] arm64: defconfig: enable PDC interrupt controller for Qualcomm SDM845 Date: Thu, 29 Aug 2019 12:12:03 -0600 Message-Id: <20190829181203.2660-15-ilina@codeaurora.org> X-Mailer: git-send-email 2.22.0 In-Reply-To: <20190829181203.2660-1-ilina@codeaurora.org> References: <20190829181203.2660-1-ilina@codeaurora.org> MIME-Version: 1.0 Sender: linux-arm-msm-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-arm-msm@vger.kernel.org Enable PDC interrupt controller for SDM845 devices. The interrupt controller can detect wakeup capable interrupts when the SoC is in a low power state. Signed-off-by: Lina Iyer --- arch/arm64/configs/defconfig | 1 + 1 file changed, 1 insertion(+) diff --git a/arch/arm64/configs/defconfig b/arch/arm64/configs/defconfig index 0e58ef02880c..310b6048054a 100644 --- a/arch/arm64/configs/defconfig +++ b/arch/arm64/configs/defconfig @@ -729,6 +729,7 @@ CONFIG_ARCH_R8A77970=y CONFIG_ARCH_R8A77980=y CONFIG_ARCH_R8A77990=y CONFIG_ARCH_R8A77995=y +CONFIG_QCOM_PDC=y CONFIG_ROCKCHIP_PM_DOMAINS=y CONFIG_ARCH_TEGRA_132_SOC=y CONFIG_ARCH_TEGRA_210_SOC=y