From patchwork Fri Aug 30 02:23:10 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Ben Chuang X-Patchwork-Id: 11122811 Return-Path: Received: from mail.kernel.org (pdx-korg-mail-1.web.codeaurora.org [172.30.200.123]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id 4B66114D5 for ; Fri, 30 Aug 2019 02:23:13 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.kernel.org (Postfix) with ESMTP id 28A0720644 for ; Fri, 30 Aug 2019 02:23:13 +0000 (UTC) Authentication-Results: mail.kernel.org; dkim=pass (2048-bit key) header.d=gmail.com header.i=@gmail.com header.b="rWDWXTP7" Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1727361AbfH3CXM (ORCPT ); Thu, 29 Aug 2019 22:23:12 -0400 Received: from mail-pf1-f194.google.com ([209.85.210.194]:43144 "EHLO mail-pf1-f194.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1727344AbfH3CXM (ORCPT ); Thu, 29 Aug 2019 22:23:12 -0400 Received: by mail-pf1-f194.google.com with SMTP id v12so3496405pfn.10; Thu, 29 Aug 2019 19:23:12 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=from:to:cc:subject:date:message-id:mime-version :content-transfer-encoding; bh=kyP8YtTFMbDNG7qsSo2w5pZq5BUurmqPvqGOvI+33I4=; b=rWDWXTP702wCGI624fpXgt3wQTyudNC5ks+AxLmDINU0IG4hpia4jffy04LubJ+6FJ 3J9fzomGghyOAFnNdIHOF92yQes/q9vsDG6AtSF/MYC/5/NC68QPpTardqn+t/tyrxpI 64Ic+KzV2muXl7r97bMzxEH53rWDI9omFh9KAdJp+QBPzhDyDRMLZigFWK6Ux4nrOGln +jpirFjI3lO1Z1hy+s54+fHYuX++TiY7g6IthPlRxKstTiCD7XEsSRP9ilR3O/mE81oR zAcgaDkXM47vtcrkUMlMGeKuDfA5hxP97i/uXSpo/OuBUvySOy2UqQZFEwuTu3NFwizs Y1DQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:mime-version :content-transfer-encoding; bh=kyP8YtTFMbDNG7qsSo2w5pZq5BUurmqPvqGOvI+33I4=; b=gytAb3y4fOVZzvhxhg99ieCDR2B1nKK6kNzC0ywF47hUfSlLM28nQJkRVl5u1GVz4A Ss5+i34Ez/z37k/QUAe3M2+SZH5Iwb/I2uya4VII7iCO6Qjb0i96nyBuRF2mOjqAkKgK CiGTsSSK+qt+1fRXUVQHdje/lqNdifnFznJ+Hk0iPfbmp7qiN0mfbsNl229WmpHEwwW8 4hasCFMLZPYFPBjkprIGGBB99wUKridUm1NC2LEjLSHLH/1DkbKUAQF15s/TGFAv6XKO aZ2HW1mOe/sKwONbmMnGuRTUdb9SQXkTvow2e9/BizwFOeiKR5e1rBZXf5EBH5ThlpHf 0+RA== X-Gm-Message-State: APjAAAV8NRRkPujBzWC0MtE7BNhmahaX3I+CxO8zbPBJVlR47trsLq6+ Vz7PXPHKSCLijA67vp7Z6UA6FQgg X-Google-Smtp-Source: APXvYqwNoezNZPMbXavWEQcLm3PgRE/QzsUs6IR2c9RsVMOYbOJ/axfZDqM7Kc++s47GBrpL7Emfhw== X-Received: by 2002:a62:8344:: with SMTP id h65mr15360588pfe.85.1567131791880; Thu, 29 Aug 2019 19:23:11 -0700 (PDT) Received: from gli-arch.genesyslogic.com.tw (60-251-58-169.HINET-IP.hinet.net. [60.251.58.169]) by smtp.gmail.com with ESMTPSA id a11sm3231896pju.2.2019.08.29.19.23.09 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 29 Aug 2019 19:23:11 -0700 (PDT) From: Ben Chuang To: adrian.hunter@intel.com, ulf.hansson@linaro.org Cc: linux-mmc@vger.kernel.org, linux-kernel@vger.kernel.org, johnsonm@danlj.org, ben.chuang@genesyslogic.com.tw, Ben Chuang Subject: [PATCH V7 1/5] mmc: sdhci: Change timeout of loop for checking internal clock stable Date: Fri, 30 Aug 2019 10:23:10 +0800 Message-Id: <20190830022310.8299-1-benchuanggli@gmail.com> X-Mailer: git-send-email 2.22.1 MIME-Version: 1.0 Sender: linux-mmc-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-mmc@vger.kernel.org From: Ben Chuang According to section 3.2.1 internal clock setup in SD Host Controller Simplified Specifications 4.20, the timeout of loop for checking internal clock stable is defined as 150ms. Signed-off-by: Ben Chuang Co-developed-by: Michael K Johnson Signed-off-by: Michael K Johnson Acked-by: Adrian Hunter --- drivers/mmc/host/sdhci.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/drivers/mmc/host/sdhci.c b/drivers/mmc/host/sdhci.c index 59acf8e3331e..bed0760a6c2a 100644 --- a/drivers/mmc/host/sdhci.c +++ b/drivers/mmc/host/sdhci.c @@ -1636,8 +1636,8 @@ void sdhci_enable_clk(struct sdhci_host *host, u16 clk) clk |= SDHCI_CLOCK_INT_EN; sdhci_writew(host, clk, SDHCI_CLOCK_CONTROL); - /* Wait max 20 ms */ - timeout = ktime_add_ms(ktime_get(), 20); + /* Wait max 150 ms */ + timeout = ktime_add_ms(ktime_get(), 150); while (1) { bool timedout = ktime_after(ktime_get(), timeout); From patchwork Fri Aug 30 02:23:25 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Ben Chuang X-Patchwork-Id: 11122813 Return-Path: Received: from mail.kernel.org (pdx-korg-mail-1.web.codeaurora.org [172.30.200.123]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id B74C914D5 for ; Fri, 30 Aug 2019 02:23:28 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.kernel.org (Postfix) with ESMTP id 9380B21874 for ; Fri, 30 Aug 2019 02:23:28 +0000 (UTC) Authentication-Results: mail.kernel.org; dkim=pass (2048-bit key) header.d=gmail.com header.i=@gmail.com header.b="KZkZXYNn" Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1727392AbfH3CX1 (ORCPT ); Thu, 29 Aug 2019 22:23:27 -0400 Received: from mail-pf1-f196.google.com ([209.85.210.196]:37063 "EHLO mail-pf1-f196.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1727344AbfH3CX1 (ORCPT ); Thu, 29 Aug 2019 22:23:27 -0400 Received: by mail-pf1-f196.google.com with SMTP id y9so3512312pfl.4; Thu, 29 Aug 2019 19:23:27 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=from:to:cc:subject:date:message-id:mime-version :content-transfer-encoding; bh=189g0JP68z9u+Ep1GWrcVIMocc6+TBCdAX4Yd+2DXKM=; b=KZkZXYNnsSOYG4pBmr3NpVOqOvf7VPO/THlxI88gRD31nCWIDvzbA3wEhdyF6CqeMx s4YmBLm2aN+FmjsRvg8q8i15zKSxJclUqrgQTVy+tiZWOuvEG46tp6993lhhpl+kG//i 7uVazj0a2Pzzs5r6VD3ZDCgAZjYbiVlRAKzZbgsGO1Lj6A3fTtKCLuXlwfjD37lPa2CV EYWMgalEtjy5moP21SSxY9J/ZnwWmGPuGlgEoHm5tXjhUfmIUTvEKFY6RDau1nxan1xY tEq4JVUrPHtznWP+gHW7k181+zOT/TVBHJ6ZTkRtdCbqz/6OrP+KLH0MT9Oen5K3qp4S ikKQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:mime-version :content-transfer-encoding; bh=189g0JP68z9u+Ep1GWrcVIMocc6+TBCdAX4Yd+2DXKM=; b=ThmgKEAkisuS63sKy0C5oxkZaHzcev/2aTpdwMbFm6nd3+USchIb/GBsVbEQLG2cJL ugfk/4uCxFrzPhjZFWXPFh14Fqloi9ZevoOyzmqCJIOOOafrIxTeK8wZBOrbOKStSal1 GH7/cTYSB6tJ0ZBQaBuAQbTGLuyAWqcwnvlif6jFGLPtyfEy+4cyZHLeR+fHOzcZ44ju LNGCawi/Q6osPPX0TIDB2rOBcVMNs0Udu26HjKCQJisw/9glOcuzmgurhuH46Ge8QIU5 MWLPGjjoSUdTdyJ/SxEqSzIzj8aUa8RJjQjEHNFnZQGHTx9x4qhXOFUWd1muy7Muny2T WRJw== X-Gm-Message-State: APjAAAUI/zfBQZ6CA2g4ZdD3+T+jS0N6irMwX7qfe6w+HSVjwyPgQQrL D9QmgwgpMnyXytbbywkcybA= X-Google-Smtp-Source: APXvYqz98XE7ZA33vSW3tGTSup6MQ14PIAiPIRYNP8U7FD5EtdNbLDTw2qEr2RUy8sVxZesoZ00FXw== X-Received: by 2002:a63:2c8:: with SMTP id 191mr10828976pgc.139.1567131807077; Thu, 29 Aug 2019 19:23:27 -0700 (PDT) Received: from gli-arch.genesyslogic.com.tw (60-251-58-169.HINET-IP.hinet.net. [60.251.58.169]) by smtp.gmail.com with ESMTPSA id l124sm8652379pgl.54.2019.08.29.19.23.25 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 29 Aug 2019 19:23:26 -0700 (PDT) From: Ben Chuang To: adrian.hunter@intel.com, ulf.hansson@linaro.org Cc: linux-mmc@vger.kernel.org, linux-kernel@vger.kernel.org, johnsonm@danlj.org, ben.chuang@genesyslogic.com.tw, Ben Chuang Subject: [PATCH V7 2/5] mmc: sdhci: Add PLL Enable support to internal clock setup Date: Fri, 30 Aug 2019 10:23:25 +0800 Message-Id: <20190830022325.8348-1-benchuanggli@gmail.com> X-Mailer: git-send-email 2.22.1 MIME-Version: 1.0 Sender: linux-mmc-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-mmc@vger.kernel.org From: Ben Chuang The GL9750 and GL9755 chipsets, and possibly others, require PLL Enable setup as part of the internal clock setup as described in 3.2.1 Internal Clock Setup Sequence of SD Host Controller Simplified Specification Version 4.20. Signed-off-by: Ben Chuang Co-developed-by: Michael K Johnson Signed-off-by: Michael K Johnson Acked-by: Adrian Hunter --- drivers/mmc/host/sdhci.c | 23 +++++++++++++++++++++++ drivers/mmc/host/sdhci.h | 1 + 2 files changed, 24 insertions(+) diff --git a/drivers/mmc/host/sdhci.c b/drivers/mmc/host/sdhci.c index bed0760a6c2a..9106ebc7a422 100644 --- a/drivers/mmc/host/sdhci.c +++ b/drivers/mmc/host/sdhci.c @@ -1653,6 +1653,29 @@ void sdhci_enable_clk(struct sdhci_host *host, u16 clk) udelay(10); } + if (host->version >= SDHCI_SPEC_410 && host->v4_mode) { + clk |= SDHCI_CLOCK_PLL_EN; + clk &= ~SDHCI_CLOCK_INT_STABLE; + sdhci_writew(host, clk, SDHCI_CLOCK_CONTROL); + + /* Wait max 150 ms */ + timeout = ktime_add_ms(ktime_get(), 150); + while (1) { + bool timedout = ktime_after(ktime_get(), timeout); + + clk = sdhci_readw(host, SDHCI_CLOCK_CONTROL); + if (clk & SDHCI_CLOCK_INT_STABLE) + break; + if (timedout) { + pr_err("%s: PLL clock never stabilised.\n", + mmc_hostname(host->mmc)); + sdhci_dumpregs(host); + return; + } + udelay(10); + } + } + clk |= SDHCI_CLOCK_CARD_EN; sdhci_writew(host, clk, SDHCI_CLOCK_CONTROL); } diff --git a/drivers/mmc/host/sdhci.h b/drivers/mmc/host/sdhci.h index 199712e7adbb..72601a4d2e95 100644 --- a/drivers/mmc/host/sdhci.h +++ b/drivers/mmc/host/sdhci.h @@ -114,6 +114,7 @@ #define SDHCI_DIV_HI_MASK 0x300 #define SDHCI_PROG_CLOCK_MODE 0x0020 #define SDHCI_CLOCK_CARD_EN 0x0004 +#define SDHCI_CLOCK_PLL_EN 0x0008 #define SDHCI_CLOCK_INT_STABLE 0x0002 #define SDHCI_CLOCK_INT_EN 0x0001 From patchwork Fri Aug 30 02:24:49 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Ben Chuang X-Patchwork-Id: 11122815 Return-Path: Received: from mail.kernel.org (pdx-korg-mail-1.web.codeaurora.org [172.30.200.123]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id 4C86B14D5 for ; Fri, 30 Aug 2019 02:24:52 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.kernel.org (Postfix) with ESMTP id 2A13621726 for ; Fri, 30 Aug 2019 02:24:52 +0000 (UTC) Authentication-Results: mail.kernel.org; dkim=pass (2048-bit key) header.d=gmail.com header.i=@gmail.com header.b="AEE15Scq" Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1727398AbfH3CYv (ORCPT ); Thu, 29 Aug 2019 22:24:51 -0400 Received: from mail-pg1-f195.google.com ([209.85.215.195]:41598 "EHLO mail-pg1-f195.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1727344AbfH3CYv (ORCPT ); Thu, 29 Aug 2019 22:24:51 -0400 Received: by mail-pg1-f195.google.com with SMTP id x15so2668840pgg.8; Thu, 29 Aug 2019 19:24:51 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=from:to:cc:subject:date:message-id:mime-version :content-transfer-encoding; bh=qfHiLZajGyQDnbfm/jvtW9Y9R5M2p7DW5ZQEIckHoIU=; b=AEE15Scqgeqfee6h9MeLygul9EiReiKiMPLySc5IHgyQDjIttqvfWRkTeHoR9cQ4ZC Bs8a+YMTsmvohPYqoa4ZISQRzf5MbaafXCVf/lvEbJCu/YCast/gVqy7hn3/3qniO9Zp Ofm4j+/PgRGeegh9vSk86mryoeb+TAfrMK/i/vpVWwato9FosqnNRsyWn+mAB3evqWjT Hkk7cBUThfvhb4JTR3JQdibcJEo7ZDKTj7ZigD0z56phvENT5F1Yjkq1PLGaV4nsoJHG yFK5ephsFoBT9XYnA5TG8p/MCcpY5l6kRaY5bw4TtQ5y3k5JLUKLdfB7vcDzdMsAVV7s PRJQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:mime-version :content-transfer-encoding; bh=qfHiLZajGyQDnbfm/jvtW9Y9R5M2p7DW5ZQEIckHoIU=; b=G1dMsfWqCbiWwYdN4aYM4ymK2o8NGPgyQan9dyE+O4ZwFEe+Kd+hUmO+v6v5NNR6jy iYV9177BOrguY2c6KvqYfg6UgGdAVGcY05PRv1z1W34vUIc2EENzYwi7vg9j2st/xWyo a0kVtt64AeEeSkCr2S+LNz54FD7olt8Yaske2l0Xj0NUi5BCRP13N9+mwmKSz0M3q8WO bg5RBmLLQ0cE7IcAhm/u88rwUHLBVYdpnE1msA5ZWI3lak9V51F+B9txhTNWjzSVwxE+ k1pIoMcERpdyrl/OcImTP8jrZheXcYNMkzGv177Uw4KgyKpYKNv4P3EJhaxvkkzssYXE bu5A== X-Gm-Message-State: APjAAAXIhDaCDPA8DWF2Jh2kIA7zTZcO8yaYtW5nCUqLbyeY4F83v38L COto5gcyi4BZthdjGAk7geo= X-Google-Smtp-Source: APXvYqzHxjwFfhhNfzkE0ZbWpuup5FH96HqX+rEvBA5/FoBj8a68JGhKksj2O3CU5esDbG3a+sOx/A== X-Received: by 2002:a62:e50f:: with SMTP id n15mr12638906pff.208.1567131890874; Thu, 29 Aug 2019 19:24:50 -0700 (PDT) Received: from gli-arch.genesyslogic.com.tw (60-251-58-169.HINET-IP.hinet.net. [60.251.58.169]) by smtp.gmail.com with ESMTPSA id 6sm4890944pfa.7.2019.08.29.19.24.49 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 29 Aug 2019 19:24:50 -0700 (PDT) From: Ben Chuang To: adrian.hunter@intel.com, ulf.hansson@linaro.org Cc: linux-mmc@vger.kernel.org, linux-kernel@vger.kernel.org, johnsonm@danlj.org, ben.chuang@genesyslogic.com.tw, Ben Chuang Subject: [PATCH V7 3/5] PCI: Add Genesys Logic, Inc. Vendor ID Date: Fri, 30 Aug 2019 10:24:49 +0800 Message-Id: <20190830022449.8445-1-benchuanggli@gmail.com> X-Mailer: git-send-email 2.22.1 MIME-Version: 1.0 Sender: linux-mmc-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-mmc@vger.kernel.org From: Ben Chuang Add the Genesys Logic, Inc. vendor ID to pci_ids.h. Signed-off-by: Ben Chuang Co-developed-by: Michael K Johnson Signed-off-by: Michael K Johnson Acked-by: Adrian Hunter --- include/linux/pci_ids.h | 2 ++ 1 file changed, 2 insertions(+) diff --git a/include/linux/pci_ids.h b/include/linux/pci_ids.h index 70e86148cb1e..4f7e12772a14 100644 --- a/include/linux/pci_ids.h +++ b/include/linux/pci_ids.h @@ -2403,6 +2403,8 @@ #define PCI_DEVICE_ID_RDC_R6061 0x6061 #define PCI_DEVICE_ID_RDC_D1010 0x1010 +#define PCI_VENDOR_ID_GLI 0x17a0 + #define PCI_VENDOR_ID_LENOVO 0x17aa #define PCI_VENDOR_ID_QCOM 0x17cb From patchwork Fri Aug 30 02:25:05 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Ben Chuang X-Patchwork-Id: 11122817 Return-Path: Received: from mail.kernel.org (pdx-korg-mail-1.web.codeaurora.org [172.30.200.123]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id 2DA3714D5 for ; Fri, 30 Aug 2019 02:25:15 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.kernel.org (Postfix) with ESMTP id 0895021874 for ; Fri, 30 Aug 2019 02:25:15 +0000 (UTC) Authentication-Results: mail.kernel.org; dkim=pass (2048-bit key) header.d=gmail.com header.i=@gmail.com header.b="Y0t9Y5cu" Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1727739AbfH3CZL (ORCPT ); Thu, 29 Aug 2019 22:25:11 -0400 Received: from mail-pl1-f193.google.com ([209.85.214.193]:39041 "EHLO mail-pl1-f193.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1727410AbfH3CZL (ORCPT ); Thu, 29 Aug 2019 22:25:11 -0400 Received: by mail-pl1-f193.google.com with SMTP id az1so1599127plb.6; Thu, 29 Aug 2019 19:25:10 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=from:to:cc:subject:date:message-id:mime-version :content-transfer-encoding; bh=Ikyf+TpBSFgGm7Vdpj1oS/xRxlgH+ALj4QoDRbTjVfY=; b=Y0t9Y5cuF6YAJ6Ar5+Ja9HO/s+x8MS5BKtq5Z6eVy3T8K8sKLZgIJdWiLeTZ0ahMYu PvBil1ljM4+nJWF4P90lOpkHmtqAnhujFau4LD4ORtod9Hw+TVuXmTGJ5X2h3nKt7kQ1 jZTGPVqW4oBqp85uxYmiqFYCojUH/Rh6QNX/T9uXoseD36d2vt10ok4sCrj4IqXpih71 QL0QSccdwC9zYkQmUd7G7QHgc+Z8y/8ozd0iooI7///6ZGKiJO8mwmZJN8+Wn+rUUDtv AOMvtXYEcNpGdyZSs2f44Ww+a0y1IqwwUie4ylb6r4f3HEkNpN+coSyN1/VZXF1yzN5K +DyQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:mime-version :content-transfer-encoding; bh=Ikyf+TpBSFgGm7Vdpj1oS/xRxlgH+ALj4QoDRbTjVfY=; b=hLd9mJToZFZ04apWLhkY7d5H2Fps1HAqoVlIzAe+x2GFuEs0HpKneWhSzexbzfwcCA IDATb9NWH9EJ8vawIaQPG78eXVWDMvIp6HrVrWV5T6/iN8qKXJIg29XfvLDiZHnVGqV3 xABOBv8Cz7V28oV191rvEScp34w3pH8X+NBLT4lnMeFbjbj88ZqjBjj3bj3+WADFT2Q4 5bCPHbRxaCPIKpzvsk7+ZvMwe5OJxes48Eti4l57H1q8AsSAscIrCgflaRhlC5uy26vl 3qcNofM4IJIQK/0W0i4uG95+f7dHg4u4LXIQ/NWsJsJ02qtShicyzNqZsWNeLcSIGU7T Yj8w== X-Gm-Message-State: APjAAAUIvymGmSBPlIBxPfBFICT3hiHNH68tcZZ/U2Tc5NJg/nqSbZ/2 UfKoRkRMHv//AhCx3UHoo9E= X-Google-Smtp-Source: APXvYqw2IXyYCTQpE7gt5NEa4NIw2wqBSwcHjNB6D3vWezTYVZRM25lS9VmGLfADQ9M2CrOIKVNMYA== X-Received: by 2002:a17:902:302:: with SMTP id 2mr13235091pld.149.1567131910448; Thu, 29 Aug 2019 19:25:10 -0700 (PDT) Received: from gli-arch.genesyslogic.com.tw (60-251-58-169.HINET-IP.hinet.net. [60.251.58.169]) by smtp.gmail.com with ESMTPSA id 4sm4609265pfn.118.2019.08.29.19.25.08 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 29 Aug 2019 19:25:09 -0700 (PDT) From: Ben Chuang To: adrian.hunter@intel.com, ulf.hansson@linaro.org Cc: linux-mmc@vger.kernel.org, linux-kernel@vger.kernel.org, johnsonm@danlj.org, ben.chuang@genesyslogic.com.tw, Ben Chuang Subject: [PATCH V7 4/5] mmc: sdhci: Export sdhci_abort_tuning function symbol Date: Fri, 30 Aug 2019 10:25:05 +0800 Message-Id: <20190830022505.8499-1-benchuanggli@gmail.com> X-Mailer: git-send-email 2.22.1 MIME-Version: 1.0 Sender: linux-mmc-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-mmc@vger.kernel.org From: Ben Chuang Export sdhci_abort_tuning() function symbols which are used by other SD Host controller driver modules. Signed-off-by: Ben Chuang Co-developed-by: Michael K Johnson Signed-off-by: Michael K Johnson Acked-by: Adrian Hunter --- drivers/mmc/host/sdhci.c | 3 ++- drivers/mmc/host/sdhci.h | 1 + 2 files changed, 3 insertions(+), 1 deletion(-) diff --git a/drivers/mmc/host/sdhci.c b/drivers/mmc/host/sdhci.c index 9106ebc7a422..0f2f110534db 100644 --- a/drivers/mmc/host/sdhci.c +++ b/drivers/mmc/host/sdhci.c @@ -2328,7 +2328,7 @@ void sdhci_reset_tuning(struct sdhci_host *host) } EXPORT_SYMBOL_GPL(sdhci_reset_tuning); -static void sdhci_abort_tuning(struct sdhci_host *host, u32 opcode) +void sdhci_abort_tuning(struct sdhci_host *host, u32 opcode) { sdhci_reset_tuning(host); @@ -2339,6 +2339,7 @@ static void sdhci_abort_tuning(struct sdhci_host *host, u32 opcode) mmc_abort_tuning(host->mmc, opcode); } +EXPORT_SYMBOL_GPL(sdhci_abort_tuning); /* * We use sdhci_send_tuning() because mmc_send_tuning() is not a good fit. SDHCI diff --git a/drivers/mmc/host/sdhci.h b/drivers/mmc/host/sdhci.h index 72601a4d2e95..437bab3af195 100644 --- a/drivers/mmc/host/sdhci.h +++ b/drivers/mmc/host/sdhci.h @@ -797,5 +797,6 @@ void sdhci_start_tuning(struct sdhci_host *host); void sdhci_end_tuning(struct sdhci_host *host); void sdhci_reset_tuning(struct sdhci_host *host); void sdhci_send_tuning(struct sdhci_host *host, u32 opcode); +void sdhci_abort_tuning(struct sdhci_host *host, u32 opcode); #endif /* __SDHCI_HW_H */ From patchwork Fri Aug 30 02:25:42 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Ben Chuang X-Patchwork-Id: 11122819 Return-Path: Received: from mail.kernel.org (pdx-korg-mail-1.web.codeaurora.org [172.30.200.123]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id 6F52214E5 for ; Fri, 30 Aug 2019 02:25:45 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.kernel.org (Postfix) with ESMTP id 371AB21874 for ; Fri, 30 Aug 2019 02:25:45 +0000 (UTC) Authentication-Results: mail.kernel.org; dkim=pass (2048-bit key) header.d=gmail.com header.i=@gmail.com header.b="GLPGcoxH" Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1727563AbfH3CZo (ORCPT ); Thu, 29 Aug 2019 22:25:44 -0400 Received: from mail-pg1-f196.google.com ([209.85.215.196]:38453 "EHLO mail-pg1-f196.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1727392AbfH3CZo (ORCPT ); Thu, 29 Aug 2019 22:25:44 -0400 Received: by mail-pg1-f196.google.com with SMTP id e11so2677235pga.5; Thu, 29 Aug 2019 19:25:44 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=from:to:cc:subject:date:message-id:mime-version :content-transfer-encoding; bh=G1DP6sVSTjUmv+v5aZNI0L/eUO/uKGvBLSqa/GLq1GE=; b=GLPGcoxHIcr+clm9fvV4dRSZbl59T+Gg45IoZa5QoEhqUSS6Zw07yB+3rhMJrS8fJs fHB975wiAahP6Ib4m2rvxR2i97fJjTQ0EpAslsdjHU6RfSa4lzY3nlc3k4nF7L4EihKk w+GHp5H/IiTBAJkudTYGW6MlUihb3ySLj6aD0qZxzQ3Od3t+g7myBilFHqei3abjLKJo JIjXFAkd/TW+AjcWLBWzktj0hGob1jcyy4upzKD+K+Z5Q/L1d+miwXKa+rGcaQSD2Y16 DR7GWNxwfedLgqqS+Xf37ElQBvkj3DNNhAX8SIRuLmtEe7zX6dTW/j2LkVXwvG3j8q+s mKMw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:mime-version :content-transfer-encoding; bh=G1DP6sVSTjUmv+v5aZNI0L/eUO/uKGvBLSqa/GLq1GE=; b=cdcZdkcHYop/vCI/EqaaBhq0XopFUBdLntvYGXrbXOv1uQj8pYtoV2xyC8OVM3p3bh rQUEH+ESV0eiEH5WW7J6amS94/QyqNhbhiHyGYaJU26gHzz9v8n6vBr8mTnJQOQICObW Xj/3BsahdBrDTUsQha00shGVCiUQs+l/Tq1AkOhPLMBTtZprrhCXZ5nIB/LOnw97R5xw yzZWZr3qk+kPo+F1bjfGLFEFjQtXmRO2ryHL0f4Am4UdFAsodHZQKSM1Yk5fcgKd5+BL s7fM97F36tfpKFc/Tc9q9u4nW5B4zF/5rHT8ENIvPLaf5U20XZK5ZJni1rRt10Hz3lOh LW2A== X-Gm-Message-State: APjAAAU8y3aYgkv3Fq0frsDD8q6ah+mu8WbBG7FS/+xkg7KBR6b3vOlB fo+S+uptljnEGwTXGJzusBc= X-Google-Smtp-Source: APXvYqynaJfQM8mrD6jZnL4YLmTtRMMF653yGlI7oSzOsWU+uyTIwh+4fOc//wibKjtx3Fvgy8IZBQ== X-Received: by 2002:a17:90a:358a:: with SMTP id r10mr13492072pjb.30.1567131943549; Thu, 29 Aug 2019 19:25:43 -0700 (PDT) Received: from gli-arch.genesyslogic.com.tw ([122.146.30.3]) by smtp.gmail.com with ESMTPSA id b18sm4915719pfi.160.2019.08.29.19.25.41 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 29 Aug 2019 19:25:42 -0700 (PDT) From: Ben Chuang To: adrian.hunter@intel.com, ulf.hansson@linaro.org Cc: linux-mmc@vger.kernel.org, linux-kernel@vger.kernel.org, johnsonm@danlj.org, ben.chuang@genesyslogic.com.tw, Ben Chuang Subject: [PATCH V7 5/5] mmc: host: sdhci-pci: Add Genesys Logic GL975x support Date: Fri, 30 Aug 2019 10:25:42 +0800 Message-Id: <20190830022542.8571-1-benchuanggli@gmail.com> X-Mailer: git-send-email 2.22.1 MIME-Version: 1.0 Sender: linux-mmc-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-mmc@vger.kernel.org From: Ben Chuang Add support for the GL9750 and GL9755 chipsets. Enable v4 mode and wait 5ms after set 1.8V signal enable for GL9750/ GL9755. Fix the value of SDHCI_MAX_CURRENT register and use the vendor tuning flow for GL9750. Signed-off-by: Ben Chuang Co-developed-by: Michael K Johnson Signed-off-by: Michael K Johnson --- drivers/mmc/host/Kconfig | 1 + drivers/mmc/host/Makefile | 2 +- drivers/mmc/host/sdhci-pci-core.c | 2 + drivers/mmc/host/sdhci-pci-gli.c | 350 ++++++++++++++++++++++++++++++ drivers/mmc/host/sdhci-pci.h | 5 + 5 files changed, 359 insertions(+), 1 deletion(-) create mode 100644 drivers/mmc/host/sdhci-pci-gli.c diff --git a/drivers/mmc/host/Kconfig b/drivers/mmc/host/Kconfig index 931770f17087..9fbfff514d6c 100644 --- a/drivers/mmc/host/Kconfig +++ b/drivers/mmc/host/Kconfig @@ -94,6 +94,7 @@ config MMC_SDHCI_PCI depends on MMC_SDHCI && PCI select MMC_CQHCI select IOSF_MBI if X86 + select MMC_SDHCI_IO_ACCESSORS help This selects the PCI Secure Digital Host Controller Interface. Most controllers found today are PCI devices. diff --git a/drivers/mmc/host/Makefile b/drivers/mmc/host/Makefile index 73578718f119..661445415090 100644 --- a/drivers/mmc/host/Makefile +++ b/drivers/mmc/host/Makefile @@ -13,7 +13,7 @@ obj-$(CONFIG_MMC_MXS) += mxs-mmc.o obj-$(CONFIG_MMC_SDHCI) += sdhci.o obj-$(CONFIG_MMC_SDHCI_PCI) += sdhci-pci.o sdhci-pci-y += sdhci-pci-core.o sdhci-pci-o2micro.o sdhci-pci-arasan.o \ - sdhci-pci-dwc-mshc.o + sdhci-pci-dwc-mshc.o sdhci-pci-gli.o obj-$(subst m,y,$(CONFIG_MMC_SDHCI_PCI)) += sdhci-pci-data.o obj-$(CONFIG_MMC_SDHCI_ACPI) += sdhci-acpi.o obj-$(CONFIG_MMC_SDHCI_PXAV3) += sdhci-pxav3.o diff --git a/drivers/mmc/host/sdhci-pci-core.c b/drivers/mmc/host/sdhci-pci-core.c index 4154ee11b47d..e5835fbf73bc 100644 --- a/drivers/mmc/host/sdhci-pci-core.c +++ b/drivers/mmc/host/sdhci-pci-core.c @@ -1682,6 +1682,8 @@ static const struct pci_device_id pci_ids[] = { SDHCI_PCI_DEVICE(O2, SEABIRD1, o2), SDHCI_PCI_DEVICE(ARASAN, PHY_EMMC, arasan), SDHCI_PCI_DEVICE(SYNOPSYS, DWC_MSHC, snps), + SDHCI_PCI_DEVICE(GLI, 9750, gl9750), + SDHCI_PCI_DEVICE(GLI, 9755, gl9755), SDHCI_PCI_DEVICE_CLASS(AMD, SYSTEM_SDHCI, PCI_CLASS_MASK, amd), /* Generic SD host controller */ {PCI_DEVICE_CLASS(SYSTEM_SDHCI, PCI_CLASS_MASK)}, diff --git a/drivers/mmc/host/sdhci-pci-gli.c b/drivers/mmc/host/sdhci-pci-gli.c new file mode 100644 index 000000000000..ed87a32b4470 --- /dev/null +++ b/drivers/mmc/host/sdhci-pci-gli.c @@ -0,0 +1,350 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright (C) 2019 Genesys Logic, Inc. + * + * Authors: Ben Chuang + * + * Version: v0.9.0 (2019-08-08) + */ + +#include +#include +#include +#include +#include +#include "sdhci.h" +#include "sdhci-pci.h" + +/* Genesys Logic extra registers */ +#define SDHCI_GLI_9750_WT 0x800 +#define SDHCI_GLI_9750_WT_EN BIT(0) +#define GLI_9750_WT_EN_ON 0x1 +#define GLI_9750_WT_EN_OFF 0x0 + +#define SDHCI_GLI_9750_DRIVING 0x860 +#define SDHCI_GLI_9750_DRIVING_1 GENMASK(11, 0) +#define SDHCI_GLI_9750_DRIVING_2 GENMASK(27, 26) +#define GLI_9750_DRIVING_1_VALUE 0xFFF +#define GLI_9750_DRIVING_2_VALUE 0x3 + +#define SDHCI_GLI_9750_PLL 0x864 +#define SDHCI_GLI_9750_PLL_TX2_INV BIT(23) +#define SDHCI_GLI_9750_PLL_TX2_DLY GENMASK(22, 20) +#define GLI_9750_PLL_TX2_INV_VALUE 0x1 +#define GLI_9750_PLL_TX2_DLY_VALUE 0x0 + +#define SDHCI_GLI_9750_SW_CTRL 0x874 +#define SDHCI_GLI_9750_SW_CTRL_4 GENMASK(7, 6) +#define GLI_9750_SW_CTRL_4_VALUE 0x3 + +#define SDHCI_GLI_9750_MISC 0x878 +#define SDHCI_GLI_9750_MISC_TX1_INV BIT(2) +#define SDHCI_GLI_9750_MISC_RX_INV BIT(3) +#define SDHCI_GLI_9750_MISC_TX1_DLY GENMASK(6, 4) +#define GLI_9750_MISC_TX1_INV_VALUE 0x0 +#define GLI_9750_MISC_RX_INV_ON 0x1 +#define GLI_9750_MISC_RX_INV_OFF 0x0 +#define GLI_9750_MISC_RX_INV_VALUE GLI_9750_MISC_RX_INV_OFF +#define GLI_9750_MISC_TX1_DLY_VALUE 0x5 + +#define SDHCI_GLI_9750_TUNING_CONTROL 0x540 +#define SDHCI_GLI_9750_TUNING_CONTROL_EN BIT(4) +#define GLI_9750_TUNING_CONTROL_EN_ON 0x1 +#define GLI_9750_TUNING_CONTROL_EN_OFF 0x0 +#define SDHCI_GLI_9750_TUNING_CONTROL_GLITCH_1 BIT(16) +#define SDHCI_GLI_9750_TUNING_CONTROL_GLITCH_2 GENMASK(20, 19) +#define GLI_9750_TUNING_CONTROL_GLITCH_1_VALUE 0x1 +#define GLI_9750_TUNING_CONTROL_GLITCH_2_VALUE 0x2 + +#define SDHCI_GLI_9750_TUNING_PARAMETERS 0x544 +#define SDHCI_GLI_9750_TUNING_PARAMETERS_RX_DLY GENMASK(2, 0) +#define GLI_9750_TUNING_PARAMETERS_RX_DLY_VALUE 0x1 + +#define GLI_MAX_TUNING_LOOP 40 + +/* Genesys Logic chipset */ +static inline void gl9750_wt_on(struct sdhci_host *host) +{ + u32 wt_value = 0; + u32 wt_enable = 0; + + wt_value = sdhci_readl(host, SDHCI_GLI_9750_WT); + wt_enable = FIELD_GET(SDHCI_GLI_9750_WT_EN, wt_value); + + if (wt_enable == GLI_9750_WT_EN_ON) + return; + + wt_value &= ~SDHCI_GLI_9750_WT_EN; + wt_value |= FIELD_PREP(SDHCI_GLI_9750_WT_EN, GLI_9750_WT_EN_ON); + + sdhci_writel(host, wt_value, SDHCI_GLI_9750_WT); +} + +static inline void gl9750_wt_off(struct sdhci_host *host) +{ + u32 wt_value = 0; + u32 wt_enable = 0; + + wt_value = sdhci_readl(host, SDHCI_GLI_9750_WT); + wt_enable = FIELD_GET(SDHCI_GLI_9750_WT_EN, wt_value); + + if (wt_enable == GLI_9750_WT_EN_OFF) + return; + + wt_value &= ~SDHCI_GLI_9750_WT_EN; + wt_value |= FIELD_PREP(SDHCI_GLI_9750_WT_EN, GLI_9750_WT_EN_OFF); + + sdhci_writel(host, wt_value, SDHCI_GLI_9750_WT); +} + +static void gli_set_9750(struct sdhci_host *host) +{ + u32 driving_value = 0; + u32 pll_value = 0; + u32 sw_ctrl_value = 0; + u32 misc_value = 0; + u32 parameter_value = 0; + u32 control_value = 0; + + u16 ctrl2 = 0; + + gl9750_wt_on(host); + + driving_value = sdhci_readl(host, SDHCI_GLI_9750_DRIVING); + pll_value = sdhci_readl(host, SDHCI_GLI_9750_PLL); + sw_ctrl_value = sdhci_readl(host, SDHCI_GLI_9750_SW_CTRL); + misc_value = sdhci_readl(host, SDHCI_GLI_9750_MISC); + parameter_value = sdhci_readl(host, SDHCI_GLI_9750_TUNING_PARAMETERS); + control_value = sdhci_readl(host, SDHCI_GLI_9750_TUNING_CONTROL); + + driving_value &= ~(SDHCI_GLI_9750_DRIVING_1); + driving_value &= ~(SDHCI_GLI_9750_DRIVING_2); + driving_value |= FIELD_PREP(SDHCI_GLI_9750_DRIVING_1, + GLI_9750_DRIVING_1_VALUE); + driving_value |= FIELD_PREP(SDHCI_GLI_9750_DRIVING_2, + GLI_9750_DRIVING_2_VALUE); + sdhci_writel(host, driving_value, SDHCI_GLI_9750_DRIVING); + + sw_ctrl_value &= ~SDHCI_GLI_9750_SW_CTRL_4; + sw_ctrl_value |= FIELD_PREP(SDHCI_GLI_9750_SW_CTRL_4, + GLI_9750_SW_CTRL_4_VALUE); + sdhci_writel(host, sw_ctrl_value, SDHCI_GLI_9750_SW_CTRL); + + /* reset the tuning flow after reinit and before starting tuning */ + pll_value &= ~SDHCI_GLI_9750_PLL_TX2_INV; + pll_value &= ~SDHCI_GLI_9750_PLL_TX2_DLY; + pll_value |= FIELD_PREP(SDHCI_GLI_9750_PLL_TX2_INV, + GLI_9750_PLL_TX2_INV_VALUE); + pll_value |= FIELD_PREP(SDHCI_GLI_9750_PLL_TX2_DLY, + GLI_9750_PLL_TX2_DLY_VALUE); + + misc_value &= ~SDHCI_GLI_9750_MISC_TX1_INV; + misc_value &= ~SDHCI_GLI_9750_MISC_RX_INV; + misc_value &= ~SDHCI_GLI_9750_MISC_TX1_DLY; + misc_value |= FIELD_PREP(SDHCI_GLI_9750_MISC_TX1_INV, + GLI_9750_MISC_TX1_INV_VALUE); + misc_value |= FIELD_PREP(SDHCI_GLI_9750_MISC_RX_INV, + GLI_9750_MISC_RX_INV_VALUE); + misc_value |= FIELD_PREP(SDHCI_GLI_9750_MISC_TX1_DLY, + GLI_9750_MISC_TX1_DLY_VALUE); + + parameter_value &= ~SDHCI_GLI_9750_TUNING_PARAMETERS_RX_DLY; + parameter_value |= FIELD_PREP(SDHCI_GLI_9750_TUNING_PARAMETERS_RX_DLY, + GLI_9750_TUNING_PARAMETERS_RX_DLY_VALUE); + + control_value &= ~SDHCI_GLI_9750_TUNING_CONTROL_GLITCH_1; + control_value &= ~SDHCI_GLI_9750_TUNING_CONTROL_GLITCH_2; + control_value |= FIELD_PREP(SDHCI_GLI_9750_TUNING_CONTROL_GLITCH_1, + GLI_9750_TUNING_CONTROL_GLITCH_1_VALUE); + control_value |= FIELD_PREP(SDHCI_GLI_9750_TUNING_CONTROL_GLITCH_2, + GLI_9750_TUNING_CONTROL_GLITCH_2_VALUE); + + sdhci_writel(host, pll_value, SDHCI_GLI_9750_PLL); + sdhci_writel(host, misc_value, SDHCI_GLI_9750_MISC); + + /* disable tuned clk */ + ctrl2 = sdhci_readw(host, SDHCI_HOST_CONTROL2); + ctrl2 &= ~SDHCI_CTRL_TUNED_CLK; + sdhci_writew(host, ctrl2, SDHCI_HOST_CONTROL2); + + /* enable tuning parameters control */ + control_value &= ~SDHCI_GLI_9750_TUNING_CONTROL_EN; + control_value |= FIELD_PREP(SDHCI_GLI_9750_TUNING_CONTROL_EN, + GLI_9750_TUNING_CONTROL_EN_ON); + sdhci_writel(host, control_value, SDHCI_GLI_9750_TUNING_CONTROL); + + /* write tuning parameters */ + sdhci_writel(host, parameter_value, SDHCI_GLI_9750_TUNING_PARAMETERS); + + /* disable tuning parameters control */ + control_value &= ~SDHCI_GLI_9750_TUNING_CONTROL_EN; + control_value |= FIELD_PREP(SDHCI_GLI_9750_TUNING_CONTROL_EN, + GLI_9750_TUNING_CONTROL_EN_OFF); + sdhci_writel(host, control_value, SDHCI_GLI_9750_TUNING_CONTROL); + + /* clear tuned clk */ + ctrl2 = sdhci_readw(host, SDHCI_HOST_CONTROL2); + ctrl2 &= ~SDHCI_CTRL_TUNED_CLK; + sdhci_writew(host, ctrl2, SDHCI_HOST_CONTROL2); + + udelay(1); + + gl9750_wt_off(host); +} + +static void gli_set_9750_rx_inv(struct sdhci_host *host, bool b) +{ + u32 misc_value = sdhci_readl(host, SDHCI_GLI_9750_MISC); + + gl9750_wt_on(host); + + misc_value = sdhci_readl(host, SDHCI_GLI_9750_MISC); + if (b) { + misc_value &= ~SDHCI_GLI_9750_MISC_RX_INV; + misc_value |= FIELD_PREP(SDHCI_GLI_9750_MISC_RX_INV, + GLI_9750_MISC_RX_INV_ON); + sdhci_writel(host, misc_value, SDHCI_GLI_9750_MISC); + } else { + misc_value &= ~SDHCI_GLI_9750_MISC_RX_INV; + misc_value |= FIELD_PREP(SDHCI_GLI_9750_MISC_RX_INV, + GLI_9750_MISC_RX_INV_OFF); + sdhci_writel(host, misc_value, SDHCI_GLI_9750_MISC); + } + + gl9750_wt_off(host); +} + +static int __sdhci_execute_tuning_9750(struct sdhci_host *host, u32 opcode) +{ + int i; + int rx_inv = 0; + + for (rx_inv = 0; rx_inv < 2; rx_inv++) { + if (rx_inv & 0x1) + gli_set_9750_rx_inv(host, true); + else + gli_set_9750_rx_inv(host, false); + + sdhci_start_tuning(host); + + for (i = 0; i < GLI_MAX_TUNING_LOOP; i++) { + u16 ctrl; + + sdhci_send_tuning(host, opcode); + + if (!host->tuning_done) { + if (rx_inv == 1) { + pr_info("%s: Tuning timeout, falling back to fixed sampling clock\n", + mmc_hostname(host->mmc)); + sdhci_abort_tuning(host, opcode); + return -ETIMEDOUT; + } + sdhci_abort_tuning(host, opcode); + break; + } + + ctrl = sdhci_readw(host, SDHCI_HOST_CONTROL2); + if (!(ctrl & SDHCI_CTRL_EXEC_TUNING)) { + if (ctrl & SDHCI_CTRL_TUNED_CLK) + return 0; /* Success! */ + break; + } + } + } + + pr_info("%s: Tuning failed, falling back to fixed sampling clock\n", + mmc_hostname(host->mmc)); + sdhci_reset_tuning(host); + return -EAGAIN; +} + +static int gl9750_execute_tuning(struct sdhci_host *host, u32 opcode) +{ + host->mmc->retune_period = 0; + if (host->tuning_mode == SDHCI_TUNING_MODE_1) + host->mmc->retune_period = host->tuning_count; + + gli_set_9750(host); + host->tuning_err = __sdhci_execute_tuning_9750(host, opcode); + sdhci_end_tuning(host); + + return 0; +} + +static int gli_probe_slot_gl9750(struct sdhci_pci_slot *slot) +{ + struct sdhci_host *host = slot->host; + + slot->host->mmc->caps2 |= MMC_CAP2_NO_SDIO; + sdhci_enable_v4_mode(host); + + return 0; +} + +static int gli_probe_slot_gl9755(struct sdhci_pci_slot *slot) +{ + struct sdhci_host *host = slot->host; + + slot->host->mmc->caps2 |= MMC_CAP2_NO_SDIO; + sdhci_enable_v4_mode(host); + + return 0; +} + +static void sdhci_gli_voltage_switch(struct sdhci_host *host) +{ + usleep_range(5000, 5500); +} + +static void sdhci_gl9750_reset(struct sdhci_host *host, u8 mask) +{ + sdhci_reset(host, mask); + gli_set_9750(host); +} + +static u32 sdhci_gl9750_readl(struct sdhci_host *host, int reg) +{ + u32 value; + + value = readl(host->ioaddr + reg); + if (unlikely(reg == SDHCI_MAX_CURRENT)) { + if (!(value & 0xff)) + value |= 0xc8; + } + return value; +} + +static const struct sdhci_ops sdhci_gl9755_ops = { + .set_clock = sdhci_set_clock, + .enable_dma = sdhci_pci_enable_dma, + .set_bus_width = sdhci_set_bus_width, + .reset = sdhci_reset, + .set_uhs_signaling = sdhci_set_uhs_signaling, + .voltage_switch = sdhci_gli_voltage_switch, +}; + +const struct sdhci_pci_fixes sdhci_gl9755 = { + .quirks = SDHCI_QUIRK_NO_ENDATTR_IN_NOPDESC, + .quirks2 = SDHCI_QUIRK2_BROKEN_DDR50, + .probe_slot = gli_probe_slot_gl9755, + .ops = &sdhci_gl9755_ops, +}; + +static const struct sdhci_ops sdhci_gl9750_ops = { + .read_l = sdhci_gl9750_readl, + .set_clock = sdhci_set_clock, + .enable_dma = sdhci_pci_enable_dma, + .set_bus_width = sdhci_set_bus_width, + .reset = sdhci_gl9750_reset, + .set_uhs_signaling = sdhci_set_uhs_signaling, + .voltage_switch = sdhci_gli_voltage_switch, + .platform_execute_tuning = gl9750_execute_tuning, +}; + +const struct sdhci_pci_fixes sdhci_gl9750 = { + .quirks = SDHCI_QUIRK_NO_ENDATTR_IN_NOPDESC, + .quirks2 = SDHCI_QUIRK2_BROKEN_DDR50, + .probe_slot = gli_probe_slot_gl9750, + .ops = &sdhci_gl9750_ops, +}; + diff --git a/drivers/mmc/host/sdhci-pci.h b/drivers/mmc/host/sdhci-pci.h index e5dc6e44c7a4..738ba5afcc20 100644 --- a/drivers/mmc/host/sdhci-pci.h +++ b/drivers/mmc/host/sdhci-pci.h @@ -65,6 +65,9 @@ #define PCI_DEVICE_ID_SYNOPSYS_DWC_MSHC 0xc202 +#define PCI_DEVICE_ID_GLI_9755 0x9755 +#define PCI_DEVICE_ID_GLI_9750 0x9750 + /* * PCI device class and mask */ @@ -185,5 +188,7 @@ int sdhci_pci_enable_dma(struct sdhci_host *host); extern const struct sdhci_pci_fixes sdhci_arasan; extern const struct sdhci_pci_fixes sdhci_snps; extern const struct sdhci_pci_fixes sdhci_o2; +extern const struct sdhci_pci_fixes sdhci_gl9750; +extern const struct sdhci_pci_fixes sdhci_gl9755; #endif /* __SDHCI_PCI_H */