From patchwork Fri Aug 30 04:32:20 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Jiaxun Yang X-Patchwork-Id: 11122913 Return-Path: Received: from mail.kernel.org (pdx-korg-mail-1.web.codeaurora.org [172.30.200.123]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id 87BFC112C for ; Fri, 30 Aug 2019 04:33:01 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.kernel.org (Postfix) with ESMTP id 65BBA21874 for ; Fri, 30 Aug 2019 04:33:01 +0000 (UTC) Authentication-Results: mail.kernel.org; dkim=pass (1024-bit key) header.d=flygoat.com header.i=@flygoat.com header.b="HfERE2Im" Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1726144AbfH3EdB (ORCPT ); Fri, 30 Aug 2019 00:33:01 -0400 Received: from forward101p.mail.yandex.net ([77.88.28.101]:59209 "EHLO forward101p.mail.yandex.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1725819AbfH3EdA (ORCPT ); Fri, 30 Aug 2019 00:33:00 -0400 Received: from mxback11g.mail.yandex.net (mxback11g.mail.yandex.net [IPv6:2a02:6b8:0:1472:2741:0:8b7:90]) by forward101p.mail.yandex.net (Yandex) with ESMTP id 7FD383280711; Fri, 30 Aug 2019 07:32:56 +0300 (MSK) Received: from smtp1p.mail.yandex.net (smtp1p.mail.yandex.net [2a02:6b8:0:1472:2741:0:8b6:6]) by mxback11g.mail.yandex.net (nwsmtp/Yandex) with ESMTP id ed7UcnEzyq-WuC8gcCF; Fri, 30 Aug 2019 07:32:56 +0300 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=flygoat.com; s=mail; t=1567139576; bh=VD9k6EC93VnKj/3YVMc7QTVJI+Lj0puUJgN+sd5hBPM=; h=Subject:To:From:Cc:Date:Message-Id; b=HfERE2Im2NgUtA1292WFPq/OzdAsL6ntfOSFHEhGOJhK8IJdAISVOFgTlDaqVnRE3 l/UQMoKGBY3Xn+rCEOFZ0vwYO68uYzqZj6bJXhOYHzY9kYwZeRNDpBgAsszjsmm7my 6Y6d9M+VXLIPD00GIlE3I+pepqAZt1+Od2pCs2as= Authentication-Results: mxback11g.mail.yandex.net; dkim=pass header.i=@flygoat.com Received: by smtp1p.mail.yandex.net (nwsmtp/Yandex) with ESMTPSA id vFuwVxmDwr-WlDGm3mn; Fri, 30 Aug 2019 07:32:54 +0300 (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits)) (Client certificate not present) From: Jiaxun Yang To: linux-mips@vger.kernel.org Cc: chenhc@lemote.com, paul.burton@mips.com, tglx@linutronix.de, jason@lakedaemon.net, maz@kernel.org, linux-kernel@vger.kernel.org, robh+dt@kernel.org, mark.rutland@arm.co, devicetree@vger.kernel.org, Jiaxun Yang Subject: [PATCH v1 06/18] dt-bindings: interrupt-controller: Add Loongson-3 IOINTC Date: Fri, 30 Aug 2019 12:32:20 +0800 Message-Id: <20190830043232.20191-1-jiaxun.yang@flygoat.com> X-Mailer: git-send-email 2.22.0 MIME-Version: 1.0 Sender: linux-mips-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-mips@vger.kernel.org Document Loongson-3 I/O Interrupt controller. Signed-off-by: Jiaxun Yang --- .../loongson,ls3-iointc.yaml | 75 +++++++++++++++++++ 1 file changed, 75 insertions(+) create mode 100644 Documentation/devicetree/bindings/interrupt-controller/loongson,ls3-iointc.yaml diff --git a/Documentation/devicetree/bindings/interrupt-controller/loongson,ls3-iointc.yaml b/Documentation/devicetree/bindings/interrupt-controller/loongson,ls3-iointc.yaml new file mode 100644 index 000000000000..9aee10abd5cd --- /dev/null +++ b/Documentation/devicetree/bindings/interrupt-controller/loongson,ls3-iointc.yaml @@ -0,0 +1,75 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: "http://devicetree.org/schemas/interrupt-controller/loongson,ls3-iointc.yaml#" +$schema: "http://devicetree.org/meta-schemas/core.yaml#" + +title: Loongson-3 I/O Interrupt Controller + +maintainers: + - Jiaxun Yang + +description: | + This interrupt controller is found in the Loongson-3 family of chips as the primary + package interrupt source which can route interrupt to interrupt line of cores. + +properties: + compatible: + const: loongson,ls3-iointc + + reg: + maxItems: 1 + + + interrupt-controller: true + + "#interrupt-cells": + description: | + Specifies the number of cells needed to encode an interrupt source. + Must be 2 or 4. + If the system requires describing interrupt line & core mapping, than + it must be 4. + + The 1st cell is the hardware interrupt number. + + The 2nd cell is the flags, encoded as follows: + bits[3:0] trigger type and level flags. + 1 = low-to-high edge triggered + 2 = high-to-low edge triggered + 4 = active high level-sensitive + 8 = active low level-sensitive. + + The 3rd is the parent interrupt line that interrupt would map to. + As the CPU preserved 4 interrupt lines for I/O, in theory any of the iointc + interrupt can be chained to any interrupt lines on a core. But currently + we can only map all the interrupt to a single parent, so this cell must be + set uniformly for all the child interrupts corresponding to the parent + interrupt. + + The 4th is the parent core that interrupt would map to. The interrupt + contoller can map any of the interrupt to the specified core on a package. + This cell determined the core. It must be the bootcore. + + If the 3rd, 4th cell is not set, it will default to the 0# interrupt line + and bootcore. + + enum: [ 2, 4 ] + +required: + - compatible + - reg + - interrupts + - interrupt-controller + - '#interrupt-cells' + + +examples: + - | + iointc: interrupt-controller@3ff01400 { + compatible = "loongson,ls3-io-intc"; + reg = <0x3ff01400 0x60>; + interrupts = <2>; + interrupt-controller; + #interrupt-cells = <4>; + }; +... From patchwork Fri Aug 30 04:32:21 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Jiaxun Yang X-Patchwork-Id: 11122915 Return-Path: Received: from mail.kernel.org (pdx-korg-mail-1.web.codeaurora.org [172.30.200.123]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id 96A8A14DE for ; Fri, 30 Aug 2019 04:33:11 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.kernel.org (Postfix) with ESMTP id 745C0215EA for ; Fri, 30 Aug 2019 04:33:11 +0000 (UTC) Authentication-Results: mail.kernel.org; dkim=pass (1024-bit key) header.d=flygoat.com header.i=@flygoat.com header.b="EmqcIx6H" Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1726236AbfH3EdL (ORCPT ); Fri, 30 Aug 2019 00:33:11 -0400 Received: from forward106p.mail.yandex.net ([77.88.28.109]:58701 "EHLO forward106p.mail.yandex.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1726090AbfH3EdL (ORCPT ); Fri, 30 Aug 2019 00:33:11 -0400 Received: from mxback12j.mail.yandex.net (mxback12j.mail.yandex.net [IPv6:2a02:6b8:0:1619::87]) by forward106p.mail.yandex.net (Yandex) with ESMTP id 1F6441C80A75; Fri, 30 Aug 2019 07:33:07 +0300 (MSK) Received: from smtp1p.mail.yandex.net (smtp1p.mail.yandex.net [2a02:6b8:0:1472:2741:0:8b6:6]) by mxback12j.mail.yandex.net (nwsmtp/Yandex) with ESMTP id EF5346hYcL-X6oeTDPq; Fri, 30 Aug 2019 07:33:07 +0300 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=flygoat.com; s=mail; t=1567139587; bh=jLzJicLkbXfHmx3eYxmpwhMZURKGvtDVrPk8smkP6xQ=; h=In-Reply-To:Subject:To:From:Cc:References:Date:Message-Id; b=EmqcIx6H6da7C5wNP5sNvzZQsBO2Dx86kxx/35sUE9/eVfcpZKztaSVCtK+1o4Ect i8fEITmt1TzjMCW7RXav5ZeDAJPEy1LZ3BmdDWu8i44Y/My1nbj5edoiuEzgxI10up 6TmmtvkrPLybcuWUAU+rd8YTU1gXWlf7Qyd8YPrs= Authentication-Results: mxback12j.mail.yandex.net; dkim=pass header.i=@flygoat.com Received: by smtp1p.mail.yandex.net (nwsmtp/Yandex) with ESMTPSA id vFuwVxmDwr-WvDGJwA3; Fri, 30 Aug 2019 07:33:03 +0300 (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits)) (Client certificate not present) From: Jiaxun Yang To: linux-mips@vger.kernel.org Cc: chenhc@lemote.com, paul.burton@mips.com, tglx@linutronix.de, jason@lakedaemon.net, maz@kernel.org, linux-kernel@vger.kernel.org, robh+dt@kernel.org, mark.rutland@arm.co, devicetree@vger.kernel.org, Jiaxun Yang Subject: [PATCH v1 07/18] irqchip: Add driver for Loongson-3 HyperTransport interrupt controller Date: Fri, 30 Aug 2019 12:32:21 +0800 Message-Id: <20190830043232.20191-2-jiaxun.yang@flygoat.com> X-Mailer: git-send-email 2.22.0 In-Reply-To: <20190830043232.20191-1-jiaxun.yang@flygoat.com> References: <20190830043232.20191-1-jiaxun.yang@flygoat.com> MIME-Version: 1.0 Sender: linux-mips-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-mips@vger.kernel.org This controller appeared on Loongson-3 family of chips to receive interrupts from PCH chip. Signed-off-by: Jiaxun Yang --- drivers/irqchip/Kconfig | 8 ++ drivers/irqchip/Makefile | 1 + drivers/irqchip/irq-ls3-htintc.c | 147 +++++++++++++++++++++++++++++++ 3 files changed, 156 insertions(+) create mode 100644 drivers/irqchip/irq-ls3-htintc.c diff --git a/drivers/irqchip/Kconfig b/drivers/irqchip/Kconfig index 8d9eac5fd4a7..b3ce0f3e43ae 100644 --- a/drivers/irqchip/Kconfig +++ b/drivers/irqchip/Kconfig @@ -480,6 +480,14 @@ config LS3_IOINTC help Support for the Loongson-3 I/O Interrupt Controller. +config LS3_HTINTC + bool "Loongson3 HyperTransport Interrupt Controller" + depends on MACH_LOONGSON64 + default y + select IRQ_DOMAIN + select GENERIC_IRQ_CHIP + help + Support for the Loongson-3 HyperTransport Interrupt Controller. endmenu config SIFIVE_PLIC diff --git a/drivers/irqchip/Makefile b/drivers/irqchip/Makefile index 49ecb8d38138..0fda94c319e9 100644 --- a/drivers/irqchip/Makefile +++ b/drivers/irqchip/Makefile @@ -103,3 +103,4 @@ obj-$(CONFIG_LS1X_IRQ) += irq-ls1x.o obj-$(CONFIG_TI_SCI_INTR_IRQCHIP) += irq-ti-sci-intr.o obj-$(CONFIG_TI_SCI_INTA_IRQCHIP) += irq-ti-sci-inta.o obj-$(CONFIG_LS3_IOINTC) += irq-ls3-iointc.o +obj-$(CONFIG_LS3_HTINTC) += irq-ls3-htintc.o diff --git a/drivers/irqchip/irq-ls3-htintc.c b/drivers/irqchip/irq-ls3-htintc.c new file mode 100644 index 000000000000..d5013606faa8 --- /dev/null +++ b/drivers/irqchip/irq-ls3-htintc.c @@ -0,0 +1,147 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Copyright (C) 2019, Jiaxun Yang + * Loongson-3 HyperTransport IRQ support + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#define HTINTC_NUM_GC 4 +#define HTINTC_GC_SIZE 0x4 +#define HTINTC_NUM_HANDLER 4 +#define HTINTC_HANDLER_SIZE 0x8 +#define HTINTC_HANDLER_IRQ 64 + +#define HTINTC_VECTOR_OFFSET 0x0 +#define HTINTC_EN_OFFSET 0x20 + +struct htintc_handler_priv { + struct irq_domain *domain; + void __iomem *handler_base; +}; + +static void htintc_chained_handle_irq(struct irq_desc *desc) +{ + struct htintc_handler_priv *priv = irq_desc_get_handler_data(desc); + struct irq_chip *chip = irq_desc_get_chip(desc); + int i; + bool handled = false; + + chained_irq_enter(chip, desc); + + for (i = 0; i < HTINTC_NUM_GC; i++) { + uint32_t irqs = readl(priv->handler_base + HTINTC_GC_SIZE * i); + + while (irqs) { + int bit = __ffs(irqs); + + generic_handle_irq(irq_find_mapping(priv->domain, bit + 32 * i)); + irqs &= ~BIT(bit); + handled = true; + } + } + + if (!handled) + spurious_interrupt(); + + chained_irq_exit(chip, desc); +} + +int __init ls3_htintc_of_init(struct device_node *node, + struct device_node *parent) +{ + struct irq_chip_generic *gc; + struct irq_chip_type *ct; + struct htintc_handler_priv *priv; + struct irq_domain *domain; + void __iomem *base; + int parent_irq[HTINTC_NUM_HANDLER], err = 0; + int i; + + priv = kzalloc(sizeof(*priv), GFP_KERNEL); + if (!priv) + return -ENOMEM; + + base = of_iomap(node, 0); + if (!base) { + err = -ENODEV; + goto out_free_priv; + } + + for (i = 0; i < HTINTC_NUM_HANDLER; i++) { + parent_irq[i] = irq_of_parse_and_map(node, i); + if (!parent_irq[i]) { + pr_err("ls3-htintc: unable to get parent irq %d\n", i); + err = -ENODEV; + goto out_iounmap; + } + } + /* Set up an IRQ domain */ + domain = irq_domain_add_linear(node, 32 * HTINTC_NUM_GC, + &irq_generic_chip_ops, NULL); + if (!domain) { + pr_err("ls3-htintc: cannot add IRQ domain\n"); + err = -ENOMEM; + goto out_iounmap; + } + + for (i = 0; i < HTINTC_NUM_HANDLER; i++) { + /* Mask all interrupts */ + writeq(0x0, base + HTINTC_EN_OFFSET + HTINTC_HANDLER_SIZE * i); + } + + err = irq_alloc_domain_generic_chips(domain, 32, 1, + node->full_name, + handle_edge_irq, + IRQ_NOPROBE, 0, + IRQ_GC_INIT_MASK_CACHE); + if (err) { + pr_err("ls3-htintc: unable to register IRQ domain\n"); + err = -ENOMEM; + goto out_free_domain; + } + + for (i = 0; i < HTINTC_NUM_GC; i++) { + gc = irq_get_domain_generic_chip(domain, i * 32); + gc->reg_base = base + HTINTC_GC_SIZE * i; + gc->domain = domain; + + ct = gc->chip_types; + ct->regs.mask = HTINTC_EN_OFFSET; + ct->regs.ack = HTINTC_VECTOR_OFFSET; + ct->chip.irq_unmask = irq_gc_mask_set_bit; + ct->chip.irq_mask = irq_gc_mask_clr_bit; + ct->chip.irq_ack = irq_gc_ack_set_bit; + } + + priv->domain = domain; + priv->handler_base = base + HTINTC_VECTOR_OFFSET; + + for (i = 0; i < HTINTC_NUM_HANDLER; i++) { + irq_set_chained_handler_and_data(parent_irq[i], + htintc_chained_handle_irq, + priv); + } + + return 0; + +out_free_domain: + irq_domain_remove(domain); +out_iounmap: + iounmap(base); +out_free_priv: + kfree(priv); + + return err; +} + +IRQCHIP_DECLARE(ls3_htintc, "loongson,ls3-htintc", ls3_htintc_of_init); From patchwork Fri Aug 30 04:32:22 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Jiaxun Yang X-Patchwork-Id: 11122919 Return-Path: Received: from mail.kernel.org (pdx-korg-mail-1.web.codeaurora.org [172.30.200.123]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id CCCE0112C for ; Fri, 30 Aug 2019 04:33:27 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.kernel.org (Postfix) with ESMTP id AA5EF22CE9 for ; Fri, 30 Aug 2019 04:33:27 +0000 (UTC) Authentication-Results: mail.kernel.org; dkim=pass (1024-bit key) header.d=flygoat.com header.i=@flygoat.com header.b="Dhr8UJ4J" Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1727434AbfH3EdU (ORCPT ); Fri, 30 Aug 2019 00:33:20 -0400 Received: from forward102o.mail.yandex.net ([37.140.190.182]:42225 "EHLO forward102o.mail.yandex.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1726090AbfH3EdU (ORCPT ); Fri, 30 Aug 2019 00:33:20 -0400 Received: from mxback10g.mail.yandex.net (mxback10g.mail.yandex.net [IPv6:2a02:6b8:0:1472:2741:0:8b7:171]) by forward102o.mail.yandex.net (Yandex) with ESMTP id EB30F66810AC; Fri, 30 Aug 2019 07:33:16 +0300 (MSK) Received: from smtp1p.mail.yandex.net (smtp1p.mail.yandex.net [2a02:6b8:0:1472:2741:0:8b6:6]) by mxback10g.mail.yandex.net (nwsmtp/Yandex) with ESMTP id TFIhJTMHWz-XGRmmxTZ; Fri, 30 Aug 2019 07:33:16 +0300 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=flygoat.com; s=mail; t=1567139596; bh=NZ7snY+0LjG9EqUoVehADJL5MGmOGv9n12pbUOd604M=; h=In-Reply-To:Subject:To:From:Cc:References:Date:Message-Id; b=Dhr8UJ4JT3XH5PxeooZ0JazptkOpIFy8fMkUo/IPEY0g6tXloCfjOn69NXLJIiLXr gfuYh+PeMNE7t/YK1+A46AsMb5g6SYnaibxzvUGh1MZxk0f4/G2GbKCSYqjnqDKnEW 7APKmkD6YZit7NkUiNwntfxy+NvqqwXuBYf/CupY= Authentication-Results: mxback10g.mail.yandex.net; dkim=pass header.i=@flygoat.com Received: by smtp1p.mail.yandex.net (nwsmtp/Yandex) with ESMTPSA id vFuwVxmDwr-X7DGwFMC; Fri, 30 Aug 2019 07:33:14 +0300 (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits)) (Client certificate not present) From: Jiaxun Yang To: linux-mips@vger.kernel.org Cc: chenhc@lemote.com, paul.burton@mips.com, tglx@linutronix.de, jason@lakedaemon.net, maz@kernel.org, linux-kernel@vger.kernel.org, robh+dt@kernel.org, mark.rutland@arm.co, devicetree@vger.kernel.org, Jiaxun Yang Subject: [PATCH v1 08/18] dt-bindings: interrupt-controller: Add Loongson-3 HTINTC Date: Fri, 30 Aug 2019 12:32:22 +0800 Message-Id: <20190830043232.20191-3-jiaxun.yang@flygoat.com> X-Mailer: git-send-email 2.22.0 In-Reply-To: <20190830043232.20191-1-jiaxun.yang@flygoat.com> References: <20190830043232.20191-1-jiaxun.yang@flygoat.com> MIME-Version: 1.0 Sender: linux-mips-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-mips@vger.kernel.org Document Loongson-3 HyperTransport Interrupt controller. Signed-off-by: Jiaxun Yang Reviewed-by: Rob Herring --- .../loongson,ls3-htintc.yaml | 55 +++++++++++++++++++ 1 file changed, 55 insertions(+) create mode 100644 Documentation/devicetree/bindings/interrupt-controller/loongson,ls3-htintc.yaml diff --git a/Documentation/devicetree/bindings/interrupt-controller/loongson,ls3-htintc.yaml b/Documentation/devicetree/bindings/interrupt-controller/loongson,ls3-htintc.yaml new file mode 100644 index 000000000000..51fee46ab060 --- /dev/null +++ b/Documentation/devicetree/bindings/interrupt-controller/loongson,ls3-htintc.yaml @@ -0,0 +1,55 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: "http://devicetree.org/schemas/interrupt-controller/loongson,ls3-htintc.yaml#" +$schema: "http://devicetree.org/meta-schemas/core.yaml#" + +title: Loongson-3 HyperTransport Interrupt Controller + +maintainers: + - Jiaxun Yang + +description: | + This interrupt controller is found in the Loongson-3 family of chips to transfer + interrupts from PCH connected on HyperTransport bus. + +properties: + compatible: + const: loongson,ls3-htintc + + reg: + maxItems: 1 + + interrupts: + maxItems: 4 + description: | + Four parent interrupts that recieve chained interrupt randomly. + + interrupt-controller: true + + '#interrupt-cells': + const: 1 + +required: + - compatible + - reg + - interrupts + - interrupt-controller + - '#interrupt-cells' + +examples: + - | + #include + htintc: interrupt-controller@fb000080 { + compatible = "loongson,ls3-htintc"; + reg = <0xfb000080 0x100>; + interrupt-controller; + #interrupt-cells = <1>; + + interrupt-parent = <&iointc>; + interrupts = <24 IRQ_TYPE_LEVEL_HIGH>, + <25 IRQ_TYPE_LEVEL_HIGH>, + <26 IRQ_TYPE_LEVEL_HIGH>, + <27 IRQ_TYPE_LEVEL_HIGH>; + }; +... From patchwork Fri Aug 30 04:32:23 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Jiaxun Yang X-Patchwork-Id: 11122921 Return-Path: Received: from mail.kernel.org (pdx-korg-mail-1.web.codeaurora.org [172.30.200.123]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id D8CBF14DE for ; Fri, 30 Aug 2019 04:33:29 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.kernel.org (Postfix) with ESMTP id B608522CE9 for ; Fri, 30 Aug 2019 04:33:29 +0000 (UTC) Authentication-Results: mail.kernel.org; dkim=pass (1024-bit key) header.d=flygoat.com header.i=@flygoat.com header.b="A1CaHrZ6" Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1726144AbfH3Ed3 (ORCPT ); Fri, 30 Aug 2019 00:33:29 -0400 Received: from forward105j.mail.yandex.net ([5.45.198.248]:50092 "EHLO forward105j.mail.yandex.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1725901AbfH3Ed3 (ORCPT ); Fri, 30 Aug 2019 00:33:29 -0400 Received: from mxback24g.mail.yandex.net (mxback24g.mail.yandex.net [IPv6:2a02:6b8:0:1472:2741:0:8b7:324]) by forward105j.mail.yandex.net (Yandex) with ESMTP id 2D1C7B20F00; Fri, 30 Aug 2019 07:33:26 +0300 (MSK) Received: from smtp1p.mail.yandex.net (smtp1p.mail.yandex.net [2a02:6b8:0:1472:2741:0:8b6:6]) by mxback24g.mail.yandex.net (nwsmtp/Yandex) with ESMTP id pV7fdG72ZP-XPx48VYU; Fri, 30 Aug 2019 07:33:26 +0300 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=flygoat.com; s=mail; t=1567139606; bh=GDPLbh2Za9If16kngBr0Vy91wenOeOyR+BDWVi+j/l8=; h=In-Reply-To:Subject:To:From:Cc:References:Date:Message-Id; b=A1CaHrZ6HcOfJhzZS+4BFCM2kqsP7dgmZp1mFMQQvuJ5oX2+ejDQC647BIDx5NMtT Y1pRkbNevKcbp76LNHGWoYVqMvqRyJNWr2lxWYr+lWS8m2OOXt4oRKLDC+au6e3kts 4sgyjAnMhs85+qrLU26B9Q47yArkXCVIm4V6z/fk= Authentication-Results: mxback24g.mail.yandex.net; dkim=pass header.i=@flygoat.com Received: by smtp1p.mail.yandex.net (nwsmtp/Yandex) with ESMTPSA id vFuwVxmDwr-XHDGfXVO; Fri, 30 Aug 2019 07:33:23 +0300 (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits)) (Client certificate not present) From: Jiaxun Yang To: linux-mips@vger.kernel.org Cc: chenhc@lemote.com, paul.burton@mips.com, tglx@linutronix.de, jason@lakedaemon.net, maz@kernel.org, linux-kernel@vger.kernel.org, robh+dt@kernel.org, mark.rutland@arm.co, devicetree@vger.kernel.org, Jiaxun Yang Subject: [PATCH v1 09/18] irqchip: i8259: Add plat-poll support Date: Fri, 30 Aug 2019 12:32:23 +0800 Message-Id: <20190830043232.20191-4-jiaxun.yang@flygoat.com> X-Mailer: git-send-email 2.22.0 In-Reply-To: <20190830043232.20191-1-jiaxun.yang@flygoat.com> References: <20190830043232.20191-1-jiaxun.yang@flygoat.com> MIME-Version: 1.0 Sender: linux-mips-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-mips@vger.kernel.org For some platforms (e.g. Loongson-3), platfrom interrupt controller supports polling interrupt vector from i8259 automaticly and generating sepreated interrupt. Thus we add plat-poll OF property for these platforms and setup sepreated chained interrupt handler. Signed-off-by: Jiaxun Yang --- drivers/irqchip/irq-i8259.c | 47 ++++++++++++++++++++++++++++++++----- 1 file changed, 41 insertions(+), 6 deletions(-) diff --git a/drivers/irqchip/irq-i8259.c b/drivers/irqchip/irq-i8259.c index d000870d9b6b..e7a9895f3b2d 100644 --- a/drivers/irqchip/irq-i8259.c +++ b/drivers/irqchip/irq-i8259.c @@ -40,6 +40,12 @@ static void mask_and_ack_8259A(struct irq_data *d); static void init_8259A(int auto_eoi); static int (*i8259_poll)(void) = i8259_irq; +struct plat_poll_priv { + struct irq_domain *domain; + int hwirq; +}; +static struct plat_poll_priv plat_poll_priv[16]; + static struct irq_chip i8259A_chip = { .name = "XT-PIC", .irq_mask = disable_8259A_irq, @@ -346,22 +352,51 @@ static void i8259_irq_dispatch(struct irq_desc *desc) generic_handle_irq(irq); } +static void plat_poll_irq_dispatch(struct irq_desc *desc) +{ + struct plat_poll_priv *priv = irq_desc_get_handler_data(desc); + unsigned int irq; + + irq = irq_linear_revmap(priv->domain, priv->hwirq); + generic_handle_irq(irq); +} + int __init i8259_of_init(struct device_node *node, struct device_node *parent) { struct irq_domain *domain; - unsigned int parent_irq; domain = __init_i8259_irqs(node); - parent_irq = irq_of_parse_and_map(node, 0); - if (!parent_irq) { - pr_err("Failed to map i8259 parent IRQ\n"); - irq_domain_remove(domain); - return -ENODEV; + if (of_find_property(node, "plat-poll", NULL)) { + int i; + + for (i = 0; i < 16; i++) { + int parent_irq = irq_of_parse_and_map(node, i); + + if (!parent_irq) { + pr_err("Failed to map %d plat-poll i8259 parent IRQ\n", i); + irq_domain_remove(domain); + return -ENODEV; + } + plat_poll_priv[i].domain = domain; + plat_poll_priv[i].hwirq = i; + irq_set_chained_handler_and_data(parent_irq, + plat_poll_irq_dispatch, + &plat_poll_priv[i]); + } + } else { + unsigned int parent_irq; + + parent_irq = irq_of_parse_and_map(node, 0); + if (!parent_irq) { + pr_err("Failed to map i8259 parent IRQ\n"); + irq_domain_remove(domain); + return -ENODEV; } irq_set_chained_handler_and_data(parent_irq, i8259_irq_dispatch, domain); + } return 0; } IRQCHIP_DECLARE(i8259, "intel,i8259", i8259_of_init); From patchwork Fri Aug 30 04:32:24 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Jiaxun Yang X-Patchwork-Id: 11122923 Return-Path: Received: from mail.kernel.org (pdx-korg-mail-1.web.codeaurora.org [172.30.200.123]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id 284AA14DE for ; Fri, 30 Aug 2019 04:33:39 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.kernel.org (Postfix) with ESMTP id 0523B22CE9 for ; Fri, 30 Aug 2019 04:33:39 +0000 (UTC) Authentication-Results: mail.kernel.org; dkim=pass (1024-bit key) header.d=flygoat.com header.i=@flygoat.com header.b="ZApguL0D" Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1727846AbfH3Edi (ORCPT ); Fri, 30 Aug 2019 00:33:38 -0400 Received: from forward102o.mail.yandex.net ([37.140.190.182]:42400 "EHLO forward102o.mail.yandex.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1726510AbfH3Edi (ORCPT ); Fri, 30 Aug 2019 00:33:38 -0400 Received: from mxback10j.mail.yandex.net (mxback10j.mail.yandex.net [IPv6:2a02:6b8:0:1619::113]) by forward102o.mail.yandex.net (Yandex) with ESMTP id 828266681208; Fri, 30 Aug 2019 07:33:35 +0300 (MSK) Received: from smtp1p.mail.yandex.net (smtp1p.mail.yandex.net [2a02:6b8:0:1472:2741:0:8b6:6]) by mxback10j.mail.yandex.net (nwsmtp/Yandex) with ESMTP id WttFCfbAvP-XZQm3GJ6; Fri, 30 Aug 2019 07:33:35 +0300 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=flygoat.com; s=mail; t=1567139615; bh=lGWrm07yEb+iDYbXl6MNXFFYrFAuttvAedBfbL1LKfs=; h=In-Reply-To:Subject:To:From:Cc:References:Date:Message-Id; b=ZApguL0DbnmD8amq5tlJ+XxxwARSvb0QUn9AypJZSPlM1sS9VYeyUbYU1N62/KObk EJ7md1pMDy2PMqxv7YDpNU77X1ff5/KW17mNscbXH7wPRPIGd6MYthnTj8YAqsVhZL AL6mCSssaQFSDnYRDDF2u1+awCBhijInob4V9tI8= Authentication-Results: mxback10j.mail.yandex.net; dkim=pass header.i=@flygoat.com Received: by smtp1p.mail.yandex.net (nwsmtp/Yandex) with ESMTPSA id vFuwVxmDwr-XQDG0QFh; Fri, 30 Aug 2019 07:33:33 +0300 (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits)) (Client certificate not present) From: Jiaxun Yang To: linux-mips@vger.kernel.org Cc: chenhc@lemote.com, paul.burton@mips.com, tglx@linutronix.de, jason@lakedaemon.net, maz@kernel.org, linux-kernel@vger.kernel.org, robh+dt@kernel.org, mark.rutland@arm.co, devicetree@vger.kernel.org, Jiaxun Yang Subject: [PATCH v1 10/18] irqchip: mips-cpu: Convert to simple domain Date: Fri, 30 Aug 2019 12:32:24 +0800 Message-Id: <20190830043232.20191-5-jiaxun.yang@flygoat.com> X-Mailer: git-send-email 2.22.0 In-Reply-To: <20190830043232.20191-1-jiaxun.yang@flygoat.com> References: <20190830043232.20191-1-jiaxun.yang@flygoat.com> MIME-Version: 1.0 Sender: linux-mips-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-mips@vger.kernel.org The old code is using legacy domain to setup irq_domain for CPU interrupts which requires irq_desc being preallocated. However, when MIPS_CPU_IRQ_BASE >= 16, irq_desc for CPU IRQs may end up unallocated and lead to incorrect behavior. Thus we convert the legacy domain to simple domain which can allocate irq_desc during initialization. Signed-off-by: Jiaxun Yang --- drivers/irqchip/irq-mips-cpu.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/irqchip/irq-mips-cpu.c b/drivers/irqchip/irq-mips-cpu.c index 95d4fd8f7a96..c3cf7fa76424 100644 --- a/drivers/irqchip/irq-mips-cpu.c +++ b/drivers/irqchip/irq-mips-cpu.c @@ -251,7 +251,7 @@ static void __init __mips_cpu_irq_init(struct device_node *of_node) clear_c0_status(ST0_IM); clear_c0_cause(CAUSEF_IP); - irq_domain = irq_domain_add_legacy(of_node, 8, MIPS_CPU_IRQ_BASE, 0, + irq_domain = irq_domain_add_simple(of_node, 8, MIPS_CPU_IRQ_BASE, &mips_cpu_intc_irq_domain_ops, NULL); if (!irq_domain) From patchwork Fri Aug 30 04:32:25 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Jiaxun Yang X-Patchwork-Id: 11122925 Return-Path: Received: from mail.kernel.org (pdx-korg-mail-1.web.codeaurora.org [172.30.200.123]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id 10969112C for ; Fri, 30 Aug 2019 04:33:54 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.kernel.org (Postfix) with ESMTP id CE30622CE3 for ; Fri, 30 Aug 2019 04:33:53 +0000 (UTC) Authentication-Results: mail.kernel.org; dkim=pass (1024-bit key) header.d=flygoat.com header.i=@flygoat.com header.b="gp8G3GFc" Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1726480AbfH3Edx (ORCPT ); Fri, 30 Aug 2019 00:33:53 -0400 Received: from forward102j.mail.yandex.net ([5.45.198.243]:42875 "EHLO forward102j.mail.yandex.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1726236AbfH3Edx (ORCPT ); Fri, 30 Aug 2019 00:33:53 -0400 Received: from mxback22o.mail.yandex.net (mxback22o.mail.yandex.net [IPv6:2a02:6b8:0:1a2d::73]) by forward102j.mail.yandex.net (Yandex) with ESMTP id DBB2AF2054B; Fri, 30 Aug 2019 07:33:49 +0300 (MSK) Received: from smtp1p.mail.yandex.net (smtp1p.mail.yandex.net [2a02:6b8:0:1472:2741:0:8b6:6]) by mxback22o.mail.yandex.net (nwsmtp/Yandex) with ESMTP id HMExJnGd6K-Xnf0EE0t; Fri, 30 Aug 2019 07:33:49 +0300 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=flygoat.com; s=mail; t=1567139629; bh=tqrCk2lHh7uLbBYfb1q4A+xs3HDXcUI81jcco/99ZUo=; h=In-Reply-To:Subject:To:From:Cc:References:Date:Message-Id; b=gp8G3GFcjOXgRz+G76T3Ux6HECtnA8COxGJRRA53LXCh0meEz7+IqMktoqkS7+IRD gDjrQqSHpQPBj/5yvNbSsH/mTJs5lpOWgiQSaxoroZ4JZGkM9Ry2e+sBpKTnx+NLZK HLQftLkZiN5L+TcXkgExXQ79l21UKQiJxSCWgNDM= Authentication-Results: mxback22o.mail.yandex.net; dkim=pass header.i=@flygoat.com Received: by smtp1p.mail.yandex.net (nwsmtp/Yandex) with ESMTPSA id vFuwVxmDwr-XaDGW9q4; Fri, 30 Aug 2019 07:33:47 +0300 (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits)) (Client certificate not present) From: Jiaxun Yang To: linux-mips@vger.kernel.org Cc: chenhc@lemote.com, paul.burton@mips.com, tglx@linutronix.de, jason@lakedaemon.net, maz@kernel.org, linux-kernel@vger.kernel.org, robh+dt@kernel.org, mark.rutland@arm.co, devicetree@vger.kernel.org, Jiaxun Yang Subject: [PATCH v1 11/18] MIPS: Loongson64: Drop legacy IRQ code Date: Fri, 30 Aug 2019 12:32:25 +0800 Message-Id: <20190830043232.20191-6-jiaxun.yang@flygoat.com> X-Mailer: git-send-email 2.22.0 In-Reply-To: <20190830043232.20191-1-jiaxun.yang@flygoat.com> References: <20190830043232.20191-1-jiaxun.yang@flygoat.com> MIME-Version: 1.0 Sender: linux-mips-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-mips@vger.kernel.org We've made generic irqchip drivers for Loongson-3 platform, it's time to say goodbye to these legacy code. Signed-off-by: Jiaxun Yang --- arch/mips/include/asm/mach-loongson64/irq.h | 1 - arch/mips/loongson64/irq.c | 167 +------------------- arch/mips/loongson64/smp.c | 26 ++- 3 files changed, 11 insertions(+), 183 deletions(-) diff --git a/arch/mips/include/asm/mach-loongson64/irq.h b/arch/mips/include/asm/mach-loongson64/irq.h index baed43285163..e57a21fc581c 100644 --- a/arch/mips/include/asm/mach-loongson64/irq.h +++ b/arch/mips/include/asm/mach-loongson64/irq.h @@ -35,7 +35,6 @@ #define LOONGSON_INT_COREx_INTy(x, y) (1<<(x) | 1<<(y+4)) /* route to int y of core x */ extern void fixup_irqs(void); -extern void loongson3_ipi_interrupt(void); #include_next #endif /* __ASM_MACH_LOONGSON64_IRQ_H_ */ diff --git a/arch/mips/loongson64/irq.c b/arch/mips/loongson64/irq.c index 4d7b80a0ffb9..78cd824cc84e 100644 --- a/arch/mips/loongson64/irq.c +++ b/arch/mips/loongson64/irq.c @@ -3,180 +3,17 @@ #include #include #include +#include #include -#include #include #include "smp.h" -/* ICU Configuration Regs - r/w */ - -#define LOONGSON_INTEDGE LOONGSON_REG(LOONGSON_REGBASE + 0x24) -#define LOONGSON_INTSTEER LOONGSON_REG(LOONGSON_REGBASE + 0x28) -#define LOONGSON_INTPOL LOONGSON_REG(LOONGSON_REGBASE + 0x2c) - -/* ICU Enable Regs - IntEn & IntISR are r/o. */ - -#define LOONGSON_INTENSET LOONGSON_REG(LOONGSON_REGBASE + 0x30) -#define LOONGSON_INTENCLR LOONGSON_REG(LOONGSON_REGBASE + 0x34) -#define LOONGSON_INTEN LOONGSON_REG(LOONGSON_REGBASE + 0x38) -#define LOONGSON_INTISR LOONGSON_REG(LOONGSON_REGBASE + 0x3c) - -extern void loongson3_send_irq_by_ipi(int cpu, int irqs); - -unsigned int irq_cpu[16] = {[0 ... 15] = -1}; -unsigned int ht_irq[] = {0, 1, 3, 4, 5, 6, 7, 8, 12, 14, 15}; -unsigned int local_irq = 1<<0 | 1<<1 | 1<<2 | 1<<7 | 1<<8 | 1<<12; - -int plat_set_irq_affinity(struct irq_data *d, const struct cpumask *affinity, - bool force) -{ - unsigned int cpu; - struct cpumask new_affinity; - - /* I/O devices are connected on package-0 */ - cpumask_copy(&new_affinity, affinity); - for_each_cpu(cpu, affinity) - if (cpu_data[cpu].package > 0) - cpumask_clear_cpu(cpu, &new_affinity); - - if (cpumask_empty(&new_affinity)) - return -EINVAL; - - cpumask_copy(d->common->affinity, &new_affinity); - - return IRQ_SET_MASK_OK_NOCOPY; -} - -static void ht_irqdispatch(void) -{ - unsigned int i, irq; - struct irq_data *irqd; - struct cpumask affinity; - - irq = LOONGSON_HT1_INT_VECTOR(0); - LOONGSON_HT1_INT_VECTOR(0) = irq; /* Acknowledge the IRQs */ - - for (i = 0; i < ARRAY_SIZE(ht_irq); i++) { - if (!(irq & (0x1 << ht_irq[i]))) - continue; - - /* handled by local core */ - if (local_irq & (0x1 << ht_irq[i])) { - do_IRQ(ht_irq[i]); - continue; - } - - irqd = irq_get_irq_data(ht_irq[i]); - cpumask_and(&affinity, irqd->common->affinity, cpu_active_mask); - if (cpumask_empty(&affinity)) { - do_IRQ(ht_irq[i]); - continue; - } - - irq_cpu[ht_irq[i]] = cpumask_next(irq_cpu[ht_irq[i]], &affinity); - if (irq_cpu[ht_irq[i]] >= nr_cpu_ids) - irq_cpu[ht_irq[i]] = cpumask_first(&affinity); - - if (irq_cpu[ht_irq[i]] == 0) { - do_IRQ(ht_irq[i]); - continue; - } - - /* balanced by other cores */ - loongson3_send_irq_by_ipi(irq_cpu[ht_irq[i]], (0x1 << ht_irq[i])); - } -} - -#define UNUSED_IPS (CAUSEF_IP5 | CAUSEF_IP4 | CAUSEF_IP1 | CAUSEF_IP0) - -asmlinkage void plat_irq_dispatch(void) -{ - unsigned int pending; - - pending = read_c0_cause() & read_c0_status() & ST0_IM; - - if (pending & CAUSEF_IP7) - do_IRQ(LOONGSON_TIMER_IRQ); -#if defined(CONFIG_SMP) - if (pending & CAUSEF_IP6) - loongson3_ipi_interrupt(); -#endif - if (pending & CAUSEF_IP3) - ht_irqdispatch(); - if (pending & CAUSEF_IP2) - do_IRQ(LOONGSON_UART_IRQ); - if (pending & UNUSED_IPS) { - pr_err("%s : spurious interrupt\n", __func__); - spurious_interrupt(); - } -} - -static inline void mask_loongson_irq(struct irq_data *d) { } -static inline void unmask_loongson_irq(struct irq_data *d) { } - - /* For MIPS IRQs which shared by all cores */ -static struct irq_chip loongson_irq_chip = { - .name = "Loongson", - .irq_ack = mask_loongson_irq, - .irq_mask = mask_loongson_irq, - .irq_mask_ack = mask_loongson_irq, - .irq_unmask = unmask_loongson_irq, - .irq_eoi = unmask_loongson_irq, -}; - -void irq_router_init(void) -{ - int i; - - /* route LPC int to cpu core0 int 0 */ - LOONGSON_INT_ROUTER_LPC = - LOONGSON_INT_COREx_INTy(loongson_sysconf.boot_cpu_id, 0); - /* route HT1 int0 ~ int7 to cpu core0 INT1*/ - for (i = 0; i < 8; i++) - LOONGSON_INT_ROUTER_HT1(i) = - LOONGSON_INT_COREx_INTy(loongson_sysconf.boot_cpu_id, 1); - /* enable HT1 interrupt */ - LOONGSON_HT1_INTN_EN(0) = 0xffffffff; - /* enable router interrupt intenset */ - LOONGSON_INT_ROUTER_INTENSET = - LOONGSON_INT_ROUTER_INTEN | (0xffff << 16) | 0x1 << 10; -} void __init arch_init_irq(void) { - struct irq_chip *chip; - - /* - * Clear all of the interrupts while we change the able around a bit. - * int-handler is not on bootstrap - */ - clear_c0_status(ST0_IM | ST0_BEV); - - /* no steer */ - LOONGSON_INTSTEER = 0; - - /* - * Mask out all interrupt by writing "1" to all bit position in - * the interrupt reset reg. - */ - LOONGSON_INTENCLR = ~0; - - clear_c0_status(ST0_IM | ST0_BEV); - - irq_router_init(); - mips_cpu_irq_init(); - init_i8259_irqs(); - chip = irq_get_chip(I8259A_IRQ_BASE); - chip->irq_set_affinity = plat_set_irq_affinity; - - irq_set_chip_and_handler(LOONGSON_UART_IRQ, - &loongson_irq_chip, handle_percpu_irq); - irq_set_chip_and_handler(LOONGSON_BRIDGE_IRQ, - &loongson_irq_chip, handle_percpu_irq); - - set_c0_status(STATUSF_IP2 | STATUSF_IP3 | STATUSF_IP6); + irqchip_init(); } #ifdef CONFIG_HOTPLUG_CPU diff --git a/arch/mips/loongson64/smp.c b/arch/mips/loongson64/smp.c index 8ad845e522fb..d53942c56a16 100644 --- a/arch/mips/loongson64/smp.c +++ b/arch/mips/loongson64/smp.c @@ -4,6 +4,7 @@ * Author: Chen Huacai, chenhc@lemote.com */ +#include #include #include #include @@ -24,6 +25,8 @@ DEFINE_PER_CPU(int, cpu_state); +#define LS_IPI_IRQ (MIPS_CPU_IRQ_BASE + 6) + static void *ipi_set0_regs[16]; static void *ipi_clear0_regs[16]; static void *ipi_status0_regs[16]; @@ -245,21 +248,13 @@ loongson3_send_ipi_mask(const struct cpumask *mask, unsigned int action) loongson3_ipi_write32((u32)action, ipi_set0_regs[cpu_logical_map(i)]); } -#define IPI_IRQ_OFFSET 6 - -void loongson3_send_irq_by_ipi(int cpu, int irqs) -{ - loongson3_ipi_write32(irqs << IPI_IRQ_OFFSET, ipi_set0_regs[cpu_logical_map(cpu)]); -} - -void loongson3_ipi_interrupt() +static irqreturn_t loongson3_ipi_interrupt(int irq, void *dev_id) { int i, cpu = smp_processor_id(); - unsigned int action, c0count, irqs; + unsigned int action, c0count; /* Load the ipi register to figure out what we're supposed to do */ action = loongson3_ipi_read32(ipi_status0_regs[cpu_logical_map(cpu)]); - irqs = action >> IPI_IRQ_OFFSET; /* Clear the ipi register to clear the interrupt */ loongson3_ipi_write32((u32)action, ipi_clear0_regs[cpu_logical_map(cpu)]); @@ -282,13 +277,7 @@ void loongson3_ipi_interrupt() __wbflush(); /* Let others see the result ASAP */ } - if (irqs) { - int irq; - while ((irq = ffs(irqs))) { - do_IRQ(irq-1); - irqs &= ~(1<<(irq-1)); - } - } + return IRQ_HANDLED; } #define MAX_LOOPS 800 @@ -384,6 +373,9 @@ static void __init loongson3_smp_setup(void) static void __init loongson3_prepare_cpus(unsigned int max_cpus) { + if (request_irq(LS_IPI_IRQ, loongson3_ipi_interrupt, + IRQF_PERCPU | IRQF_NO_SUSPEND, "SMP_IPI", NULL)) + pr_err("Failed to request IPI IRQ\n"); init_cpu_present(cpu_possible_mask); per_cpu(cpu_state, smp_processor_id()) = CPU_ONLINE; } From patchwork Fri Aug 30 04:32:26 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Jiaxun Yang X-Patchwork-Id: 11122927 Return-Path: Received: from mail.kernel.org (pdx-korg-mail-1.web.codeaurora.org [172.30.200.123]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id 05DE5112C for ; Fri, 30 Aug 2019 04:34:04 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.kernel.org (Postfix) with ESMTP id D70EF22CE9 for ; Fri, 30 Aug 2019 04:34:03 +0000 (UTC) Authentication-Results: mail.kernel.org; dkim=pass (1024-bit key) header.d=flygoat.com header.i=@flygoat.com header.b="Qk1t3lIJ" Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1727434AbfH3EeD (ORCPT ); Fri, 30 Aug 2019 00:34:03 -0400 Received: from forward104o.mail.yandex.net ([37.140.190.179]:41190 "EHLO forward104o.mail.yandex.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1726236AbfH3EeD (ORCPT ); Fri, 30 Aug 2019 00:34:03 -0400 Received: from mxback30g.mail.yandex.net (mxback30g.mail.yandex.net [IPv6:2a02:6b8:0:1472:2741:0:8b7:330]) by forward104o.mail.yandex.net (Yandex) with ESMTP id 393B4940BE1; Fri, 30 Aug 2019 07:33:59 +0300 (MSK) Received: from smtp1p.mail.yandex.net (smtp1p.mail.yandex.net [2a02:6b8:0:1472:2741:0:8b6:6]) by mxback30g.mail.yandex.net (nwsmtp/Yandex) with ESMTP id aoMsNdSviV-XwFG9X8f; Fri, 30 Aug 2019 07:33:59 +0300 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=flygoat.com; s=mail; t=1567139639; bh=1wA0RivgWt4iFC4/HQ9Vbdnus6VesHHOMA3MK/kN4kM=; h=In-Reply-To:Subject:To:From:Cc:References:Date:Message-Id; b=Qk1t3lIJpVwkJgxldpO6hUx5bDRYkurfZbdBCTQZle5oT1bdSdEzkWwuONe6o51Ar 3uldG2aT8vPWuag43K/Ko7WAgKyjUg9p7+scDljhBUaAZ2nswNDtJjYU6jIzMcyw3z vaPPFHUpAy4sy03289XSysTspm1ys3g3OCAQmc/8= Authentication-Results: mxback30g.mail.yandex.net; dkim=pass header.i=@flygoat.com Received: by smtp1p.mail.yandex.net (nwsmtp/Yandex) with ESMTPSA id vFuwVxmDwr-XoDG0YYA; Fri, 30 Aug 2019 07:33:57 +0300 (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits)) (Client certificate not present) From: Jiaxun Yang To: linux-mips@vger.kernel.org Cc: chenhc@lemote.com, paul.burton@mips.com, tglx@linutronix.de, jason@lakedaemon.net, maz@kernel.org, linux-kernel@vger.kernel.org, robh+dt@kernel.org, mark.rutland@arm.co, devicetree@vger.kernel.org, Jiaxun Yang Subject: [PATCH v1 12/18] dt-bindings: mips: Add loongson cpus & boards Date: Fri, 30 Aug 2019 12:32:26 +0800 Message-Id: <20190830043232.20191-7-jiaxun.yang@flygoat.com> X-Mailer: git-send-email 2.22.0 In-Reply-To: <20190830043232.20191-1-jiaxun.yang@flygoat.com> References: <20190830043232.20191-1-jiaxun.yang@flygoat.com> MIME-Version: 1.0 Sender: linux-mips-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-mips@vger.kernel.org Prepare for later dts. Signed-off-by: Jiaxun Yang --- .../bindings/mips/loongson/cpus.yaml | 38 +++++++++++ .../bindings/mips/loongson/devices.yaml | 64 +++++++++++++++++++ 2 files changed, 102 insertions(+) create mode 100644 Documentation/devicetree/bindings/mips/loongson/cpus.yaml create mode 100644 Documentation/devicetree/bindings/mips/loongson/devices.yaml diff --git a/Documentation/devicetree/bindings/mips/loongson/cpus.yaml b/Documentation/devicetree/bindings/mips/loongson/cpus.yaml new file mode 100644 index 000000000000..dc6dd5114d5e --- /dev/null +++ b/Documentation/devicetree/bindings/mips/loongson/cpus.yaml @@ -0,0 +1,38 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/mips/loongson/cpus.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Loongson CPUs bindings + +maintainers: + - Jiaxun Yang + +description: |+ + The device tree allows to describe the layout of CPUs in a system through + the "cpus" node, which in turn contains a number of subnodes (ie "cpu") + defining properties for every cpu. + + Bindings for CPU nodes follow the Devicetree Specification, available from: + + https://www.devicetree.org/specifications/ + +properties: + reg: + maxItems: 1 + description: | + Physical ID of a CPU, Can be read from CP0 EBase.CPUNum. + + compatible: + enum: + - loongson,gs464 + - loongson,gs464e + - loongson,gs264 + - loongson,gs464v + +required: + - device_type + - reg + - compatible +... diff --git a/Documentation/devicetree/bindings/mips/loongson/devices.yaml b/Documentation/devicetree/bindings/mips/loongson/devices.yaml new file mode 100644 index 000000000000..aa6c42013d2c --- /dev/null +++ b/Documentation/devicetree/bindings/mips/loongson/devices.yaml @@ -0,0 +1,64 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/mips/loongson/devices.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Loongson based Platforms Device Tree Bindings + +maintainers: + - Jiaxun Yang +description: | + Devices with a Loongson CPU shall have the following properties. + +properties: + $nodename: + const: '/' + compatible: + oneOf: + + - description: Loongson 3A1000 + RS780E 1Way + items: + - const: loongson,ls3a1000-780e-1way + + - description: Loongson 3A1000 + RS780E 2Way + items: + - const: loongson,ls3a1000-780e-2way + + - description: Loongson 3A1000 + RS780E 4Way + items: + - const: loongson,ls3a1000-780e-4way + + - description: Loongson 3B1000/1500 + RS780E 1Way + items: + - const: loongson,ls3b-780e-1way + + - description: Loongson 3B1000/1500 + RS780E 2Way + items: + - const: loongson,ls3b-780e-2way + + - description: Loongson 3A2000 + RS780E 1Way + items: + - const: loongson,ls3a2000-780e-1way + + - description: Loongson 3A2000 + RS780E 2Way + items: + - const: loongson,ls3a2000-780e-2way + + - description: Loongson 3A2000 + RS780E 4Way + items: + - const: loongson,ls3a2000-780e-4way + + - description: Loongson 3A3000 + RS780E 1Way + items: + - const: loongson,ls3a3000-780e-1way + + - description: Loongson 3A3000 + RS780E 2Way + items: + - const: loongson,ls3a3000-780e-2way + + - description: Loongson 3A3000 + RS780E 4Way + items: + - const: loongson,ls3a3000-780e-4way + +... From patchwork Fri Aug 30 04:32:27 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Jiaxun Yang X-Patchwork-Id: 11122929 Return-Path: Received: from mail.kernel.org (pdx-korg-mail-1.web.codeaurora.org [172.30.200.123]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id 7751A14DE for ; Fri, 30 Aug 2019 04:34:11 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.kernel.org (Postfix) with ESMTP id 555AB22CE9 for ; Fri, 30 Aug 2019 04:34:11 +0000 (UTC) Authentication-Results: mail.kernel.org; dkim=pass (1024-bit key) header.d=flygoat.com header.i=@flygoat.com header.b="wEdYiSXz" Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1728158AbfH3EeL (ORCPT ); Fri, 30 Aug 2019 00:34:11 -0400 Received: from forward103j.mail.yandex.net ([5.45.198.246]:40468 "EHLO forward103j.mail.yandex.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1727900AbfH3EeK (ORCPT ); Fri, 30 Aug 2019 00:34:10 -0400 Received: from mxback29g.mail.yandex.net (mxback29g.mail.yandex.net [IPv6:2a02:6b8:0:1472:2741:0:8b7:329]) by forward103j.mail.yandex.net (Yandex) with ESMTP id EA523674076C; Fri, 30 Aug 2019 07:34:07 +0300 (MSK) Received: from smtp1p.mail.yandex.net (smtp1p.mail.yandex.net [2a02:6b8:0:1472:2741:0:8b6:6]) by mxback29g.mail.yandex.net (nwsmtp/Yandex) with ESMTP id bnaFSH0bwA-Y7IeprpS; Fri, 30 Aug 2019 07:34:07 +0300 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=flygoat.com; s=mail; t=1567139647; bh=KqSC2kgjOwolQ3VxE+oPXlHyAIFfqyGw3F6AmU6BiBw=; h=In-Reply-To:Subject:To:From:Cc:References:Date:Message-Id; b=wEdYiSXzJhIH3vCjHDy5Dy99lpbq9w5Lbo582Xub18rZu6iMMJNaHEEIKr29GYzgE 8k65AUmca+4zJvg+AoxqUexMnUNv0JskcFRyHIDielrGexEs/bswYwMsHKS9ly9dg+ C2a0Tze/Vy5Paewexx8MZTn06Nn+TDO5tGi6D5o4= Authentication-Results: mxback29g.mail.yandex.net; dkim=pass header.i=@flygoat.com Received: by smtp1p.mail.yandex.net (nwsmtp/Yandex) with ESMTPSA id vFuwVxmDwr-XxDG0HVq; Fri, 30 Aug 2019 07:34:05 +0300 (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits)) (Client certificate not present) From: Jiaxun Yang To: linux-mips@vger.kernel.org Cc: chenhc@lemote.com, paul.burton@mips.com, tglx@linutronix.de, jason@lakedaemon.net, maz@kernel.org, linux-kernel@vger.kernel.org, robh+dt@kernel.org, mark.rutland@arm.co, devicetree@vger.kernel.org, Jiaxun Yang Subject: [PATCH v1 13/18] dt-bindings: Document loongson vendor-prefix Date: Fri, 30 Aug 2019 12:32:27 +0800 Message-Id: <20190830043232.20191-8-jiaxun.yang@flygoat.com> X-Mailer: git-send-email 2.22.0 In-Reply-To: <20190830043232.20191-1-jiaxun.yang@flygoat.com> References: <20190830043232.20191-1-jiaxun.yang@flygoat.com> MIME-Version: 1.0 Sender: linux-mips-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-mips@vger.kernel.org Loongson is a MIPS-compatible processor vendor. Signed-off-by: Jiaxun Yang Acked-by: Rob Herring --- Documentation/devicetree/bindings/vendor-prefixes.yaml | 2 ++ 1 file changed, 2 insertions(+) diff --git a/Documentation/devicetree/bindings/vendor-prefixes.yaml b/Documentation/devicetree/bindings/vendor-prefixes.yaml index 6992bbbbffab..855d5b7a6660 100644 --- a/Documentation/devicetree/bindings/vendor-prefixes.yaml +++ b/Documentation/devicetree/bindings/vendor-prefixes.yaml @@ -529,6 +529,8 @@ patternProperties: description: Linear Technology Corporation "^logicpd,.*": description: Logic PD, Inc. + "^loongson,.*": + description: Loongson Technology Corporation Limited "^lsi,.*": description: LSI Corp. (LSI Logic) "^lwn,.*": From patchwork Fri Aug 30 04:32:28 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Jiaxun Yang X-Patchwork-Id: 11122933 Return-Path: Received: from mail.kernel.org (pdx-korg-mail-1.web.codeaurora.org [172.30.200.123]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id 78A05112C for ; Fri, 30 Aug 2019 04:35:06 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.kernel.org (Postfix) with ESMTP id 408BA2186A for ; Fri, 30 Aug 2019 04:35:06 +0000 (UTC) Authentication-Results: mail.kernel.org; dkim=pass (1024-bit key) header.d=flygoat.com header.i=@flygoat.com header.b="hxzo877T" Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1725819AbfH3EfG (ORCPT ); Fri, 30 Aug 2019 00:35:06 -0400 Received: from forward103p.mail.yandex.net ([77.88.28.106]:47563 "EHLO forward103p.mail.yandex.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1726480AbfH3EfF (ORCPT ); Fri, 30 Aug 2019 00:35:05 -0400 Received: from mxback16g.mail.yandex.net (mxback16g.mail.yandex.net [IPv6:2a02:6b8:0:1472:2741:0:8b7:316]) by forward103p.mail.yandex.net (Yandex) with ESMTP id 2331C18C0C7E; Fri, 30 Aug 2019 07:35:01 +0300 (MSK) Received: from smtp1p.mail.yandex.net (smtp1p.mail.yandex.net [2a02:6b8:0:1472:2741:0:8b6:6]) by mxback16g.mail.yandex.net (nwsmtp/Yandex) with ESMTP id 5ou7LevmWC-Z0MGIOhe; Fri, 30 Aug 2019 07:35:01 +0300 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=flygoat.com; s=mail; t=1567139701; bh=HukssETrEWZOMmhh/v0AklAY9DSgNSg14oMPsc2f5NI=; h=In-Reply-To:Subject:To:From:Cc:References:Date:Message-Id; b=hxzo877TR6PXOA07Cb58hYz7V03qGu6zcYfF1RCpA6bu9wppLd/F+Ue/b+lAgOBA4 06nmNpm7spjidD5Q/sBqRHEKwbqaOg9hdd6CkgdrOB37sGu/HbOpEZQOj8ara7Lm5E S59qRgNyC8YHLwdibFYJZiIGvyKN7/oUShyWH9CE= Authentication-Results: mxback16g.mail.yandex.net; dkim=pass header.i=@flygoat.com Received: by smtp1p.mail.yandex.net (nwsmtp/Yandex) with ESMTPSA id vFuwVxmDwr-Y8DGTCtM; Fri, 30 Aug 2019 07:34:57 +0300 (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits)) (Client certificate not present) From: Jiaxun Yang To: linux-mips@vger.kernel.org Cc: chenhc@lemote.com, paul.burton@mips.com, tglx@linutronix.de, jason@lakedaemon.net, maz@kernel.org, linux-kernel@vger.kernel.org, robh+dt@kernel.org, mark.rutland@arm.co, devicetree@vger.kernel.org, Jiaxun Yang Subject: [PATCH v1 14/18] MIPS: Loongson64: Add generic dts Date: Fri, 30 Aug 2019 12:32:28 +0800 Message-Id: <20190830043232.20191-9-jiaxun.yang@flygoat.com> X-Mailer: git-send-email 2.22.0 In-Reply-To: <20190830043232.20191-1-jiaxun.yang@flygoat.com> References: <20190830043232.20191-1-jiaxun.yang@flygoat.com> MIME-Version: 1.0 Sender: linux-mips-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-mips@vger.kernel.org Add generic device dts for Loongson-3 devices. They seems identical but will be different later. Signed-off-by: Jiaxun Yang --- arch/mips/Kconfig | 4 +- arch/mips/boot/dts/Makefile | 1 + arch/mips/boot/dts/loongson/Makefile | 8 + arch/mips/boot/dts/loongson/ls3-2nodes.dtsi | 8 + arch/mips/boot/dts/loongson/ls3-4nodes.dtsi | 15 ++ arch/mips/boot/dts/loongson/ls3-cpus.dtsi | 150 ++++++++++++++++++ arch/mips/boot/dts/loongson/ls3-gs464.dtsi | 18 +++ arch/mips/boot/dts/loongson/ls3-gs464e.dtsi | 18 +++ .../boot/dts/loongson/ls3-rs780e-pch.dtsi | 35 ++++ arch/mips/boot/dts/loongson/ls3a-package.dtsi | 59 +++++++ .../boot/dts/loongson/ls3a1000_780e_1way.dts | 12 ++ .../boot/dts/loongson/ls3a1000_780e_2way.dts | 13 ++ .../boot/dts/loongson/ls3a1000_780e_4way.dts | 13 ++ .../boot/dts/loongson/ls3a2000_780e_1way.dts | 12 ++ .../boot/dts/loongson/ls3a2000_780e_2way.dts | 13 ++ .../boot/dts/loongson/ls3a2000_780e_4way.dts | 13 ++ .../boot/dts/loongson/ls3a3000_780e_1way.dts | 12 ++ .../boot/dts/loongson/ls3a3000_780e_2way.dts | 13 ++ .../boot/dts/loongson/ls3a3000_780e_4way.dts | 13 ++ arch/mips/boot/dts/loongson/ls3b-package.dtsi | 59 +++++++ .../mips/boot/dts/loongson/ls3b_780e_1way.dts | 13 ++ .../mips/boot/dts/loongson/ls3b_780e_2way.dts | 13 ++ 22 files changed, 514 insertions(+), 1 deletion(-) create mode 100644 arch/mips/boot/dts/loongson/Makefile create mode 100644 arch/mips/boot/dts/loongson/ls3-2nodes.dtsi create mode 100644 arch/mips/boot/dts/loongson/ls3-4nodes.dtsi create mode 100644 arch/mips/boot/dts/loongson/ls3-cpus.dtsi create mode 100644 arch/mips/boot/dts/loongson/ls3-gs464.dtsi create mode 100644 arch/mips/boot/dts/loongson/ls3-gs464e.dtsi create mode 100644 arch/mips/boot/dts/loongson/ls3-rs780e-pch.dtsi create mode 100644 arch/mips/boot/dts/loongson/ls3a-package.dtsi create mode 100644 arch/mips/boot/dts/loongson/ls3a1000_780e_1way.dts create mode 100644 arch/mips/boot/dts/loongson/ls3a1000_780e_2way.dts create mode 100644 arch/mips/boot/dts/loongson/ls3a1000_780e_4way.dts create mode 100644 arch/mips/boot/dts/loongson/ls3a2000_780e_1way.dts create mode 100644 arch/mips/boot/dts/loongson/ls3a2000_780e_2way.dts create mode 100644 arch/mips/boot/dts/loongson/ls3a2000_780e_4way.dts create mode 100644 arch/mips/boot/dts/loongson/ls3a3000_780e_1way.dts create mode 100644 arch/mips/boot/dts/loongson/ls3a3000_780e_2way.dts create mode 100644 arch/mips/boot/dts/loongson/ls3a3000_780e_4way.dts create mode 100644 arch/mips/boot/dts/loongson/ls3b-package.dtsi create mode 100644 arch/mips/boot/dts/loongson/ls3b_780e_1way.dts create mode 100644 arch/mips/boot/dts/loongson/ls3b_780e_2way.dts diff --git a/arch/mips/Kconfig b/arch/mips/Kconfig index 92a2ee773a40..1c27c3a4e036 100644 --- a/arch/mips/Kconfig +++ b/arch/mips/Kconfig @@ -485,6 +485,8 @@ config MACH_LOONGSON64 select SYS_SUPPORTS_LITTLE_ENDIAN select ZONE_DMA32 select SYS_SUPPORTS_ZBOOT + select USE_OF + select BUILTIN_DTB help This enables the support of Loongson-3A/3B/2-series-soc processors @@ -3074,7 +3076,7 @@ endchoice choice prompt "Kernel command line type" if !CMDLINE_OVERRIDE default MIPS_CMDLINE_FROM_DTB if USE_OF && !ATH79 && !MACH_INGENIC && \ - !MIPS_MALTA && \ + !MACH_LOONGSON64 && !MIPS_MALTA && \ !CAVIUM_OCTEON_SOC default MIPS_CMDLINE_FROM_BOOTLOADER diff --git a/arch/mips/boot/dts/Makefile b/arch/mips/boot/dts/Makefile index 1e79cab8e269..d429a69bfe30 100644 --- a/arch/mips/boot/dts/Makefile +++ b/arch/mips/boot/dts/Makefile @@ -4,6 +4,7 @@ subdir-y += cavium-octeon subdir-y += img subdir-y += ingenic subdir-y += lantiq +subdir-y += loongson subdir-y += mscc subdir-y += mti subdir-y += netlogic diff --git a/arch/mips/boot/dts/loongson/Makefile b/arch/mips/boot/dts/loongson/Makefile new file mode 100644 index 000000000000..25dca8a89d5d --- /dev/null +++ b/arch/mips/boot/dts/loongson/Makefile @@ -0,0 +1,8 @@ +# SPDX_License_Identifier: GPL_2.0 +dtb-$(CONFIG_MACH_LOONGSON64) += ls3a1000_780e_1way.dtb ls3a1000_780e_2way.dtb ls3a1000_780e_4way.dtb \ + ls3b_780e_1way.dtb ls3b_780e_2way.dtb \ + ls3a2000_780e_1way.dtb ls3a2000_780e_2way.dtb ls3a2000_780e_4way.dtb \ + ls3a3000_780e_1way.dtb ls3a3000_780e_2way.dtb ls3a3000_780e_4way.dtb + + +obj-$(CONFIG_BUILTIN_DTB) += $(addsuffix .o, $(dtb-y)) diff --git a/arch/mips/boot/dts/loongson/ls3-2nodes.dtsi b/arch/mips/boot/dts/loongson/ls3-2nodes.dtsi new file mode 100644 index 000000000000..3103a4f96f68 --- /dev/null +++ b/arch/mips/boot/dts/loongson/ls3-2nodes.dtsi @@ -0,0 +1,8 @@ +// SPDX-License-Identifier: GPL-2.0 + +&cpu4 { status = "okay"; }; +&cpu5 { status = "okay"; }; +&cpu6 { status = "okay"; }; +&cpu7 { status = "okay"; }; + +&scache1 { status = "okay"; }; diff --git a/arch/mips/boot/dts/loongson/ls3-4nodes.dtsi b/arch/mips/boot/dts/loongson/ls3-4nodes.dtsi new file mode 100644 index 000000000000..be8cca52c072 --- /dev/null +++ b/arch/mips/boot/dts/loongson/ls3-4nodes.dtsi @@ -0,0 +1,15 @@ +// SPDX-License-Identifier: GPL-2.0 + +/include/ "ls3-2nodes.dtsi" + +&cpu8 { status = "okay"; }; +&cpu9 { status = "okay"; }; +&cpu10 { status = "okay"; }; +&cpu11 { status = "okay"; }; +&cpu12 { status = "okay"; }; +&cpu13 { status = "okay"; }; +&cpu14 { status = "okay"; }; +&cpu15 { status = "okay"; }; + +&scache2 { status = "okay"; }; +&scache3 { status = "okay"; }; diff --git a/arch/mips/boot/dts/loongson/ls3-cpus.dtsi b/arch/mips/boot/dts/loongson/ls3-cpus.dtsi new file mode 100644 index 000000000000..5adfbbace027 --- /dev/null +++ b/arch/mips/boot/dts/loongson/ls3-cpus.dtsi @@ -0,0 +1,150 @@ +// SPDX-License-Identifier: GPL-2.0 + +/ { + #address-cells = <2>; + #size-cells = <2>; + + /* + * Loongson-3 may have as many as 4 nodes, each node has 4 cores. + * Each core has its own pcache and cores in the same node share scache. + * CPU 0-3 should always exist in all the systems. + */ + cpus { + #address-cells = <1>; + #size-cells = <0>; + + cpu0: cpu@0 { + device_type = "cpu"; + reg = <0x0>; + next-level-cache = <&scache0>; + }; + + cpu1: cpu@1 { + device_type = "cpu"; + reg = <0x1>; + next-level-cache = <&scache0>; + }; + + cpu2: cpu@2 { + device_type = "cpu"; + reg = <0x2>; + next-level-cache = <&scache0>; + }; + + cpu3: cpu@3 { + device_type = "cpu"; + reg = <0x3>; + next-level-cache = <&scache0>; + }; + + cpu4: cpu@4 { + status = "disabled"; + device_type = "cpu"; + reg = <0x4>; + next-level-cache = <&scache1>; + }; + + cpu5: cpu@5 { + status = "disabled"; + device_type = "cpu"; + reg = <0x5>; + next-level-cache = <&scache1>; + }; + + cpu6: cpu@6 { + status = "disabled"; + device_type = "cpu"; + reg = <0x6>; + next-level-cache = <&scache1>; + }; + + cpu7: cpu@7 { + status = "disabled"; + device_type = "cpu"; + reg = <0x7>; + next-level-cache = <&scache1>; + }; + + cpu8: cpu@8 { + status = "disabled"; + device_type = "cpu"; + reg = <0x8>; + next-level-cache = <&scache2>; + }; + + cpu9: cpu@9 { + status = "disabled"; + device_type = "cpu"; + reg = <0x9>; + next-level-cache = <&scache2>; + }; + + cpu10: cpu@a { + status = "disabled"; + device_type = "cpu"; + reg = <0xa>; + next-level-cache = <&scache2>; + }; + + cpu11: cpu@b { + status = "disabled"; + device_type = "cpu"; + reg = <0xb>; + next-level-cache = <&scache2>; + }; + + cpu12: cpu@c { + status = "disabled"; + device_type = "cpu"; + reg = <0xc>; + next-level-cache = <&scache3>; + }; + + cpu13: cpu@d { + status = "disabled"; + device_type = "cpu"; + reg = <0xd>; + next-level-cache = <&scache3>; + }; + + cpu14: cpu@e { + status = "disabled"; + device_type = "cpu"; + reg = <0xe>; + next-level-cache = <&scache3>; + }; + + cpu15: cpu@f { + status = "disabled"; + device_type = "cpu"; + reg = <0xf>; + next-level-cache = <&scache3>; + }; + + scache0: l2-cache0 { + compatible = "cache"; + }; + + scache1: l2-cache1 { + status = "disabled"; + compatible = "cache"; + }; + + scache2: l2-cache2 { + status = "disabled"; + compatible = "cache"; + }; + + scache3: l2-cache3 { + status = "disabled"; + compatible = "cache"; + }; + }; + + cpuintc: interrupt-controller { + #address-cells = <0>; + #interrupt-cells = <1>; + interrupt-controller; + compatible = "mti,cpu-interrupt-controller"; + }; +}; diff --git a/arch/mips/boot/dts/loongson/ls3-gs464.dtsi b/arch/mips/boot/dts/loongson/ls3-gs464.dtsi new file mode 100644 index 000000000000..54d7be042150 --- /dev/null +++ b/arch/mips/boot/dts/loongson/ls3-gs464.dtsi @@ -0,0 +1,18 @@ +// SPDX-License-Identifier: GPL-2.0 + +&cpu0 { compatible = "loongson,gs464"; }; +&cpu1 { compatible = "loongson,gs464"; }; +&cpu2 { compatible = "loongson,gs464"; }; +&cpu3 { compatible = "loongson,gs464"; }; +&cpu4 { compatible = "loongson,gs464"; }; +&cpu5 { compatible = "loongson,gs464"; }; +&cpu6 { compatible = "loongson,gs464"; }; +&cpu7 { compatible = "loongson,gs464"; }; +&cpu8 { compatible = "loongson,gs464"; }; +&cpu9 { compatible = "loongson,gs464"; }; +&cpu10 { compatible = "loongson,gs464"; }; +&cpu11 { compatible = "loongson,gs464"; }; +&cpu12 { compatible = "loongson,gs464"; }; +&cpu13 { compatible = "loongson,gs464"; }; +&cpu14 { compatible = "loongson,gs464"; }; +&cpu15 { compatible = "loongson,gs464"; }; diff --git a/arch/mips/boot/dts/loongson/ls3-gs464e.dtsi b/arch/mips/boot/dts/loongson/ls3-gs464e.dtsi new file mode 100644 index 000000000000..c5f545ef8d94 --- /dev/null +++ b/arch/mips/boot/dts/loongson/ls3-gs464e.dtsi @@ -0,0 +1,18 @@ +// SPDX-License-Identifier: GPL-2.0 + +&cpu0 { compatible = "loongson,gs464e"; }; +&cpu1 { compatible = "loongson,gs464e"; }; +&cpu2 { compatible = "loongson,gs464e"; }; +&cpu3 { compatible = "loongson,gs464e"; }; +&cpu4 { compatible = "loongson,gs464e"; }; +&cpu5 { compatible = "loongson,gs464e"; }; +&cpu6 { compatible = "loongson,gs464e"; }; +&cpu7 { compatible = "loongson,gs464e"; }; +&cpu8 { compatible = "loongson,gs464e"; }; +&cpu9 { compatible = "loongson,gs464e"; }; +&cpu10 { compatible = "loongson,gs464e"; }; +&cpu11 { compatible = "loongson,gs464e"; }; +&cpu12 { compatible = "loongson,gs464e"; }; +&cpu13 { compatible = "loongson,gs464e"; }; +&cpu14 { compatible = "loongson,gs464e"; }; +&cpu15 { compatible = "loongson,gs464e"; }; diff --git a/arch/mips/boot/dts/loongson/ls3-rs780e-pch.dtsi b/arch/mips/boot/dts/loongson/ls3-rs780e-pch.dtsi new file mode 100644 index 000000000000..4e760bf1a883 --- /dev/null +++ b/arch/mips/boot/dts/loongson/ls3-rs780e-pch.dtsi @@ -0,0 +1,35 @@ +// SPDX-License-Identifier: GPL-2.0 + +/ { + pch { + compatible = "simple-bus"; + #address-cells = <2>; + #size-cells = <1>; + ranges = <0x000 0x10000000 0x000 0x10000000 0x10000000 + 0x000 0x40000000 0x000 0x40000000 0x40000000>; + + isa { + compatible = "isa"; + #address-cells = <2>; + #size-cells = <1>; + ranges = <1 0 0 0 0x1000>; + + i8259: interrupt-controller@20 { + compatible = "intel,i8259"; + interrupt-controller; + #interrupt-cells = <1>; + plat-poll; + interrupts = <0>, <1>, <2>, <3>, <4>, <5>, <6>, <7>, + <8>, <9>, <10>, <11>, <12>, <13>, <14>, <15>; + interrupt-parent = <&htintc>; + }; + + rtc0: rtc@70 { + compatible = "motorola,mc146818"; + reg = <1 0x70 0x8>; + interrupts = <8>; + interrupt-parent = <&i8259>; + }; + }; + }; +}; diff --git a/arch/mips/boot/dts/loongson/ls3a-package.dtsi b/arch/mips/boot/dts/loongson/ls3a-package.dtsi new file mode 100644 index 000000000000..d4b7227f827d --- /dev/null +++ b/arch/mips/boot/dts/loongson/ls3a-package.dtsi @@ -0,0 +1,59 @@ +// SPDX-License-Identifier: GPL-2.0 + +#include + +/ { + package@0 { + compatible = "simple-bus"; + #address-cells = <2>; + #size-cells = <1>; + ranges = <0 0x1fe00000 0 0x1fe00000 0x100000 + 0 0x3ff00000 0 0x3ff00000 0x100000 + 0xEFD 0xFB000000 0xEFD 0xFB000000 0x10000000 /* 3A HT Config Space */>; + + iointc: interrupt-controller@3ff01400 { + compatible = "loongson,ls3-iointc"; + reg = <0 0x3ff01400 0x64>; + + interrupt-controller; + #interrupt-cells = <2>; + + interrupt-parent = <&cpuintc>; + interrupts = <2>; + }; + + cpu_uart0: serial@1fe001e0 { + device_type = "serial"; + compatible = "ns16550a"; + reg = <0 0x1fe001e0 0x8>; + clock-frequency = <33000000>; + interrupt-parent = <&iointc>; + interrupts = <10 IRQ_TYPE_LEVEL_HIGH>; + no-loopback-test; + }; + + cpu_uart1: serial@1fe001e8 { + status = "disabled"; + device_type = "serial"; + compatible = "ns16550a"; + reg = <0 0x1fe001e8 0x8>; + clock-frequency = <33000000>; + interrupts = <10 IRQ_TYPE_LEVEL_HIGH>; + interrupt-parent = <&iointc>; + no-loopback-test; + }; + + htintc: interrupt-controller@0xEFDFB000080 { + compatible = "loongson,ls3-htintc"; + reg = <0xEFD 0xFB000080 0x100>; + interrupt-controller; + #interrupt-cells = <1>; + + interrupt-parent = <&iointc>; + interrupts = <24 IRQ_TYPE_LEVEL_HIGH>, + <25 IRQ_TYPE_LEVEL_HIGH>, + <26 IRQ_TYPE_LEVEL_HIGH>, + <27 IRQ_TYPE_LEVEL_HIGH>; + }; + }; +}; diff --git a/arch/mips/boot/dts/loongson/ls3a1000_780e_1way.dts b/arch/mips/boot/dts/loongson/ls3a1000_780e_1way.dts new file mode 100644 index 000000000000..91cc0a4a277f --- /dev/null +++ b/arch/mips/boot/dts/loongson/ls3a1000_780e_1way.dts @@ -0,0 +1,12 @@ +// SPDX-License-Identifier: GPL-2.0 + +/dts-v1/; + +#include "ls3-cpus.dtsi" +#include "ls3-gs464.dtsi" +#include "ls3a-package.dtsi" +#include "ls3-rs780e-pch.dtsi" + +/ { + compatible = "loongson,ls3a1000-780e-1way"; +}; diff --git a/arch/mips/boot/dts/loongson/ls3a1000_780e_2way.dts b/arch/mips/boot/dts/loongson/ls3a1000_780e_2way.dts new file mode 100644 index 000000000000..47da242797fb --- /dev/null +++ b/arch/mips/boot/dts/loongson/ls3a1000_780e_2way.dts @@ -0,0 +1,13 @@ +// SPDX-License-Identifier: GPL-2.0 + +/dts-v1/; + +#include "ls3-cpus.dtsi" +#include "ls3-gs464.dtsi" +#include "ls3a-package.dtsi" +#include "ls3-2nodes.dtsi" +#include "ls3-rs780e-pch.dtsi" + +/ { + compatible = "loongson,ls3a1000-780e-2way"; +}; diff --git a/arch/mips/boot/dts/loongson/ls3a1000_780e_4way.dts b/arch/mips/boot/dts/loongson/ls3a1000_780e_4way.dts new file mode 100644 index 000000000000..1e4dfad78a64 --- /dev/null +++ b/arch/mips/boot/dts/loongson/ls3a1000_780e_4way.dts @@ -0,0 +1,13 @@ +// SPDX-License-Identifier: GPL-2.0 + +/dts-v1/; + +#include "ls3-cpus.dtsi" +#include "ls3-gs464.dtsi" +#include "ls3a-package.dtsi" +#include "ls3-4nodes.dtsi" +#include "ls3-rs780e-pch.dtsi" + +/ { + compatible = "loongson,ls3a1000-780e-4way"; +}; diff --git a/arch/mips/boot/dts/loongson/ls3a2000_780e_1way.dts b/arch/mips/boot/dts/loongson/ls3a2000_780e_1way.dts new file mode 100644 index 000000000000..0701a3f2925b --- /dev/null +++ b/arch/mips/boot/dts/loongson/ls3a2000_780e_1way.dts @@ -0,0 +1,12 @@ +// SPDX-License-Identifier: GPL-2.0 + +/dts-v1/; + +#include "ls3-cpus.dtsi" +#include "ls3-gs464e.dtsi" +#include "ls3a-package.dtsi" +#include "ls3-rs780e-pch.dtsi" + +/ { + compatible = "loongson,ls3a2000-780e-1way"; +}; diff --git a/arch/mips/boot/dts/loongson/ls3a2000_780e_2way.dts b/arch/mips/boot/dts/loongson/ls3a2000_780e_2way.dts new file mode 100644 index 000000000000..bc4cf750651a --- /dev/null +++ b/arch/mips/boot/dts/loongson/ls3a2000_780e_2way.dts @@ -0,0 +1,13 @@ +// SPDX-License-Identifier: GPL-2.0 + +/dts-v1/; + +#include "ls3-cpus.dtsi" +#include "ls3-gs464e.dtsi" +#include "ls3a-package.dtsi" +#include "ls3-2nodes.dtsi" +#include "ls3-rs780e-pch.dtsi" + +/ { + compatible = "loongson,ls3a2000-780e-2way"; +}; diff --git a/arch/mips/boot/dts/loongson/ls3a2000_780e_4way.dts b/arch/mips/boot/dts/loongson/ls3a2000_780e_4way.dts new file mode 100644 index 000000000000..ba0e5321d1dd --- /dev/null +++ b/arch/mips/boot/dts/loongson/ls3a2000_780e_4way.dts @@ -0,0 +1,13 @@ +// SPDX-License-Identifier: GPL-2.0 + +/dts-v1/; + +#include "ls3-cpus.dtsi" +#include "ls3-gs464e.dtsi" +#include "ls3a-package.dtsi" +#include "ls3-4nodes.dtsi" +#include "ls3-rs780e-pch.dtsi" + +/ { + compatible = "loongson,ls3a2000-780e-4way"; +}; diff --git a/arch/mips/boot/dts/loongson/ls3a3000_780e_1way.dts b/arch/mips/boot/dts/loongson/ls3a3000_780e_1way.dts new file mode 100644 index 000000000000..bb70f936a9bd --- /dev/null +++ b/arch/mips/boot/dts/loongson/ls3a3000_780e_1way.dts @@ -0,0 +1,12 @@ +// SPDX-License-Identifier: GPL-2.0 + +/dts-v1/; + +#include "ls3-cpus.dtsi" +#include "ls3-gs464e.dtsi" +#include "ls3a-package.dtsi" +#include "ls3-rs780e-pch.dtsi" + +/ { + compatible = "loongson,ls3a3000-780e-1way"; +}; diff --git a/arch/mips/boot/dts/loongson/ls3a3000_780e_2way.dts b/arch/mips/boot/dts/loongson/ls3a3000_780e_2way.dts new file mode 100644 index 000000000000..ce1ac9db1804 --- /dev/null +++ b/arch/mips/boot/dts/loongson/ls3a3000_780e_2way.dts @@ -0,0 +1,13 @@ +// SPDX-License-Identifier: GPL-2.0 + +/dts-v1/; + +#include "ls3-cpus.dtsi" +#include "ls3-gs464e.dtsi" +#include "ls3a-package.dtsi" +#include "ls3-2nodes.dtsi" +#include "ls3-rs780e-pch.dtsi" + +/ { + compatible = "loongson,ls3a3000-780e-2way"; +}; diff --git a/arch/mips/boot/dts/loongson/ls3a3000_780e_4way.dts b/arch/mips/boot/dts/loongson/ls3a3000_780e_4way.dts new file mode 100644 index 000000000000..990c150f1d92 --- /dev/null +++ b/arch/mips/boot/dts/loongson/ls3a3000_780e_4way.dts @@ -0,0 +1,13 @@ +// SPDX-License-Identifier: GPL-2.0 + +/dts-v1/; + +#include "ls3-cpus.dtsi" +#include "ls3-gs464e.dtsi" +#include "ls3a-package.dtsi" +#include "ls3-4nodes.dtsi" +#include "ls3-rs780e-pch.dtsi" + +/ { + compatible = "loongson,ls3a3000-780e-4way"; +}; diff --git a/arch/mips/boot/dts/loongson/ls3b-package.dtsi b/arch/mips/boot/dts/loongson/ls3b-package.dtsi new file mode 100644 index 000000000000..cceca27aa0d9 --- /dev/null +++ b/arch/mips/boot/dts/loongson/ls3b-package.dtsi @@ -0,0 +1,59 @@ +// SPDX-License-Identifier: GPL-2.0 + +#include + +/ { + package@0 { + compatible = "simple-bus"; + #address-cells = <2>; + #size-cells = <1>; + ranges = <0 0x1fe00000 0 0x1fe00000 0x100000 + 0 0x3ff00000 0 0x3ff00000 0x100000 + 0x1EFD 0xFB000000 0x1EFD 0xFB000000 0x10000000 /* 3B HT Config Space */>; + + iointc: interrupt-controller@3ff01400 { + compatible = "loongson,ls3-iointc"; + reg = <0 0x3ff01400 0x64>; + + interrupt-controller; + #interrupt-cells = <2>; + + interrupt-parent = <&cpuintc>; + interrupts = <2>; + }; + + cpu_uart0: serial@1fe001e0 { + device_type = "serial"; + compatible = "ns16550a"; + reg = <0 0x1fe001e0 0x8>; + clock-frequency = <33000000>; + interrupts = <10 IRQ_TYPE_LEVEL_HIGH>; + interrupt-parent = <&iointc>; + no-loopback-test; + }; + + cpu_uart1: serial@1fe001e8 { + status = "disabled"; + device_type = "serial"; + compatible = "ns16550a"; + reg = <0 0x1fe001e8 0x8>; + clock-frequency = <33000000>; + interrupts = <10 IRQ_TYPE_LEVEL_HIGH>; + interrupt-parent = <&iointc>; + no-loopback-test; + }; + + htintc: interrupt-controller@0x1EFDFB000080 { + compatible = "loongson,ls3-htintc"; + reg = <0x1EFD 0xFB000080 0x100>; + interrupt-controller; + #interrupt-cells = <1>; + + interrupt-parent = <&iointc>; + interrupts = <24 IRQ_TYPE_LEVEL_HIGH>, + <25 IRQ_TYPE_LEVEL_HIGH>, + <26 IRQ_TYPE_LEVEL_HIGH>, + <27 IRQ_TYPE_LEVEL_HIGH>; + }; + }; +}; diff --git a/arch/mips/boot/dts/loongson/ls3b_780e_1way.dts b/arch/mips/boot/dts/loongson/ls3b_780e_1way.dts new file mode 100644 index 000000000000..e1f82ccca26f --- /dev/null +++ b/arch/mips/boot/dts/loongson/ls3b_780e_1way.dts @@ -0,0 +1,13 @@ +// SPDX-License-Identifier: GPL-2.0 + +/dts-v1/; + +#include "ls3-cpus.dtsi" +#include "ls3-gs464.dtsi" +#include "ls3b-package.dtsi" +#include "ls3-2nodes.dtsi" /* Yes, ls3b have 2 nodes per way */ +#include "ls3-rs780e-pch.dtsi" + +/ { + compatible = "loongson,ls3b-780e-1way"; +}; diff --git a/arch/mips/boot/dts/loongson/ls3b_780e_2way.dts b/arch/mips/boot/dts/loongson/ls3b_780e_2way.dts new file mode 100644 index 000000000000..9b21554cd521 --- /dev/null +++ b/arch/mips/boot/dts/loongson/ls3b_780e_2way.dts @@ -0,0 +1,13 @@ +// SPDX-License-Identifier: GPL-2.0 + +/dts-v1/; + +#include "ls3-cpus.dtsi" +#include "ls3-gs464.dtsi" +#include "ls3b-package.dtsi" +#include "ls3-4nodes.dtsi" /* Yes, ls3b have 2 nodes per way */ +#include "ls3-rs780e-pch.dtsi" + +/ { + compatible = "loongson,ls3b-780e-2way"; +}; From patchwork Fri Aug 30 04:32:29 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Jiaxun Yang X-Patchwork-Id: 11122935 Return-Path: Received: from mail.kernel.org (pdx-korg-mail-1.web.codeaurora.org [172.30.200.123]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id 47189112C for ; Fri, 30 Aug 2019 04:35:15 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.kernel.org (Postfix) with ESMTP id 1B24522CE9 for ; Fri, 30 Aug 2019 04:35:15 +0000 (UTC) Authentication-Results: mail.kernel.org; dkim=pass (1024-bit key) header.d=flygoat.com header.i=@flygoat.com header.b="rRs7Eb9F" Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1727836AbfH3EfO (ORCPT ); Fri, 30 Aug 2019 00:35:14 -0400 Received: from forward103p.mail.yandex.net ([77.88.28.106]:47682 "EHLO forward103p.mail.yandex.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1726480AbfH3EfO (ORCPT ); Fri, 30 Aug 2019 00:35:14 -0400 Received: from mxback29j.mail.yandex.net (mxback29j.mail.yandex.net [IPv6:2a02:6b8:0:1619::229]) by forward103p.mail.yandex.net (Yandex) with ESMTP id 8232518C0C7E; Fri, 30 Aug 2019 07:35:10 +0300 (MSK) Received: from smtp1p.mail.yandex.net (smtp1p.mail.yandex.net [2a02:6b8:0:1472:2741:0:8b6:6]) by mxback29j.mail.yandex.net (nwsmtp/Yandex) with ESMTP id Way484iZ88-ZAe8O3hD; Fri, 30 Aug 2019 07:35:10 +0300 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=flygoat.com; s=mail; t=1567139710; bh=uODOggA2sU/UqD6k394mdw/7H2tJIvZOdHb9aJWDEtI=; h=In-Reply-To:Subject:To:From:Cc:References:Date:Message-Id; b=rRs7Eb9Fh0fasVVgk3J0m4lYJ/1L0jzsGA4LeUXsDafxFE8U9OaZhWO0Imd7noP1G GLiDnJSp+Sa2pwBxO6gVWAa7FF7LwQ07kwinE2Kvfi4I5Lw/FgesFupH9O+znGZhFY eIoUaFvD/ufcHyJqfJ9yRKAwxgxxv6p/hlcMlgCU= Authentication-Results: mxback29j.mail.yandex.net; dkim=pass header.i=@flygoat.com Received: by smtp1p.mail.yandex.net (nwsmtp/Yandex) with ESMTPSA id vFuwVxmDwr-Z1DGWT5u; Fri, 30 Aug 2019 07:35:08 +0300 (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits)) (Client certificate not present) From: Jiaxun Yang To: linux-mips@vger.kernel.org Cc: chenhc@lemote.com, paul.burton@mips.com, tglx@linutronix.de, jason@lakedaemon.net, maz@kernel.org, linux-kernel@vger.kernel.org, robh+dt@kernel.org, mark.rutland@arm.co, devicetree@vger.kernel.org, Jiaxun Yang Subject: [PATCH v1 15/18] MIPS: Loongson64: Load built-in dtbs Date: Fri, 30 Aug 2019 12:32:29 +0800 Message-Id: <20190830043232.20191-10-jiaxun.yang@flygoat.com> X-Mailer: git-send-email 2.22.0 In-Reply-To: <20190830043232.20191-1-jiaxun.yang@flygoat.com> References: <20190830043232.20191-1-jiaxun.yang@flygoat.com> MIME-Version: 1.0 Sender: linux-mips-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-mips@vger.kernel.org Load proper dtb according to firmware passed parameters and CPU PRID. Signed-off-by: Jiaxun Yang --- .../asm/mach-loongson64/builtin_dtbs.h | 26 +++++++ .../include/asm/mach-loongson64/loongson64.h | 2 + arch/mips/loongson64/env.c | 67 +++++++++++++++++++ arch/mips/loongson64/setup.c | 15 +++++ 4 files changed, 110 insertions(+) create mode 100644 arch/mips/include/asm/mach-loongson64/builtin_dtbs.h diff --git a/arch/mips/include/asm/mach-loongson64/builtin_dtbs.h b/arch/mips/include/asm/mach-loongson64/builtin_dtbs.h new file mode 100644 index 000000000000..106287d54069 --- /dev/null +++ b/arch/mips/include/asm/mach-loongson64/builtin_dtbs.h @@ -0,0 +1,26 @@ +/* SPDX-License-Identifier: GPL-2.0-or-later */ +/* + * Copyright (C) 2019 Jiaxun Yang + * + * Built-in Generic dtbs for MACH_LOONGSON64 + */ + +#ifndef __ASM_MACH_LOONGSON64_BUILTIN_DTBS_H_ +#define __ASM_MACH_LOONGSON64_BUILTIN_DTBS_H_ + +extern u32 __dtb_ls3a1000_780e_1way_begin[]; +extern u32 __dtb_ls3a1000_780e_2way_begin[]; +extern u32 __dtb_ls3a1000_780e_4way_begin[]; + +extern u32 __dtb_ls3b_780e_1way_begin[]; +extern u32 __dtb_ls3b_780e_2way_begin[]; + +extern u32 __dtb_ls3a2000_780e_1way_begin[]; +extern u32 __dtb_ls3a2000_780e_2way_begin[]; +extern u32 __dtb_ls3a2000_780e_4way_begin[]; + +extern u32 __dtb_ls3a3000_780e_1way_begin[]; +extern u32 __dtb_ls3a3000_780e_2way_begin[]; +extern u32 __dtb_ls3a3000_780e_4way_begin[]; + +#endif diff --git a/arch/mips/include/asm/mach-loongson64/loongson64.h b/arch/mips/include/asm/mach-loongson64/loongson64.h index d877adb99d33..78daa3fb3fa7 100644 --- a/arch/mips/include/asm/mach-loongson64/loongson64.h +++ b/arch/mips/include/asm/mach-loongson64/loongson64.h @@ -45,4 +45,6 @@ extern u64 loongson_freqctrl[MAX_PACKAGES]; extern const struct plat_smp_ops loongson3_smp_ops; extern void __init prom_init_lefi(void); +extern void *loongson_fdt_blob; + #endif diff --git a/arch/mips/loongson64/env.c b/arch/mips/loongson64/env.c index 93658cfbf3a6..e46203c4a348 100644 --- a/arch/mips/loongson64/env.c +++ b/arch/mips/loongson64/env.c @@ -20,6 +20,7 @@ #include #include +#include #include u32 cpu_clock_freq; @@ -126,6 +127,72 @@ void __init prom_init_lefi(void) loongson_sysconf.cores_per_node - 1) / loongson_sysconf.cores_per_node; + if ((read_c0_prid() & PRID_IMP_MASK) == PRID_IMP_LOONGSON_64) { + switch (read_c0_prid() & PRID_REV_MASK) { + case PRID_REV_LOONGSON3A_R1: + switch (loongson_sysconf.nr_nodes) { + case 4: + loongson_fdt_blob = __dtb_ls3a1000_780e_4way_begin; + break; + case 2: + loongson_fdt_blob = __dtb_ls3a1000_780e_2way_begin; + break; + case 1: + default: + loongson_fdt_blob = __dtb_ls3a1000_780e_1way_begin; + break; + } + break; + case PRID_REV_LOONGSON3A_R2_0: + case PRID_REV_LOONGSON3A_R2_1: + switch (loongson_sysconf.nr_nodes) { + case 4: + loongson_fdt_blob = __dtb_ls3a2000_780e_4way_begin; + break; + case 2: + loongson_fdt_blob = __dtb_ls3a2000_780e_2way_begin; + break; + case 1: + default: + loongson_fdt_blob = __dtb_ls3a2000_780e_1way_begin; + break; + } + break; + case PRID_REV_LOONGSON3A_R3_0: + case PRID_REV_LOONGSON3A_R3_1: + switch (loongson_sysconf.nr_nodes) { + case 4: + loongson_fdt_blob = __dtb_ls3a3000_780e_4way_begin; + break; + case 2: + loongson_fdt_blob = __dtb_ls3a3000_780e_2way_begin; + break; + case 1: + default: + loongson_fdt_blob = __dtb_ls3a3000_780e_1way_begin; + break; + } + break; + case PRID_REV_LOONGSON3B_R1: + case PRID_REV_LOONGSON3B_R2: + switch (loongson_sysconf.nr_nodes) { + case 4: + loongson_fdt_blob = __dtb_ls3b_780e_2way_begin; + break; + case 2: + default: + loongson_fdt_blob = __dtb_ls3b_780e_1way_begin; + break; + } + break; + default: + break; + } + } + + if (!loongson_fdt_blob) + pr_err("Failed to determine built-in Loongson64 dtb\n"); + loongson_sysconf.pci_mem_start_addr = eirq_source->pci_mem_start_addr; loongson_sysconf.pci_mem_end_addr = eirq_source->pci_mem_end_addr; loongson_sysconf.pci_io_base = eirq_source->pci_io_start_addr; diff --git a/arch/mips/loongson64/setup.c b/arch/mips/loongson64/setup.c index 24432adc8350..3b850b3128ea 100644 --- a/arch/mips/loongson64/setup.c +++ b/arch/mips/loongson64/setup.c @@ -7,9 +7,15 @@ #include #include #include +#include +#include + +#include #include +void *loongson_fdt_blob; + static void wbflush_loongson(void) { asm(".set\tpush\n\t" @@ -81,6 +87,8 @@ void __init prom_free_prom_memory(void) void __init plat_mem_setup(void) { + if (loongson_fdt_blob) + __dt_setup_arch(loongson_fdt_blob); } void __init plat_time_init(void) @@ -90,3 +98,10 @@ void __init plat_time_init(void) #endif } +void __init device_tree_init(void) +{ + if (!initial_boot_params) + return; + + unflatten_and_copy_device_tree(); +} From patchwork Fri Aug 30 04:32:30 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Jiaxun Yang X-Patchwork-Id: 11122937 Return-Path: Received: from mail.kernel.org (pdx-korg-mail-1.web.codeaurora.org [172.30.200.123]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id 3D34E14DE for ; Fri, 30 Aug 2019 04:35:28 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.kernel.org (Postfix) with ESMTP id 1BA2C22CE3 for ; Fri, 30 Aug 2019 04:35:28 +0000 (UTC) Authentication-Results: mail.kernel.org; dkim=pass (1024-bit key) header.d=flygoat.com header.i=@flygoat.com header.b="HzETLpJB" Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1725819AbfH3EfY (ORCPT ); Fri, 30 Aug 2019 00:35:24 -0400 Received: from forward102o.mail.yandex.net ([37.140.190.182]:43897 "EHLO forward102o.mail.yandex.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1726480AbfH3EfY (ORCPT ); Fri, 30 Aug 2019 00:35:24 -0400 Received: from mxback4g.mail.yandex.net (mxback4g.mail.yandex.net [IPv6:2a02:6b8:0:1472:2741:0:8b7:165]) by forward102o.mail.yandex.net (Yandex) with ESMTP id 168BB6681213; Fri, 30 Aug 2019 07:35:20 +0300 (MSK) Received: from smtp1p.mail.yandex.net (smtp1p.mail.yandex.net [2a02:6b8:0:1472:2741:0:8b6:6]) by mxback4g.mail.yandex.net (nwsmtp/Yandex) with ESMTP id WKrtwAmmS7-ZJi4Ix3V; Fri, 30 Aug 2019 07:35:20 +0300 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=flygoat.com; s=mail; t=1567139720; bh=56yIpBaPTcDpv+2CSHxhnG2/tslm4Nn5nP6/+R6e3HA=; h=In-Reply-To:Subject:To:From:Cc:References:Date:Message-Id; b=HzETLpJBlOHA5npFmzCnlY0iLOyLFv41EjIztmbuupLVIKYv2dNOy1FfjSm11aqDO 68q0ysN4z1LE9ZJpGgeXlMgJWhM2+QSSRBEqro+WdaN81E6uWQ/zMbM4jTwLSWOK9y btv2ZzeIKCbeZE5HbZdVDpl15pBxYFy9Cys4e4EQ= Authentication-Results: mxback4g.mail.yandex.net; dkim=pass header.i=@flygoat.com Received: by smtp1p.mail.yandex.net (nwsmtp/Yandex) with ESMTPSA id vFuwVxmDwr-ZADGa7Ue; Fri, 30 Aug 2019 07:35:17 +0300 (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits)) (Client certificate not present) From: Jiaxun Yang To: linux-mips@vger.kernel.org Cc: chenhc@lemote.com, paul.burton@mips.com, tglx@linutronix.de, jason@lakedaemon.net, maz@kernel.org, linux-kernel@vger.kernel.org, robh+dt@kernel.org, mark.rutland@arm.co, devicetree@vger.kernel.org, Jiaxun Yang Subject: [PATCH v1 16/18] MIPS: Loongson: Regenerate defconfigs Date: Fri, 30 Aug 2019 12:32:30 +0800 Message-Id: <20190830043232.20191-11-jiaxun.yang@flygoat.com> X-Mailer: git-send-email 2.22.0 In-Reply-To: <20190830043232.20191-1-jiaxun.yang@flygoat.com> References: <20190830043232.20191-1-jiaxun.yang@flygoat.com> MIME-Version: 1.0 Sender: linux-mips-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-mips@vger.kernel.org We've touched kconfig a lot in previous patches. Signed-off-by: Jiaxun Yang --- arch/mips/configs/fuloong2e_defconfig | 8 +++----- arch/mips/configs/lemote2f_defconfig | 8 ++------ arch/mips/configs/loongson3_defconfig | 12 ++++-------- 3 files changed, 9 insertions(+), 19 deletions(-) diff --git a/arch/mips/configs/fuloong2e_defconfig b/arch/mips/configs/fuloong2e_defconfig index 7a7af706e898..ae8a904ef812 100644 --- a/arch/mips/configs/fuloong2e_defconfig +++ b/arch/mips/configs/fuloong2e_defconfig @@ -15,8 +15,7 @@ CONFIG_EXPERT=y # CONFIG_COMPAT_BRK is not set CONFIG_SLAB=y CONFIG_PROFILING=y -CONFIG_MACH_LOONGSON64=y -CONFIG_PCI=y +CONFIG_MACH_LOONGSON2EF=y CONFIG_MIPS32_O32=y CONFIG_MIPS32_N32=y # CONFIG_SUSPEND is not set @@ -36,8 +35,6 @@ CONFIG_IP_MULTICAST=y CONFIG_IP_PNP=y CONFIG_IP_PNP_BOOTP=y CONFIG_NET_IPIP=m -# CONFIG_INET_XFRM_MODE_TRANSPORT is not set -# CONFIG_INET_XFRM_MODE_TUNNEL is not set # CONFIG_INET_DIAG is not set # CONFIG_IPV6 is not set CONFIG_NETFILTER=y @@ -83,6 +80,7 @@ CONFIG_IP_NF_ARPFILTER=m CONFIG_IP_NF_ARP_MANGLE=m CONFIG_PHONET=m CONFIG_NET_9P=m +CONFIG_PCI=y CONFIG_FW_LOADER=m CONFIG_MTD=m CONFIG_MTD_BLOCK=m @@ -142,6 +140,7 @@ CONFIG_HW_RANDOM=y CONFIG_I2C=m CONFIG_I2C_CHARDEV=m CONFIG_I2C_VIAPRO=m +CONFIG_GPIOLIB=y # CONFIG_HWMON is not set CONFIG_FB=y CONFIG_FB_RADEON=y @@ -217,7 +216,6 @@ CONFIG_NLS_CODEPAGE_936=y CONFIG_NLS_ISO8859_1=y CONFIG_NLS_UTF8=y CONFIG_CRYPTO_AUTHENC=m -CONFIG_CRYPTO_GCM=m CONFIG_CRYPTO_CTS=m CONFIG_CRYPTO_PCBC=m CONFIG_CRYPTO_XTS=m diff --git a/arch/mips/configs/lemote2f_defconfig b/arch/mips/configs/lemote2f_defconfig index d44f1469cf64..0cbe1240314d 100644 --- a/arch/mips/configs/lemote2f_defconfig +++ b/arch/mips/configs/lemote2f_defconfig @@ -12,11 +12,10 @@ CONFIG_LOG_BUF_SHIFT=15 CONFIG_BLK_DEV_INITRD=y CONFIG_EXPERT=y CONFIG_PROFILING=y -CONFIG_MACH_LOONGSON64=y +CONFIG_MACH_LOONGSON2EF=y CONFIG_LEMOTE_MACH2F=y CONFIG_KEXEC=y # CONFIG_SECCOMP is not set -CONFIG_PCI=y CONFIG_MIPS32_O32=y CONFIG_MIPS32_N32=y CONFIG_HIBERNATION=y @@ -26,7 +25,6 @@ CONFIG_MODULES=y CONFIG_MODULE_UNLOAD=y CONFIG_MODVERSIONS=y CONFIG_BLK_DEV_INTEGRITY=y -CONFIG_IOSCHED_DEADLINE=m CONFIG_BINFMT_MISC=m CONFIG_NET=y CONFIG_PACKET=y @@ -44,9 +42,6 @@ CONFIG_IP_MROUTE=y CONFIG_IP_PIMSM_V1=y CONFIG_IP_PIMSM_V2=y CONFIG_SYN_COOKIES=y -CONFIG_INET_XFRM_MODE_TRANSPORT=m -CONFIG_INET_XFRM_MODE_TUNNEL=m -CONFIG_INET_XFRM_MODE_BEET=m CONFIG_TCP_CONG_ADVANCED=y CONFIG_TCP_CONG_BIC=y CONFIG_DEFAULT_BIC=y @@ -77,6 +72,7 @@ CONFIG_MAC80211=m CONFIG_MAC80211_LEDS=y CONFIG_RFKILL=m CONFIG_RFKILL_INPUT=y +CONFIG_PCI=y CONFIG_BLK_DEV_LOOP=y CONFIG_BLK_DEV_CRYPTOLOOP=m CONFIG_BLK_DEV_RAM=y diff --git a/arch/mips/configs/loongson3_defconfig b/arch/mips/configs/loongson3_defconfig index 90ee0084d786..66fb44b4d845 100644 --- a/arch/mips/configs/loongson3_defconfig +++ b/arch/mips/configs/loongson3_defconfig @@ -24,15 +24,9 @@ CONFIG_BLK_DEV_INITRD=y CONFIG_SYSCTL_SYSCALL=y CONFIG_EMBEDDED=y CONFIG_MACH_LOONGSON64=y -CONFIG_LOONGSON_MACH3X=y CONFIG_SMP=y CONFIG_HZ_256=y CONFIG_KEXEC=y -CONFIG_PCIEPORTBUS=y -CONFIG_HOTPLUG_PCI_PCIE=y -# CONFIG_PCIEAER is not set -CONFIG_PCIEASPM_PERFORMANCE=y -CONFIG_HOTPLUG_PCI=y CONFIG_MIPS32_O32=y CONFIG_MIPS32_N32=y CONFIG_MODULES=y @@ -41,8 +35,6 @@ CONFIG_MODULE_UNLOAD=y CONFIG_MODULE_FORCE_UNLOAD=y CONFIG_MODVERSIONS=y CONFIG_PARTITION_ADVANCED=y -CONFIG_IOSCHED_DEADLINE=m -CONFIG_CFQ_GROUP_IOSCHED=y CONFIG_BINFMT_MISC=m CONFIG_KSM=y CONFIG_NET=y @@ -97,6 +89,10 @@ CONFIG_CFG80211_WEXT=y CONFIG_MAC80211=m CONFIG_RFKILL=m CONFIG_RFKILL_INPUT=y +CONFIG_PCIEPORTBUS=y +CONFIG_HOTPLUG_PCI_PCIE=y +CONFIG_PCIEASPM_PERFORMANCE=y +CONFIG_HOTPLUG_PCI=y CONFIG_DEVTMPFS=y CONFIG_DEVTMPFS_MOUNT=y CONFIG_MTD=m From patchwork Fri Aug 30 04:32:31 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Jiaxun Yang X-Patchwork-Id: 11122939 Return-Path: Received: from mail.kernel.org (pdx-korg-mail-1.web.codeaurora.org [172.30.200.123]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id 38E0814DE for ; Fri, 30 Aug 2019 04:35:33 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.kernel.org (Postfix) with ESMTP id 0CE8F22CE9 for ; Fri, 30 Aug 2019 04:35:33 +0000 (UTC) Authentication-Results: mail.kernel.org; dkim=pass (1024-bit key) header.d=flygoat.com header.i=@flygoat.com header.b="H9GaTT4i" Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1726486AbfH3Efc (ORCPT ); Fri, 30 Aug 2019 00:35:32 -0400 Received: from forward102j.mail.yandex.net ([5.45.198.243]:44023 "EHLO forward102j.mail.yandex.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1726480AbfH3Efc (ORCPT ); Fri, 30 Aug 2019 00:35:32 -0400 Received: from mxback21j.mail.yandex.net (mxback21j.mail.yandex.net [IPv6:2a02:6b8:0:1619::221]) by forward102j.mail.yandex.net (Yandex) with ESMTP id 682F5F2054B; Fri, 30 Aug 2019 07:35:30 +0300 (MSK) Received: from smtp1p.mail.yandex.net (smtp1p.mail.yandex.net [2a02:6b8:0:1472:2741:0:8b6:6]) by mxback21j.mail.yandex.net (nwsmtp/Yandex) with ESMTP id zPP7Q29Vb1-ZUcKoO5S; Fri, 30 Aug 2019 07:35:30 +0300 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=flygoat.com; s=mail; t=1567139730; bh=AeLVvDOQmHy6G47IkTrmzDnQl83QFttkNmeUEWRztaA=; h=In-Reply-To:Subject:To:From:Cc:References:Date:Message-Id; b=H9GaTT4i9BlBWXLv+KSd8HaeiRpOgs/7aAK5ZKBJ+gYNpu2Vm/MWx8VzBPrsUdzAm TP9OFU0Wf5nszTkBssJnUbCaS/UMEPHoHv6y/FSidDvQLFTsrMRUXcZ7of2DSTIamI /hj1X2a2T3DWcAr0GAu3OQTmfcZDh9OxwaOnk1R4= Authentication-Results: mxback21j.mail.yandex.net; dkim=pass header.i=@flygoat.com Received: by smtp1p.mail.yandex.net (nwsmtp/Yandex) with ESMTPSA id vFuwVxmDwr-ZKDG1LNL; Fri, 30 Aug 2019 07:35:28 +0300 (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits)) (Client certificate not present) From: Jiaxun Yang To: linux-mips@vger.kernel.org Cc: chenhc@lemote.com, paul.burton@mips.com, tglx@linutronix.de, jason@lakedaemon.net, maz@kernel.org, linux-kernel@vger.kernel.org, robh+dt@kernel.org, mark.rutland@arm.co, devicetree@vger.kernel.org, Jiaxun Yang Subject: [PATCH v1 17/18] MAINTAINERS: Add new pathes to LOONGSON64 ARCHITECTURE Date: Fri, 30 Aug 2019 12:32:31 +0800 Message-Id: <20190830043232.20191-12-jiaxun.yang@flygoat.com> X-Mailer: git-send-email 2.22.0 In-Reply-To: <20190830043232.20191-1-jiaxun.yang@flygoat.com> References: <20190830043232.20191-1-jiaxun.yang@flygoat.com> MIME-Version: 1.0 Sender: linux-mips-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-mips@vger.kernel.org Place newly submited irqchip drivers and devicetree support under MIPS/LOONGSON64 ARCHITECTURE. Signed-off-by: Jiaxun Yang --- MAINTAINERS | 3 +++ 1 file changed, 3 insertions(+) diff --git a/MAINTAINERS b/MAINTAINERS index d5d4fed632e6..242970af939c 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -10760,9 +10760,12 @@ MIPS/LOONGSON64 ARCHITECTURE M: Huacai Chen L: linux-mips@vger.kernel.org S: Maintained +F: arch/mips/boot/dts/loongson/ F: arch/mips/loongson64/ F: arch/mips/include/asm/mach-loongson64/ F: drivers/platform/mips/cpu_hwmon.c +F: drivers/irqchip/irq-ls3-* +F: Documentation/devicetree/bindings/interrupt-controller/loongson,ls3-* F: drivers/*/*loongson3* F: drivers/*/*/*loongson3* From patchwork Fri Aug 30 04:32:32 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Jiaxun Yang X-Patchwork-Id: 11122941 Return-Path: Received: from mail.kernel.org (pdx-korg-mail-1.web.codeaurora.org [172.30.200.123]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id E13AE112C for ; Fri, 30 Aug 2019 04:35:41 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.kernel.org (Postfix) with ESMTP id BF48922CE3 for ; Fri, 30 Aug 2019 04:35:41 +0000 (UTC) Authentication-Results: mail.kernel.org; dkim=pass (1024-bit key) header.d=flygoat.com header.i=@flygoat.com header.b="Q0hLb42e" Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1726480AbfH3Efl (ORCPT ); Fri, 30 Aug 2019 00:35:41 -0400 Received: from forward103j.mail.yandex.net ([5.45.198.246]:42402 "EHLO forward103j.mail.yandex.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1725648AbfH3Efl (ORCPT ); Fri, 30 Aug 2019 00:35:41 -0400 Received: from mxback30j.mail.yandex.net (mxback30j.mail.yandex.net [IPv6:2a02:6b8:0:1619::230]) by forward103j.mail.yandex.net (Yandex) with ESMTP id E5D5D6741178; Fri, 30 Aug 2019 07:35:38 +0300 (MSK) Received: from smtp1p.mail.yandex.net (smtp1p.mail.yandex.net [2a02:6b8:0:1472:2741:0:8b6:6]) by mxback30j.mail.yandex.net (nwsmtp/Yandex) with ESMTP id 32U7f9lBw7-Zcri6gdt; Fri, 30 Aug 2019 07:35:38 +0300 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=flygoat.com; s=mail; t=1567139738; bh=vrMkaB9xn2ZE/mMPhncAwnoH2UZZVYCo5x0BeJ38aIs=; h=In-Reply-To:Subject:To:From:Cc:References:Date:Message-Id; b=Q0hLb42eEIAgd3tuXr+Ysh9mGKETNBAamYbgahhoX534I1WvSgPi/GbolwJaMyjLJ y934WyjHDo7olFddOMSZraquQ9GMTx/GmDaKFp89Y0P0ZfLi+H/GzLPbItXfvez1iY bcW9zXpyaN8n2Nn6b5QS74PbqEcDP9KlPuOQVWMQ= Authentication-Results: mxback30j.mail.yandex.net; dkim=pass header.i=@flygoat.com Received: by smtp1p.mail.yandex.net (nwsmtp/Yandex) with ESMTPSA id vFuwVxmDwr-ZUDG4Ds5; Fri, 30 Aug 2019 07:35:36 +0300 (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits)) (Client certificate not present) From: Jiaxun Yang To: linux-mips@vger.kernel.org Cc: chenhc@lemote.com, paul.burton@mips.com, tglx@linutronix.de, jason@lakedaemon.net, maz@kernel.org, linux-kernel@vger.kernel.org, robh+dt@kernel.org, mark.rutland@arm.co, devicetree@vger.kernel.org, Jiaxun Yang Subject: [PATCH v1 18/18] MAINTAINERS: Add myself as maintainer of LOONGSON64 Date: Fri, 30 Aug 2019 12:32:32 +0800 Message-Id: <20190830043232.20191-13-jiaxun.yang@flygoat.com> X-Mailer: git-send-email 2.22.0 In-Reply-To: <20190830043232.20191-1-jiaxun.yang@flygoat.com> References: <20190830043232.20191-1-jiaxun.yang@flygoat.com> MIME-Version: 1.0 Sender: linux-mips-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-mips@vger.kernel.org I'm going to help with LOONGSON64 maintainance as well. Signed-off-by: Jiaxun Yang --- MAINTAINERS | 1 + 1 file changed, 1 insertion(+) diff --git a/MAINTAINERS b/MAINTAINERS index 242970af939c..e14edf51ee15 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -10758,6 +10758,7 @@ F: drivers/*/*/*loongson2* MIPS/LOONGSON64 ARCHITECTURE M: Huacai Chen +M: Jiaxun Yang L: linux-mips@vger.kernel.org S: Maintained F: arch/mips/boot/dts/loongson/