From patchwork Fri Aug 30 13:45:08 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Geert Uytterhoeven X-Patchwork-Id: 11124005 X-Patchwork-Delegate: geert@linux-m68k.org Return-Path: Received: from mail.kernel.org (pdx-korg-mail-1.web.codeaurora.org [172.30.200.123]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id 4A51814DE for ; Fri, 30 Aug 2019 13:50:24 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.kernel.org (Postfix) with ESMTP id 3142323405 for ; Fri, 30 Aug 2019 13:50:24 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1727884AbfH3NuX (ORCPT ); Fri, 30 Aug 2019 09:50:23 -0400 Received: from xavier.telenet-ops.be ([195.130.132.52]:55532 "EHLO xavier.telenet-ops.be" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1727780AbfH3NuV (ORCPT ); Fri, 30 Aug 2019 09:50:21 -0400 Received: from ramsan ([84.194.98.4]) by xavier.telenet-ops.be with bizsmtp id vRqK2000305gfCL01RqKwV; Fri, 30 Aug 2019 15:50:19 +0200 Received: from rox.of.borg ([192.168.97.57]) by ramsan with esmtp (Exim 4.90_1) (envelope-from ) id 1i3hIA-0003KX-Vj; Fri, 30 Aug 2019 15:50:18 +0200 Received: from geert by rox.of.borg with local (Exim 4.90_1) (envelope-from ) id 1i3hDK-00037W-OY; Fri, 30 Aug 2019 15:45:18 +0200 From: Geert Uytterhoeven To: Michael Turquette , Stephen Boyd Cc: linux-clk@vger.kernel.org, linux-renesas-soc@vger.kernel.org, Geert Uytterhoeven Subject: [PATCH v2 1/8] clk: renesas: rcar-gen2: Improve arithmetic divisions Date: Fri, 30 Aug 2019 15:45:08 +0200 Message-Id: <20190830134515.11925-2-geert+renesas@glider.be> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20190830134515.11925-1-geert+renesas@glider.be> References: <20190830134515.11925-1-geert+renesas@glider.be> Sender: linux-renesas-soc-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-renesas-soc@vger.kernel.org - Use div64_ul() instead of div_u64() if the divisor is unsigned long, to avoid truncation to 32-bit on 64-bit platforms, - Prefer ULL constant suffixes over casts to u64, - Prioritize multiplication over division, to increase accuracy. Signed-off-by: Geert Uytterhoeven Reviewed-by: Niklas Söderlund --- v2: - New. --- drivers/clk/renesas/rcar-gen2-cpg.c | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) diff --git a/drivers/clk/renesas/rcar-gen2-cpg.c b/drivers/clk/renesas/rcar-gen2-cpg.c index f596a2dafcf4d8d1..c378505830f0bacc 100644 --- a/drivers/clk/renesas/rcar-gen2-cpg.c +++ b/drivers/clk/renesas/rcar-gen2-cpg.c @@ -72,10 +72,10 @@ static long cpg_z_clk_round_rate(struct clk_hw *hw, unsigned long rate, if (!prate) prate = 1; - mult = div_u64((u64)rate * 32, prate); + mult = div64_ul(rate * 32ULL, prate); mult = clamp(mult, 1U, 32U); - return *parent_rate / 32 * mult; + return div_u64((u64)*parent_rate * mult, 32); } static int cpg_z_clk_set_rate(struct clk_hw *hw, unsigned long rate, @@ -86,7 +86,7 @@ static int cpg_z_clk_set_rate(struct clk_hw *hw, unsigned long rate, u32 val, kick; unsigned int i; - mult = div_u64((u64)rate * 32, parent_rate); + mult = div64_ul(rate * 32ULL, parent_rate); mult = clamp(mult, 1U, 32U); if (readl(zclk->kick_reg) & CPG_FRQCRB_KICK) From patchwork Fri Aug 30 13:45:09 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Geert Uytterhoeven X-Patchwork-Id: 11124003 X-Patchwork-Delegate: geert@linux-m68k.org Return-Path: Received: from mail.kernel.org (pdx-korg-mail-1.web.codeaurora.org [172.30.200.123]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id 2860318EC for ; Fri, 30 Aug 2019 13:50:24 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.kernel.org (Postfix) with ESMTP id 0FA6623407 for ; Fri, 30 Aug 2019 13:50:24 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1727876AbfH3NuV (ORCPT ); Fri, 30 Aug 2019 09:50:21 -0400 Received: from xavier.telenet-ops.be ([195.130.132.52]:55540 "EHLO xavier.telenet-ops.be" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1727735AbfH3NuU (ORCPT ); Fri, 30 Aug 2019 09:50:20 -0400 Received: from ramsan ([84.194.98.4]) by xavier.telenet-ops.be with bizsmtp id vRqK2000205gfCL01RqKwU; Fri, 30 Aug 2019 15:50:19 +0200 Received: from rox.of.borg ([192.168.97.57]) by ramsan with esmtp (Exim 4.90_1) (envelope-from ) id 1i3hIA-0003KX-Uo; Fri, 30 Aug 2019 15:50:18 +0200 Received: from geert by rox.of.borg with local (Exim 4.90_1) (envelope-from ) id 1i3hDK-00037Y-PL; Fri, 30 Aug 2019 15:45:18 +0200 From: Geert Uytterhoeven To: Michael Turquette , Stephen Boyd Cc: linux-clk@vger.kernel.org, linux-renesas-soc@vger.kernel.org, Geert Uytterhoeven Subject: [PATCH v2 2/8] clk: renesas: rcar-gen3: Improve arithmetic divisions Date: Fri, 30 Aug 2019 15:45:09 +0200 Message-Id: <20190830134515.11925-3-geert+renesas@glider.be> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20190830134515.11925-1-geert+renesas@glider.be> References: <20190830134515.11925-1-geert+renesas@glider.be> Sender: linux-renesas-soc-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-renesas-soc@vger.kernel.org - Use div64_ul() instead of div_u64() if the divisor is unsigned long, to avoid truncation to 32-bit on 64-bit platforms, - Use div_u64() for 64-by-32 divisions. Signed-off-by: Geert Uytterhoeven Reviewed-by: Niklas Söderlund --- v2: - New. --- drivers/clk/renesas/rcar-gen3-cpg.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/drivers/clk/renesas/rcar-gen3-cpg.c b/drivers/clk/renesas/rcar-gen3-cpg.c index 043ab6ed9d550732..3480284a08308134 100644 --- a/drivers/clk/renesas/rcar-gen3-cpg.c +++ b/drivers/clk/renesas/rcar-gen3-cpg.c @@ -122,10 +122,10 @@ static long cpg_z_clk_round_rate(struct clk_hw *hw, unsigned long rate, unsigned int mult; prate = *parent_rate / zclk->fixed_div; - mult = div_u64(rate * 32ULL, prate); + mult = div64_ul(rate * 32ULL, prate); mult = clamp(mult, 1U, 32U); - return (u64)prate * mult / 32; + return div_u64((u64)prate * mult, 32); } static int cpg_z_clk_set_rate(struct clk_hw *hw, unsigned long rate, From patchwork Fri Aug 30 13:45:10 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Geert Uytterhoeven X-Patchwork-Id: 11123979 X-Patchwork-Delegate: geert@linux-m68k.org Return-Path: Received: from mail.kernel.org (pdx-korg-mail-1.web.codeaurora.org [172.30.200.123]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id 2DC3B18EC for ; Fri, 30 Aug 2019 13:50:22 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.kernel.org (Postfix) with ESMTP id 0CEDF2342E for ; Fri, 30 Aug 2019 13:50:22 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1727781AbfH3NuV (ORCPT ); Fri, 30 Aug 2019 09:50:21 -0400 Received: from xavier.telenet-ops.be ([195.130.132.52]:55518 "EHLO xavier.telenet-ops.be" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1727820AbfH3NuV (ORCPT ); Fri, 30 Aug 2019 09:50:21 -0400 Received: from ramsan ([84.194.98.4]) by xavier.telenet-ops.be with bizsmtp id vRqJ2000m05gfCL01RqJwR; Fri, 30 Aug 2019 15:50:19 +0200 Received: from rox.of.borg ([192.168.97.57]) by ramsan with esmtp (Exim 4.90_1) (envelope-from ) id 1i3hIA-0003KX-Nf; Fri, 30 Aug 2019 15:50:18 +0200 Received: from geert by rox.of.borg with local (Exim 4.90_1) (envelope-from ) id 1i3hDK-00037c-QB; Fri, 30 Aug 2019 15:45:18 +0200 From: Geert Uytterhoeven To: Michael Turquette , Stephen Boyd Cc: linux-clk@vger.kernel.org, linux-renesas-soc@vger.kernel.org, Geert Uytterhoeven Subject: [PATCH v2 3/8] clk: renesas: rcar-gen3: Avoid double table iteration in SD .set_rate() Date: Fri, 30 Aug 2019 15:45:10 +0200 Message-Id: <20190830134515.11925-4-geert+renesas@glider.be> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20190830134515.11925-1-geert+renesas@glider.be> References: <20190830134515.11925-1-geert+renesas@glider.be> Sender: linux-renesas-soc-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-renesas-soc@vger.kernel.org The .set_rate() callback for the SD clocks is always called with a valid clock rate, returned by .round_rate(). Hence there is no need to iterate through the divider table twice: once to repeat the work done by .round_rate(), and a second time to find the corresponding divider entry. Just iterate once, looking for the divider that matches the passed clock rate. Signed-off-by: Geert Uytterhoeven Reviewed-by: Niklas Söderlund --- v2: - No changes. --- drivers/clk/renesas/rcar-gen3-cpg.c | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) diff --git a/drivers/clk/renesas/rcar-gen3-cpg.c b/drivers/clk/renesas/rcar-gen3-cpg.c index 3480284a08308134..9f457411984b1ca4 100644 --- a/drivers/clk/renesas/rcar-gen3-cpg.c +++ b/drivers/clk/renesas/rcar-gen3-cpg.c @@ -339,14 +339,14 @@ static long cpg_sd_clock_round_rate(struct clk_hw *hw, unsigned long rate, } static int cpg_sd_clock_set_rate(struct clk_hw *hw, unsigned long rate, - unsigned long parent_rate) + unsigned long parent_rate) { struct sd_clock *clock = to_sd_clock(hw); - unsigned int div = cpg_sd_clock_calc_div(clock, rate, parent_rate); unsigned int i; for (i = 0; i < clock->div_num; i++) - if (div == clock->div_table[i].div) + if (rate == DIV_ROUND_CLOSEST(parent_rate, + clock->div_table[i].div)) break; if (i >= clock->div_num) From patchwork Fri Aug 30 13:45:11 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Geert Uytterhoeven X-Patchwork-Id: 11123995 X-Patchwork-Delegate: geert@linux-m68k.org Return-Path: Received: from mail.kernel.org (pdx-korg-mail-1.web.codeaurora.org [172.30.200.123]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id 778E919A1 for ; Fri, 30 Aug 2019 13:50:23 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.kernel.org (Postfix) with ESMTP id 56B7623405 for ; Fri, 30 Aug 2019 13:50:23 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1727958AbfH3NuW (ORCPT ); Fri, 30 Aug 2019 09:50:22 -0400 Received: from baptiste.telenet-ops.be ([195.130.132.51]:52314 "EHLO baptiste.telenet-ops.be" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1727959AbfH3NuW (ORCPT ); Fri, 30 Aug 2019 09:50:22 -0400 Received: from ramsan ([84.194.98.4]) by baptiste.telenet-ops.be with bizsmtp id vRqJ2000u05gfCL01RqKdp; Fri, 30 Aug 2019 15:50:19 +0200 Received: from rox.of.borg ([192.168.97.57]) by ramsan with esmtp (Exim 4.90_1) (envelope-from ) id 1i3hIA-0003KX-Ts; Fri, 30 Aug 2019 15:50:18 +0200 Received: from geert by rox.of.borg with local (Exim 4.90_1) (envelope-from ) id 1i3hDK-00037f-Qz; Fri, 30 Aug 2019 15:45:18 +0200 From: Geert Uytterhoeven To: Michael Turquette , Stephen Boyd Cc: linux-clk@vger.kernel.org, linux-renesas-soc@vger.kernel.org, Geert Uytterhoeven Subject: [PATCH v2 4/8] clk: renesas: rcar-gen3: Absorb cpg_sd_clock_calc_div() Date: Fri, 30 Aug 2019 15:45:11 +0200 Message-Id: <20190830134515.11925-5-geert+renesas@glider.be> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20190830134515.11925-1-geert+renesas@glider.be> References: <20190830134515.11925-1-geert+renesas@glider.be> Sender: linux-renesas-soc-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-renesas-soc@vger.kernel.org cpg_sd_clock_round_rate() is the sole caller of cpg_sd_clock_calc_div(), hence absorb the latter into the former. Signed-off-by: Geert Uytterhoeven Reviewed-by: Niklas Söderlund --- v2: - Split off from "clk: renesas: rcar-gen3: Switch SD clocks to .determine_rate()". --- drivers/clk/renesas/rcar-gen3-cpg.c | 19 +++++-------------- 1 file changed, 5 insertions(+), 14 deletions(-) diff --git a/drivers/clk/renesas/rcar-gen3-cpg.c b/drivers/clk/renesas/rcar-gen3-cpg.c index 9f457411984b1ca4..12ea5c9a671de788 100644 --- a/drivers/clk/renesas/rcar-gen3-cpg.c +++ b/drivers/clk/renesas/rcar-gen3-cpg.c @@ -309,15 +309,15 @@ static unsigned long cpg_sd_clock_recalc_rate(struct clk_hw *hw, clock->div_table[clock->cur_div_idx].div); } -static unsigned int cpg_sd_clock_calc_div(struct sd_clock *clock, - unsigned long rate, - unsigned long parent_rate) +static long cpg_sd_clock_round_rate(struct clk_hw *hw, unsigned long rate, + unsigned long *parent_rate) { unsigned long calc_rate, diff, diff_min = ULONG_MAX; + struct sd_clock *clock = to_sd_clock(hw); unsigned int i, best_div = 0; for (i = 0; i < clock->div_num; i++) { - calc_rate = DIV_ROUND_CLOSEST(parent_rate, + calc_rate = DIV_ROUND_CLOSEST(*parent_rate, clock->div_table[i].div); diff = calc_rate > rate ? calc_rate - rate : rate - calc_rate; if (diff < diff_min) { @@ -326,16 +326,7 @@ static unsigned int cpg_sd_clock_calc_div(struct sd_clock *clock, } } - return best_div; -} - -static long cpg_sd_clock_round_rate(struct clk_hw *hw, unsigned long rate, - unsigned long *parent_rate) -{ - struct sd_clock *clock = to_sd_clock(hw); - unsigned int div = cpg_sd_clock_calc_div(clock, rate, *parent_rate); - - return DIV_ROUND_CLOSEST(*parent_rate, div); + return DIV_ROUND_CLOSEST(*parent_rate, best_div); } static int cpg_sd_clock_set_rate(struct clk_hw *hw, unsigned long rate, From patchwork Fri Aug 30 13:45:12 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Geert Uytterhoeven X-Patchwork-Id: 11123975 X-Patchwork-Delegate: geert@linux-m68k.org Return-Path: Received: from mail.kernel.org (pdx-korg-mail-1.web.codeaurora.org [172.30.200.123]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id CC09514DE for ; Fri, 30 Aug 2019 13:50:21 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.kernel.org (Postfix) with ESMTP id B4E882342E for ; Fri, 30 Aug 2019 13:50:21 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1727961AbfH3NuV (ORCPT ); Fri, 30 Aug 2019 09:50:21 -0400 Received: from baptiste.telenet-ops.be ([195.130.132.51]:52310 "EHLO baptiste.telenet-ops.be" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1727936AbfH3NuV (ORCPT ); Fri, 30 Aug 2019 09:50:21 -0400 Received: from ramsan ([84.194.98.4]) by baptiste.telenet-ops.be with bizsmtp id vRqJ2000r05gfCL01RqJdm; Fri, 30 Aug 2019 15:50:19 +0200 Received: from rox.of.borg ([192.168.97.57]) by ramsan with esmtp (Exim 4.90_1) (envelope-from ) id 1i3hIA-0003KX-Sw; Fri, 30 Aug 2019 15:50:18 +0200 Received: from geert by rox.of.borg with local (Exim 4.90_1) (envelope-from ) id 1i3hDK-00037i-Sf; Fri, 30 Aug 2019 15:45:18 +0200 From: Geert Uytterhoeven To: Michael Turquette , Stephen Boyd Cc: linux-clk@vger.kernel.org, linux-renesas-soc@vger.kernel.org, Geert Uytterhoeven Subject: [PATCH v2 5/8] clk: renesas: rcar-gen3: Loop to find best rate in cpg_sd_clock_round_rate() Date: Fri, 30 Aug 2019 15:45:12 +0200 Message-Id: <20190830134515.11925-6-geert+renesas@glider.be> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20190830134515.11925-1-geert+renesas@glider.be> References: <20190830134515.11925-1-geert+renesas@glider.be> Sender: linux-renesas-soc-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-renesas-soc@vger.kernel.org cpg_sd_clock_round_rate() really needs the best rate, not the best divider. Hence change the iteration to find the former, and get rid of the final division. Add an out-of-range rate check while at it. Signed-off-by: Geert Uytterhoeven Reviewed-by: Niklas Söderlund --- v2: - Split off from "clk: renesas: rcar-gen3: Switch SD clocks to .determine_rate()". --- drivers/clk/renesas/rcar-gen3-cpg.c | 12 ++++++++---- 1 file changed, 8 insertions(+), 4 deletions(-) diff --git a/drivers/clk/renesas/rcar-gen3-cpg.c b/drivers/clk/renesas/rcar-gen3-cpg.c index 12ea5c9a671de788..a612045cba7d97b7 100644 --- a/drivers/clk/renesas/rcar-gen3-cpg.c +++ b/drivers/clk/renesas/rcar-gen3-cpg.c @@ -312,21 +312,25 @@ static unsigned long cpg_sd_clock_recalc_rate(struct clk_hw *hw, static long cpg_sd_clock_round_rate(struct clk_hw *hw, unsigned long rate, unsigned long *parent_rate) { - unsigned long calc_rate, diff, diff_min = ULONG_MAX; + unsigned long best_rate = ULONG_MAX, diff_min = ULONG_MAX; struct sd_clock *clock = to_sd_clock(hw); - unsigned int i, best_div = 0; + unsigned long calc_rate, diff; + unsigned int i; for (i = 0; i < clock->div_num; i++) { calc_rate = DIV_ROUND_CLOSEST(*parent_rate, clock->div_table[i].div); diff = calc_rate > rate ? calc_rate - rate : rate - calc_rate; if (diff < diff_min) { - best_div = clock->div_table[i].div; + best_rate = calc_rate; diff_min = diff; } } - return DIV_ROUND_CLOSEST(*parent_rate, best_div); + if (best_rate > LONG_MAX) + return -EINVAL; + + return best_rate; } static int cpg_sd_clock_set_rate(struct clk_hw *hw, unsigned long rate, From patchwork Fri Aug 30 13:45:13 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Geert Uytterhoeven X-Patchwork-Id: 11123989 X-Patchwork-Delegate: geert@linux-m68k.org Return-Path: Received: from mail.kernel.org (pdx-korg-mail-1.web.codeaurora.org [172.30.200.123]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id 03AFE18EC for ; Fri, 30 Aug 2019 13:50:23 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.kernel.org (Postfix) with ESMTP id DDA5A2341B for ; Fri, 30 Aug 2019 13:50:22 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1727754AbfH3NuW (ORCPT ); Fri, 30 Aug 2019 09:50:22 -0400 Received: from baptiste.telenet-ops.be ([195.130.132.51]:52320 "EHLO baptiste.telenet-ops.be" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1727922AbfH3NuV (ORCPT ); Fri, 30 Aug 2019 09:50:21 -0400 Received: from ramsan ([84.194.98.4]) by baptiste.telenet-ops.be with bizsmtp id vRqJ2000n05gfCL01RqJdl; Fri, 30 Aug 2019 15:50:19 +0200 Received: from rox.of.borg ([192.168.97.57]) by ramsan with esmtp (Exim 4.90_1) (envelope-from ) id 1i3hIA-0003KX-Rz; Fri, 30 Aug 2019 15:50:18 +0200 Received: from geert by rox.of.borg with local (Exim 4.90_1) (envelope-from ) id 1i3hDK-00037l-Ts; Fri, 30 Aug 2019 15:45:18 +0200 From: Geert Uytterhoeven To: Michael Turquette , Stephen Boyd Cc: linux-clk@vger.kernel.org, linux-renesas-soc@vger.kernel.org, Geert Uytterhoeven Subject: [PATCH v2 6/8] clk: renesas: rcar-gen2: Switch Z clock to .determine_rate() Date: Fri, 30 Aug 2019 15:45:13 +0200 Message-Id: <20190830134515.11925-7-geert+renesas@glider.be> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20190830134515.11925-1-geert+renesas@glider.be> References: <20190830134515.11925-1-geert+renesas@glider.be> Sender: linux-renesas-soc-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-renesas-soc@vger.kernel.org As the .round_rate() callback returns a long clock rate, it cannot return clock rates that do not fit in signed long, but do fit in unsigned long. Hence switch the Z clock on R-Car Gen2 from the old .round_rate() callback to the newer .determine_rate() callback, which does not suffer from this limitation. This includes implementing range checking. Signed-off-by: Geert Uytterhoeven --- v2: - Use div_u64() for division by unsigned long, - Rebased. --- drivers/clk/renesas/rcar-gen2-cpg.c | 23 +++++++++++++---------- 1 file changed, 13 insertions(+), 10 deletions(-) diff --git a/drivers/clk/renesas/rcar-gen2-cpg.c b/drivers/clk/renesas/rcar-gen2-cpg.c index c378505830f0bacc..d4fa3dc3e2a2632f 100644 --- a/drivers/clk/renesas/rcar-gen2-cpg.c +++ b/drivers/clk/renesas/rcar-gen2-cpg.c @@ -63,19 +63,22 @@ static unsigned long cpg_z_clk_recalc_rate(struct clk_hw *hw, return div_u64((u64)parent_rate * mult, 32); } -static long cpg_z_clk_round_rate(struct clk_hw *hw, unsigned long rate, - unsigned long *parent_rate) +static int cpg_z_clk_determine_rate(struct clk_hw *hw, + struct clk_rate_request *req) { - unsigned long prate = *parent_rate; - unsigned int mult; + unsigned long prate = req->best_parent_rate; + unsigned int min_mult, max_mult, mult; - if (!prate) - prate = 1; + min_mult = max(div64_ul(req->min_rate * 32ULL, prate), 1ULL); + max_mult = min(div64_ul(req->max_rate * 32ULL, prate), 32ULL); + if (max_mult < min_mult) + return -EINVAL; - mult = div64_ul(rate * 32ULL, prate); - mult = clamp(mult, 1U, 32U); + mult = div64_ul(req->rate * 32ULL, prate); + mult = clamp(mult, min_mult, max_mult); - return div_u64((u64)*parent_rate * mult, 32); + req->rate = div_u64((u64)prate * mult, 32); + return 0; } static int cpg_z_clk_set_rate(struct clk_hw *hw, unsigned long rate, @@ -126,7 +129,7 @@ static int cpg_z_clk_set_rate(struct clk_hw *hw, unsigned long rate, static const struct clk_ops cpg_z_clk_ops = { .recalc_rate = cpg_z_clk_recalc_rate, - .round_rate = cpg_z_clk_round_rate, + .determine_rate = cpg_z_clk_determine_rate, .set_rate = cpg_z_clk_set_rate, }; From patchwork Fri Aug 30 13:45:14 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Geert Uytterhoeven X-Patchwork-Id: 11124009 X-Patchwork-Delegate: geert@linux-m68k.org Return-Path: Received: from mail.kernel.org (pdx-korg-mail-1.web.codeaurora.org [172.30.200.123]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id 98A6A1395 for ; Fri, 30 Aug 2019 13:50:24 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.kernel.org (Postfix) with ESMTP id 7453323405 for ; Fri, 30 Aug 2019 13:50:24 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1727780AbfH3NuX (ORCPT ); Fri, 30 Aug 2019 09:50:23 -0400 Received: from xavier.telenet-ops.be ([195.130.132.52]:55544 "EHLO xavier.telenet-ops.be" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1727783AbfH3NuV (ORCPT ); Fri, 30 Aug 2019 09:50:21 -0400 Received: from ramsan ([84.194.98.4]) by xavier.telenet-ops.be with bizsmtp id vRqJ2000u05gfCL01RqJwS; Fri, 30 Aug 2019 15:50:19 +0200 Received: from rox.of.borg ([192.168.97.57]) by ramsan with esmtp (Exim 4.90_1) (envelope-from ) id 1i3hIA-0003KX-Qq; Fri, 30 Aug 2019 15:50:18 +0200 Received: from geert by rox.of.borg with local (Exim 4.90_1) (envelope-from ) id 1i3hDK-00037o-Ud; Fri, 30 Aug 2019 15:45:18 +0200 From: Geert Uytterhoeven To: Michael Turquette , Stephen Boyd Cc: linux-clk@vger.kernel.org, linux-renesas-soc@vger.kernel.org, Geert Uytterhoeven Subject: [PATCH v2 7/8] clk: renesas: rcar-gen3: Switch Z clocks to .determine_rate() Date: Fri, 30 Aug 2019 15:45:14 +0200 Message-Id: <20190830134515.11925-8-geert+renesas@glider.be> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20190830134515.11925-1-geert+renesas@glider.be> References: <20190830134515.11925-1-geert+renesas@glider.be> Sender: linux-renesas-soc-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-renesas-soc@vger.kernel.org As the .round_rate() callback returns a long clock rate, it cannot return clock rates that do not fit in signed long, but do fit in unsigned long. Hence switch the Z clocks on R-Car Gen3 from the old .round_rate() callback to the newer .determine_rate() callback, which does not suffer from this limitation. This includes implementing range checking. Signed-off-by: Geert Uytterhoeven --- v2: - Use div_u64() for division by unsigned long, - Rebased. --- drivers/clk/renesas/rcar-gen3-cpg.c | 22 ++++++++++++++-------- 1 file changed, 14 insertions(+), 8 deletions(-) diff --git a/drivers/clk/renesas/rcar-gen3-cpg.c b/drivers/clk/renesas/rcar-gen3-cpg.c index a612045cba7d97b7..176f908929b3920f 100644 --- a/drivers/clk/renesas/rcar-gen3-cpg.c +++ b/drivers/clk/renesas/rcar-gen3-cpg.c @@ -114,18 +114,24 @@ static unsigned long cpg_z_clk_recalc_rate(struct clk_hw *hw, 32 * zclk->fixed_div); } -static long cpg_z_clk_round_rate(struct clk_hw *hw, unsigned long rate, - unsigned long *parent_rate) +static int cpg_z_clk_determine_rate(struct clk_hw *hw, + struct clk_rate_request *req) { struct cpg_z_clk *zclk = to_z_clk(hw); + unsigned int min_mult, max_mult, mult; unsigned long prate; - unsigned int mult; - prate = *parent_rate / zclk->fixed_div; - mult = div64_ul(rate * 32ULL, prate); - mult = clamp(mult, 1U, 32U); + prate = req->best_parent_rate / zclk->fixed_div; + min_mult = max(div64_ul(req->min_rate * 32ULL, prate), 1ULL); + max_mult = min(div64_ul(req->max_rate * 32ULL, prate), 32ULL); + if (max_mult < min_mult) + return -EINVAL; - return div_u64((u64)prate * mult, 32); + mult = div64_ul(req->rate * 32ULL, prate); + mult = clamp(mult, min_mult, max_mult); + + req->rate = div_u64((u64)prate * mult, 32); + return 0; } static int cpg_z_clk_set_rate(struct clk_hw *hw, unsigned long rate, @@ -172,7 +178,7 @@ static int cpg_z_clk_set_rate(struct clk_hw *hw, unsigned long rate, static const struct clk_ops cpg_z_clk_ops = { .recalc_rate = cpg_z_clk_recalc_rate, - .round_rate = cpg_z_clk_round_rate, + .determine_rate = cpg_z_clk_determine_rate, .set_rate = cpg_z_clk_set_rate, }; From patchwork Fri Aug 30 13:45:15 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Geert Uytterhoeven X-Patchwork-Id: 11123987 X-Patchwork-Delegate: geert@linux-m68k.org Return-Path: Received: from mail.kernel.org (pdx-korg-mail-1.web.codeaurora.org [172.30.200.123]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id D5C451908 for ; Fri, 30 Aug 2019 13:50:22 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.kernel.org (Postfix) with ESMTP id BC96B2342A for ; Fri, 30 Aug 2019 13:50:22 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1727945AbfH3NuW (ORCPT ); Fri, 30 Aug 2019 09:50:22 -0400 Received: from baptiste.telenet-ops.be ([195.130.132.51]:52322 "EHLO baptiste.telenet-ops.be" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1727923AbfH3NuV (ORCPT ); Fri, 30 Aug 2019 09:50:21 -0400 Received: from ramsan ([84.194.98.4]) by baptiste.telenet-ops.be with bizsmtp id vRqJ2000l05gfCL01RqJdj; Fri, 30 Aug 2019 15:50:19 +0200 Received: from rox.of.borg ([192.168.97.57]) by ramsan with esmtp (Exim 4.90_1) (envelope-from ) id 1i3hIA-0003KX-Pv; Fri, 30 Aug 2019 15:50:18 +0200 Received: from geert by rox.of.borg with local (Exim 4.90_1) (envelope-from ) id 1i3hDK-00037r-VO; Fri, 30 Aug 2019 15:45:18 +0200 From: Geert Uytterhoeven To: Michael Turquette , Stephen Boyd Cc: linux-clk@vger.kernel.org, linux-renesas-soc@vger.kernel.org, Geert Uytterhoeven Subject: [PATCH v2 8/8] clk: renesas: rcar-gen3: Switch SD clocks to .determine_rate() Date: Fri, 30 Aug 2019 15:45:15 +0200 Message-Id: <20190830134515.11925-9-geert+renesas@glider.be> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20190830134515.11925-1-geert+renesas@glider.be> References: <20190830134515.11925-1-geert+renesas@glider.be> Sender: linux-renesas-soc-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-renesas-soc@vger.kernel.org As the .round_rate() callback returns a long clock rate, it cannot return clock rates that do not fit in signed long, but do fit in unsigned long. Hence switch the SD clocks on R-Car Gen3 from the old .round_rate() callback to the newer .determine_rate() callback, which does not suffer from this limitation. This includes implementing range checking. Signed-off-by: Geert Uytterhoeven --- v2: - Extract cpg_sd_clock_calc_div() absorption and best rate calculation into their own patches. --- drivers/clk/renesas/rcar-gen3-cpg.c | 19 ++++++++++++------- 1 file changed, 12 insertions(+), 7 deletions(-) diff --git a/drivers/clk/renesas/rcar-gen3-cpg.c b/drivers/clk/renesas/rcar-gen3-cpg.c index 176f908929b3920f..7b47743097395102 100644 --- a/drivers/clk/renesas/rcar-gen3-cpg.c +++ b/drivers/clk/renesas/rcar-gen3-cpg.c @@ -315,8 +315,8 @@ static unsigned long cpg_sd_clock_recalc_rate(struct clk_hw *hw, clock->div_table[clock->cur_div_idx].div); } -static long cpg_sd_clock_round_rate(struct clk_hw *hw, unsigned long rate, - unsigned long *parent_rate) +static int cpg_sd_clock_determine_rate(struct clk_hw *hw, + struct clk_rate_request *req) { unsigned long best_rate = ULONG_MAX, diff_min = ULONG_MAX; struct sd_clock *clock = to_sd_clock(hw); @@ -324,19 +324,24 @@ static long cpg_sd_clock_round_rate(struct clk_hw *hw, unsigned long rate, unsigned int i; for (i = 0; i < clock->div_num; i++) { - calc_rate = DIV_ROUND_CLOSEST(*parent_rate, + calc_rate = DIV_ROUND_CLOSEST(req->best_parent_rate, clock->div_table[i].div); - diff = calc_rate > rate ? calc_rate - rate : rate - calc_rate; + if (calc_rate < req->min_rate || calc_rate > req->max_rate) + continue; + + diff = calc_rate > req->rate ? calc_rate - req->rate + : req->rate - calc_rate; if (diff < diff_min) { best_rate = calc_rate; diff_min = diff; } } - if (best_rate > LONG_MAX) + if (best_rate == ULONG_MAX) return -EINVAL; - return best_rate; + req->rate = best_rate; + return 0; } static int cpg_sd_clock_set_rate(struct clk_hw *hw, unsigned long rate, @@ -367,7 +372,7 @@ static const struct clk_ops cpg_sd_clock_ops = { .disable = cpg_sd_clock_disable, .is_enabled = cpg_sd_clock_is_enabled, .recalc_rate = cpg_sd_clock_recalc_rate, - .round_rate = cpg_sd_clock_round_rate, + .determine_rate = cpg_sd_clock_determine_rate, .set_rate = cpg_sd_clock_set_rate, };