From patchwork Mon Sep 2 10:55:47 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "H. Nikolaus Schaller" X-Patchwork-Id: 11126359 Return-Path: Received: from mail.kernel.org (pdx-korg-mail-1.web.codeaurora.org [172.30.200.123]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id 34DFA174A for ; Mon, 2 Sep 2019 10:56:25 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.kernel.org (Postfix) with ESMTP id 12E6922CF7 for ; Mon, 2 Sep 2019 10:56:25 +0000 (UTC) Authentication-Results: mail.kernel.org; dkim=fail reason="signature verification failed" (2048-bit key) header.d=goldelico.com header.i=@goldelico.com header.b="gOSJJjdE" Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1731278AbfIBK4N (ORCPT ); Mon, 2 Sep 2019 06:56:13 -0400 Received: from mo4-p02-ob.smtp.rzone.de ([85.215.255.80]:9024 "EHLO mo4-p02-ob.smtp.rzone.de" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1726273AbfIBK4N (ORCPT ); Mon, 2 Sep 2019 06:56:13 -0400 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; t=1567421769; s=strato-dkim-0002; d=goldelico.com; h=References:In-Reply-To:Message-Id:Date:Subject:Cc:To:From: X-RZG-CLASS-ID:X-RZG-AUTH:From:Subject:Sender; bh=y6d8yUncj9yKT4vPDXI1EkBvhxcQKzs69RFC22lGlXA=; b=gOSJJjdEJP2KV5cvZNuypTn0n4XK+nXzt9m6gft2FK4AcE+bPjhvpk6H2z+ZhXRtZU xipoWqY0Loa01WbfujgraiYAIKI/NfbmZnyYlU078/Egmo1nc2uiympRvK0wX4hVXa1A lgeQ6QdL5dHNWMCk43nGNQCKjXwl1FeXB4+I0kWy5tv4zecZRBrOE7046MVP0W9J+O9N Yv7b+1go1AuklIBf0WBOzw+grRE3xnkXFQ6to3cdwtSI7xn3scskoZW7bwRFAdBoQu2J lgKT4wIcolObr10kS45TSz+sPlexS8PBdJbvFNEpWQ7FIQn9go9BaWfPIojItxWgfbuw cU7g== X-RZG-AUTH: ":JGIXVUS7cutRB/49FwqZ7WcJeFKiMhflhwDubTJ9o1mfYzBGHXL8GTnvuHRT" X-RZG-CLASS-ID: mo00 Received: from iMac.fritz.box by smtp.strato.de (RZmta 44.27.0 DYNA|AUTH) with ESMTPSA id u036f9v82AtqPvi (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (curve secp521r1 with 521 ECDH bits, eq. 15360 bits RSA)) (Client did not present a certificate); Mon, 2 Sep 2019 12:55:52 +0200 (CEST) From: "H. Nikolaus Schaller" To: =?utf-8?q?Beno=C3=AEt_Cousson?= , Tony Lindgren , Rob Herring , Adam Ford , =?utf-8?q?Andr=C3=A9_Roth?= , Mark Rutland , "Rafael J. Wysocki" , Viresh Kumar Cc: linux-omap@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-pm@vger.kernel.org, letux-kernel@openphoenux.org, kernel@pyra-handheld.com, "H. Nikolaus Schaller" Subject: [RFC 1/5] cpufreq: ti-cpufreq: add support for omap34xx and omap36xx Date: Mon, 2 Sep 2019 12:55:47 +0200 Message-Id: <01a2f0db82bbed4cc8f7b04d8d4e1d7108c8f4bd.1567421750.git.hns@goldelico.com> X-Mailer: git-send-email 2.19.1 In-Reply-To: References: MIME-Version: 1.0 Sender: linux-omap-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-omap@vger.kernel.org This adds code and tables to read the silicon revision and eFuse (speed binned / 720 MHz grade) bits for selecting opp-v2 table entries. Since these bits are not always part of the syscon register range (like for am3, am4, dra7), we add code to directly read the register values using ioremap() if syscon access fails. Signed-off-by: H. Nikolaus Schaller --- drivers/cpufreq/ti-cpufreq.c | 86 +++++++++++++++++++++++++++++++++++- 1 file changed, 84 insertions(+), 2 deletions(-) diff --git a/drivers/cpufreq/ti-cpufreq.c b/drivers/cpufreq/ti-cpufreq.c index 2ad1ae17932d..5c5ca4577093 100644 --- a/drivers/cpufreq/ti-cpufreq.c +++ b/drivers/cpufreq/ti-cpufreq.c @@ -31,6 +31,11 @@ #define DRA7_EFUSE_OD_MPU_OPP BIT(1) #define DRA7_EFUSE_HIGH_MPU_OPP BIT(2) +#define OMAP3_CONTROL_DEVICE_STATUS 0x4800244C +#define OMAP3_CONTROL_IDCODE 0x4830A204 +#define OMAP34xx_ProdID_SKUID 0x4830A20C +#define OMAP3_SYSCON_BASE (0x48000000 + 0x2000 + 0x270) + #define VERSION_COUNT 2 struct ti_cpufreq_data; @@ -84,6 +89,13 @@ static unsigned long dra7_efuse_xlate(struct ti_cpufreq_data *opp_data, return calculated_efuse; } +static unsigned long omap3_efuse_xlate(struct ti_cpufreq_data *opp_data, + unsigned long efuse) +{ + /* OPP enable bit ("Speed Binned") */ + return BIT(efuse); +} + static struct ti_cpufreq_soc_data am3x_soc_data = { .efuse_xlate = amx3_efuse_xlate, .efuse_fallback = AM33XX_800M_ARM_MPU_MAX_FREQ, @@ -111,6 +123,56 @@ static struct ti_cpufreq_soc_data dra7_soc_data = { .multi_regulator = true, }; +/* + * OMAP35x TRM (SPRUF98K): + * CONTROL_IDCODE (0x4830 A204) describes Silicon revisions. + * Control OMAP Status Register 15:0 (Address 0x4800 244C) + * to separate between omap3503, omap3515, omap3525, omap3530 + * and feature presence. + * There are encodings for versions limited to 400/266MHz + * but we ignore. + * Not clear if this also holds for omap34xx. + * some eFuse values e.g. CONTROL_FUSE_OPP1_VDD1 + * are stored in the SYSCON register range + * Register 0x4830A20C [ProdID.SKUID] [0:3] + * 0x0 for normal 600/430MHz device. + * 0x8 for 720/520MHz device. + * Not clear what omap34xx value is. + */ + +static struct ti_cpufreq_soc_data omap34xx_soc_data = { + .efuse_xlate = omap3_efuse_xlate, + .efuse_offset = OMAP34xx_ProdID_SKUID - OMAP3_SYSCON_BASE, + .efuse_shift = 3, + .efuse_mask = BIT(3), + .rev_offset = OMAP3_CONTROL_IDCODE - OMAP3_SYSCON_BASE, + .multi_regulator = false, +}; + +/* + * AM/DM37x TRM (SPRUGN4M) + * CONTROL_IDCODE (0x4830 A204) describes Silicon revisions. + * Control Device Status Register 15:0 (Address 0x4800 244C) + * to separate between am3703, am3715, dm3725, dm3730 + * and feature presence. + * Speed Binned = Bit 9 + * 0 800/600 MHz + * 1 1000/800 MHz + * some eFuse values e.g. CONTROL_FUSE_OPP 1G_VDD1 + * are stored in the SYSCON register range. + * There is no 0x4830A20C [ProdID.SKUID] register (exists but + * seems to always read as 0). + */ + +static struct ti_cpufreq_soc_data omap36xx_soc_data = { + .efuse_xlate = omap3_efuse_xlate, + .efuse_offset = OMAP3_CONTROL_DEVICE_STATUS - OMAP3_SYSCON_BASE, + .efuse_shift = 9, + .efuse_mask = BIT(9), + .rev_offset = OMAP3_CONTROL_IDCODE - OMAP3_SYSCON_BASE, + .multi_regulator = false, +}; + /** * ti_cpufreq_get_efuse() - Parse and return efuse value present on SoC * @opp_data: pointer to ti_cpufreq_data context @@ -127,7 +189,15 @@ static int ti_cpufreq_get_efuse(struct ti_cpufreq_data *opp_data, ret = regmap_read(opp_data->syscon, opp_data->soc_data->efuse_offset, &efuse); - if (ret) { + if (ret == -EIO) { + /* not a syscon register! */ + void __iomem *regs = ioremap(OMAP3_SYSCON_BASE + + opp_data->soc_data->efuse_offset, 4); + + efuse = readl(regs); + iounmap(regs); + } + else if (ret) { dev_err(dev, "Failed to read the efuse value from syscon: %d\n", ret); @@ -158,7 +228,15 @@ static int ti_cpufreq_get_rev(struct ti_cpufreq_data *opp_data, ret = regmap_read(opp_data->syscon, opp_data->soc_data->rev_offset, &revision); - if (ret) { + if (ret == -EIO) { + /* not a syscon register! */ + void __iomem *regs = ioremap(OMAP3_SYSCON_BASE + + opp_data->soc_data->rev_offset, 4); + + revision = readl(regs); + iounmap(regs); + } + else if (ret) { dev_err(dev, "Failed to read the revision number from syscon: %d\n", ret); @@ -190,6 +268,10 @@ static const struct of_device_id ti_cpufreq_of_match[] = { { .compatible = "ti,am33xx", .data = &am3x_soc_data, }, { .compatible = "ti,am43", .data = &am4x_soc_data, }, { .compatible = "ti,dra7", .data = &dra7_soc_data }, + { .compatible = "ti,omap3430", .data = &omap34xx_soc_data, }, + { .compatible = "ti,omap34xx", .data = &omap34xx_soc_data, }, + { .compatible = "ti,omap3630", .data = &omap36xx_soc_data, }, + { .compatible = "ti,omap36xx", .data = &omap36xx_soc_data, }, {}, }; From patchwork Mon Sep 2 10:55:48 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "H. Nikolaus Schaller" X-Patchwork-Id: 11126355 Return-Path: Received: from mail.kernel.org (pdx-korg-mail-1.web.codeaurora.org [172.30.200.123]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id 09F0715E9 for ; Mon, 2 Sep 2019 10:56:16 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.kernel.org (Postfix) with ESMTP id D4BAB21744 for ; Mon, 2 Sep 2019 10:56:15 +0000 (UTC) Authentication-Results: mail.kernel.org; dkim=fail reason="signature verification failed" (2048-bit key) header.d=goldelico.com header.i=@goldelico.com header.b="Ajhyy4l5" Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1731431AbfIBK4P (ORCPT ); Mon, 2 Sep 2019 06:56:15 -0400 Received: from mo4-p02-ob.smtp.rzone.de ([85.215.255.80]:14793 "EHLO mo4-p02-ob.smtp.rzone.de" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1731282AbfIBK4O (ORCPT ); Mon, 2 Sep 2019 06:56:14 -0400 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; t=1567421769; s=strato-dkim-0002; d=goldelico.com; h=References:In-Reply-To:Message-Id:Date:Subject:Cc:To:From: X-RZG-CLASS-ID:X-RZG-AUTH:From:Subject:Sender; bh=SgVZjtfRM6OwS1wslTEUrBn/bi4Z6ukTMWTd8zdRnZ0=; b=Ajhyy4l5R9jnQXbuHXped6aRVYcfFiBP6SMyJAwgZ55h1xlJOva4VLHER68cuvl/nq KLmOfJ/PbHVY4xx/TXpBp4yzVILKJA4laFtutcb7MhWS7K8pLEnqMOhMKEtaXul9RWbr cYc1f6psFInFWVnridfj0swKCEyanBsdOFXZ/J/jnS0p2Kp29NJx//NmlWCkXmSSl2dQ 62jUEmz4u1y5BiQGthElFSddaSh9uqTJPEnBAqv0TUTOH+EDjkUREFJEbYeH6MWB9jKt ATHPyC5t4G3bI+N7OOLS6uqybhNJHdFHtZdKrIpH6yrlqmfYUBAKKJtx8za55bnSnbUE EMDw== X-RZG-AUTH: ":JGIXVUS7cutRB/49FwqZ7WcJeFKiMhflhwDubTJ9o1mfYzBGHXL8GTnvuHRT" X-RZG-CLASS-ID: mo00 Received: from iMac.fritz.box by smtp.strato.de (RZmta 44.27.0 DYNA|AUTH) with ESMTPSA id u036f9v82AtrPvj (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (curve secp521r1 with 521 ECDH bits, eq. 15360 bits RSA)) (Client did not present a certificate); Mon, 2 Sep 2019 12:55:53 +0200 (CEST) From: "H. Nikolaus Schaller" To: =?utf-8?q?Beno=C3=AEt_Cousson?= , Tony Lindgren , Rob Herring , Adam Ford , =?utf-8?q?Andr=C3=A9_Roth?= , Mark Rutland , "Rafael J. Wysocki" , Viresh Kumar Cc: linux-omap@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-pm@vger.kernel.org, letux-kernel@openphoenux.org, kernel@pyra-handheld.com, "H. Nikolaus Schaller" Subject: [RFC 2/5] ARM: dts: add support for opp-v2 for omap34xx and omap36xx Date: Mon, 2 Sep 2019 12:55:48 +0200 Message-Id: X-Mailer: git-send-email 2.19.1 In-Reply-To: References: MIME-Version: 1.0 Sender: linux-omap-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-omap@vger.kernel.org In addition, move omap3 from whitelist to blacklist in cpufreq-dt-platdev in the same patch, because doing either first breaks operation and may make trouble in bisect. Signed-off-by: H. Nikolaus Schaller --- arch/arm/boot/dts/omap34xx.dtsi | 59 +++++++++++++++++++++++----- arch/arm/boot/dts/omap36xx.dtsi | 47 ++++++++++++++++++---- drivers/cpufreq/cpufreq-dt-platdev.c | 2 +- 3 files changed, 90 insertions(+), 18 deletions(-) diff --git a/arch/arm/boot/dts/omap34xx.dtsi b/arch/arm/boot/dts/omap34xx.dtsi index f572a477f74c..b92645d6d981 100644 --- a/arch/arm/boot/dts/omap34xx.dtsi +++ b/arch/arm/boot/dts/omap34xx.dtsi @@ -16,19 +16,60 @@ / { cpus { cpu: cpu@0 { - /* OMAP343x/OMAP35xx variants OPP1-5 */ - operating-points = < - /* kHz uV */ - 125000 975000 - 250000 1075000 - 500000 1200000 - 550000 1270000 - 600000 1350000 - >; + /* OMAP343x/OMAP35xx variants OPP1-6 */ + operating-points-v2 = <&cpu0_opp_table>; + clock-latency = <300000>; /* From legacy driver */ }; }; + /* see Documentation/devicetree/bindings/opp/opp.txt */ + cpu0_opp_table: opp-table { + compatible = "operating-points-v2-ti-cpu"; + syscon = <&scm_conf>; + + opp1-125000000 { + opp-hz = /bits/ 64 <125000000>; + // we currently only select the max voltage from table Table 3-3 of the omap3530 Data sheet (SPRS507F) + // could also be single + opp-microvolt = <975000 975000 975000>; + // first value is silicon revision, second one 720MHz Device Identification + opp-supported-hw = <0xffffffff 3>; + }; + + opp2-250000000 { + opp-hz = /bits/ 64 <250000000>; + opp-microvolt = <1075000 1075000 1075000>; + opp-supported-hw = <0xffffffff 3>; + opp-suspend; + }; + + opp3-500000000 { + opp-hz = /bits/ 64 <500000000>; + opp-microvolt = <1200000 1200000 1200000>; + opp-supported-hw = <0xffffffff 3>; + }; + + opp4-550000000 { + opp-hz = /bits/ 64 <550000000>; + opp-microvolt = <1270000 1270000 1270000>; + opp-supported-hw = <0xffffffff 3>; + }; + + opp5-600000000 { + opp-hz = /bits/ 64 <600000000>; + opp-microvolt = <1350000 1350000 1350000>; + opp-supported-hw = <0xffffffff 3>; + }; + + opp6-720000000 { + opp-hz = /bits/ 64 <720000000>; + opp-microvolt = <1350000 1350000 1350000>; + /* only high-speed grade omap3530 devices */ + opp-supported-hw = <0xffffffff 2>; + }; + }; + ocp@68000000 { omap3_pmx_core2: pinmux@480025d8 { compatible = "ti,omap3-padconf", "pinctrl-single"; diff --git a/arch/arm/boot/dts/omap36xx.dtsi b/arch/arm/boot/dts/omap36xx.dtsi index 6fb23ada1f64..1595814585df 100644 --- a/arch/arm/boot/dts/omap36xx.dtsi +++ b/arch/arm/boot/dts/omap36xx.dtsi @@ -19,15 +19,46 @@ }; cpus { - /* OMAP3630/OMAP37xx 'standard device' variants OPP50 to OPP130 */ + /* OMAP3630/OMAP37xx variants OPP50 to OPP130 and OPP1G */ cpu: cpu@0 { - operating-points = < - /* kHz uV */ - 300000 1012500 - 600000 1200000 - 800000 1325000 - >; - clock-latency = <300000>; /* From legacy driver */ + operating-points-v2 = <&cpu0_opp_table>; + + clock-latency = <300000>; /* From omap-cpufreq driver */ + }; + }; + + /* see Documentation/devicetree/bindings/opp/opp.txt */ + cpu0_opp_table: opp-table { + compatible = "operating-points-v2-ti-cpu"; + syscon = <&scm_conf>; + + opp50-300000000 { + opp-hz = /bits/ 64 <300000000>; + // we currently only select the max voltage from table Table 4-19 of the DM3730 Data sheet (SPRS685B) + // could also be single + opp-microvolt = <1012500 1012500 1012500>; + // first value is silicon revision, second one is "speed binned + opp-supported-hw = <0xffffffff 3>; + opp-suspend; + }; + + opp100-600000000 { + opp-hz = /bits/ 64 <600000000>; + opp-microvolt = <1200000 1200000 1200000>; + opp-supported-hw = <0xffffffff 3>; + }; + + opp130-800000000 { + opp-hz = /bits/ 64 <800000000>; + opp-microvolt = <1325000 1325000 1325000>; + opp-supported-hw = <0xffffffff 3>; + }; + + opp1g-1000000000 { + opp-hz = /bits/ 64 <1000000000>; + opp-microvolt = <1375000 1375000 1375000>; + /* only on am/dm37x with speed-binned bit set */ + opp-supported-hw = <0xffffffff 2>; }; }; diff --git a/drivers/cpufreq/cpufreq-dt-platdev.c b/drivers/cpufreq/cpufreq-dt-platdev.c index 03dc4244ab00..68b7fc4225f8 100644 --- a/drivers/cpufreq/cpufreq-dt-platdev.c +++ b/drivers/cpufreq/cpufreq-dt-platdev.c @@ -86,7 +86,6 @@ static const struct of_device_id whitelist[] __initconst = { { .compatible = "st-ericsson,u9540", }, { .compatible = "ti,omap2", }, - { .compatible = "ti,omap3", }, { .compatible = "ti,omap4", }, { .compatible = "ti,omap5", }, @@ -132,6 +131,7 @@ static const struct of_device_id blacklist[] __initconst = { { .compatible = "ti,am33xx", }, { .compatible = "ti,am43", }, { .compatible = "ti,dra7", }, + { .compatible = "ti,omap3", }, { } }; From patchwork Mon Sep 2 10:55:49 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "H. Nikolaus Schaller" X-Patchwork-Id: 11126351 Return-Path: Received: from mail.kernel.org (pdx-korg-mail-1.web.codeaurora.org [172.30.200.123]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id 8984514F7 for ; Mon, 2 Sep 2019 10:56:07 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.kernel.org (Postfix) with ESMTP id 5EF81217F4 for ; Mon, 2 Sep 2019 10:56:07 +0000 (UTC) Authentication-Results: mail.kernel.org; dkim=fail reason="signature verification failed" (2048-bit key) header.d=goldelico.com header.i=@goldelico.com header.b="GBNH2xTn" Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1730702AbfIBK4G (ORCPT ); Mon, 2 Sep 2019 06:56:06 -0400 Received: from mo4-p02-ob.smtp.rzone.de ([85.215.255.81]:33273 "EHLO mo4-p02-ob.smtp.rzone.de" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1726273AbfIBK4G (ORCPT ); Mon, 2 Sep 2019 06:56:06 -0400 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; t=1567421762; s=strato-dkim-0002; d=goldelico.com; h=References:In-Reply-To:Message-Id:Date:Subject:Cc:To:From: X-RZG-CLASS-ID:X-RZG-AUTH:From:Subject:Sender; bh=066Rqa4dJD1flQL69Q2YCPKoI7wVEYGXrGAi/IMoM5o=; b=GBNH2xTnuZB04j9PeDOkPNquE4mcMt2YC7oR/dBhTfhRcqXsA9QXvDk2yUjr0JpI7f aeGxCFvxXm2l3cRCTWloSHT2pG+UK8ckuyVxDxcyXqUZ0RYq13Ih9NIUnCks9m4H3CQe JOtJLZhuxZo38/rJ3Zp0RLqlnQafcFxqaH0LY7iE7xQOOlyCPv4DXgfnyR7rF/BujwFq nqxv64vldP1t8ZCfWaxpqodRWmbLukLRi965jQ4frB/fRsLLzsVM2U0aG6XVhPT7DQOx rfLtpldEoebyADxfArOpZ8LAVB3c4oFFLpqd5LbS4/+fcky4IEamJEak/FJUAzjOfIwp h8UA== X-RZG-AUTH: ":JGIXVUS7cutRB/49FwqZ7WcJeFKiMhflhwDubTJ9o1mfYzBGHXL8GTnvuHRT" X-RZG-CLASS-ID: mo00 Received: from iMac.fritz.box by smtp.strato.de (RZmta 44.27.0 DYNA|AUTH) with ESMTPSA id u036f9v82AtsPvk (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (curve secp521r1 with 521 ECDH bits, eq. 15360 bits RSA)) (Client did not present a certificate); Mon, 2 Sep 2019 12:55:54 +0200 (CEST) From: "H. Nikolaus Schaller" To: =?utf-8?q?Beno=C3=AEt_Cousson?= , Tony Lindgren , Rob Herring , Adam Ford , =?utf-8?q?Andr=C3=A9_Roth?= , Mark Rutland , "Rafael J. Wysocki" , Viresh Kumar Cc: linux-omap@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-pm@vger.kernel.org, letux-kernel@openphoenux.org, kernel@pyra-handheld.com, "H. Nikolaus Schaller" Subject: [RFC 3/5] ARM: dts: omap3-evm-37xx: fix compatible from omap3630 to omap36xx Date: Mon, 2 Sep 2019 12:55:49 +0200 Message-Id: X-Mailer: git-send-email 2.19.1 In-Reply-To: References: MIME-Version: 1.0 Sender: linux-omap-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-omap@vger.kernel.org All other boards use compatible = "omap36xx". Signed-off-by: H. Nikolaus Schaller --- arch/arm/boot/dts/omap3-evm-37xx.dts | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/arm/boot/dts/omap3-evm-37xx.dts b/arch/arm/boot/dts/omap3-evm-37xx.dts index e0c0382388f0..311550ee4eae 100644 --- a/arch/arm/boot/dts/omap3-evm-37xx.dts +++ b/arch/arm/boot/dts/omap3-evm-37xx.dts @@ -10,7 +10,7 @@ / { model = "TI OMAP37XX EVM (TMDSEVM3730)"; - compatible = "ti,omap3-evm-37xx", "ti,omap3630", "ti,omap3"; + compatible = "ti,omap3-evm-37xx", "ti,omap36xx", "ti,omap3"; }; &omap3_pmx_core2 { From patchwork Mon Sep 2 10:55:50 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "H. Nikolaus Schaller" X-Patchwork-Id: 11126361 Return-Path: Received: from mail.kernel.org (pdx-korg-mail-1.web.codeaurora.org [172.30.200.123]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id 93DA814F7 for ; Mon, 2 Sep 2019 10:56:29 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.kernel.org (Postfix) with ESMTP id 7475A22CF7 for ; Mon, 2 Sep 2019 10:56:29 +0000 (UTC) Authentication-Results: mail.kernel.org; dkim=fail reason="signature verification failed" (2048-bit key) header.d=goldelico.com header.i=@goldelico.com header.b="cYdiNQXM" Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1731287AbfIBK4Z (ORCPT ); Mon, 2 Sep 2019 06:56:25 -0400 Received: from mo4-p03-ob.smtp.rzone.de ([85.215.255.103]:8124 "EHLO mo4-p03-ob.smtp.rzone.de" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1731285AbfIBK4N (ORCPT ); Mon, 2 Sep 2019 06:56:13 -0400 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; t=1567421769; s=strato-dkim-0002; d=goldelico.com; h=References:In-Reply-To:Message-Id:Date:Subject:Cc:To:From: X-RZG-CLASS-ID:X-RZG-AUTH:From:Subject:Sender; bh=iDHDcTZofAwFtKZ+JtaTo+qsb9dMO/SudfMjC+bQAcY=; b=cYdiNQXMOopAQSmQ6Zk3tTDwG9iRrD8vhNY3Zay2vAt3v3GgZfiwj4Eua714D/9UHp Rwfrbznp/GXRrgHBNMT1ESe8qPs2nxW6W9X1O/03D9wvJ9mfj/jUsPrI7cY+t8Q/brdy 3F8/HlqwsZmY56LonAzDCXlPwvLj11p/EOQ2AjQdYIATuUawL6zATB3hV40cRecbmvXT X9alRVD/x3vSyVry9yz+NR0+tnQXBKlaxZDKjEiyAYqULn4kBAOwdKkTfS3nmhdJ/P9S M46zlEXBiL4692NVJzmDsdPO+XpLhab5KSqDH4Q/kEXtEF3btHNWOYBWq+V3nnelOmLH uIcw== X-RZG-AUTH: ":JGIXVUS7cutRB/49FwqZ7WcJeFKiMhflhwDubTJ9o1mfYzBGHXL8GTnvuHRT" X-RZG-CLASS-ID: mo00 Received: from iMac.fritz.box by smtp.strato.de (RZmta 44.27.0 DYNA|AUTH) with ESMTPSA id u036f9v82AtsPvl (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (curve secp521r1 with 521 ECDH bits, eq. 15360 bits RSA)) (Client did not present a certificate); Mon, 2 Sep 2019 12:55:54 +0200 (CEST) From: "H. Nikolaus Schaller" To: =?utf-8?q?Beno=C3=AEt_Cousson?= , Tony Lindgren , Rob Herring , Adam Ford , =?utf-8?q?Andr=C3=A9_Roth?= , Mark Rutland , "Rafael J. Wysocki" , Viresh Kumar Cc: linux-omap@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-pm@vger.kernel.org, letux-kernel@openphoenux.org, kernel@pyra-handheld.com, "H. Nikolaus Schaller" Subject: [RFC 4/5] ARM: dts: omap3-n950-n9: remove opp-v1 table Date: Mon, 2 Sep 2019 12:55:50 +0200 Message-Id: <2f978667c1533e46e3a5df58871e9048f3eb74e9.1567421751.git.hns@goldelico.com> X-Mailer: git-send-email 2.19.1 In-Reply-To: References: MIME-Version: 1.0 Sender: linux-omap-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-omap@vger.kernel.org With opp-v2 in omap36xx.dtsi and ti-cpufreq driver the 1GHz capability is automatically detected. Signed-off-by: H. Nikolaus Schaller --- arch/arm/boot/dts/omap3-n950-n9.dtsi | 7 ------- 1 file changed, 7 deletions(-) diff --git a/arch/arm/boot/dts/omap3-n950-n9.dtsi b/arch/arm/boot/dts/omap3-n950-n9.dtsi index 5441e9ffdbb4..e98b0c615f19 100644 --- a/arch/arm/boot/dts/omap3-n950-n9.dtsi +++ b/arch/arm/boot/dts/omap3-n950-n9.dtsi @@ -11,13 +11,6 @@ cpus { cpu@0 { cpu0-supply = <&vcc>; - operating-points = < - /* kHz uV */ - 300000 1012500 - 600000 1200000 - 800000 1325000 - 1000000 1375000 - >; }; }; From patchwork Mon Sep 2 10:55:51 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "H. Nikolaus Schaller" X-Patchwork-Id: 11126357 Return-Path: Received: from mail.kernel.org (pdx-korg-mail-1.web.codeaurora.org [172.30.200.123]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id EE21614F7 for ; Mon, 2 Sep 2019 10:56:24 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.kernel.org (Postfix) with ESMTP id CE80D22DBF for ; Mon, 2 Sep 2019 10:56:24 +0000 (UTC) Authentication-Results: mail.kernel.org; dkim=fail reason="signature verification failed" (2048-bit key) header.d=goldelico.com header.i=@goldelico.com header.b="b2uv6Ph+" Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1731478AbfIBK4U (ORCPT ); Mon, 2 Sep 2019 06:56:20 -0400 Received: from mo4-p03-ob.smtp.rzone.de ([81.169.146.173]:14946 "EHLO mo4-p03-ob.smtp.rzone.de" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1731287AbfIBK4O (ORCPT ); Mon, 2 Sep 2019 06:56:14 -0400 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; t=1567421770; s=strato-dkim-0002; d=goldelico.com; h=References:In-Reply-To:Message-Id:Date:Subject:Cc:To:From: X-RZG-CLASS-ID:X-RZG-AUTH:From:Subject:Sender; bh=gyaJxhpKOrJkSBef5H5LmgKUYEaxN9j94o+XGsFhaN0=; b=b2uv6Ph+Hyo7biLYyQZ9hSuNeyIbJUCTvcYDNXSrUf34fd0BCg1Lggv9szi2v+XEl6 GMPfF+BTJBZaxFH7RFI3EWCSF01+PDHbOcN8Vtp3LyXea9jZvne+j06s2KV4pV1jxEZ0 EB3lZHySjp/Vv8fkL+7NTVfPAlUMW3vKpOl76nlIMmiHia2ZB26Hg942hhM9bl8B/WOq LALbTRIV9DQSJqAdm4Dx0t009cqVnJoDrJrRe37ibB3shp2Fkznv88BzlR54Z7JViXTt pt0IcjSgEnkiRDbzBXJSWGwI+X/+3nWsSoVeW5eywqljr60cFF1coz1eqN8UA/jRCeP5 /ELA== X-RZG-AUTH: ":JGIXVUS7cutRB/49FwqZ7WcJeFKiMhflhwDubTJ9o1mfYzBGHXL8GTnvuHRT" X-RZG-CLASS-ID: mo00 Received: from iMac.fritz.box by smtp.strato.de (RZmta 44.27.0 DYNA|AUTH) with ESMTPSA id u036f9v82AtsPvm (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (curve secp521r1 with 521 ECDH bits, eq. 15360 bits RSA)) (Client did not present a certificate); Mon, 2 Sep 2019 12:55:54 +0200 (CEST) From: "H. Nikolaus Schaller" To: =?utf-8?q?Beno=C3=AEt_Cousson?= , Tony Lindgren , Rob Herring , Adam Ford , =?utf-8?q?Andr=C3=A9_Roth?= , Mark Rutland , "Rafael J. Wysocki" , Viresh Kumar Cc: linux-omap@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-pm@vger.kernel.org, letux-kernel@openphoenux.org, kernel@pyra-handheld.com, "H. Nikolaus Schaller" Subject: [RFC 5/5] ARM: dts: omap3-beagle: make explicitly compatible to ti,omap34xx Date: Mon, 2 Sep 2019 12:55:51 +0200 Message-Id: <150eb34a95b2e7ead8ac81a9ab275592ea31595b.1567421751.git.hns@goldelico.com> X-Mailer: git-send-email 2.19.1 In-Reply-To: References: MIME-Version: 1.0 Sender: linux-omap-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-omap@vger.kernel.org Matching the ti-cpufreq driver needs to specify explicitly if a board uses an omap34xx or omap36xx chip. Signed-off-by: H. Nikolaus Schaller --- arch/arm/boot/dts/omap3-beagle.dts | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/arm/boot/dts/omap3-beagle.dts b/arch/arm/boot/dts/omap3-beagle.dts index e3df3c166902..d47213c7a4d0 100644 --- a/arch/arm/boot/dts/omap3-beagle.dts +++ b/arch/arm/boot/dts/omap3-beagle.dts @@ -8,7 +8,7 @@ / { model = "TI OMAP3 BeagleBoard"; - compatible = "ti,omap3-beagle", "ti,omap3"; + compatible = "ti,omap3-beagle", "ti,omap34xx", "ti,omap3"; cpus { cpu@0 {