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[81.2.115.148]) by smtp.gmail.com with ESMTPSA id a18sm24435188wrt.18.2019.09.03.08.36.35 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 03 Sep 2019 08:36:36 -0700 (PDT) From: Peter Maydell To: qemu-devel@nongnu.org Date: Tue, 3 Sep 2019 16:36:13 +0100 Message-Id: <20190903153633.6651-2-peter.maydell@linaro.org> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20190903153633.6651-1-peter.maydell@linaro.org> References: <20190903153633.6651-1-peter.maydell@linaro.org> MIME-Version: 1.0 X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2a00:1450:4864:20::42c Subject: [Qemu-devel] [PULL 01/21] Revert "target/arm: Use unallocated_encoding for aarch32" X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patchwork-qemu-devel=patchwork.kernel.org@nongnu.org Sender: "Qemu-devel" From: Richard Henderson This reverts commit 3cb36637157088892e9e33ddb1034bffd1251d3b. Despite the fact that the text for the call to gen_exception_insn is identical for aarch64 and aarch32, the implementation inside gen_exception_insn is totally different. This fixes exceptions raised from aarch64. Reported-by: Laurent Desnogues Signed-off-by: Richard Henderson Reviewed-by: Laurent Desnogues Message-id: 20190826151536.6771-2-richard.henderson@linaro.org Signed-off-by: Peter Maydell --- target/arm/translate-a64.h | 2 ++ target/arm/translate.h | 2 -- target/arm/translate-a64.c | 7 +++++++ target/arm/translate-vfp.inc.c | 3 ++- target/arm/translate.c | 22 ++++++++++------------ 5 files changed, 21 insertions(+), 15 deletions(-) diff --git a/target/arm/translate-a64.h b/target/arm/translate-a64.h index 12ad8ac6ed1..9cd2b3d2389 100644 --- a/target/arm/translate-a64.h +++ b/target/arm/translate-a64.h @@ -18,6 +18,8 @@ #ifndef TARGET_ARM_TRANSLATE_A64_H #define TARGET_ARM_TRANSLATE_A64_H +void unallocated_encoding(DisasContext *s); + #define unsupported_encoding(s, insn) \ do { \ qemu_log_mask(LOG_UNIMP, \ diff --git a/target/arm/translate.h b/target/arm/translate.h index 92ef790be9e..64304c957ee 100644 --- a/target/arm/translate.h +++ b/target/arm/translate.h @@ -99,8 +99,6 @@ typedef struct DisasCompare { bool value_global; } DisasCompare; -void unallocated_encoding(DisasContext *s); - /* Share the TCG temporaries common between 32 and 64 bit modes. */ extern TCGv_i32 cpu_NF, cpu_ZF, cpu_CF, cpu_VF; extern TCGv_i64 cpu_exclusive_addr; diff --git a/target/arm/translate-a64.c b/target/arm/translate-a64.c index 6fd0b779d37..9183f89ba39 100644 --- a/target/arm/translate-a64.c +++ b/target/arm/translate-a64.c @@ -338,6 +338,13 @@ static inline void gen_goto_tb(DisasContext *s, int n, uint64_t dest) } } +void unallocated_encoding(DisasContext *s) +{ + /* Unallocated and reserved encodings are uncategorized */ + gen_exception_insn(s, s->pc_curr, EXCP_UDEF, syn_uncategorized(), + default_exception_el(s)); +} + static void init_tmp_a64_array(DisasContext *s) { #ifdef CONFIG_DEBUG_TCG diff --git a/target/arm/translate-vfp.inc.c b/target/arm/translate-vfp.inc.c index 3e8ea80493b..5065d4524cd 100644 --- a/target/arm/translate-vfp.inc.c +++ b/target/arm/translate-vfp.inc.c @@ -108,7 +108,8 @@ static bool full_vfp_access_check(DisasContext *s, bool ignore_vfp_enabled) if (!s->vfp_enabled && !ignore_vfp_enabled) { assert(!arm_dc_feature(s, ARM_FEATURE_M)); - unallocated_encoding(s); + gen_exception_insn(s, s->pc_curr, EXCP_UDEF, syn_uncategorized(), + default_exception_el(s)); return false; } diff --git a/target/arm/translate.c b/target/arm/translate.c index cbe19b7a625..2aac9aae681 100644 --- a/target/arm/translate.c +++ b/target/arm/translate.c @@ -1231,13 +1231,6 @@ static void gen_exception_bkpt_insn(DisasContext *s, uint32_t syn) s->base.is_jmp = DISAS_NORETURN; } -void unallocated_encoding(DisasContext *s) -{ - /* Unallocated and reserved encodings are uncategorized */ - gen_exception_insn(s, s->pc_curr, EXCP_UDEF, syn_uncategorized(), - default_exception_el(s)); -} - /* Force a TB lookup after an instruction that changes the CPU state. */ static inline void gen_lookup_tb(DisasContext *s) { @@ -1268,7 +1261,8 @@ static inline void gen_hlt(DisasContext *s, int imm) return; } - unallocated_encoding(s); + gen_exception_insn(s, s->pc_curr, EXCP_UDEF, syn_uncategorized(), + default_exception_el(s)); } static inline void gen_add_data_offset(DisasContext *s, unsigned int insn, @@ -7580,7 +7574,8 @@ static void gen_srs(DisasContext *s, } if (undef) { - unallocated_encoding(s); + gen_exception_insn(s, s->pc_curr, EXCP_UDEF, syn_uncategorized(), + default_exception_el(s)); return; } @@ -9201,7 +9196,8 @@ static void disas_arm_insn(DisasContext *s, unsigned int insn) break; default: illegal_op: - unallocated_encoding(s); + gen_exception_insn(s, s->pc_curr, EXCP_UDEF, syn_uncategorized(), + default_exception_el(s)); break; } } @@ -10886,7 +10882,8 @@ static void disas_thumb2_insn(DisasContext *s, uint32_t insn) } return; illegal_op: - unallocated_encoding(s); + gen_exception_insn(s, s->pc_curr, EXCP_UDEF, syn_uncategorized(), + default_exception_el(s)); } static void disas_thumb_insn(DisasContext *s, uint32_t insn) @@ -11709,7 +11706,8 @@ static void disas_thumb_insn(DisasContext *s, uint32_t insn) return; illegal_op: undef: - unallocated_encoding(s); + gen_exception_insn(s, s->pc_curr, EXCP_UDEF, syn_uncategorized(), + default_exception_el(s)); } static bool insn_crosses_page(CPUARMState *env, DisasContext *s) From patchwork Tue Sep 3 15:36:14 2019 Content-Type: text/plain; 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[81.2.115.148]) by smtp.gmail.com with ESMTPSA id a18sm24435188wrt.18.2019.09.03.08.36.37 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 03 Sep 2019 08:36:37 -0700 (PDT) From: Peter Maydell To: qemu-devel@nongnu.org Date: Tue, 3 Sep 2019 16:36:14 +0100 Message-Id: <20190903153633.6651-3-peter.maydell@linaro.org> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20190903153633.6651-1-peter.maydell@linaro.org> References: <20190903153633.6651-1-peter.maydell@linaro.org> MIME-Version: 1.0 X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2a00:1450:4864:20::335 Subject: [Qemu-devel] [PULL 02/21] target/arm: Factor out unallocated_encoding for aarch32 X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patchwork-qemu-devel=patchwork.kernel.org@nongnu.org Sender: "Qemu-devel" From: Richard Henderson Make this a static function private to translate.c. Thus we can use the same idiom between aarch64 and aarch32 without actually sharing function implementations. Signed-off-by: Richard Henderson Reviewed-by: Laurent Desnogues Message-id: 20190826151536.6771-3-richard.henderson@linaro.org Signed-off-by: Peter Maydell --- target/arm/translate-vfp.inc.c | 3 +-- target/arm/translate.c | 22 ++++++++++++---------- 2 files changed, 13 insertions(+), 12 deletions(-) diff --git a/target/arm/translate-vfp.inc.c b/target/arm/translate-vfp.inc.c index 5065d4524cd..3e8ea80493b 100644 --- a/target/arm/translate-vfp.inc.c +++ b/target/arm/translate-vfp.inc.c @@ -108,8 +108,7 @@ static bool full_vfp_access_check(DisasContext *s, bool ignore_vfp_enabled) if (!s->vfp_enabled && !ignore_vfp_enabled) { assert(!arm_dc_feature(s, ARM_FEATURE_M)); - gen_exception_insn(s, s->pc_curr, EXCP_UDEF, syn_uncategorized(), - default_exception_el(s)); + unallocated_encoding(s); return false; } diff --git a/target/arm/translate.c b/target/arm/translate.c index 2aac9aae681..66311580c05 100644 --- a/target/arm/translate.c +++ b/target/arm/translate.c @@ -1231,6 +1231,13 @@ static void gen_exception_bkpt_insn(DisasContext *s, uint32_t syn) s->base.is_jmp = DISAS_NORETURN; } +static void unallocated_encoding(DisasContext *s) +{ + /* Unallocated and reserved encodings are uncategorized */ + gen_exception_insn(s, s->pc_curr, EXCP_UDEF, syn_uncategorized(), + default_exception_el(s)); +} + /* Force a TB lookup after an instruction that changes the CPU state. */ static inline void gen_lookup_tb(DisasContext *s) { @@ -1261,8 +1268,7 @@ static inline void gen_hlt(DisasContext *s, int imm) return; } - gen_exception_insn(s, s->pc_curr, EXCP_UDEF, syn_uncategorized(), - default_exception_el(s)); + unallocated_encoding(s); } static inline void gen_add_data_offset(DisasContext *s, unsigned int insn, @@ -7574,8 +7580,7 @@ static void gen_srs(DisasContext *s, } if (undef) { - gen_exception_insn(s, s->pc_curr, EXCP_UDEF, syn_uncategorized(), - default_exception_el(s)); + unallocated_encoding(s); return; } @@ -9196,8 +9201,7 @@ static void disas_arm_insn(DisasContext *s, unsigned int insn) break; default: illegal_op: - gen_exception_insn(s, s->pc_curr, EXCP_UDEF, syn_uncategorized(), - default_exception_el(s)); + unallocated_encoding(s); break; } } @@ -10882,8 +10886,7 @@ static void disas_thumb2_insn(DisasContext *s, uint32_t insn) } return; illegal_op: - gen_exception_insn(s, s->pc_curr, EXCP_UDEF, syn_uncategorized(), - default_exception_el(s)); + unallocated_encoding(s); } static void disas_thumb_insn(DisasContext *s, uint32_t insn) @@ -11706,8 +11709,7 @@ static void disas_thumb_insn(DisasContext *s, uint32_t insn) return; illegal_op: undef: - gen_exception_insn(s, s->pc_curr, EXCP_UDEF, syn_uncategorized(), - default_exception_el(s)); + unallocated_encoding(s); } static bool insn_crosses_page(CPUARMState *env, DisasContext *s) From patchwork Tue Sep 3 15:36:15 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Peter Maydell X-Patchwork-Id: 11128281 Return-Path: Received: from mail.kernel.org (pdx-korg-mail-1.web.codeaurora.org [172.30.200.123]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id 0A51216B1 for ; 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[81.2.115.148]) by smtp.gmail.com with ESMTPSA id a18sm24435188wrt.18.2019.09.03.08.36.38 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 03 Sep 2019 08:36:39 -0700 (PDT) From: Peter Maydell To: qemu-devel@nongnu.org Date: Tue, 3 Sep 2019 16:36:15 +0100 Message-Id: <20190903153633.6651-4-peter.maydell@linaro.org> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20190903153633.6651-1-peter.maydell@linaro.org> References: <20190903153633.6651-1-peter.maydell@linaro.org> MIME-Version: 1.0 X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2a00:1450:4864:20::341 Subject: [Qemu-devel] [PULL 03/21] target/arm: Allow ARMCPRegInfo read/write functions to throw exceptions X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patchwork-qemu-devel=patchwork.kernel.org@nongnu.org Sender: "Qemu-devel" Currently the only part of an ARMCPRegInfo which is allowed to cause a CPU exception is the access function, which returns a value indicating that some flavour of UNDEF should be generated. For the ATS system instructions, we would like to conditionally generate exceptions as part of the writefn, because some faults during the page table walk (like external aborts) should cause an exception to be raised rather than returning a value. There are several ways we could do this: * plumb the GETPC() value from the top level set_cp_reg/get_cp_reg helper functions through into the readfn and writefn hooks * add extra readfn_with_ra/writefn_with_ra hooks that take the GETPC() value * require the ATS instructions to provide a dummy accessfn, which serves no purpose except to cause the code generation to emit TCG ops to sync the CPU state * add an ARM_CP_ flag to mark the ARMCPRegInfo as possibly throwing an exception in its read/write hooks, and make the codegen sync the CPU state before calling the hooks if the flag is set This patch opts for the last of these, as it is fairly simple to implement and doesn't require invasive changes like updating the readfn/writefn hook function prototype signature. Signed-off-by: Peter Maydell Reviewed-by: Richard Henderson Tested-by: Edgar E. Iglesias Message-id: 20190816125802.25877-2-peter.maydell@linaro.org --- target/arm/cpu.h | 6 +++++- target/arm/translate-a64.c | 6 ++++++ target/arm/translate.c | 7 +++++++ 3 files changed, 18 insertions(+), 1 deletion(-) diff --git a/target/arm/cpu.h b/target/arm/cpu.h index 0981303170a..297ad5e47ad 100644 --- a/target/arm/cpu.h +++ b/target/arm/cpu.h @@ -2212,6 +2212,9 @@ static inline uint64_t cpreg_to_kvm_id(uint32_t cpregid) * IO indicates that this register does I/O and therefore its accesses * need to be surrounded by gen_io_start()/gen_io_end(). In particular, * registers which implement clocks or timers require this. + * RAISES_EXC is for when the read or write hook might raise an exception; + * the generated code will synchronize the CPU state before calling the hook + * so that it is safe for the hook to call raise_exception(). */ #define ARM_CP_SPECIAL 0x0001 #define ARM_CP_CONST 0x0002 @@ -2230,10 +2233,11 @@ static inline uint64_t cpreg_to_kvm_id(uint32_t cpregid) #define ARM_CP_FPU 0x1000 #define ARM_CP_SVE 0x2000 #define ARM_CP_NO_GDB 0x4000 +#define ARM_CP_RAISES_EXC 0x8000 /* Used only as a terminator for ARMCPRegInfo lists */ #define ARM_CP_SENTINEL 0xffff /* Mask of only the flag bits in a type field */ -#define ARM_CP_FLAG_MASK 0x70ff +#define ARM_CP_FLAG_MASK 0xf0ff /* Valid values for ARMCPRegInfo state field, indicating which of * the AArch32 and AArch64 execution states this register is visible in. diff --git a/target/arm/translate-a64.c b/target/arm/translate-a64.c index 9183f89ba39..4d09ae6f424 100644 --- a/target/arm/translate-a64.c +++ b/target/arm/translate-a64.c @@ -1714,6 +1714,12 @@ static void handle_sys(DisasContext *s, uint32_t insn, bool isread, tcg_temp_free_ptr(tmpptr); tcg_temp_free_i32(tcg_syn); tcg_temp_free_i32(tcg_isread); + } else if (ri->type & ARM_CP_RAISES_EXC) { + /* + * The readfn or writefn might raise an exception; + * synchronize the CPU state in case it does. + */ + gen_a64_set_pc_im(s->pc_curr); } /* Handle special cases first */ diff --git a/target/arm/translate.c b/target/arm/translate.c index 66311580c05..78d93f63cab 100644 --- a/target/arm/translate.c +++ b/target/arm/translate.c @@ -7191,6 +7191,13 @@ static int disas_coproc_insn(DisasContext *s, uint32_t insn) tcg_temp_free_ptr(tmpptr); tcg_temp_free_i32(tcg_syn); tcg_temp_free_i32(tcg_isread); + } else if (ri->type & ARM_CP_RAISES_EXC) { + /* + * The readfn or writefn might raise an exception; + * synchronize the CPU state in case it does. + */ + gen_set_condexec(s); + gen_set_pc_im(s, s->pc_curr); } /* Handle special cases first */ From patchwork Tue Sep 3 15:36:16 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Peter Maydell X-Patchwork-Id: 11128285 Return-Path: Received: from mail.kernel.org (pdx-korg-mail-1.web.codeaurora.org [172.30.200.123]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id 746EC14F7 for ; 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[81.2.115.148]) by smtp.gmail.com with ESMTPSA id a18sm24435188wrt.18.2019.09.03.08.36.39 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 03 Sep 2019 08:36:40 -0700 (PDT) From: Peter Maydell To: qemu-devel@nongnu.org Date: Tue, 3 Sep 2019 16:36:16 +0100 Message-Id: <20190903153633.6651-5-peter.maydell@linaro.org> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20190903153633.6651-1-peter.maydell@linaro.org> References: <20190903153633.6651-1-peter.maydell@linaro.org> MIME-Version: 1.0 X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2a00:1450:4864:20::344 Subject: [Qemu-devel] [PULL 04/21] target/arm: Take exceptions on ATS instructions when needed X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patchwork-qemu-devel=patchwork.kernel.org@nongnu.org Sender: "Qemu-devel" The translation table walk for an ATS instruction can result in various faults. In general these are just reported back via the PAR_EL1 fault status fields, but in some cases the architecture requires that the fault is turned into an exception: * synchronous stage 2 faults of any kind during AT S1E0* and AT S1E1* instructions executed from NS EL1 fault to EL2 or EL3 * synchronous external aborts are taken as Data Abort exceptions (This is documented in the v8A Arm ARM DDI0487A.e D5.2.11 and G5.13.4.) Signed-off-by: Peter Maydell Reviewed-by: Richard Henderson Tested-by: Edgar E. Iglesias Message-id: 20190816125802.25877-3-peter.maydell@linaro.org --- target/arm/helper.c | 107 +++++++++++++++++++++++++++++++++++++------- 1 file changed, 92 insertions(+), 15 deletions(-) diff --git a/target/arm/helper.c b/target/arm/helper.c index 7e0d5398ab8..507026c9154 100644 --- a/target/arm/helper.c +++ b/target/arm/helper.c @@ -2946,6 +2946,73 @@ static uint64_t do_ats_write(CPUARMState *env, uint64_t value, ret = get_phys_addr(env, value, access_type, mmu_idx, &phys_addr, &attrs, &prot, &page_size, &fi, &cacheattrs); + if (ret) { + /* + * Some kinds of translation fault must cause exceptions rather + * than being reported in the PAR. + */ + int current_el = arm_current_el(env); + int target_el; + uint32_t syn, fsr, fsc; + bool take_exc = false; + + if (fi.s1ptw && current_el == 1 && !arm_is_secure(env) + && (mmu_idx == ARMMMUIdx_S1NSE1 || mmu_idx == ARMMMUIdx_S1NSE0)) { + /* + * Synchronous stage 2 fault on an access made as part of the + * translation table walk for AT S1E0* or AT S1E1* insn + * executed from NS EL1. If this is a synchronous external abort + * and SCR_EL3.EA == 1, then we take a synchronous external abort + * to EL3. Otherwise the fault is taken as an exception to EL2, + * and HPFAR_EL2 holds the faulting IPA. + */ + if (fi.type == ARMFault_SyncExternalOnWalk && + (env->cp15.scr_el3 & SCR_EA)) { + target_el = 3; + } else { + env->cp15.hpfar_el2 = extract64(fi.s2addr, 12, 47) << 4; + target_el = 2; + } + take_exc = true; + } else if (fi.type == ARMFault_SyncExternalOnWalk) { + /* + * Synchronous external aborts during a translation table walk + * are taken as Data Abort exceptions. + */ + if (fi.stage2) { + if (current_el == 3) { + target_el = 3; + } else { + target_el = 2; + } + } else { + target_el = exception_target_el(env); + } + take_exc = true; + } + + if (take_exc) { + /* Construct FSR and FSC using same logic as arm_deliver_fault() */ + if (target_el == 2 || arm_el_is_aa64(env, target_el) || + arm_s1_regime_using_lpae_format(env, mmu_idx)) { + fsr = arm_fi_to_lfsc(&fi); + fsc = extract32(fsr, 0, 6); + } else { + fsr = arm_fi_to_sfsc(&fi); + fsc = 0x3f; + } + /* + * Report exception with ESR indicating a fault due to a + * translation table walk for a cache maintenance instruction. + */ + syn = syn_data_abort_no_iss(current_el == target_el, + fi.ea, 1, fi.s1ptw, 1, fsc); + env->exception.vaddress = value; + env->exception.fsr = fsr; + raise_exception(env, EXCP_DATA_ABORT, syn, target_el); + } + } + if (is_a64(env)) { format64 = true; } else if (arm_feature(env, ARM_FEATURE_LPAE)) { @@ -3150,7 +3217,7 @@ static const ARMCPRegInfo vapa_cp_reginfo[] = { /* This underdecoding is safe because the reginfo is NO_RAW. */ { .name = "ATS", .cp = 15, .crn = 7, .crm = 8, .opc1 = 0, .opc2 = CP_ANY, .access = PL1_W, .accessfn = ats_access, - .writefn = ats_write, .type = ARM_CP_NO_RAW }, + .writefn = ats_write, .type = ARM_CP_NO_RAW | ARM_CP_RAISES_EXC }, #endif REGINFO_SENTINEL }; @@ -4283,35 +4350,45 @@ static const ARMCPRegInfo v8_cp_reginfo[] = { /* 64 bit address translation operations */ { .name = "AT_S1E1R", .state = ARM_CP_STATE_AA64, .opc0 = 1, .opc1 = 0, .crn = 7, .crm = 8, .opc2 = 0, - .access = PL1_W, .type = ARM_CP_NO_RAW, .writefn = ats_write64 }, + .access = PL1_W, .type = ARM_CP_NO_RAW | ARM_CP_RAISES_EXC, + .writefn = ats_write64 }, { .name = "AT_S1E1W", .state = ARM_CP_STATE_AA64, .opc0 = 1, .opc1 = 0, .crn = 7, .crm = 8, .opc2 = 1, - .access = PL1_W, .type = ARM_CP_NO_RAW, .writefn = ats_write64 }, + .access = PL1_W, .type = ARM_CP_NO_RAW | ARM_CP_RAISES_EXC, + .writefn = ats_write64 }, { .name = "AT_S1E0R", .state = ARM_CP_STATE_AA64, .opc0 = 1, .opc1 = 0, .crn = 7, .crm = 8, .opc2 = 2, - .access = PL1_W, .type = ARM_CP_NO_RAW, .writefn = ats_write64 }, + .access = PL1_W, .type = ARM_CP_NO_RAW | ARM_CP_RAISES_EXC, + .writefn = ats_write64 }, { .name = "AT_S1E0W", .state = ARM_CP_STATE_AA64, .opc0 = 1, .opc1 = 0, .crn = 7, .crm = 8, .opc2 = 3, - .access = PL1_W, .type = ARM_CP_NO_RAW, .writefn = ats_write64 }, + .access = PL1_W, .type = ARM_CP_NO_RAW | ARM_CP_RAISES_EXC, + .writefn = ats_write64 }, { .name = "AT_S12E1R", .state = ARM_CP_STATE_AA64, .opc0 = 1, .opc1 = 4, .crn = 7, .crm = 8, .opc2 = 4, - .access = PL2_W, .type = ARM_CP_NO_RAW, .writefn = ats_write64 }, + .access = PL2_W, .type = ARM_CP_NO_RAW | ARM_CP_RAISES_EXC, + .writefn = ats_write64 }, { .name = "AT_S12E1W", .state = ARM_CP_STATE_AA64, .opc0 = 1, .opc1 = 4, .crn = 7, .crm = 8, .opc2 = 5, - .access = PL2_W, .type = ARM_CP_NO_RAW, .writefn = ats_write64 }, + .access = PL2_W, .type = ARM_CP_NO_RAW | ARM_CP_RAISES_EXC, + .writefn = ats_write64 }, { .name = "AT_S12E0R", .state = ARM_CP_STATE_AA64, .opc0 = 1, .opc1 = 4, .crn = 7, .crm = 8, .opc2 = 6, - .access = PL2_W, .type = ARM_CP_NO_RAW, .writefn = ats_write64 }, + .access = PL2_W, .type = ARM_CP_NO_RAW | ARM_CP_RAISES_EXC, + .writefn = ats_write64 }, { .name = "AT_S12E0W", .state = ARM_CP_STATE_AA64, .opc0 = 1, .opc1 = 4, .crn = 7, .crm = 8, .opc2 = 7, - .access = PL2_W, .type = ARM_CP_NO_RAW, .writefn = ats_write64 }, + .access = PL2_W, .type = ARM_CP_NO_RAW | ARM_CP_RAISES_EXC, + .writefn = ats_write64 }, /* AT S1E2* are elsewhere as they UNDEF from EL3 if EL2 is not present */ { .name = "AT_S1E3R", .state = ARM_CP_STATE_AA64, .opc0 = 1, .opc1 = 6, .crn = 7, .crm = 8, .opc2 = 0, - .access = PL3_W, .type = ARM_CP_NO_RAW, .writefn = ats_write64 }, + .access = PL3_W, .type = ARM_CP_NO_RAW | ARM_CP_RAISES_EXC, + .writefn = ats_write64 }, { .name = "AT_S1E3W", .state = ARM_CP_STATE_AA64, .opc0 = 1, .opc1 = 6, .crn = 7, .crm = 8, .opc2 = 1, - .access = PL3_W, .type = ARM_CP_NO_RAW, .writefn = ats_write64 }, + .access = PL3_W, .type = ARM_CP_NO_RAW | ARM_CP_RAISES_EXC, + .writefn = ats_write64 }, { .name = "PAR_EL1", .state = ARM_CP_STATE_AA64, .type = ARM_CP_ALIAS, .opc0 = 3, .opc1 = 0, .crn = 7, .crm = 4, .opc2 = 0, @@ -4893,11 +4970,11 @@ static const ARMCPRegInfo el2_cp_reginfo[] = { { .name = "AT_S1E2R", .state = ARM_CP_STATE_AA64, .opc0 = 1, .opc1 = 4, .crn = 7, .crm = 8, .opc2 = 0, .access = PL2_W, .accessfn = at_s1e2_access, - .type = ARM_CP_NO_RAW, .writefn = ats_write64 }, + .type = ARM_CP_NO_RAW | ARM_CP_RAISES_EXC, .writefn = ats_write64 }, { .name = "AT_S1E2W", .state = ARM_CP_STATE_AA64, .opc0 = 1, .opc1 = 4, .crn = 7, .crm = 8, .opc2 = 1, .access = PL2_W, .accessfn = at_s1e2_access, - .type = ARM_CP_NO_RAW, .writefn = ats_write64 }, + .type = ARM_CP_NO_RAW | ARM_CP_RAISES_EXC, .writefn = ats_write64 }, /* The AArch32 ATS1H* operations are CONSTRAINED UNPREDICTABLE * if EL2 is not implemented; we choose to UNDEF. Behaviour at EL3 * with SCR.NS == 0 outside Monitor mode is UNPREDICTABLE; we choose @@ -4905,10 +4982,10 @@ static const ARMCPRegInfo el2_cp_reginfo[] = { */ { .name = "ATS1HR", .cp = 15, .opc1 = 4, .crn = 7, .crm = 8, .opc2 = 0, .access = PL2_W, - .writefn = ats1h_write, .type = ARM_CP_NO_RAW }, + .writefn = ats1h_write, .type = ARM_CP_NO_RAW | ARM_CP_RAISES_EXC }, { .name = "ATS1HW", .cp = 15, .opc1 = 4, .crn = 7, .crm = 8, .opc2 = 1, .access = PL2_W, - .writefn = ats1h_write, .type = ARM_CP_NO_RAW }, + .writefn = ats1h_write, .type = ARM_CP_NO_RAW | ARM_CP_RAISES_EXC }, { .name = "CNTHCTL_EL2", .state = ARM_CP_STATE_BOTH, .opc0 = 3, .opc1 = 4, .crn = 14, .crm = 1, .opc2 = 0, /* ARMv7 requires bit 0 and 1 to reset to 1. ARMv8 defines the From patchwork Tue Sep 3 15:36:17 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Peter Maydell X-Patchwork-Id: 11128283 Return-Path: Received: from mail.kernel.org (pdx-korg-mail-1.web.codeaurora.org [172.30.200.123]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id 5772717EF for ; Tue, 3 Sep 2019 15:41:58 +0000 (UTC) Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id 2D7BC23774 for ; Tue, 3 Sep 2019 15:41:58 +0000 (UTC) Authentication-Results: mail.kernel.org; dkim=fail reason="signature verification failed" (2048-bit key) header.d=linaro.org header.i=@linaro.org header.b="LtU2+jem" DMARC-Filter: OpenDMARC Filter v1.3.2 mail.kernel.org 2D7BC23774 Authentication-Results: mail.kernel.org; dmarc=fail (p=none dis=none) header.from=linaro.org Authentication-Results: mail.kernel.org; spf=pass smtp.mailfrom=qemu-devel-bounces+patchwork-qemu-devel=patchwork.kernel.org@nongnu.org Received: from localhost ([::1]:47730 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1i5AwO-0008I7-Ok for patchwork-qemu-devel@patchwork.kernel.org; Tue, 03 Sep 2019 11:41:56 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:59181) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1i5ArN-0002l1-Iu for qemu-devel@nongnu.org; Tue, 03 Sep 2019 11:36:46 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1i5ArM-0005uN-58 for qemu-devel@nongnu.org; Tue, 03 Sep 2019 11:36:45 -0400 Received: from mail-wr1-x42b.google.com ([2a00:1450:4864:20::42b]:38082) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1i5ArL-0005tZ-UC for qemu-devel@nongnu.org; Tue, 03 Sep 2019 11:36:44 -0400 Received: by mail-wr1-x42b.google.com with SMTP id l11so9174222wrx.5 for ; Tue, 03 Sep 2019 08:36:43 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:subject:date:message-id:in-reply-to:references:mime-version :content-transfer-encoding; bh=m+TKKTWvRC4vo5fFotjFs4jfzAaPam+tpeNKcBhEHyY=; b=LtU2+jemSfwD3cFVVwWrgxblNdAATqWm5NFyBMUO6CWtPZvCewtBisJiMdHSqzzjxd UEJ3i0QHH/mEmLlCjO1W4QbnEqyc2TWnWCCk2CtJKTgLXykZmG8vRJzSJbYTMe44UE4A UYI3R87slDe5vJSYkR6YMLu15Z9SH4wFhzv5SW8MtDP3bvoc5gi+6JH00Pm7ZHSda10b sMrZKgTKjP3BEzm+mgiFUgHZKCD/fYv5aF6qqccxO0iHYvFEVjHURZjkJFsmg3Kui8sS Z5fUZMwTGC0tE2d9d/BLdXI0itzL0SxecOj05oGsC48vpjxGDd2O4GQ5JFd9UQD48fm5 rNIg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=m+TKKTWvRC4vo5fFotjFs4jfzAaPam+tpeNKcBhEHyY=; b=PbM8eYg3Uz2yIWQ5kC9h+WFGwz+EtRUgnVOzc7Dxn9C7I24c6gelXZJJq7WB8dRdRh tQrP5nBXRbhUkdSo5UmLjCNBpD2KYzxO2tSDouawXJQ8kj9CXMSQ6g5wj5taXmeWUgUL c5F8DOB5U4A+ZRNt8760ZiAQzIrnvyUmOluHOwU6cn3XwcgWVef/x54shm+Uimu06Mw6 JxvbptKhUMbP6O/Pnj+9M4IdYHRWERlaGpLvifHb0ABcodOV0UpbdL0b2JXwAgml7RR1 51DKvit7hkcnva1QR5ra+Cf54Gy/fjQ4FjWBVWkEpaXKqRNgcRiB/TKQSkm2wZjK4Ymm RXKA== X-Gm-Message-State: APjAAAWj84vPMT2sivmoBmB5xkI2I8YoPoLAR0bHyaMglc+UdFUb8rpL rCiphZWSG15tR1ATTZjXuSHkoazTv4u5Og== X-Google-Smtp-Source: APXvYqxhjK5DkqNH5wtFReeiGX3+PCjtlmg7w0+jK7tirA/FbpzrLooG1gzfrcPwZ7Lv6UMt8tBf5Q== X-Received: by 2002:a5d:6ac8:: with SMTP id u8mr7732013wrw.104.1567525002604; Tue, 03 Sep 2019 08:36:42 -0700 (PDT) Received: from orth.archaic.org.uk (orth.archaic.org.uk. [81.2.115.148]) by smtp.gmail.com with ESMTPSA id a18sm24435188wrt.18.2019.09.03.08.36.41 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 03 Sep 2019 08:36:41 -0700 (PDT) From: Peter Maydell To: qemu-devel@nongnu.org Date: Tue, 3 Sep 2019 16:36:17 +0100 Message-Id: <20190903153633.6651-6-peter.maydell@linaro.org> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20190903153633.6651-1-peter.maydell@linaro.org> References: <20190903153633.6651-1-peter.maydell@linaro.org> MIME-Version: 1.0 X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2a00:1450:4864:20::42b Subject: [Qemu-devel] [PULL 05/21] aspeed/timer: Provide back-pressure information for short periods X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patchwork-qemu-devel=patchwork.kernel.org@nongnu.org Sender: "Qemu-devel" From: Andrew Jeffery First up: This is not the way the hardware behaves. However, it helps resolve real-world problems with short periods being used under Linux. Commit 4451d3f59f2a ("clocksource/drivers/fttmr010: Fix set_next_event handler") in Linux fixed the timer driver to correctly schedule the next event for the Aspeed controller, and in combination with 5daa8212c08e ("ARM: dts: aspeed: Describe random number device") Linux will now set a timer with a period as low as 1us. Configuring a qemu timer with such a short period results in spending time handling the interrupt in the model rather than executing guest code, leading to noticeable "sticky" behaviour in the guest. The behaviour of Linux is correct with respect to the hardware, so we need to improve our handling under emulation. The approach chosen is to provide back-pressure information by calculating an acceptable minimum number of ticks to be set on the model. Under Linux an additional read is added in the timer configuration path to detect back-pressure, which will never occur on hardware. However if back-pressure is observed, the driver alerts the clock event subsystem, which then performs its own next event dilation via a config option - d1748302f70b ("clockevents: Make minimum delay adjustments configurable") A minimum period of 5us was experimentally determined on a Lenovo T480s, which I've increased to 20us for "safety". Signed-off-by: Andrew Jeffery Reviewed-by: Joel Stanley Reviewed-by: Philippe Mathieu-Daudé Tested-by: Joel Stanley Signed-off-by: Cédric Le Goater Message-id: 20190704055150.4899-1-clg@kaod.org [clg: - changed the computation of min_ticks to be done each time the timer value is reloaded. It removes the ordering issue of the timer and scu reset handlers but is slightly slower ] - introduced TIMER_MIN_NS - introduced calculate_min_ticks() ] Signed-off-by: Cédric Le Goater Signed-off-by: Peter Maydell --- hw/timer/aspeed_timer.c | 17 ++++++++++++++++- 1 file changed, 16 insertions(+), 1 deletion(-) diff --git a/hw/timer/aspeed_timer.c b/hw/timer/aspeed_timer.c index ed81d5c44c7..59c2bbeee60 100644 --- a/hw/timer/aspeed_timer.c +++ b/hw/timer/aspeed_timer.c @@ -44,6 +44,13 @@ enum timer_ctrl_op { op_pulse_enable }; +/* + * Minimum value of the reload register to filter out short period + * timers which have a noticeable impact in emulation. 5us should be + * enough, use 20us for "safety". + */ +#define TIMER_MIN_NS (20 * SCALE_US) + /** * Avoid mutual references between AspeedTimerCtrlState and AspeedTimer * structs, as it's a waste of memory. The ptimer BH callback needs to know @@ -98,6 +105,14 @@ static inline uint32_t calculate_ticks(struct AspeedTimer *t, uint64_t now_ns) return t->reload - MIN(t->reload, ticks); } +static uint32_t calculate_min_ticks(AspeedTimer *t, uint32_t value) +{ + uint32_t rate = calculate_rate(t); + uint32_t min_ticks = muldiv64(TIMER_MIN_NS, rate, NANOSECONDS_PER_SECOND); + + return value < min_ticks ? min_ticks : value; +} + static inline uint64_t calculate_time(struct AspeedTimer *t, uint32_t ticks) { uint64_t delta_ns; @@ -261,7 +276,7 @@ static void aspeed_timer_set_value(AspeedTimerCtrlState *s, int timer, int reg, switch (reg) { case TIMER_REG_RELOAD: old_reload = t->reload; - t->reload = value; + t->reload = calculate_min_ticks(t, value); /* If the reload value was not previously set, or zero, and * the current value is valid, try to start the timer if it is From patchwork Tue Sep 3 15:36:18 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Peter Maydell X-Patchwork-Id: 11128289 Return-Path: Received: from mail.kernel.org (pdx-korg-mail-1.web.codeaurora.org [172.30.200.123]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id 2E22213B1 for ; Tue, 3 Sep 2019 15:46:50 +0000 (UTC) Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id 0265C2077B for ; Tue, 3 Sep 2019 15:46:50 +0000 (UTC) Authentication-Results: mail.kernel.org; dkim=fail reason="signature verification failed" (2048-bit key) header.d=linaro.org header.i=@linaro.org header.b="jtOX8o8a" DMARC-Filter: OpenDMARC Filter v1.3.2 mail.kernel.org 0265C2077B Authentication-Results: mail.kernel.org; dmarc=fail (p=none dis=none) header.from=linaro.org Authentication-Results: mail.kernel.org; spf=pass smtp.mailfrom=qemu-devel-bounces+patchwork-qemu-devel=patchwork.kernel.org@nongnu.org Received: from localhost ([::1]:47788 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1i5B16-0003c2-2j for patchwork-qemu-devel@patchwork.kernel.org; Tue, 03 Sep 2019 11:46:48 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:59194) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1i5ArO-0002mQ-KR for qemu-devel@nongnu.org; Tue, 03 Sep 2019 11:36:47 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1i5ArN-0005vE-9x for qemu-devel@nongnu.org; Tue, 03 Sep 2019 11:36:46 -0400 Received: from mail-wr1-x435.google.com ([2a00:1450:4864:20::435]:35654) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1i5ArN-0005uc-3i for qemu-devel@nongnu.org; Tue, 03 Sep 2019 11:36:45 -0400 Received: by mail-wr1-x435.google.com with SMTP id g7so18034427wrx.2 for ; Tue, 03 Sep 2019 08:36:45 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:subject:date:message-id:in-reply-to:references:mime-version :content-transfer-encoding; bh=NH3h4g6hlFhS6RKG3sIpGzTOMf5SCVInEe1V7vBG3qg=; b=jtOX8o8auFMGzcrCxB3sDZjE0P/pUUOUS1eLpjgznJPW5k+JqxaO6x2RwfJ/E9XU72 FL8x8XUij3JXYpngGMtEFf5D8XXrW95TgEyT56ekRn84SHWAb38/s1E1CblICNayx/s9 ma95EjmuUy8NTc72TpJT/mtfkhWOPdRRcAEHqADf8ZrvuHSfcK8QxIGwKXR5R+/sO+wI xDAiF62eokHL/Y8zFvDY0LcXgcfVY4C38l+k875wHUrJGyhAi/dHYTXAj8GDwABntoL1 MTrFSEQzkgynUAbRfNC9YsOG/YsH2RnjEi4XnSCBo/bqqo9E1LMsP6m53NC0RGrH/cY/ CEeA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=NH3h4g6hlFhS6RKG3sIpGzTOMf5SCVInEe1V7vBG3qg=; b=C1dwUBkhTPeC6nmE84kgwL9om0X2r59McqkDj0WObhTKPV9ipDVK0AVdb6CicBs7ps SqevrnOUqyDKlZ95cRmwfncxs4Nh4qRi4UkXEw3q++4aXGz8MsHcLMloSoUj2Jsp686f xWip/CVM5ZHNZyvIkS8ixUA3sztqWwC9D7fA+j+7wFPVYk1fu7ipOtRRdXY/lO6YS/pm b2t1mmoqFKAcVSUvt69/wTn31KSnAJv7p9aFpQKtyIkc2NpaXOUj0iZ0YKrx9lY38Mrb BblRSHMOxnpvCqnJg6NP7P9WZA5x411XD77vmH4y2M3vSnYCs6dIp8f+w6xoySWhDE5q agGQ== X-Gm-Message-State: APjAAAUipdff4vSWdZWfqZMnBRgmM/dG/nyUwEO2nBOf3x1hxZag5Mb/ jaf9v46MU+rqs2hhZCtLBKlkZPQs+XOd4A== X-Google-Smtp-Source: APXvYqwCMgmyCLGLfOq74oSrV6xyF0mt1fKoM5Es+YOSXm8R+uQv2qRzjaeagkArVyZV0zmgj6l2HA== X-Received: by 2002:adf:e74c:: with SMTP id c12mr7481836wrn.173.1567525003715; Tue, 03 Sep 2019 08:36:43 -0700 (PDT) Received: from orth.archaic.org.uk (orth.archaic.org.uk. [81.2.115.148]) by smtp.gmail.com with ESMTPSA id a18sm24435188wrt.18.2019.09.03.08.36.42 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 03 Sep 2019 08:36:42 -0700 (PDT) From: Peter Maydell To: qemu-devel@nongnu.org Date: Tue, 3 Sep 2019 16:36:18 +0100 Message-Id: <20190903153633.6651-7-peter.maydell@linaro.org> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20190903153633.6651-1-peter.maydell@linaro.org> References: <20190903153633.6651-1-peter.maydell@linaro.org> MIME-Version: 1.0 X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2a00:1450:4864:20::435 Subject: [Qemu-devel] [PULL 06/21] memory: Remove unused memory_region_iommu_replay_all() X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patchwork-qemu-devel=patchwork.kernel.org@nongnu.org Sender: "Qemu-devel" From: Eric Auger memory_region_iommu_replay_all is not used. Remove it. Signed-off-by: Eric Auger Reported-by: Peter Maydell Reviewed-by: Philippe Mathieu-Daudé Reviewed-by: Peter Xu Message-id: 20190822172350.12008-2-eric.auger@redhat.com Signed-off-by: Peter Maydell --- include/exec/memory.h | 10 ---------- memory.c | 9 --------- 2 files changed, 19 deletions(-) diff --git a/include/exec/memory.h b/include/exec/memory.h index fddc2ff48a7..ecca388e69d 100644 --- a/include/exec/memory.h +++ b/include/exec/memory.h @@ -1086,16 +1086,6 @@ void memory_region_register_iommu_notifier(MemoryRegion *mr, */ void memory_region_iommu_replay(IOMMUMemoryRegion *iommu_mr, IOMMUNotifier *n); -/** - * memory_region_iommu_replay_all: replay existing IOMMU translations - * to all the notifiers registered. - * - * Note: this is not related to record-and-replay functionality. - * - * @iommu_mr: the memory region to observe - */ -void memory_region_iommu_replay_all(IOMMUMemoryRegion *iommu_mr); - /** * memory_region_unregister_iommu_notifier: unregister a notifier for * changes to IOMMU translation entries. diff --git a/memory.c b/memory.c index 7fd93b1d42d..a23ff3cc2ac 100644 --- a/memory.c +++ b/memory.c @@ -1922,15 +1922,6 @@ void memory_region_iommu_replay(IOMMUMemoryRegion *iommu_mr, IOMMUNotifier *n) } } -void memory_region_iommu_replay_all(IOMMUMemoryRegion *iommu_mr) -{ - IOMMUNotifier *notifier; - - IOMMU_NOTIFIER_FOREACH(notifier, iommu_mr) { - memory_region_iommu_replay(iommu_mr, notifier); - } -} - void memory_region_unregister_iommu_notifier(MemoryRegion *mr, IOMMUNotifier *n) { From patchwork Tue Sep 3 15:36:19 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Peter Maydell X-Patchwork-Id: 11128291 Return-Path: Received: from mail.kernel.org (pdx-korg-mail-1.web.codeaurora.org [172.30.200.123]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id A84801398 for ; Tue, 3 Sep 2019 15:46:51 +0000 (UTC) Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id 7E12E2077B for ; Tue, 3 Sep 2019 15:46:51 +0000 (UTC) Authentication-Results: mail.kernel.org; dkim=fail reason="signature verification failed" (2048-bit key) header.d=linaro.org header.i=@linaro.org header.b="X4G4gp8m" DMARC-Filter: OpenDMARC Filter v1.3.2 mail.kernel.org 7E12E2077B Authentication-Results: mail.kernel.org; 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[81.2.115.148]) by smtp.gmail.com with ESMTPSA id a18sm24435188wrt.18.2019.09.03.08.36.43 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 03 Sep 2019 08:36:44 -0700 (PDT) From: Peter Maydell To: qemu-devel@nongnu.org Date: Tue, 3 Sep 2019 16:36:19 +0100 Message-Id: <20190903153633.6651-8-peter.maydell@linaro.org> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20190903153633.6651-1-peter.maydell@linaro.org> References: <20190903153633.6651-1-peter.maydell@linaro.org> MIME-Version: 1.0 X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2a00:1450:4864:20::434 Subject: [Qemu-devel] [PULL 07/21] hw/arm/smmuv3: Log a guest error when decoding an invalid STE X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patchwork-qemu-devel=patchwork.kernel.org@nongnu.org Sender: "Qemu-devel" From: Eric Auger Log a guest error when encountering an invalid STE. Signed-off-by: Eric Auger Reviewed-by: Philippe Mathieu-Daudé Message-id: 20190822172350.12008-5-eric.auger@redhat.com Signed-off-by: Peter Maydell --- hw/arm/smmuv3.c | 1 + 1 file changed, 1 insertion(+) diff --git a/hw/arm/smmuv3.c b/hw/arm/smmuv3.c index 2eaf07fb5f6..31ac4b15c30 100644 --- a/hw/arm/smmuv3.c +++ b/hw/arm/smmuv3.c @@ -320,6 +320,7 @@ static int decode_ste(SMMUv3State *s, SMMUTransCfg *cfg, uint32_t config; if (!STE_VALID(ste)) { + qemu_log_mask(LOG_GUEST_ERROR, "invalid STE\n"); goto bad_ste; } From patchwork Tue Sep 3 15:36:20 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Peter Maydell X-Patchwork-Id: 11128299 Return-Path: Received: from mail.kernel.org (pdx-korg-mail-1.web.codeaurora.org [172.30.200.123]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id C9DBE1398 for ; Tue, 3 Sep 2019 15:50:47 +0000 (UTC) Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id A030A2343A for ; Tue, 3 Sep 2019 15:50:47 +0000 (UTC) Authentication-Results: mail.kernel.org; dkim=fail reason="signature verification failed" (2048-bit key) header.d=linaro.org header.i=@linaro.org header.b="o91Y+kEZ" DMARC-Filter: OpenDMARC Filter v1.3.2 mail.kernel.org A030A2343A Authentication-Results: mail.kernel.org; dmarc=fail (p=none dis=none) header.from=linaro.org Authentication-Results: mail.kernel.org; spf=pass smtp.mailfrom=qemu-devel-bounces+patchwork-qemu-devel=patchwork.kernel.org@nongnu.org Received: from localhost ([::1]:47870 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1i5B4w-0007SG-Gh for patchwork-qemu-devel@patchwork.kernel.org; Tue, 03 Sep 2019 11:50:46 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:59220) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1i5ArQ-0002ov-7f for qemu-devel@nongnu.org; Tue, 03 Sep 2019 11:36:49 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1i5ArO-0005wO-Uf for qemu-devel@nongnu.org; Tue, 03 Sep 2019 11:36:48 -0400 Received: from mail-wr1-x434.google.com ([2a00:1450:4864:20::434]:37757) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1i5ArO-0005w0-ON for qemu-devel@nongnu.org; Tue, 03 Sep 2019 11:36:46 -0400 Received: by mail-wr1-x434.google.com with SMTP id z11so17998295wrt.4 for ; Tue, 03 Sep 2019 08:36:46 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:subject:date:message-id:in-reply-to:references:mime-version :content-transfer-encoding; bh=zwgsbRC7S/9tqfeU7JxypMKTOKpf8DEKt23oGutI3as=; b=o91Y+kEZ9ekJhZ76S0+e42h5hPE+3kvnLpVzMB6dhI+DFwhhNUYHILeaREJX1UJzKl oVdSpgzLxEAdhulwoDfUTWicwSlMXkWsMT2J3OZ1oKmi2FAQsaeluiatxD5Y4+Lvyqi1 o+7XHPB8iWqEEeefzKQpvmudreDJ0UYXfrviw+EAFct0zrOG/YgMUE39nhZ59LuxPzdu TSC+g8j1KOtChSr1V97Im4Q6/VH0bsaeyKkHc+Og7rYiXBy8KGEndtSfJFPZ3hZNZQWO Cac6bQVFLX9jwi9BkBMufl5/48Nm9zMN3P5PLzMbqSgrSfsfzUYU9Lr0GmZHEzA7Ll27 mhaA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=zwgsbRC7S/9tqfeU7JxypMKTOKpf8DEKt23oGutI3as=; b=pr77NqenQARtAYF08SKV+iOuYlFHnHYmfSwD8OpdULhQIQPBk3dARc59ZF1oyagKzl IoUxhIGD3E4xMC8c8e/IfOqPaZ9I9aSE+uv7FrMzCpE8PUrKKlHHtuC+H3Q9Nbxvwy8m Yxa0XOBXKHS0buCydCAo28ulLFjORpz+pcL79ptcBx2nj+QLpNj7AhMaDctD58FG4fxy w/Zh7WckMQg+1EvlRU4kTvD5uf5mnosiZfOuWFiHzFCJYaH8z1bmN+8/wBtEhC9MMSjy 8iVpnqz7weKI5ka694nkEXgH4EugBh7PGIvrIOYL0fUVuZuq16Ft65YqNxSK86UNN8p3 VaCQ== X-Gm-Message-State: APjAAAV3XaOlFuu1trcJckr0Lb+CPcVmyRWJM3Lap5nv6q3PeofBlL/G OBHyFeu/lagQDQMIAdUeXciyWUHHF5E2AA== X-Google-Smtp-Source: APXvYqyxfhmZVOQC6h9j4JCQgWAc0MfurL2rR1HUFR01uHr0B+cMRjQK22n2NqCkoEvzI/hStjA4tg== X-Received: by 2002:adf:fb11:: with SMTP id c17mr1500573wrr.0.1567525005632; Tue, 03 Sep 2019 08:36:45 -0700 (PDT) Received: from orth.archaic.org.uk (orth.archaic.org.uk. [81.2.115.148]) by smtp.gmail.com with ESMTPSA id a18sm24435188wrt.18.2019.09.03.08.36.44 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 03 Sep 2019 08:36:45 -0700 (PDT) From: Peter Maydell To: qemu-devel@nongnu.org Date: Tue, 3 Sep 2019 16:36:20 +0100 Message-Id: <20190903153633.6651-9-peter.maydell@linaro.org> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20190903153633.6651-1-peter.maydell@linaro.org> References: <20190903153633.6651-1-peter.maydell@linaro.org> MIME-Version: 1.0 X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2a00:1450:4864:20::434 Subject: [Qemu-devel] [PULL 08/21] hw/arm/smmuv3: Remove spurious error messages on IOVA invalidations X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patchwork-qemu-devel=patchwork.kernel.org@nongnu.org Sender: "Qemu-devel" From: Eric Auger An IOVA/ASID invalidation is notified to all IOMMU Memory Regions through smmuv3_inv_notifiers_iova/smmuv3_notify_iova. When the notification occurs it is possible that some of the PCIe devices associated to the notified regions do not have a valid stream table entry. In that case we output a LOG_GUEST_ERROR message, for example: invalid sid= (L1STD span=0) "smmuv3_notify_iova error decoding the configuration for iommu mr= This is unfortunate as the user gets the impression that there are some translation decoding errors whereas there are not. This patch adds a new field in SMMUEventInfo that tells whether the detection of an invalid STE must lead to an error report. invalid_ste_allowed is set before doing the invalidations and kept unset on actual translation. The other configuration decoding error messages are kept since if the STE is valid then the rest of the config must be correct. Signed-off-by: Eric Auger Message-id: 20190822172350.12008-6-eric.auger@redhat.com Reviewed-by: Peter Maydell Signed-off-by: Peter Maydell --- hw/arm/smmuv3-internal.h | 1 + hw/arm/smmuv3.c | 19 +++++++++++-------- 2 files changed, 12 insertions(+), 8 deletions(-) diff --git a/hw/arm/smmuv3-internal.h b/hw/arm/smmuv3-internal.h index b160289cd12..d190181ef1b 100644 --- a/hw/arm/smmuv3-internal.h +++ b/hw/arm/smmuv3-internal.h @@ -381,6 +381,7 @@ typedef struct SMMUEventInfo { uint32_t sid; bool recorded; bool record_trans_faults; + bool inval_ste_allowed; union { struct { uint32_t ssid; diff --git a/hw/arm/smmuv3.c b/hw/arm/smmuv3.c index 31ac4b15c30..db051dcac87 100644 --- a/hw/arm/smmuv3.c +++ b/hw/arm/smmuv3.c @@ -320,7 +320,9 @@ static int decode_ste(SMMUv3State *s, SMMUTransCfg *cfg, uint32_t config; if (!STE_VALID(ste)) { - qemu_log_mask(LOG_GUEST_ERROR, "invalid STE\n"); + if (!event->inval_ste_allowed) { + qemu_log_mask(LOG_GUEST_ERROR, "invalid STE\n"); + } goto bad_ste; } @@ -407,8 +409,10 @@ static int smmu_find_ste(SMMUv3State *s, uint32_t sid, STE *ste, if (!span) { /* l2ptr is not valid */ - qemu_log_mask(LOG_GUEST_ERROR, - "invalid sid=%d (L1STD span=0)\n", sid); + if (!event->inval_ste_allowed) { + qemu_log_mask(LOG_GUEST_ERROR, + "invalid sid=%d (L1STD span=0)\n", sid); + } event->type = SMMU_EVT_C_BAD_STREAMID; return -EINVAL; } @@ -603,7 +607,9 @@ static IOMMUTLBEntry smmuv3_translate(IOMMUMemoryRegion *mr, hwaddr addr, SMMUDevice *sdev = container_of(mr, SMMUDevice, iommu); SMMUv3State *s = sdev->smmu; uint32_t sid = smmu_get_sid(sdev); - SMMUEventInfo event = {.type = SMMU_EVT_NONE, .sid = sid}; + SMMUEventInfo event = {.type = SMMU_EVT_NONE, + .sid = sid, + .inval_ste_allowed = false}; SMMUPTWEventInfo ptw_info = {}; SMMUTranslationStatus status; SMMUState *bs = ARM_SMMU(s); @@ -796,16 +802,13 @@ static void smmuv3_notify_iova(IOMMUMemoryRegion *mr, dma_addr_t iova) { SMMUDevice *sdev = container_of(mr, SMMUDevice, iommu); - SMMUEventInfo event = {}; + SMMUEventInfo event = {.inval_ste_allowed = true}; SMMUTransTableInfo *tt; SMMUTransCfg *cfg; IOMMUTLBEntry entry; cfg = smmuv3_get_config(sdev, &event); if (!cfg) { - qemu_log_mask(LOG_GUEST_ERROR, - "%s error decoding the configuration for iommu mr=%s\n", - __func__, mr->parent_obj.name); return; } From patchwork Tue Sep 3 15:36:21 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Peter Maydell X-Patchwork-Id: 11128277 Return-Path: Received: from mail.kernel.org (pdx-korg-mail-1.web.codeaurora.org [172.30.200.123]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id 13B6A16B1 for ; Tue, 3 Sep 2019 15:40:08 +0000 (UTC) Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id DDA392077B for ; Tue, 3 Sep 2019 15:40:07 +0000 (UTC) Authentication-Results: mail.kernel.org; dkim=fail reason="signature verification failed" (2048-bit key) header.d=linaro.org header.i=@linaro.org header.b="Zkenw7tN" DMARC-Filter: OpenDMARC Filter v1.3.2 mail.kernel.org DDA392077B Authentication-Results: mail.kernel.org; dmarc=fail (p=none dis=none) header.from=linaro.org Authentication-Results: mail.kernel.org; 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X-Received-From: 2a00:1450:4864:20::429 Subject: [Qemu-devel] [PULL 09/21] target/arm: Fix SMMLS argument order X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patchwork-qemu-devel=patchwork.kernel.org@nongnu.org Sender: "Qemu-devel" From: Richard Henderson The previous simplification got the order of operands to the subtraction wrong. Since the 64-bit product is the subtrahend, we must use a 64-bit subtract to properly compute the borrow from the low-part of the product. Fixes: 5f8cd06ebcf5 ("target/arm: Simplify SMMLA, SMMLAR, SMMLS, SMMLSR") Reported-by: Laurent Desnogues Signed-off-by: Richard Henderson Tested-by: Laurent Desnogues Message-id: 20190829013258.16102-1-richard.henderson@linaro.org Reviewed-by: Peter Maydell Signed-off-by: Peter Maydell --- target/arm/translate.c | 20 ++++++++++++++++++-- 1 file changed, 18 insertions(+), 2 deletions(-) diff --git a/target/arm/translate.c b/target/arm/translate.c index 78d93f63cab..cfebd35d268 100644 --- a/target/arm/translate.c +++ b/target/arm/translate.c @@ -8831,7 +8831,16 @@ static void disas_arm_insn(DisasContext *s, unsigned int insn) if (rd != 15) { tmp3 = load_reg(s, rd); if (insn & (1 << 6)) { - tcg_gen_sub_i32(tmp, tmp, tmp3); + /* + * For SMMLS, we need a 64-bit subtract. + * Borrow caused by a non-zero multiplicand + * lowpart, and the correct result lowpart + * for rounding. + */ + TCGv_i32 zero = tcg_const_i32(0); + tcg_gen_sub2_i32(tmp2, tmp, zero, tmp3, + tmp2, tmp); + tcg_temp_free_i32(zero); } else { tcg_gen_add_i32(tmp, tmp, tmp3); } @@ -10075,7 +10084,14 @@ static void disas_thumb2_insn(DisasContext *s, uint32_t insn) if (insn & (1 << 20)) { tcg_gen_add_i32(tmp, tmp, tmp3); } else { - tcg_gen_sub_i32(tmp, tmp, tmp3); + /* + * For SMMLS, we need a 64-bit subtract. + * Borrow caused by a non-zero multiplicand lowpart, + * and the correct result lowpart for rounding. + */ + TCGv_i32 zero = tcg_const_i32(0); + tcg_gen_sub2_i32(tmp2, tmp, zero, tmp3, tmp2, tmp); + tcg_temp_free_i32(zero); } tcg_temp_free_i32(tmp3); } From patchwork Tue Sep 3 15:36:22 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Peter Maydell X-Patchwork-Id: 11128307 Return-Path: Received: from mail.kernel.org (pdx-korg-mail-1.web.codeaurora.org [172.30.200.123]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id 1249514F7 for ; Tue, 3 Sep 2019 15:53:38 +0000 (UTC) Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id DCCDE22CF8 for ; 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[81.2.115.148]) by smtp.gmail.com with ESMTPSA id a18sm24435188wrt.18.2019.09.03.08.36.46 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 03 Sep 2019 08:36:47 -0700 (PDT) From: Peter Maydell To: qemu-devel@nongnu.org Date: Tue, 3 Sep 2019 16:36:22 +0100 Message-Id: <20190903153633.6651-11-peter.maydell@linaro.org> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20190903153633.6651-1-peter.maydell@linaro.org> References: <20190903153633.6651-1-peter.maydell@linaro.org> MIME-Version: 1.0 X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2a00:1450:4864:20::32d Subject: [Qemu-devel] [PULL 10/21] hw/arm: Use ARM_CPU_TYPE_NAME() macro when appropriate X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patchwork-qemu-devel=patchwork.kernel.org@nongnu.org Sender: "Qemu-devel" From: Philippe Mathieu-Daudé Commit ba1ba5cca introduce the ARM_CPU_TYPE_NAME() macro. Unify the code base by use it in all places. Reviewed-by: Alistair Francis Signed-off-by: Philippe Mathieu-Daudé Reviewed-by: Richard Henderson Message-id: 20190823143249.8096-2-philmd@redhat.com Signed-off-by: Peter Maydell --- hw/arm/allwinner-a10.c | 3 ++- hw/arm/cubieboard.c | 3 ++- hw/arm/digic.c | 3 ++- hw/arm/fsl-imx25.c | 2 +- hw/arm/fsl-imx31.c | 2 +- hw/arm/fsl-imx6.c | 3 ++- hw/arm/fsl-imx6ul.c | 2 +- hw/arm/xlnx-zynqmp.c | 8 ++++---- 8 files changed, 15 insertions(+), 11 deletions(-) diff --git a/hw/arm/allwinner-a10.c b/hw/arm/allwinner-a10.c index 73810a44402..118032c8c72 100644 --- a/hw/arm/allwinner-a10.c +++ b/hw/arm/allwinner-a10.c @@ -30,7 +30,8 @@ static void aw_a10_init(Object *obj) AwA10State *s = AW_A10(obj); object_initialize_child(obj, "cpu", &s->cpu, sizeof(s->cpu), - "cortex-a8-" TYPE_ARM_CPU, &error_abort, NULL); + ARM_CPU_TYPE_NAME("cortex-a8"), + &error_abort, NULL); sysbus_init_child_obj(obj, "intc", &s->intc, sizeof(s->intc), TYPE_AW_A10_PIC); diff --git a/hw/arm/cubieboard.c b/hw/arm/cubieboard.c index 38e0ca0f533..ed8d2333a07 100644 --- a/hw/arm/cubieboard.c +++ b/hw/arm/cubieboard.c @@ -81,7 +81,8 @@ static void cubieboard_init(MachineState *machine) static void cubieboard_machine_init(MachineClass *mc) { - mc->desc = "cubietech cubieboard"; + mc->desc = "cubietech cubieboard (Cortex-A9)"; + mc->default_cpu_type = ARM_CPU_TYPE_NAME("cortex-a9"); mc->init = cubieboard_init; mc->block_default_type = IF_IDE; mc->units_per_default_bus = 1; diff --git a/hw/arm/digic.c b/hw/arm/digic.c index 4f524658756..22434a65a28 100644 --- a/hw/arm/digic.c +++ b/hw/arm/digic.c @@ -37,7 +37,8 @@ static void digic_init(Object *obj) int i; object_initialize_child(obj, "cpu", &s->cpu, sizeof(s->cpu), - "arm946-" TYPE_ARM_CPU, &error_abort, NULL); + ARM_CPU_TYPE_NAME("arm946"), + &error_abort, NULL); for (i = 0; i < DIGIC4_NB_TIMERS; i++) { #define DIGIC_TIMER_NAME_MLEN 11 diff --git a/hw/arm/fsl-imx25.c b/hw/arm/fsl-imx25.c index 532d088298b..2b2fdb203a2 100644 --- a/hw/arm/fsl-imx25.c +++ b/hw/arm/fsl-imx25.c @@ -36,7 +36,7 @@ static void fsl_imx25_init(Object *obj) FslIMX25State *s = FSL_IMX25(obj); int i; - object_initialize(&s->cpu, sizeof(s->cpu), "arm926-" TYPE_ARM_CPU); + object_initialize(&s->cpu, sizeof(s->cpu), ARM_CPU_TYPE_NAME("arm926")); sysbus_init_child_obj(obj, "avic", &s->avic, sizeof(s->avic), TYPE_IMX_AVIC); diff --git a/hw/arm/fsl-imx31.c b/hw/arm/fsl-imx31.c index 1a37a7b997c..6760de3c8c1 100644 --- a/hw/arm/fsl-imx31.c +++ b/hw/arm/fsl-imx31.c @@ -33,7 +33,7 @@ static void fsl_imx31_init(Object *obj) FslIMX31State *s = FSL_IMX31(obj); int i; - object_initialize(&s->cpu, sizeof(s->cpu), "arm1136-" TYPE_ARM_CPU); + object_initialize(&s->cpu, sizeof(s->cpu), ARM_CPU_TYPE_NAME("arm1136")); sysbus_init_child_obj(obj, "avic", &s->avic, sizeof(s->avic), TYPE_IMX_AVIC); diff --git a/hw/arm/fsl-imx6.c b/hw/arm/fsl-imx6.c index 8c397ef04ba..552145b24ec 100644 --- a/hw/arm/fsl-imx6.c +++ b/hw/arm/fsl-imx6.c @@ -43,7 +43,8 @@ static void fsl_imx6_init(Object *obj) for (i = 0; i < MIN(ms->smp.cpus, FSL_IMX6_NUM_CPUS); i++) { snprintf(name, NAME_SIZE, "cpu%d", i); object_initialize_child(obj, name, &s->cpu[i], sizeof(s->cpu[i]), - "cortex-a9-" TYPE_ARM_CPU, &error_abort, NULL); + ARM_CPU_TYPE_NAME("cortex-a9"), + &error_abort, NULL); } sysbus_init_child_obj(obj, "a9mpcore", &s->a9mpcore, sizeof(s->a9mpcore), diff --git a/hw/arm/fsl-imx6ul.c b/hw/arm/fsl-imx6ul.c index b074177a71d..c405b68d1dd 100644 --- a/hw/arm/fsl-imx6ul.c +++ b/hw/arm/fsl-imx6ul.c @@ -34,7 +34,7 @@ static void fsl_imx6ul_init(Object *obj) int i; object_initialize_child(obj, "cpu0", &s->cpu, sizeof(s->cpu), - "cortex-a7-" TYPE_ARM_CPU, &error_abort, NULL); + ARM_CPU_TYPE_NAME("cortex-a7"), &error_abort, NULL); /* * A7MPCORE diff --git a/hw/arm/xlnx-zynqmp.c b/hw/arm/xlnx-zynqmp.c index 0f587e63d35..fb03c60ebb8 100644 --- a/hw/arm/xlnx-zynqmp.c +++ b/hw/arm/xlnx-zynqmp.c @@ -196,8 +196,8 @@ static void xlnx_zynqmp_create_rpu(MachineState *ms, XlnxZynqMPState *s, object_initialize_child(OBJECT(&s->rpu_cluster), "rpu-cpu[*]", &s->rpu_cpu[i], sizeof(s->rpu_cpu[i]), - "cortex-r5f-" TYPE_ARM_CPU, &error_abort, - NULL); + ARM_CPU_TYPE_NAME("cortex-r5f"), + &error_abort, NULL); name = object_get_canonical_path_component(OBJECT(&s->rpu_cpu[i])); if (strcmp(name, boot_cpu)) { @@ -237,8 +237,8 @@ static void xlnx_zynqmp_init(Object *obj) for (i = 0; i < num_apus; i++) { object_initialize_child(OBJECT(&s->apu_cluster), "apu-cpu[*]", &s->apu_cpu[i], sizeof(s->apu_cpu[i]), - "cortex-a53-" TYPE_ARM_CPU, &error_abort, - NULL); + ARM_CPU_TYPE_NAME("cortex-a53"), + &error_abort, NULL); } sysbus_init_child_obj(obj, "gic", &s->gic, sizeof(s->gic), From patchwork Tue Sep 3 15:36:23 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Peter Maydell X-Patchwork-Id: 11128301 Return-Path: Received: from mail.kernel.org (pdx-korg-mail-1.web.codeaurora.org [172.30.200.123]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id 9CBF81398 for ; Tue, 3 Sep 2019 15:50:49 +0000 (UTC) Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id 734852343A for ; Tue, 3 Sep 2019 15:50:49 +0000 (UTC) Authentication-Results: mail.kernel.org; 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[81.2.115.148]) by smtp.gmail.com with ESMTPSA id a18sm24435188wrt.18.2019.09.03.08.36.47 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 03 Sep 2019 08:36:48 -0700 (PDT) From: Peter Maydell To: qemu-devel@nongnu.org Date: Tue, 3 Sep 2019 16:36:23 +0100 Message-Id: <20190903153633.6651-12-peter.maydell@linaro.org> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20190903153633.6651-1-peter.maydell@linaro.org> References: <20190903153633.6651-1-peter.maydell@linaro.org> MIME-Version: 1.0 X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2a00:1450:4864:20::336 Subject: [Qemu-devel] [PULL 11/21] hw/arm: Use object_initialize_child for correct reference counting X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patchwork-qemu-devel=patchwork.kernel.org@nongnu.org Sender: "Qemu-devel" From: Philippe Mathieu-Daudé As explained in commit aff39be0ed97: Both functions, object_initialize() and object_property_add_child() increase the reference counter of the new object, so one of the references has to be dropped afterwards to get the reference counting right. Otherwise the child object will not be properly cleaned up when the parent gets destroyed. Thus let's use now object_initialize_child() instead to get the reference counting here right. Reviewed-by: Peter Maydell Signed-off-by: Philippe Mathieu-Daudé Reviewed-by: Thomas Huth Reviewed-by: Richard Henderson Message-id: 20190823143249.8096-3-philmd@redhat.com Signed-off-by: Peter Maydell --- hw/arm/mcimx7d-sabre.c | 9 ++++----- hw/arm/mps2-tz.c | 15 +++++++-------- hw/arm/musca.c | 9 +++++---- 3 files changed, 16 insertions(+), 17 deletions(-) diff --git a/hw/arm/mcimx7d-sabre.c b/hw/arm/mcimx7d-sabre.c index 97b8bb788a1..78b87c502fc 100644 --- a/hw/arm/mcimx7d-sabre.c +++ b/hw/arm/mcimx7d-sabre.c @@ -30,7 +30,6 @@ static void mcimx7d_sabre_init(MachineState *machine) { static struct arm_boot_info boot_info; MCIMX7Sabre *s = g_new0(MCIMX7Sabre, 1); - Object *soc; int i; if (machine->ram_size > FSL_IMX7_MMDC_SIZE) { @@ -49,10 +48,10 @@ static void mcimx7d_sabre_init(MachineState *machine) .nb_cpus = machine->smp.cpus, }; - object_initialize(&s->soc, sizeof(s->soc), TYPE_FSL_IMX7); - soc = OBJECT(&s->soc); - object_property_add_child(OBJECT(machine), "soc", soc, &error_fatal); - object_property_set_bool(soc, true, "realized", &error_fatal); + object_initialize_child(OBJECT(machine), "soc", + &s->soc, sizeof(s->soc), + TYPE_FSL_IMX7, &error_fatal, NULL); + object_property_set_bool(OBJECT(&s->soc), true, "realized", &error_fatal); memory_region_allocate_system_memory(&s->ram, NULL, "mcimx7d-sabre.ram", machine->ram_size); diff --git a/hw/arm/mps2-tz.c b/hw/arm/mps2-tz.c index d85dc2c4bd8..6b24aaacded 100644 --- a/hw/arm/mps2-tz.c +++ b/hw/arm/mps2-tz.c @@ -427,10 +427,10 @@ static void mps2tz_common_init(MachineState *machine) /* The sec_resp_cfg output from the IoTKit must be split into multiple * lines, one for each of the PPCs we create here, plus one per MSC. */ - object_initialize(&mms->sec_resp_splitter, sizeof(mms->sec_resp_splitter), - TYPE_SPLIT_IRQ); - object_property_add_child(OBJECT(machine), "sec-resp-splitter", - OBJECT(&mms->sec_resp_splitter), &error_abort); + object_initialize_child(OBJECT(machine), "sec-resp-splitter", + &mms->sec_resp_splitter, + sizeof(mms->sec_resp_splitter), + TYPE_SPLIT_IRQ, &error_abort, NULL); object_property_set_int(OBJECT(&mms->sec_resp_splitter), ARRAY_SIZE(mms->ppc) + ARRAY_SIZE(mms->msc), "num-lines", &error_fatal); @@ -465,10 +465,9 @@ static void mps2tz_common_init(MachineState *machine) * Tx, Rx and "combined" IRQs are sent to the NVIC separately. * Create the OR gate for this. */ - object_initialize(&mms->uart_irq_orgate, sizeof(mms->uart_irq_orgate), - TYPE_OR_IRQ); - object_property_add_child(OBJECT(mms), "uart-irq-orgate", - OBJECT(&mms->uart_irq_orgate), &error_abort); + object_initialize_child(OBJECT(mms), "uart-irq-orgate", + &mms->uart_irq_orgate, sizeof(mms->uart_irq_orgate), + TYPE_OR_IRQ, &error_abort, NULL); object_property_set_int(OBJECT(&mms->uart_irq_orgate), 10, "num-lines", &error_fatal); object_property_set_bool(OBJECT(&mms->uart_irq_orgate), true, diff --git a/hw/arm/musca.c b/hw/arm/musca.c index ddd8842732c..68db4b5b387 100644 --- a/hw/arm/musca.c +++ b/hw/arm/musca.c @@ -424,10 +424,11 @@ static void musca_init(MachineState *machine) * The sec_resp_cfg output from the SSE-200 must be split into multiple * lines, one for each of the PPCs we create here. */ - object_initialize(&mms->sec_resp_splitter, sizeof(mms->sec_resp_splitter), - TYPE_SPLIT_IRQ); - object_property_add_child(OBJECT(machine), "sec-resp-splitter", - OBJECT(&mms->sec_resp_splitter), &error_fatal); + object_initialize_child(OBJECT(machine), "sec-resp-splitter", + &mms->sec_resp_splitter, + sizeof(mms->sec_resp_splitter), + TYPE_SPLIT_IRQ, &error_fatal, NULL); + object_property_set_int(OBJECT(&mms->sec_resp_splitter), ARRAY_SIZE(mms->ppc), "num-lines", &error_fatal); object_property_set_bool(OBJECT(&mms->sec_resp_splitter), true, From patchwork Tue Sep 3 15:36:24 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Peter Maydell X-Patchwork-Id: 11128293 Return-Path: Received: from mail.kernel.org (pdx-korg-mail-1.web.codeaurora.org [172.30.200.123]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id 9CD001398 for ; Tue, 3 Sep 2019 15:46:53 +0000 (UTC) Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id 73BF72077B for ; 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[81.2.115.148]) by smtp.gmail.com with ESMTPSA id a18sm24435188wrt.18.2019.09.03.08.36.49 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 03 Sep 2019 08:36:49 -0700 (PDT) From: Peter Maydell To: qemu-devel@nongnu.org Date: Tue, 3 Sep 2019 16:36:24 +0100 Message-Id: <20190903153633.6651-13-peter.maydell@linaro.org> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20190903153633.6651-1-peter.maydell@linaro.org> References: <20190903153633.6651-1-peter.maydell@linaro.org> MIME-Version: 1.0 X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2a00:1450:4864:20::32f Subject: [Qemu-devel] [PULL 12/21] hw/arm: Use sysbus_init_child_obj for correct reference counting X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patchwork-qemu-devel=patchwork.kernel.org@nongnu.org Sender: "Qemu-devel" From: Philippe Mathieu-Daudé Both object_initialize() and qdev_set_parent_bus() increase the reference counter of the new object, so one of the references has to be dropped afterwards to get the reference counting right. In machine model code this refcount leak is not particularly problematic because (unlike devices) machines will never be created on demand via QMP, and they are never destroyed. But in any case let's use the new sysbus_init_child_obj() instead to get the reference counting here right. Signed-off-by: Philippe Mathieu-Daudé Reviewed-by: Richard Henderson Message-id: 20190823143249.8096-4-philmd@redhat.com [PMM: rewrote commit message] Signed-off-by: Peter Maydell --- hw/arm/exynos4_boards.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/hw/arm/exynos4_boards.c b/hw/arm/exynos4_boards.c index f69358a5ba8..2781d8bd419 100644 --- a/hw/arm/exynos4_boards.c +++ b/hw/arm/exynos4_boards.c @@ -131,8 +131,8 @@ exynos4_boards_init_common(MachineState *machine, exynos4_boards_init_ram(s, get_system_memory(), exynos4_board_ram_size[board_type]); - object_initialize(&s->soc, sizeof(s->soc), TYPE_EXYNOS4210_SOC); - qdev_set_parent_bus(DEVICE(&s->soc), sysbus_get_default()); + sysbus_init_child_obj(OBJECT(machine), "soc", + &s->soc, sizeof(s->soc), TYPE_EXYNOS4210_SOC); object_property_set_bool(OBJECT(&s->soc), true, "realized", &error_fatal); From patchwork Tue Sep 3 15:36:25 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Peter Maydell X-Patchwork-Id: 11128303 Return-Path: Received: from mail.kernel.org (pdx-korg-mail-1.web.codeaurora.org [172.30.200.123]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id 40FE21398 for ; Tue, 3 Sep 2019 15:51:47 +0000 (UTC) Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id 165E32343A for ; Tue, 3 Sep 2019 15:51:47 +0000 (UTC) Authentication-Results: mail.kernel.org; dkim=fail reason="signature verification failed" (2048-bit key) header.d=linaro.org header.i=@linaro.org header.b="ujKY9P2v" DMARC-Filter: OpenDMARC Filter v1.3.2 mail.kernel.org 165E32343A Authentication-Results: mail.kernel.org; dmarc=fail (p=none dis=none) header.from=linaro.org Authentication-Results: mail.kernel.org; spf=pass smtp.mailfrom=qemu-devel-bounces+patchwork-qemu-devel=patchwork.kernel.org@nongnu.org Received: from localhost ([::1]:47882 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1i5B5t-00009g-MB for patchwork-qemu-devel@patchwork.kernel.org; Tue, 03 Sep 2019 11:51:45 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:59286) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1i5ArW-0002wh-2s for qemu-devel@nongnu.org; Tue, 03 Sep 2019 11:36:54 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1i5ArU-000604-FW for qemu-devel@nongnu.org; Tue, 03 Sep 2019 11:36:53 -0400 Received: from mail-wm1-x330.google.com ([2a00:1450:4864:20::330]:55772) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1i5ArU-0005zX-7t for qemu-devel@nongnu.org; Tue, 03 Sep 2019 11:36:52 -0400 Received: by mail-wm1-x330.google.com with SMTP id g207so14752246wmg.5 for ; Tue, 03 Sep 2019 08:36:52 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:subject:date:message-id:in-reply-to:references:mime-version :content-transfer-encoding; bh=xlVfa4X6hgu0Qn72UxF4DtuCgLqcTN2WoNHXseq96d4=; b=ujKY9P2v5YCHnJzMvyPvXblDgaUyDasFclg/wwG2Er/Hsty0EXCSswXrE0eAfiKfTX mZS/JFWypyn/50URYp/xiRLqlt2pHfApU04QCLWoHnpjvImyXJkyZAAaz5PcHyKAJayU 3zQes/E2pAUOS/CpzRPvEbP+DhCqhaukDCexSTTvgrw3ZYGKXMPM7Ia5PVKdqAerwOL0 ZWYcpcib2wTp8lRQ9ulhTcNATbiTd5tzNGYND5ByhUdhsIDQ4XUkh/Vlal/IfXGa7u2u F+5lYhgIGUuw6Bw4MXPksxscoxNhQaN4mlEpPUt/yANRh+BBO9WJpchMu5CaxvnqB6+3 0KPQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=xlVfa4X6hgu0Qn72UxF4DtuCgLqcTN2WoNHXseq96d4=; b=TMqswbo+aw52/yfOVXOrMQsTdVdCb8NDJUmEnYCSqhO1sO46I5rULCXetcf0fZIS93 /pCvKQ7bNHs8Wn9mx3mq9BhyFK3vvVXQKeY1jsrUUloBukztJekkyhvYUg58h2egFXmw ZeCvAgZ3SCeTZzvodO0EGCvjXAvrlJjK5vVcsAL0XVegEXADA38MdfhvXyLIQ3nvoZph lD6xOu8gsRjrEauh+y6m1eX30sp/AJSWxIHe1qn/BCy4/P+veayrHe3jGVFOdsWSVMeH Jk7HHv8WCuAG4wscvW3IU+Lu6ANWXhbXVCgiRxZT8oSlgjkWs0Ymq7OHk4CC83X39LHT Jdog== X-Gm-Message-State: APjAAAUzTGsgUl61eMPGddaJiuO3dE11xx2VBhfOqkJCWlk1PQKMx9dd lgSWBkudqnDEmfV2zE/CRIVqfGhorC/8lg== X-Google-Smtp-Source: APXvYqx8PpmJRf//JZ9GrCdTFZMzXhhVRG8+yR6+xTff1ifLIkttG0Cv2OJlz32rNAY/xZfqhwNVmQ== X-Received: by 2002:a1c:740b:: with SMTP id p11mr869715wmc.6.1567525011013; Tue, 03 Sep 2019 08:36:51 -0700 (PDT) Received: from orth.archaic.org.uk (orth.archaic.org.uk. [81.2.115.148]) by smtp.gmail.com with ESMTPSA id a18sm24435188wrt.18.2019.09.03.08.36.50 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 03 Sep 2019 08:36:50 -0700 (PDT) From: Peter Maydell To: qemu-devel@nongnu.org Date: Tue, 3 Sep 2019 16:36:25 +0100 Message-Id: <20190903153633.6651-14-peter.maydell@linaro.org> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20190903153633.6651-1-peter.maydell@linaro.org> References: <20190903153633.6651-1-peter.maydell@linaro.org> MIME-Version: 1.0 X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2a00:1450:4864:20::330 Subject: [Qemu-devel] [PULL 13/21] hw/arm/fsl-imx: Add the cpu as child of the SoC object X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patchwork-qemu-devel=patchwork.kernel.org@nongnu.org Sender: "Qemu-devel" From: Philippe Mathieu-Daudé Child properties form the composition tree. All objects need to be a child of another object. Objects can only be a child of one object. Respect this with the i.MX SoC, to get a cleaner composition tree. Signed-off-by: Philippe Mathieu-Daudé Reviewed-by: Richard Henderson Message-id: 20190823143249.8096-5-philmd@redhat.com Signed-off-by: Peter Maydell --- hw/arm/fsl-imx25.c | 4 +++- hw/arm/fsl-imx31.c | 4 +++- 2 files changed, 6 insertions(+), 2 deletions(-) diff --git a/hw/arm/fsl-imx25.c b/hw/arm/fsl-imx25.c index 2b2fdb203a2..3cb5a8fdfd7 100644 --- a/hw/arm/fsl-imx25.c +++ b/hw/arm/fsl-imx25.c @@ -36,7 +36,9 @@ static void fsl_imx25_init(Object *obj) FslIMX25State *s = FSL_IMX25(obj); int i; - object_initialize(&s->cpu, sizeof(s->cpu), ARM_CPU_TYPE_NAME("arm926")); + object_initialize_child(obj, "cpu", &s->cpu, sizeof(s->cpu), + ARM_CPU_TYPE_NAME("arm926"), + &error_abort, NULL); sysbus_init_child_obj(obj, "avic", &s->avic, sizeof(s->avic), TYPE_IMX_AVIC); diff --git a/hw/arm/fsl-imx31.c b/hw/arm/fsl-imx31.c index 6760de3c8c1..55e90d104bc 100644 --- a/hw/arm/fsl-imx31.c +++ b/hw/arm/fsl-imx31.c @@ -33,7 +33,9 @@ static void fsl_imx31_init(Object *obj) FslIMX31State *s = FSL_IMX31(obj); int i; - object_initialize(&s->cpu, sizeof(s->cpu), ARM_CPU_TYPE_NAME("arm1136")); + object_initialize_child(obj, "cpu", &s->cpu, sizeof(s->cpu), + ARM_CPU_TYPE_NAME("arm1136"), + &error_abort, NULL); sysbus_init_child_obj(obj, "avic", &s->avic, sizeof(s->avic), TYPE_IMX_AVIC); From patchwork Tue Sep 3 15:36:26 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Peter Maydell X-Patchwork-Id: 11128287 Return-Path: Received: from mail.kernel.org (pdx-korg-mail-1.web.codeaurora.org [172.30.200.123]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id A9DCB14F7 for ; Tue, 3 Sep 2019 15:43:02 +0000 (UTC) Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id 7DEAD206B8 for ; Tue, 3 Sep 2019 15:43:02 +0000 (UTC) Authentication-Results: mail.kernel.org; dkim=fail reason="signature verification failed" (2048-bit key) header.d=linaro.org header.i=@linaro.org header.b="rPK2hf4T" DMARC-Filter: OpenDMARC Filter v1.3.2 mail.kernel.org 7DEAD206B8 Authentication-Results: mail.kernel.org; dmarc=fail (p=none dis=none) header.from=linaro.org Authentication-Results: mail.kernel.org; spf=pass smtp.mailfrom=qemu-devel-bounces+patchwork-qemu-devel=patchwork.kernel.org@nongnu.org Received: from localhost ([::1]:47742 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1i5AxR-0001Db-Be for patchwork-qemu-devel@patchwork.kernel.org; Tue, 03 Sep 2019 11:43:01 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:59294) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1i5ArW-0002yB-Hy for qemu-devel@nongnu.org; Tue, 03 Sep 2019 11:36:56 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1i5ArV-00060q-CY for qemu-devel@nongnu.org; Tue, 03 Sep 2019 11:36:54 -0400 Received: from mail-wm1-x329.google.com ([2a00:1450:4864:20::329]:53089) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1i5ArV-00060F-6C for qemu-devel@nongnu.org; Tue, 03 Sep 2019 11:36:53 -0400 Received: by mail-wm1-x329.google.com with SMTP id t17so18753650wmi.2 for ; Tue, 03 Sep 2019 08:36:53 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:subject:date:message-id:in-reply-to:references:mime-version :content-transfer-encoding; bh=Jh428xFMZspE9pzmT4T/vs6lA+3UmLCdDqsT/xMT5PA=; b=rPK2hf4Tm3a3xnzX1tqtxXub5x15pPJcI11sH/pYEdjJd7Vy+LC5W4UsULfAUXDnMD G60b3LkNc7BxVSKh2wjvodE/SxtrWKQhWuyGChggHeundz6Zhkv555z0VDhAgviIjzSY DYgjsNFXUYpomxw1k1zXyySCTj01a9XGQ5j9WqqEYTfQRYqh0FkwT0rsKmaF6gIVXqW5 /5Zp4/1G1BO/q6vz2BWnxbzL64E3xCvOyyhoKDUJwPzbt0A/61+lsNQxfWadS5P7qMZd 6g/3sB31q74KZft20MC/cxOCiBoZIuZUtO3XErk/v2xjspGEqs+k1KEY3dlpIGG4lmgV mZPw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=Jh428xFMZspE9pzmT4T/vs6lA+3UmLCdDqsT/xMT5PA=; b=p5VEyZiz7aoHEgMYLuNYtcv702FQIuiVZAEmDqdnw5mecESQbkYfsxNUOtHaPV9Zwi 7mc1ff1y+0suyy3ItHV/tNcCmYlpVLBSUFzjzqagwYrkNW1hu7bBR2C2WuaGQ2dJMjKf iTMniYzfgti4yQ78j+P2AeDRsEAkPPCLyZzVQTKYjXxA7EjxwIfaXQDnYO8iBkhflmEE yT04S5/HtGyASC9Q6OiF05FDSmmtKBwvzAmQHzOT1n1IQBi6K/h7/RWVjJOxAXBFYEsA 0eBwgF2EJdmgC1/OE79CmbaTgfiL/32s12Fp7XjumOK/dA76sQBS/KzaF/OzbnxxsYWl 2NNw== X-Gm-Message-State: APjAAAXsO08f4iuQaAyBOakIkveWDvNTU6vJA6bubhSRbpDjnfAUHUc/ Edh4Qq5e6w+5k2JAGDW1aSMDYqq895Vlbw== X-Google-Smtp-Source: APXvYqy8me/hDC390Sh1q3+M3E44cZXcICos3F3vPTxp5U4Lf6XsePitp2aUfG99oU/gDPD6vyvLTA== X-Received: by 2002:a7b:cb0f:: with SMTP id u15mr717576wmj.173.1567525011888; Tue, 03 Sep 2019 08:36:51 -0700 (PDT) Received: from orth.archaic.org.uk (orth.archaic.org.uk. [81.2.115.148]) by smtp.gmail.com with ESMTPSA id a18sm24435188wrt.18.2019.09.03.08.36.51 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 03 Sep 2019 08:36:51 -0700 (PDT) From: Peter Maydell To: qemu-devel@nongnu.org Date: Tue, 3 Sep 2019 16:36:26 +0100 Message-Id: <20190903153633.6651-15-peter.maydell@linaro.org> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20190903153633.6651-1-peter.maydell@linaro.org> References: <20190903153633.6651-1-peter.maydell@linaro.org> MIME-Version: 1.0 X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2a00:1450:4864:20::329 Subject: [Qemu-devel] [PULL 14/21] hw/dma/xilinx_axi: Use object_initialize_child for correct ref. counting X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patchwork-qemu-devel=patchwork.kernel.org@nongnu.org Sender: "Qemu-devel" From: Philippe Mathieu-Daudé As explained in commit aff39be0ed97: Both functions, object_initialize() and object_property_add_child() increase the reference counter of the new object, so one of the references has to be dropped afterwards to get the reference counting right. Otherwise the child object will not be properly cleaned up when the parent gets destroyed. Thus let's use now object_initialize_child() instead to get the reference counting here right. Reviewed-by: Alistair Francis Signed-off-by: Philippe Mathieu-Daudé Reviewed-by: Thomas Huth Reviewed-by: Richard Henderson Message-id: 20190823143249.8096-6-philmd@redhat.com Signed-off-by: Peter Maydell --- hw/dma/xilinx_axidma.c | 16 ++++++++-------- 1 file changed, 8 insertions(+), 8 deletions(-) diff --git a/hw/dma/xilinx_axidma.c b/hw/dma/xilinx_axidma.c index d176df6d449..a254275b64e 100644 --- a/hw/dma/xilinx_axidma.c +++ b/hw/dma/xilinx_axidma.c @@ -566,14 +566,14 @@ static void xilinx_axidma_init(Object *obj) XilinxAXIDMA *s = XILINX_AXI_DMA(obj); SysBusDevice *sbd = SYS_BUS_DEVICE(obj); - object_initialize(&s->rx_data_dev, sizeof(s->rx_data_dev), - TYPE_XILINX_AXI_DMA_DATA_STREAM); - object_initialize(&s->rx_control_dev, sizeof(s->rx_control_dev), - TYPE_XILINX_AXI_DMA_CONTROL_STREAM); - object_property_add_child(OBJECT(s), "axistream-connected-target", - (Object *)&s->rx_data_dev, &error_abort); - object_property_add_child(OBJECT(s), "axistream-control-connected-target", - (Object *)&s->rx_control_dev, &error_abort); + object_initialize_child(OBJECT(s), "axistream-connected-target", + &s->rx_data_dev, sizeof(s->rx_data_dev), + TYPE_XILINX_AXI_DMA_DATA_STREAM, &error_abort, + NULL); + object_initialize_child(OBJECT(s), "axistream-control-connected-target", + &s->rx_control_dev, sizeof(s->rx_control_dev), + TYPE_XILINX_AXI_DMA_CONTROL_STREAM, &error_abort, + NULL); sysbus_init_irq(sbd, &s->streams[0].irq); sysbus_init_irq(sbd, &s->streams[1].irq); From patchwork Tue Sep 3 15:36:27 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Peter Maydell X-Patchwork-Id: 11128295 Return-Path: Received: from mail.kernel.org (pdx-korg-mail-1.web.codeaurora.org [172.30.200.123]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id E2BBA14F7 for ; Tue, 3 Sep 2019 15:48:43 +0000 (UTC) Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id AF66223431 for ; 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[81.2.115.148]) by smtp.gmail.com with ESMTPSA id a18sm24435188wrt.18.2019.09.03.08.36.51 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 03 Sep 2019 08:36:52 -0700 (PDT) From: Peter Maydell To: qemu-devel@nongnu.org Date: Tue, 3 Sep 2019 16:36:27 +0100 Message-Id: <20190903153633.6651-16-peter.maydell@linaro.org> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20190903153633.6651-1-peter.maydell@linaro.org> References: <20190903153633.6651-1-peter.maydell@linaro.org> MIME-Version: 1.0 X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2a00:1450:4864:20::32e Subject: [Qemu-devel] [PULL 15/21] hw/net/xilinx_axi: Use object_initialize_child for correct ref. counting X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patchwork-qemu-devel=patchwork.kernel.org@nongnu.org Sender: "Qemu-devel" From: Philippe Mathieu-Daudé As explained in commit aff39be0ed97: Both functions, object_initialize() and object_property_add_child() increase the reference counter of the new object, so one of the references has to be dropped afterwards to get the reference counting right. Otherwise the child object will not be properly cleaned up when the parent gets destroyed. Thus let's use now object_initialize_child() instead to get the reference counting here right. Reviewed-by: Alistair Francis Signed-off-by: Philippe Mathieu-Daudé Reviewed-by: Thomas Huth Reviewed-by: Richard Henderson Message-id: 20190823143249.8096-7-philmd@redhat.com Signed-off-by: Peter Maydell --- hw/net/xilinx_axienet.c | 17 ++++++++--------- 1 file changed, 8 insertions(+), 9 deletions(-) diff --git a/hw/net/xilinx_axienet.c b/hw/net/xilinx_axienet.c index d8716a1f737..2c8c065401a 100644 --- a/hw/net/xilinx_axienet.c +++ b/hw/net/xilinx_axienet.c @@ -994,15 +994,14 @@ static void xilinx_enet_init(Object *obj) XilinxAXIEnet *s = XILINX_AXI_ENET(obj); SysBusDevice *sbd = SYS_BUS_DEVICE(obj); - object_initialize(&s->rx_data_dev, sizeof(s->rx_data_dev), - TYPE_XILINX_AXI_ENET_DATA_STREAM); - object_initialize(&s->rx_control_dev, sizeof(s->rx_control_dev), - TYPE_XILINX_AXI_ENET_CONTROL_STREAM); - object_property_add_child(OBJECT(s), "axistream-connected-target", - (Object *)&s->rx_data_dev, &error_abort); - object_property_add_child(OBJECT(s), "axistream-control-connected-target", - (Object *)&s->rx_control_dev, &error_abort); - + object_initialize_child(OBJECT(s), "axistream-connected-target", + &s->rx_data_dev, sizeof(s->rx_data_dev), + TYPE_XILINX_AXI_ENET_DATA_STREAM, &error_abort, + NULL); + object_initialize_child(OBJECT(s), "axistream-control-connected-target", + &s->rx_control_dev, sizeof(s->rx_control_dev), + TYPE_XILINX_AXI_ENET_CONTROL_STREAM, &error_abort, + NULL); sysbus_init_irq(sbd, &s->irq); memory_region_init_io(&s->iomem, OBJECT(s), &enet_ops, s, "enet", 0x40000); From patchwork Tue Sep 3 15:36:28 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Peter Maydell X-Patchwork-Id: 11128305 Return-Path: Received: from mail.kernel.org (pdx-korg-mail-1.web.codeaurora.org [172.30.200.123]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id CFD081398 for ; Tue, 3 Sep 2019 15:51:55 +0000 (UTC) Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id A6C922343A for ; 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[81.2.115.148]) by smtp.gmail.com with ESMTPSA id a18sm24435188wrt.18.2019.09.03.08.36.53 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 03 Sep 2019 08:36:54 -0700 (PDT) From: Peter Maydell To: qemu-devel@nongnu.org Date: Tue, 3 Sep 2019 16:36:28 +0100 Message-Id: <20190903153633.6651-17-peter.maydell@linaro.org> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20190903153633.6651-1-peter.maydell@linaro.org> References: <20190903153633.6651-1-peter.maydell@linaro.org> MIME-Version: 1.0 X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2a00:1450:4864:20::32d Subject: [Qemu-devel] [PULL 16/21] includes: remove stale [smp|max]_cpus externs X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patchwork-qemu-devel=patchwork.kernel.org@nongnu.org Sender: "Qemu-devel" From: Alex Bennée Commit a5e0b3311 removed these in favour of querying machine properties. Remove the extern declarations as well. Signed-off-by: Alex Bennée Reviewed-by: Philippe Mathieu-Daudé Reviewed-by: Richard Henderson Message-id: 20190828165307.18321-6-alex.bennee@linaro.org Cc: Like Xu Message-Id: <20190711130546.18578-1-alex.bennee@linaro.org> Signed-off-by: Peter Maydell --- include/sysemu/sysemu.h | 2 -- 1 file changed, 2 deletions(-) diff --git a/include/sysemu/sysemu.h b/include/sysemu/sysemu.h index d2c38f611a3..44f18eb7394 100644 --- a/include/sysemu/sysemu.h +++ b/include/sysemu/sysemu.h @@ -42,8 +42,6 @@ extern const char *keyboard_layout; extern int win2k_install_hack; extern int alt_grab; extern int ctrl_grab; -extern int smp_cpus; -extern unsigned int max_cpus; extern int cursor_hide; extern int graphic_rotate; extern int no_quit; From patchwork Tue Sep 3 15:36:29 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Peter Maydell X-Patchwork-Id: 11128313 Return-Path: Received: from mail.kernel.org (pdx-korg-mail-1.web.codeaurora.org [172.30.200.123]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id 9EA3314F7 for ; Tue, 3 Sep 2019 15:54:37 +0000 (UTC) Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id 72DE522CF8 for ; Tue, 3 Sep 2019 15:54:37 +0000 (UTC) Authentication-Results: mail.kernel.org; dkim=fail reason="signature verification failed" (2048-bit key) header.d=linaro.org header.i=@linaro.org header.b="BibhaDgh" DMARC-Filter: OpenDMARC Filter v1.3.2 mail.kernel.org 72DE522CF8 Authentication-Results: mail.kernel.org; dmarc=fail (p=none dis=none) header.from=linaro.org Authentication-Results: mail.kernel.org; spf=pass smtp.mailfrom=qemu-devel-bounces+patchwork-qemu-devel=patchwork.kernel.org@nongnu.org Received: from localhost ([::1]:47948 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1i5B8e-000425-20 for patchwork-qemu-devel@patchwork.kernel.org; Tue, 03 Sep 2019 11:54:36 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:59334) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1i5Ara-00034r-8J for qemu-devel@nongnu.org; Tue, 03 Sep 2019 11:36:59 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1i5ArZ-00063G-2U for qemu-devel@nongnu.org; Tue, 03 Sep 2019 11:36:57 -0400 Received: from mail-wr1-x432.google.com ([2a00:1450:4864:20::432]:42964) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1i5ArY-00062a-Sb for qemu-devel@nongnu.org; Tue, 03 Sep 2019 11:36:57 -0400 Received: by mail-wr1-x432.google.com with SMTP id b16so17977645wrq.9 for ; Tue, 03 Sep 2019 08:36:56 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:subject:date:message-id:in-reply-to:references:mime-version :content-transfer-encoding; bh=nR0JGIs4B0XqG/9nvKTr4WHZcNIZDzXugHm2rJffA5M=; b=BibhaDghWk5wZz/Qw7wSjtQzUPC8PRJ426VZ9tIC2phcGd4q8m68y4ErUO0t2zZeoM 6JFqrOUeKNICgdi7tiFWduE68C6Ok6PtfbfEm8LPmcRpQeUDjPHGZNh13/tR/4tYZTWy UFlU/u4sEpj4dhhs2CeHLsNHcHRqQZFRNTBInX0Tg3/BKMbpCfoX6Kx18rNDK3QbtJN8 mHgFfp95LMdi6GveSXWGt8Li+APoQnkswka/YtmVFM7SW7knv7TpIIT5beP0zBuzVPlK ikir7iL5Fhrwg0wvQxdeNytVJ9yeFeLdpXm5Ch6ApwjEI2n/3MlOZLc/BL9Np8ig7iQB kmJg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=nR0JGIs4B0XqG/9nvKTr4WHZcNIZDzXugHm2rJffA5M=; b=VT5hzWt1FrmX17LbYEcyrO5JfJGTsvkpYfcs0A1y/wlik0oyDolThO5RLpf9iXZJN9 19dlgGC9IgWXDCTLRMDccnySmWz1u+OkMmw/VrRGBjQgSzFBd1UfMKh4HtlSCdn5Retn q9+5AIGaFIWZo/7/Lhav7MNhagd7qsnysMO7i6fYeCBaQpIJbJXaHnKiyrMgLLvCFOKS OWkRF0Trmu35ahXyWT4XIvo4+f8swSlZnvnyMeTx2d5SSVHARjJPfqBx+eSwBRmgK1vV 3FY69/vBN3KwluCZFsgixBGMqRwtYMBqsM52uibiU/bqkRODRfQ7aRfx49EV094IJRhE xNCA== X-Gm-Message-State: APjAAAUT4akFLAGB90rc+TjuRHGggg6mofF69G8a8pndRy1A9ndu3CNC 5B81pJ9gyfpNuy/dR9BxKLBDUqSUkmO+1w== X-Google-Smtp-Source: APXvYqw0gbgGwLL1WAOWJf6H9B1SjX9aWo2AXYeHRaB3anBbF8e442c9Z0mpM2vro0TDlRGg700x5w== X-Received: by 2002:a5d:4044:: with SMTP id w4mr6493827wrp.281.1567525015708; Tue, 03 Sep 2019 08:36:55 -0700 (PDT) Received: from orth.archaic.org.uk (orth.archaic.org.uk. [81.2.115.148]) by smtp.gmail.com with ESMTPSA id a18sm24435188wrt.18.2019.09.03.08.36.54 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 03 Sep 2019 08:36:55 -0700 (PDT) From: Peter Maydell To: qemu-devel@nongnu.org Date: Tue, 3 Sep 2019 16:36:29 +0100 Message-Id: <20190903153633.6651-18-peter.maydell@linaro.org> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20190903153633.6651-1-peter.maydell@linaro.org> References: <20190903153633.6651-1-peter.maydell@linaro.org> MIME-Version: 1.0 X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2a00:1450:4864:20::432 Subject: [Qemu-devel] [PULL 17/21] tcg/README: fix typo s/afterwise/afterwards/ X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patchwork-qemu-devel=patchwork.kernel.org@nongnu.org Sender: "Qemu-devel" From: "Emilio G. Cota" Afterwise is "wise after the fact", as in "hindsight". Here we meant "afterwards" (as in "subsequently"). Fix it. Reviewed-by: Alex Bennée Signed-off-by: Emilio G. Cota Reviewed-by: Richard Henderson Signed-off-by: Alex Bennée Reviewed-by: Philippe Mathieu-Daudé Message-id: 20190828165307.18321-7-alex.bennee@linaro.org Signed-off-by: Peter Maydell --- tcg/README | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/tcg/README b/tcg/README index 21fcdf737ff..ef9be5ba90e 100644 --- a/tcg/README +++ b/tcg/README @@ -101,7 +101,7 @@ This can be overridden using the following function modifiers: canonical locations before calling the helper. - TCG_CALL_NO_WRITE_GLOBALS means that the helper does not modify any globals. They will only be saved to their canonical location before calling helpers, - but they won't be reloaded afterwise. + but they won't be reloaded afterwards. - TCG_CALL_NO_SIDE_EFFECTS means that the call to the function is removed if the return value is not used. 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X-Received-From: 2a00:1450:4864:20::330 Subject: [Qemu-devel] [PULL 18/21] atomic_template: fix indentation in GEN_ATOMIC_HELPER X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patchwork-qemu-devel=patchwork.kernel.org@nongnu.org Sender: "Qemu-devel" From: "Emilio G. Cota" Reviewed-by: Alex Bennée Signed-off-by: Emilio G. Cota Reviewed-by: Richard Henderson Signed-off-by: Alex Bennée Reviewed-by: Philippe Mathieu-Daudé Message-id: 20190828165307.18321-8-alex.bennee@linaro.org Signed-off-by: Peter Maydell --- accel/tcg/atomic_template.h | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/accel/tcg/atomic_template.h b/accel/tcg/atomic_template.h index 5aaf1862539..df9c8388178 100644 --- a/accel/tcg/atomic_template.h +++ b/accel/tcg/atomic_template.h @@ -284,7 +284,7 @@ ABI_TYPE ATOMIC_NAME(xchg)(CPUArchState *env, target_ulong addr, #define GEN_ATOMIC_HELPER(X) \ ABI_TYPE ATOMIC_NAME(X)(CPUArchState *env, target_ulong addr, \ - ABI_TYPE val EXTRA_ARGS) \ + ABI_TYPE val EXTRA_ARGS) \ { \ ATOMIC_MMU_DECLS; \ DATA_TYPE *haddr = ATOMIC_MMU_LOOKUP; \ From patchwork Tue Sep 3 15:36:31 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Peter Maydell X-Patchwork-Id: 11128315 Return-Path: Received: from mail.kernel.org (pdx-korg-mail-1.web.codeaurora.org [172.30.200.123]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id 0B76E14F7 for ; Tue, 3 Sep 2019 15:56:23 +0000 (UTC) Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id D323D22CF8 for ; Tue, 3 Sep 2019 15:56:22 +0000 (UTC) Authentication-Results: mail.kernel.org; dkim=fail reason="signature verification failed" (2048-bit key) header.d=linaro.org header.i=@linaro.org header.b="ufVRrbvm" DMARC-Filter: OpenDMARC Filter v1.3.2 mail.kernel.org D323D22CF8 Authentication-Results: mail.kernel.org; dmarc=fail (p=none dis=none) header.from=linaro.org Authentication-Results: mail.kernel.org; spf=pass smtp.mailfrom=qemu-devel-bounces+patchwork-qemu-devel=patchwork.kernel.org@nongnu.org Received: from localhost ([::1]:47988 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1i5BAL-0006Js-PQ for patchwork-qemu-devel@patchwork.kernel.org; Tue, 03 Sep 2019 11:56:21 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:59360) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1i5Arb-00037O-OF for qemu-devel@nongnu.org; Tue, 03 Sep 2019 11:37:00 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1i5Ara-00064T-Ny for qemu-devel@nongnu.org; Tue, 03 Sep 2019 11:36:59 -0400 Received: from mail-wm1-x32d.google.com ([2a00:1450:4864:20::32d]:39517) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1i5Ara-00063x-I8 for qemu-devel@nongnu.org; Tue, 03 Sep 2019 11:36:58 -0400 Received: by mail-wm1-x32d.google.com with SMTP id n2so17415590wmk.4 for ; Tue, 03 Sep 2019 08:36:58 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:subject:date:message-id:in-reply-to:references:mime-version :content-transfer-encoding; bh=kAtyZQk6NvWQZv/UvMqc94DjvSUcAjVyZvv+e5jcwsg=; b=ufVRrbvmnUO3sAPlmFdH4FPqyU1RViehbvFdCZQSl/XvhmTDR0sYYhiZdCKS6UWSrb jTvwz2b60ID/LmgS2xwWVYxeZeEtljiwi0jrDgROKf5Rd7z96x6Y3f3OK/AbUUWw9dDZ Wo9JU2lPNiZrmRpf2U/FwWunGjctqNarYZbodI2WoImycKSl5NYaMUeZnH9w7qL8KKWU Q1hBUReEr8+J5RiarcE+ZWOkhU68FErYGfEiJfZTocvVuGmmgp/cTwdkdJUkUngounfQ BVTl99C/J3NzveMLuGmJZXuILH19jt/Cb90vxMF+avI3kily825GnZxHAyyhFYYRJg+y BYcA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=kAtyZQk6NvWQZv/UvMqc94DjvSUcAjVyZvv+e5jcwsg=; b=eaNTB5RGSDa4J2+wKHKWRdvJxAujriGoB1/9+DKDlP38b9c+lnwwKT+2LCh4umCUa3 ZfAWYHxBaJrun+d5fzBwR0uqyGgRKxLWd5/gcA8OW1nVEUNZjaHYC+fAN74yXcS6kkLI wFLj7uP8GsBnbni2u5bocB40ghqKfDIUmc3h1siKmGUPOAufqvQfzoToOCuUPKMeh+1J 9jWEHYjKs0ZWQH9pUvOaurVCOqkAoQdANEHS50Iz5N/7K1z1Jx0tRBQfE8DEYKRPy2Gs wd8d6UsMysME1c9bfQ1Zh+/8oVAcYPQ2Nk5EKRfGIorHvdTkA7Jt5w8SWg4YKn8SMuIj Lxtw== X-Gm-Message-State: APjAAAWiSeEzHfVQ/w3J7tgUQXJ4wsbEMjyriyOQDlvuW1PIy2pgNqRP mylTHHnxXG3hfeY1VIwWJkS5umutX687uA== X-Google-Smtp-Source: APXvYqznNKGlOSvpfldra8Epa0Fvf6owV9x3orzdP0qlSpXZUBkshe5Q2rbUpPzKxhepbk3ZnrGZaw== X-Received: by 2002:a7b:cb03:: with SMTP id u3mr862225wmj.58.1567525017461; Tue, 03 Sep 2019 08:36:57 -0700 (PDT) Received: from orth.archaic.org.uk (orth.archaic.org.uk. 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X-Received-From: 2a00:1450:4864:20::32d Subject: [Qemu-devel] [PULL 19/21] include/exec/cpu-defs.h: fix typo X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patchwork-qemu-devel=patchwork.kernel.org@nongnu.org Sender: "Qemu-devel" From: Alex Bennée Signed-off-by: Alex Bennée Reviewed-by: Richard Henderson Reviewed-by: Alex Bennée Reviewed-by: Philippe Mathieu-Daudé Message-id: 20190828165307.18321-10-alex.bennee@linaro.org Signed-off-by: Peter Maydell --- include/exec/cpu-defs.h | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/include/exec/cpu-defs.h b/include/exec/cpu-defs.h index 189709b6deb..be946ba1ce5 100644 --- a/include/exec/cpu-defs.h +++ b/include/exec/cpu-defs.h @@ -231,7 +231,7 @@ typedef struct CPUTLB { } CPUTLB; #endif /* !CONFIG_USER_ONLY && CONFIG_TCG */ /* - * This structure must be placed in ArchCPU immedately + * This structure must be placed in ArchCPU immediately * before CPUArchState, as a field named "neg". */ typedef struct CPUNegativeOffsetState { From patchwork Tue Sep 3 15:36:32 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Peter Maydell X-Patchwork-Id: 11128309 Return-Path: Received: from mail.kernel.org (pdx-korg-mail-1.web.codeaurora.org [172.30.200.123]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id 57A4F1398 for ; Tue, 3 Sep 2019 15:54:27 +0000 (UTC) Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id 2DD2F22CF8 for ; Tue, 3 Sep 2019 15:54:27 +0000 (UTC) Authentication-Results: mail.kernel.org; dkim=fail reason="signature verification failed" (2048-bit key) header.d=linaro.org header.i=@linaro.org header.b="hqVt7v0A" DMARC-Filter: OpenDMARC Filter v1.3.2 mail.kernel.org 2DD2F22CF8 Authentication-Results: mail.kernel.org; dmarc=fail (p=none dis=none) header.from=linaro.org Authentication-Results: mail.kernel.org; spf=pass smtp.mailfrom=qemu-devel-bounces+patchwork-qemu-devel=patchwork.kernel.org@nongnu.org Received: from localhost ([::1]:47942 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1i5B8T-0003pP-T1 for patchwork-qemu-devel@patchwork.kernel.org; Tue, 03 Sep 2019 11:54:25 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:59374) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1i5Arc-00038d-J2 for qemu-devel@nongnu.org; Tue, 03 Sep 2019 11:37:01 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1i5Arb-00065G-Kz for qemu-devel@nongnu.org; Tue, 03 Sep 2019 11:37:00 -0400 Received: from mail-wr1-x444.google.com ([2a00:1450:4864:20::444]:40774) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1i5Arb-00064Z-EF for qemu-devel@nongnu.org; Tue, 03 Sep 2019 11:36:59 -0400 Received: by mail-wr1-x444.google.com with SMTP id c3so17988349wrd.7 for ; Tue, 03 Sep 2019 08:36:59 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:subject:date:message-id:in-reply-to:references:mime-version :content-transfer-encoding; bh=PQwumxLD0naoGLveJArJ+0uz+trgPMLG7ByeUUTiw3c=; b=hqVt7v0A+RHc8yPlc+/akWP8XDgvXvaCpwmsl8C06sRocrkdWgnZ4fsB2UBzgf5FeW baJvJHoeqRruO5xRJvCqaz+xq+JxV8G2WMV9sumfMKCmU3HQ4m7eLPgFn66J2AWNH3qk L/i4g+q3XJgETBgyjmZ/2vV4GchANz4g6gBUUJzIGKACnJWUpmLdF0KwmyH3lPMknZMO R1ztMvOYpqxx6GyhY3pBySM6mKd3JvVut5axbzgkHbhaGdOQWHzCTvyqpQKtgs5dENXo KaKQq/jk9fZgfyi0VPw+nb7OCqJZxwDDOlDkePssbaonwHo2wv2gNRVpVnlsVGdhw/gD ftGw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=PQwumxLD0naoGLveJArJ+0uz+trgPMLG7ByeUUTiw3c=; b=eZStrrTHJ6wH9HtqS0wZ4dbiBYsEznAgqPYyAMNy8ikcZKUuBqrFQymJv771c+RLw7 DsPZQHk7AeTyrl1IMdqKT15EZbtuVVFPpe/aqeXUivVLGMbB48ksgUPIH5DPm7EGRGBe +CswelAycBjR5PASXSsGYRXNnzgFghjHWZJx0hUXvcIJ/qE2IfyrcdJgBYDXbKfo+eua EdzQ3ho3hlmd0UO/+j5I4OJbslX+9fBqzHab1bKF0S4Wcjqu1UWbzcMF0/Q+HH6q8ayP OI4wx2VpGZyrdQOMlfAm6+/PLiZgD1cOb8xu31SiJP/0Aox5hv7D3CKliUfijyqJiY1n cC/w== X-Gm-Message-State: APjAAAVtGyHaLZnhvkiq+gkrHAJl1+waBCU0GEVKcqI90CvGgq4Momtf tN6lVngm+nWH3sQbxwuPsCltILcGNL+Jmg== X-Google-Smtp-Source: APXvYqxb6VFRSxmBw5yM1EvaeAJ4KQfy4lw+UlWyHv58aLXC6tn5xi88QV1KsbWpYZu8SFGnbvRkkw== X-Received: by 2002:a5d:6ac8:: with SMTP id u8mr7733455wrw.104.1567525018262; Tue, 03 Sep 2019 08:36:58 -0700 (PDT) Received: from orth.archaic.org.uk (orth.archaic.org.uk. [81.2.115.148]) by smtp.gmail.com with ESMTPSA id a18sm24435188wrt.18.2019.09.03.08.36.57 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 03 Sep 2019 08:36:57 -0700 (PDT) From: Peter Maydell To: qemu-devel@nongnu.org Date: Tue, 3 Sep 2019 16:36:32 +0100 Message-Id: <20190903153633.6651-21-peter.maydell@linaro.org> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20190903153633.6651-1-peter.maydell@linaro.org> References: <20190903153633.6651-1-peter.maydell@linaro.org> MIME-Version: 1.0 X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2a00:1450:4864:20::444 Subject: [Qemu-devel] [PULL 20/21] target/arm: Free TCG temps in trans_VMOV_64_sp() X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patchwork-qemu-devel=patchwork.kernel.org@nongnu.org Sender: "Qemu-devel" The function neon_store_reg32() doesn't free the TCG temp that it is passed, so the caller must do that. We got this right in most places but forgot to free the TCG temps in trans_VMOV_64_sp(). Cc: qemu-stable@nongnu.org Signed-off-by: Peter Maydell Reviewed-by: Richard Henderson Reviewed-by: Philippe Mathieu-Daudé Message-id: 20190827121931.26836-1-peter.maydell@linaro.org --- target/arm/translate-vfp.inc.c | 2 ++ 1 file changed, 2 insertions(+) diff --git a/target/arm/translate-vfp.inc.c b/target/arm/translate-vfp.inc.c index 3e8ea80493b..9ae980bef63 100644 --- a/target/arm/translate-vfp.inc.c +++ b/target/arm/translate-vfp.inc.c @@ -880,8 +880,10 @@ static bool trans_VMOV_64_sp(DisasContext *s, arg_VMOV_64_sp *a) /* gpreg to fpreg */ tmp = load_reg(s, a->rt); neon_store_reg32(tmp, a->vm); + tcg_temp_free_i32(tmp); tmp = load_reg(s, a->rt2); neon_store_reg32(tmp, a->vm + 1); + tcg_temp_free_i32(tmp); } return true; From patchwork Tue Sep 3 15:36:33 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Peter Maydell X-Patchwork-Id: 11128323 Return-Path: Received: from mail.kernel.org (pdx-korg-mail-1.web.codeaurora.org [172.30.200.123]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id 683A714F7 for ; Tue, 3 Sep 2019 15:59:50 +0000 (UTC) Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id 3CEC122CF8 for ; Tue, 3 Sep 2019 15:59:50 +0000 (UTC) Authentication-Results: mail.kernel.org; dkim=fail reason="signature verification failed" (2048-bit key) header.d=linaro.org header.i=@linaro.org header.b="P4QFAkZQ" DMARC-Filter: OpenDMARC Filter v1.3.2 mail.kernel.org 3CEC122CF8 Authentication-Results: mail.kernel.org; dmarc=fail (p=none dis=none) header.from=linaro.org Authentication-Results: mail.kernel.org; spf=pass smtp.mailfrom=qemu-devel-bounces+patchwork-qemu-devel=patchwork.kernel.org@nongnu.org Received: from localhost ([::1]:48036 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1i5BDh-00010A-1f for patchwork-qemu-devel@patchwork.kernel.org; Tue, 03 Sep 2019 11:59:49 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:59385) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1i5Are-0003B2-0q for qemu-devel@nongnu.org; Tue, 03 Sep 2019 11:37:03 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1i5Arc-000668-IE for qemu-devel@nongnu.org; Tue, 03 Sep 2019 11:37:01 -0400 Received: from mail-wr1-x443.google.com ([2a00:1450:4864:20::443]:46451) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1i5Arc-00065U-BR for qemu-devel@nongnu.org; Tue, 03 Sep 2019 11:37:00 -0400 Received: by mail-wr1-x443.google.com with SMTP id h7so16669879wrt.13 for ; Tue, 03 Sep 2019 08:37:00 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:subject:date:message-id:in-reply-to:references:mime-version :content-transfer-encoding; bh=ajJo8M0JKSN4/WIzHMm40PvDhk2VCRR0BAjSpMU/81k=; b=P4QFAkZQ0uPKN9bmnYswYYaDaeqzSk3Kd6jvJn7CT+qdusrc1gJxROdlmQITrBdLma S+pewE9V4UF4QfRPzghDME6hBwVf6/se0pOWMcpQfDvttaZUExuPk79DgrUBXZt3BOna C+n5iXtcS7jK9kzrr+W2dwBG1B3iT01lfZvSFMMz7GjWG4Ezvr1n02ECuYgeHtNZaBMc rOlK3H0XLGII0EpKnLZtAlhyE18qgcV5O9AILyZfKxEa/hdqcNjuusQJGsnA+5rhPXHf D7qUbqRX+nFf0kpZckGlRFKudms75YmjvU1/pEfPo0L8PpaM/xLlWFkutJERp/JeIhQ5 IcJw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=ajJo8M0JKSN4/WIzHMm40PvDhk2VCRR0BAjSpMU/81k=; b=cfYpRKZzBIBQWe7DsEssCnZNgpWQNxa5mpy+9OBUPZbVy/38s+9fHxYfaVHKg181Xf 59IzRdO/iWcsGN3yLC9aD2by3q9HX9x4oIsqK18kqc82MGTPhdMSa6/V6i4R+cVeD5aZ 2tTczPVAJNOf9HzTXPqqY5Hq33lnIAcCsfdSokdFCkfHIrWYZM6afRKrFlDWb8pV59HH JvMPfK8ebzzHGMm4BMzDqmwsaVlBcsigwfTVNi2UjrP7KRNn5m/TqlVjc+Gu7dh+crvw DivAZpIjebyQwkwgnBG+Tp64ts31q8UTYvmOlAKZzf+I5s5+mgpfiW2+AMZwUApC2h8X JWOg== X-Gm-Message-State: APjAAAUfb5mhTx87qKh+XYOiMIydC5FBeQlI/1SUDjskj3LeI2cWQzTv 8RRYNqHL4/+dRGgYUi+HpDEPk9Dtu9gdLg== X-Google-Smtp-Source: APXvYqxxpHq0YVSRLmNmMQh1+Fs3gEcwzmEU65xBoVMiSBtxJGqUzk0xEx4O3tOmymtgroue2D70sg== X-Received: by 2002:adf:eec5:: with SMTP id a5mr43743729wrp.352.1567525019151; Tue, 03 Sep 2019 08:36:59 -0700 (PDT) Received: from orth.archaic.org.uk (orth.archaic.org.uk. [81.2.115.148]) by smtp.gmail.com with ESMTPSA id a18sm24435188wrt.18.2019.09.03.08.36.58 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 03 Sep 2019 08:36:58 -0700 (PDT) From: Peter Maydell To: qemu-devel@nongnu.org Date: Tue, 3 Sep 2019 16:36:33 +0100 Message-Id: <20190903153633.6651-22-peter.maydell@linaro.org> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20190903153633.6651-1-peter.maydell@linaro.org> References: <20190903153633.6651-1-peter.maydell@linaro.org> MIME-Version: 1.0 X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2a00:1450:4864:20::443 Subject: [Qemu-devel] [PULL 21/21] target/arm: Don't abort on M-profile exception return in linux-user mode X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patchwork-qemu-devel=patchwork.kernel.org@nongnu.org Sender: "Qemu-devel" An attempt to do an exception-return (branch to one of the magic addresses) in linux-user mode for M-profile should behave like a normal branch, because linux-user mode is always going to be in 'handler' mode. This used to work, but we broke it when we added support for the M-profile security extension in commit d02a8698d7ae2bfed. In that commit we allowed even handler-mode calls to magic return values to be checked for and dealt with by causing an EXCP_EXCEPTION_EXIT exception to be taken, because this is needed for the FNC_RETURN return-from-non-secure-function-call handling. For system mode we added a check in do_v7m_exception_exit() to make any spurious calls from Handler mode behave correctly, but forgot that linux-user mode would also be affected. How an attempted return-from-non-secure-function-call in linux-user mode should be handled is not clear -- on real hardware it would result in return to secure code (not to the Linux kernel) which could then handle the error in any way it chose. For QEMU we take the simple approach of treating this erroneous return the same way it would be handled on a CPU without the security extensions -- treat it as a normal branch. The upshot of all this is that for linux-user mode we should never do any of the bx_excret magic, so the code change is simple. This ought to be a weird corner case that only affects broken guest code (because Linux user processes should never be attempting to do exception returns or NS function returns), except that the code that assigns addresses in RAM for the process and stack in our linux-user code does not attempt to avoid this magic address range, so legitimate code attempting to return to a trampoline routine on the stack can fall into this case. This change fixes those programs, but we should also look at restricting the range of memory we use for M-profile linux-user guests to the area that would be real RAM in hardware. Cc: qemu-stable@nongnu.org Reported-by: Christophe Lyon Reviewed-by: Richard Henderson Signed-off-by: Peter Maydell Message-id: 20190822131534.16602-1-peter.maydell@linaro.org Fixes: https://bugs.launchpad.net/qemu/+bug/1840922 Signed-off-by: Peter Maydell --- target/arm/translate.c | 21 ++++++++++++++++++++- 1 file changed, 20 insertions(+), 1 deletion(-) diff --git a/target/arm/translate.c b/target/arm/translate.c index cfebd35d268..615859e23c5 100644 --- a/target/arm/translate.c +++ b/target/arm/translate.c @@ -915,10 +915,27 @@ static inline void gen_bx(DisasContext *s, TCGv_i32 var) store_cpu_field(var, thumb); } -/* Set PC and Thumb state from var. var is marked as dead. +/* + * Set PC and Thumb state from var. var is marked as dead. * For M-profile CPUs, include logic to detect exception-return * branches and handle them. This is needed for Thumb POP/LDM to PC, LDR to PC, * and BX reg, and no others, and happens only for code in Handler mode. + * The Security Extension also requires us to check for the FNC_RETURN + * which signals a function return from non-secure state; this can happen + * in both Handler and Thread mode. + * To avoid having to do multiple comparisons in inline generated code, + * we make the check we do here loose, so it will match for EXC_RETURN + * in Thread mode. For system emulation do_v7m_exception_exit() checks + * for these spurious cases and returns without doing anything (giving + * the same behaviour as for a branch to a non-magic address). + * + * In linux-user mode it is unclear what the right behaviour for an + * attempted FNC_RETURN should be, because in real hardware this will go + * directly to Secure code (ie not the Linux kernel) which will then treat + * the error in any way it chooses. For QEMU we opt to make the FNC_RETURN + * attempt behave the way it would on a CPU without the security extension, + * which is to say "like a normal branch". That means we can simply treat + * all branches as normal with no magic address behaviour. */ static inline void gen_bx_excret(DisasContext *s, TCGv_i32 var) { @@ -926,10 +943,12 @@ static inline void gen_bx_excret(DisasContext *s, TCGv_i32 var) * s->base.is_jmp that we need to do the rest of the work later. */ gen_bx(s, var); +#ifndef CONFIG_USER_ONLY if (arm_dc_feature(s, ARM_FEATURE_M_SECURITY) || (s->v7m_handler_mode && arm_dc_feature(s, ARM_FEATURE_M))) { s->base.is_jmp = DISAS_BX_EXCRET; } +#endif } static inline void gen_bx_excret_final_code(DisasContext *s)