From patchwork Tue Sep 3 21:57:54 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Oliver Upton X-Patchwork-Id: 11129041 Return-Path: Received: from mail.kernel.org (pdx-korg-mail-1.web.codeaurora.org [172.30.200.123]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id 4C5751398 for ; Tue, 3 Sep 2019 21:58:10 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.kernel.org (Postfix) with ESMTP id 2CB1122DBF for ; Tue, 3 Sep 2019 21:58:10 +0000 (UTC) Authentication-Results: mail.kernel.org; dkim=pass (2048-bit key) header.d=google.com header.i=@google.com header.b="CsgxhoKj" Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1726618AbfICV6J (ORCPT ); Tue, 3 Sep 2019 17:58:09 -0400 Received: from mail-pf1-f201.google.com ([209.85.210.201]:34161 "EHLO mail-pf1-f201.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1725977AbfICV6I (ORCPT ); Tue, 3 Sep 2019 17:58:08 -0400 Received: by mail-pf1-f201.google.com with SMTP id i2so15079351pfe.1 for ; Tue, 03 Sep 2019 14:58:08 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=20161025; h=date:in-reply-to:message-id:mime-version:references:subject:from:to :cc; bh=NRnaqKGOMM6Gjnc7Eddxq9QW9f6iAXK8LuOyj+cE24g=; b=CsgxhoKjBKHgFbzYo6dd9pFseWpzj5zcbk+HgNRBZbbkTXkitapVLutpUGTot5qvkX SWEop8n4jTkw0hHbv2FAdWL369nAGHTLDPBGuly3uUvRFPfLdunNwoJqrEf/KtJ9QPm3 aG3W3RfZ5DlPvdldWmcXAocTQyfMZTk4cBFZpoX8Om7/S2FascWU6bPM/8FISiOfOeqW /b/sjYMFLaH9tteCmLY4EtCOQ3aLE/soQf+m/mFkoGy+N3kGQh4aG0+gBQH76JsGou/l TsyTaTkM8BsT1oSgwI4cLvqW3dQHgRWyE361b2nL9UcPe7cC6gALHATj0SOLnD1m2W/X TqyQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:date:in-reply-to:message-id:mime-version :references:subject:from:to:cc; bh=NRnaqKGOMM6Gjnc7Eddxq9QW9f6iAXK8LuOyj+cE24g=; b=TuKSKrAeUeOE2sbBf4285VCgHdTMFkoVxQUJE2zcfKu0ParkuOWKudEAeLqrv8DOlK BvkuziCGWHJ4357+j8RZyn2C/3HgeHiyMPERXHYqnbog6lI5jLxC4gVfzHJE+3bEI1TW PvqhnIRlRrZTFN1/7vXU0fVgQ//204FWg/ASgl4lStb7eP7X/ZhKKUdLKE3ffUr1BnSf jpyq0CG0+QnNJV2chkfc5RE4rliZfD3uB8vlM16WSGmvL/Jws0iFOSMybFIUacGs07eO BkgSxkFRAHP42p5SDYVKMY/Yg2O+PYgDD1glGc2CkETZ32RmjPVju8Q9TJrwIM2dzSiJ bffg== X-Gm-Message-State: APjAAAXYW8If+dQkkSOMxlp1KAbEKbdxdIvJtD/2lN6iw1m2kQ9CKq1g oUyomRWsvmbPLC1lhd+uXsDjoMQwAW9SxpMYWNq3sYAPfJnP7Re+4KsjBUNvlt/0e2/nPoYjcm5 1ybcwCHHcV6kjxgMpxDghXMnJyVVnJTzmB8tfHcllzzZ1ykWw/87hkdqPqg== X-Google-Smtp-Source: APXvYqzZ3af0gEwBYRpliQddxD82oMBbJ5OKlxf/8ROle4Qg+Q6ObuxMkPfpf9gBifZnXgi+6RkL2xjXUdU= X-Received: by 2002:a63:f048:: with SMTP id s8mr31617484pgj.26.1567547887571; Tue, 03 Sep 2019 14:58:07 -0700 (PDT) Date: Tue, 3 Sep 2019 14:57:54 -0700 In-Reply-To: <20190903215801.183193-1-oupton@google.com> Message-Id: <20190903215801.183193-2-oupton@google.com> Mime-Version: 1.0 References: <20190903215801.183193-1-oupton@google.com> X-Mailer: git-send-email 2.23.0.187.g17f5b7556c-goog Subject: [PATCH v3 1/8] KVM: nVMX: Use kvm_set_msr to load IA32_PERF_GLOBAL_CTRL on vmexit From: Oliver Upton To: kvm@vger.kernel.org, Paolo Bonzini , " =?utf-8?b?UmFkaW0gS3LEjW3DocWZ?= " Cc: Jim Mattson , Peter Shier , Krish Sadhukhan , Sean Christopherson , Oliver Upton Sender: kvm-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: kvm@vger.kernel.org The existing implementation for loading the IA32_PERF_GLOBAL_CTRL MSR on VM-exit was incorrect, as the next call to atomic_switch_perf_msrs() could cause this value to be overwritten. Instead, call kvm_set_msr() which will allow atomic_switch_perf_msrs() to correctly set the values. Suggested-by: Jim Mattson Co-developed-by: Krish Sadhukhan Signed-off-by: Krish Sadhukhan Signed-off-by: Oliver Upton --- arch/x86/kvm/vmx/nested.c | 13 ++++++++++--- 1 file changed, 10 insertions(+), 3 deletions(-) diff --git a/arch/x86/kvm/vmx/nested.c b/arch/x86/kvm/vmx/nested.c index ced9fba32598..b0ca34bf4d21 100644 --- a/arch/x86/kvm/vmx/nested.c +++ b/arch/x86/kvm/vmx/nested.c @@ -3724,6 +3724,7 @@ static void load_vmcs12_host_state(struct kvm_vcpu *vcpu, struct vmcs12 *vmcs12) { struct kvm_segment seg; + struct msr_data msr_info; u32 entry_failure_code; if (vmcs12->vm_exit_controls & VM_EXIT_LOAD_IA32_EFER) @@ -3800,9 +3801,15 @@ static void load_vmcs12_host_state(struct kvm_vcpu *vcpu, vmcs_write64(GUEST_IA32_PAT, vmcs12->host_ia32_pat); vcpu->arch.pat = vmcs12->host_ia32_pat; } - if (vmcs12->vm_exit_controls & VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL) - vmcs_write64(GUEST_IA32_PERF_GLOBAL_CTRL, - vmcs12->host_ia32_perf_global_ctrl); + if (vmcs12->vm_exit_controls & VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL) { + msr_info.host_initiated = false; + msr_info.index = MSR_CORE_PERF_GLOBAL_CTRL; + msr_info.data = vmcs12->host_ia32_perf_global_ctrl; + if (kvm_set_msr(vcpu, &msr_info)) + pr_debug_ratelimited( + "%s cannot write MSR (0x%x, 0x%llx)\n", + __func__, msr_info.index, msr_info.data); + } /* Set L1 segment info according to Intel SDM 27.5.2 Loading Host Segment and Descriptor-Table Registers */ From patchwork Tue Sep 3 21:57:55 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Oliver Upton X-Patchwork-Id: 11129043 Return-Path: Received: from mail.kernel.org (pdx-korg-mail-1.web.codeaurora.org [172.30.200.123]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id EFD0D1398 for ; Tue, 3 Sep 2019 21:58:11 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.kernel.org (Postfix) with ESMTP id D0A7F22DBF for ; Tue, 3 Sep 2019 21:58:11 +0000 (UTC) Authentication-Results: mail.kernel.org; dkim=pass (2048-bit key) header.d=google.com header.i=@google.com header.b="j7BQYA63" Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1727001AbfICV6L (ORCPT ); Tue, 3 Sep 2019 17:58:11 -0400 Received: from mail-pf1-f201.google.com ([209.85.210.201]:47518 "EHLO mail-pf1-f201.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1726394AbfICV6L (ORCPT ); Tue, 3 Sep 2019 17:58:11 -0400 Received: by mail-pf1-f201.google.com with SMTP id t65so6822141pfd.14 for ; Tue, 03 Sep 2019 14:58:10 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=20161025; h=date:in-reply-to:message-id:mime-version:references:subject:from:to :cc; bh=fcoVJDUBj34OIRUUO2z2NksJF6mZCBPDrz/OCdU83nk=; b=j7BQYA63JpJqVOR5aEh4D6opVG/GYwcDtirUeR+Ydzume/HQNBBbIUcYglPCgXEdF9 6/asZ9/8VREqh454J+sOuIoMO5vTF5SgMDFxB1BHJjd3DfcCHJ5HV+n/djK8+PNM6ht6 bV7faZAXSXo0nOC6AqsiNUsN7TLXOaDQHpErnh+J9iQQZQ/niGSKnr0M+u5OfMvXyJTh cSlESh+hTZBjVqgyXgrObxS6GtZF7ae/dMvCiGoyGWHukS/Ai/Ui4hWwWNdszSVjNyyu bbTv/eci8dlEfXr6/dSz1VhUrIoxxVUGjfc/697GH3D3GxDW55KqZDQ/rK9UlihhCQ6s ye3A== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:date:in-reply-to:message-id:mime-version :references:subject:from:to:cc; bh=fcoVJDUBj34OIRUUO2z2NksJF6mZCBPDrz/OCdU83nk=; b=qFjnBFnO8HqHl39NufiYQKYHX5pKCeEZaFMiNaoQ2gOafeVO1bH2zTHnqeQOS3akmN Cpa4cV1uty7FhIGxj0gU7XZuSc9lkGsk3Sf6PDsBkLYvqdm4M8ElD95d89kV/3RWpavm gmroXJHDhy3vWiUnjuqEDadI6le0Y/C0oWAPqccnqeBoGZI0mtwzmimAAW4JAeZ98Bvb yk8tnQtqGSF5YKBHCdONUkTlNSjxlmdPiD42pUlgJSscdFkRM2dV5lpW8+EHRLGInCkE wWHylBvd+VzYG47m5V8fXq1knXkMY5D2jVgoN3gEXY0VpLmXF6TrB5VUTZAHQnbpdmMe tN4A== X-Gm-Message-State: APjAAAUnS8NTSj/wvw7JfZtTSFxf4FwzcWyhghgXqtD/dI6cmQ6wU24U rvJteNB4Yw3JfIGSGCOMK6evv1AG22GEue5RTzkDvzRZG18x/NlGO5F7sZirRGym2ucVSDLxCXu sRdwMZZ5MzqGNkL8i4h8twuNBnNR5IO1Mm4QEBT6Ky1t3GZWHa8HCm022Fw== X-Google-Smtp-Source: APXvYqxWgOK4N6r7+8i9Jga2cqoWS7suhD2Oxa0gNlgODI2Z/700nGhN1P83tbtmf6Yg4/PM4l/9likjiiE= X-Received: by 2002:a65:6114:: with SMTP id z20mr32656978pgu.141.1567547889917; Tue, 03 Sep 2019 14:58:09 -0700 (PDT) Date: Tue, 3 Sep 2019 14:57:55 -0700 In-Reply-To: <20190903215801.183193-1-oupton@google.com> Message-Id: <20190903215801.183193-3-oupton@google.com> Mime-Version: 1.0 References: <20190903215801.183193-1-oupton@google.com> X-Mailer: git-send-email 2.23.0.187.g17f5b7556c-goog Subject: [PATCH v3 2/8] KVM: nVMX: Load GUEST_IA32_PERF_GLOBAL_CTRL MSR on vm-entry From: Oliver Upton To: kvm@vger.kernel.org, Paolo Bonzini , " =?utf-8?b?UmFkaW0gS3LEjW3DocWZ?= " Cc: Jim Mattson , Peter Shier , Krish Sadhukhan , Sean Christopherson , Oliver Upton Sender: kvm-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: kvm@vger.kernel.org Add condition to prepare_vmcs02 which loads IA32_PERF_GLOBAL_CTRL on VM-entry if the "load IA32_PERF_GLOBAL_CTRL" bit on the VM-entry control is set. Use kvm_set_msr() rather than directly writing to the field to avoid overwrite by atomic_switch_perf_msrs(). Suggested-by: Jim Mattson Co-developed-by: Krish Sadhukhan Signed-off-by: Krish Sadhukhan Signed-off-by: Oliver Upton --- arch/x86/kvm/vmx/nested.c | 11 +++++++++++ 1 file changed, 11 insertions(+) diff --git a/arch/x86/kvm/vmx/nested.c b/arch/x86/kvm/vmx/nested.c index b0ca34bf4d21..9ba90b38d74b 100644 --- a/arch/x86/kvm/vmx/nested.c +++ b/arch/x86/kvm/vmx/nested.c @@ -2281,6 +2281,7 @@ static int prepare_vmcs02(struct kvm_vcpu *vcpu, struct vmcs12 *vmcs12, { struct vcpu_vmx *vmx = to_vmx(vcpu); struct hv_enlightened_vmcs *hv_evmcs = vmx->nested.hv_evmcs; + struct msr_data msr_info; bool load_guest_pdptrs_vmcs12 = false; if (vmx->nested.dirty_vmcs12 || hv_evmcs) { @@ -2404,6 +2405,16 @@ static int prepare_vmcs02(struct kvm_vcpu *vcpu, struct vmcs12 *vmcs12, if (!enable_ept) vcpu->arch.walk_mmu->inject_page_fault = vmx_inject_page_fault_nested; + if (vmcs12->vm_entry_controls & VM_ENTRY_LOAD_IA32_PERF_GLOBAL_CTRL) { + msr_info.host_initiated = false; + msr_info.index = MSR_CORE_PERF_GLOBAL_CTRL; + msr_info.data = vmcs12->guest_ia32_perf_global_ctrl; + if (kvm_set_msr(vcpu, &msr_info)) + pr_debug_ratelimited( + "%s cannot write MSR (0x%x, 0x%llx)\n", + __func__, msr_info.index, msr_info.data); + } + kvm_rsp_write(vcpu, vmcs12->guest_rsp); kvm_rip_write(vcpu, vmcs12->guest_rip); return 0; From patchwork Tue Sep 3 21:57:56 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Oliver Upton X-Patchwork-Id: 11129045 Return-Path: Received: from mail.kernel.org (pdx-korg-mail-1.web.codeaurora.org [172.30.200.123]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id 7AFDC13B1 for ; Tue, 3 Sep 2019 21:58:14 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.kernel.org (Postfix) with ESMTP id 5BEAB22DBF for ; Tue, 3 Sep 2019 21:58:14 +0000 (UTC) Authentication-Results: mail.kernel.org; dkim=pass (2048-bit key) header.d=google.com header.i=@google.com header.b="ks/oEu66" Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1726440AbfICV6N (ORCPT ); Tue, 3 Sep 2019 17:58:13 -0400 Received: from mail-pf1-f201.google.com ([209.85.210.201]:52931 "EHLO mail-pf1-f201.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1725977AbfICV6N (ORCPT ); Tue, 3 Sep 2019 17:58:13 -0400 Received: by mail-pf1-f201.google.com with SMTP id r17so13825059pfr.19 for ; Tue, 03 Sep 2019 14:58:12 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=20161025; h=date:in-reply-to:message-id:mime-version:references:subject:from:to :cc; bh=JSryJzYZ9PIhYaiF8Id4XIwHE6X9RIx2Lk1b+qLQLNs=; b=ks/oEu66jZHhGVVy5s0324/EZ7rOy3Ql6s3n4x/MEqRMZrzn+OUzaTcb1u3QNiSbFg cNk5EC7wUqB88Ambim1v+dBj72q5rtiIr+xNJT9Kq6/iL2YkrHqZSfZkNrVpmQgprItC Ane/Nyqh/BKuJR4lriyo92sIbYqZuMjn9CuyV2CuehJ5cbSWns3JVjIaT6UJpHklskPC B5AZ06WhDPSrV1F/vdfeDCsVpi+yLobXZHmbhbRSDfC+ZlWVR/EWC4fPBBtJ1Mz1iDaP 8N73HyiMKYeBF8AuIUpGm2qh1VMmy1uhk47GSIG0IJ5v4oKpAhLI0ioyi2IE0t8nGerY UMUw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:date:in-reply-to:message-id:mime-version :references:subject:from:to:cc; bh=JSryJzYZ9PIhYaiF8Id4XIwHE6X9RIx2Lk1b+qLQLNs=; b=aFS0Fl7nwEVnQyCWF0YgssqDQZB2qT/Ogdvup12ffNstG5Bg2FAsKEfr+M7EqX0HsM IqO1dTgBVyBaEh5HoqnUuxwJd2/vaOzVHxnEOxvpgwvE2N90LGq9GePDEdm9ByNTDhOS tzB80tJ6tjcsBIs5DFY7Q2rNHYkKqHXnJrv0l6wU9L712rWPkajBl/oQeubK//dqDO6N eemtghU24jSpejM2H/Pv6iXt3BTo44ikvAS9pckpxWaUg8ryZtJON+SKOSerOEA0dL5x nYMjqMMEqA+2V72m8qgAJQntEqEMXlJEylubvulASnifZPA8xh9C5M2D9PqHTMOh6z3N W0Jg== X-Gm-Message-State: APjAAAVqbd6vwmuhNEVJyKkTQM3v+7t2QT0H0IcnRLIXfzef+2EnXtYQ HePxtM1ZwwiZ4ycpBT+X86mDRuMt5UvaykKBNli+uaGuDHQbClCbeuikMEslSE7wLVPOSHCJfOs 1m+Hz7vShOdDLpCugPaxknNsX4ELs/85fEFZHwfNO9BtlBuzk8wQYk9epPQ== X-Google-Smtp-Source: APXvYqxAkxLsaAqjDGK3fMNdYwwrHtOMVVexaOGxjd1TziFl84bKa8uAWVC67iEv9N5/G+fsS7P9l2DzhJo= X-Received: by 2002:a65:50c5:: with SMTP id s5mr32209259pgp.368.1567547891904; Tue, 03 Sep 2019 14:58:11 -0700 (PDT) Date: Tue, 3 Sep 2019 14:57:56 -0700 In-Reply-To: <20190903215801.183193-1-oupton@google.com> Message-Id: <20190903215801.183193-4-oupton@google.com> Mime-Version: 1.0 References: <20190903215801.183193-1-oupton@google.com> X-Mailer: git-send-email 2.23.0.187.g17f5b7556c-goog Subject: [PATCH v3 3/8] KVM: VMX: Add helper to check reserved bits in IA32_PERF_GLOBAL_CTRL From: Oliver Upton To: kvm@vger.kernel.org, Paolo Bonzini , " =?utf-8?b?UmFkaW0gS3LEjW3DocWZ?= " Cc: Jim Mattson , Peter Shier , Krish Sadhukhan , Sean Christopherson , Oliver Upton Sender: kvm-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: kvm@vger.kernel.org Create a helper function to check the validity of a proposed value for IA32_PERF_GLOBAL_CTRL from the existing check in intel_pmu_set_msr(). Per Intel's SDM, the reserved bits in IA32_PERF_GLOBAL_CTRL must be cleared for the corresponding host/guest state fields. Suggested-by: Jim Mattson Co-developed-by: Krish Sadhukhan Signed-off-by: Krish Sadhukhan Signed-off-by: Oliver Upton --- arch/x86/kvm/pmu.h | 6 ++++++ arch/x86/kvm/vmx/pmu_intel.c | 2 +- 2 files changed, 7 insertions(+), 1 deletion(-) diff --git a/arch/x86/kvm/pmu.h b/arch/x86/kvm/pmu.h index 58265f761c3b..67a0f6da567c 100644 --- a/arch/x86/kvm/pmu.h +++ b/arch/x86/kvm/pmu.h @@ -79,6 +79,12 @@ static inline bool pmc_is_enabled(struct kvm_pmc *pmc) return kvm_x86_ops->pmu_ops->pmc_is_enabled(pmc); } +static inline bool kvm_is_valid_perf_global_ctrl(struct kvm_pmu *pmu, + u64 data) +{ + return !(pmu->global_ctrl_mask & data); +} + /* returns general purpose PMC with the specified MSR. Note that it can be * used for both PERFCTRn and EVNTSELn; that is why it accepts base as a * paramenter to tell them apart. diff --git a/arch/x86/kvm/vmx/pmu_intel.c b/arch/x86/kvm/vmx/pmu_intel.c index 4dea0e0e7e39..963766d631ad 100644 --- a/arch/x86/kvm/vmx/pmu_intel.c +++ b/arch/x86/kvm/vmx/pmu_intel.c @@ -223,7 +223,7 @@ static int intel_pmu_set_msr(struct kvm_vcpu *vcpu, struct msr_data *msr_info) case MSR_CORE_PERF_GLOBAL_CTRL: if (pmu->global_ctrl == data) return 0; - if (!(data & pmu->global_ctrl_mask)) { + if (kvm_is_valid_perf_global_ctrl(pmu, data)) { global_ctrl_changed(pmu, data); return 0; } From patchwork Tue Sep 3 21:57:57 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Oliver Upton X-Patchwork-Id: 11129047 Return-Path: Received: from mail.kernel.org (pdx-korg-mail-1.web.codeaurora.org [172.30.200.123]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id D3FBE13B1 for ; Tue, 3 Sep 2019 21:58:16 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.kernel.org (Postfix) with ESMTP id B4B7622DBF for ; Tue, 3 Sep 2019 21:58:16 +0000 (UTC) Authentication-Results: mail.kernel.org; dkim=pass (2048-bit key) header.d=google.com header.i=@google.com header.b="kBn3nfzt" Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1727102AbfICV6P (ORCPT ); Tue, 3 Sep 2019 17:58:15 -0400 Received: from mail-qt1-f201.google.com ([209.85.160.201]:44879 "EHLO mail-qt1-f201.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1726925AbfICV6P (ORCPT ); Tue, 3 Sep 2019 17:58:15 -0400 Received: by mail-qt1-f201.google.com with SMTP id x11so20493334qtm.11 for ; Tue, 03 Sep 2019 14:58:14 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=20161025; h=date:in-reply-to:message-id:mime-version:references:subject:from:to :cc; bh=Opg5K1QfrL8nEMY8t4QOtAKo0xuR0xFxDl5Hh7Z9H/0=; b=kBn3nfztver7r9D+hzMmnoPglCIssZB2FdcQTAlHzxYOpqfSCCCGptkaBJZ9xdqO8J mV7LJKJ/vemFGcLOEsPz/J2fYtmKUTkCSnfC7bGnfYzQaLuyrUqoTbi5yF7Xwl1CcZ1M Wf23ltbOYiXIpPjWPWVae22mUX8UvZVFncszCdGw0+6TZ8dcgFL6PgIKZ9OS6j+UZQ/I CvF+Zde64wiRZzGm7aIlbNjhpPhrFTA+eHF4IwAvVPGS3TvYTns1NoBJSVZI6aUSTnNs FmwRZ8o8dYWKWnQ7b0K2m1amoIrlrYnejORBny7Rt97j9EbCMeGcxGE9qibzOnGTLO6u xsxA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:date:in-reply-to:message-id:mime-version :references:subject:from:to:cc; bh=Opg5K1QfrL8nEMY8t4QOtAKo0xuR0xFxDl5Hh7Z9H/0=; b=oVcdtCY+R1drZAIyE01hBrR+ufGt2Hdf8A+ZR3y8DRKYuSahTnjtvmYy0SB3uJ35EN rPoYvQaOSh6f0tRIu+2JricppviqO2F1yE78H8WkNS8MnSxmGCoLIdFZpBLZ/AoeQEgq vVxWXTWyEPMbn5lzFT8ERYNYkHrfNjIddx1uH/6SYXY6P4BTX2njGUMmLVJvz9mBGcrq xr72rmCisiVnOiUZOE3a7NbTf+/eNYbQpRFNZX10BaLm76OGH+IgGFT8liALdV2oaG8j d4SQAd7bjSXWNv3p1Uust924a9QijXcB23sfcE8Ynga9qs10IaD4iPX2kpJlTWPyqDVi EiJA== X-Gm-Message-State: APjAAAUfVrfxt29RpLlIIvgP1q9nI55o4RFvULqSzBDDLG5jxtp829uw HrFLefSoLOUrIDYLkQAZ2T0u9jTufgjfjBqKSwczRF1LX0UL+D5yLiMP5f0dhMisj4sg0xoUgeY yTJIXpmsOUweWRBX9f2rqno1jCgTUGChzXr4uKXqFkz0xoCx9aqO5w9VVNg== X-Google-Smtp-Source: APXvYqws81C6DD7UQhkw6fevjmRA8koAn5oqA6UujleS/CsVshy/hkxW0TdDQqYJ1vH8ZiDmMsKbqeOADZg= X-Received: by 2002:ad4:4152:: with SMTP id z18mr12996110qvp.236.1567547894129; Tue, 03 Sep 2019 14:58:14 -0700 (PDT) Date: Tue, 3 Sep 2019 14:57:57 -0700 In-Reply-To: <20190903215801.183193-1-oupton@google.com> Message-Id: <20190903215801.183193-5-oupton@google.com> Mime-Version: 1.0 References: <20190903215801.183193-1-oupton@google.com> X-Mailer: git-send-email 2.23.0.187.g17f5b7556c-goog Subject: [PATCH v3 4/8] KVM: nVMX: check GUEST_IA32_PERF_GLOBAL_CTRL on VM-Entry From: Oliver Upton To: kvm@vger.kernel.org, Paolo Bonzini , " =?utf-8?b?UmFkaW0gS3LEjW3DocWZ?= " Cc: Jim Mattson , Peter Shier , Krish Sadhukhan , Sean Christopherson , Oliver Upton Sender: kvm-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: kvm@vger.kernel.org Add condition to nested_vmx_check_guest_state() to check the validity of GUEST_IA32_PERF_GLOBAL_CTRL. Per Intel's SDM Vol 3 26.3.1.1: If the "load IA32_PERF_GLOBAL_CTRL" VM-entry control is 1, bits reserved in the IA32_PERF_GLOBAL_CTRL MSR must be 0 in the field for that register. Suggested-by: Jim Mattson Co-developed-by: Krish Sadhukhan Signed-off-by: Krish Sadhukhan Signed-off-by: Oliver Upton --- arch/x86/kvm/vmx/nested.c | 7 +++++++ 1 file changed, 7 insertions(+) diff --git a/arch/x86/kvm/vmx/nested.c b/arch/x86/kvm/vmx/nested.c index 9ba90b38d74b..6c3aa3bcede3 100644 --- a/arch/x86/kvm/vmx/nested.c +++ b/arch/x86/kvm/vmx/nested.c @@ -10,6 +10,7 @@ #include "hyperv.h" #include "mmu.h" #include "nested.h" +#include "pmu.h" #include "trace.h" #include "x86.h" @@ -2732,6 +2733,7 @@ static int nested_vmx_check_guest_state(struct kvm_vcpu *vcpu, u32 *exit_qual) { bool ia32e; + struct kvm_pmu *pmu = vcpu_to_pmu(vcpu); *exit_qual = ENTRY_FAIL_DEFAULT; @@ -2748,6 +2750,11 @@ static int nested_vmx_check_guest_state(struct kvm_vcpu *vcpu, return -EINVAL; } + if (vmcs12->vm_entry_controls & VM_ENTRY_LOAD_IA32_PERF_GLOBAL_CTRL && + !kvm_is_valid_perf_global_ctrl(pmu, + vmcs12->guest_ia32_perf_global_ctrl)) + return -EINVAL; + /* * If the load IA32_EFER VM-entry control is 1, the following checks * are performed on the field for the IA32_EFER MSR: From patchwork Tue Sep 3 21:57:58 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Oliver Upton X-Patchwork-Id: 11129049 Return-Path: Received: from mail.kernel.org (pdx-korg-mail-1.web.codeaurora.org [172.30.200.123]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id D00BA1398 for ; Tue, 3 Sep 2019 21:58:18 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.kernel.org (Postfix) with ESMTP id AD35222CF7 for ; Tue, 3 Sep 2019 21:58:18 +0000 (UTC) Authentication-Results: mail.kernel.org; dkim=pass (2048-bit key) header.d=google.com header.i=@google.com header.b="V/9Vc1xd" Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1727061AbfICV6R (ORCPT ); Tue, 3 Sep 2019 17:58:17 -0400 Received: from mail-pf1-f202.google.com ([209.85.210.202]:34163 "EHLO mail-pf1-f202.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1727065AbfICV6R (ORCPT ); Tue, 3 Sep 2019 17:58:17 -0400 Received: by mail-pf1-f202.google.com with SMTP id i2so15079528pfe.1 for ; Tue, 03 Sep 2019 14:58:17 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=20161025; h=date:in-reply-to:message-id:mime-version:references:subject:from:to :cc; bh=7Sol8OKiw/oCQXDixwbMZoIVJoNgDr7xxGx+BS9mMiE=; b=V/9Vc1xdHGogcVS6tApZhv6WLjCahUjH174W8VjpbfFUG9hWtP+1WJZSX3rsVDV/Eo Zjya5sSKxezh6H3gwyHSrf+Wzui8ho39Ayu2k7E6o/e7wQDQQLts5RgMUjrEs1GPPzF1 Gcj5DMhxrjBM3exQY48C+aYWdqpDu6OtaWwnff73wXNRoVQS26SUtS7FMEQ7SgkOSd6Z HZ2c350ickyPWpqayFVZ9kctR5dsV+3RyhE64bRXV8hvzcn0lSFtDBYJu546TSbICHfX IVQ5PlfYNRKh+pofIDumvaBgQhoUzYaSeVijsJlQar9T+BlTDo+wc70AHcgxl6p2jwAy 4Zrw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:date:in-reply-to:message-id:mime-version :references:subject:from:to:cc; bh=7Sol8OKiw/oCQXDixwbMZoIVJoNgDr7xxGx+BS9mMiE=; b=Q3JmOOyHmmiCKsYHgaoqoVws83keP0aqFsLJSSCR5pKZILOU/fxoa9Ae3SwjzyI2wY OQLwerULIF1CG58vJ9kumRTx9t7AgjmnWt35bZLtlr9T4HyVVQgRlbVcuciYuA2THXfx LmlNy0LGnGoLGFchmEi7xIA+3CCim4eszmtlsJXCpHoUYcb2iSzmNLwlbIxAsg5pAEJ8 G1xBDGwxzDXul6UQfn9evzQWacuqxH+hfpgmQsYb3mFm8uyV1KffBb3YQaWeu9EGi0LR mcmJmS1ERuoxy1NHtHfywsHs7cbIK8cQZf0+j5mC5WF3OHvtptOhphcFRmYhKQHJgPJd d9Hg== X-Gm-Message-State: APjAAAVH+AWj0lVcxQCcrH6MjdIHIxbXXV0e4p2lSl9rjeCeuz/vXQfh PvpQ3z9dwZdPwaZ0o5y4g1Xb/FDbMdLOeie56Xvetvc3EavJQAUtMUMsbROM3PETfufw4oH87Hi lLLZ4Ylimdq+cDhQYFGV2RhKHmoh1r0UopS0fs/qRRBTqZ9IseiGXKxpUoQ== X-Google-Smtp-Source: APXvYqwFHtdiefGj+vxMUBnF3rRfClh7X4fWeIsJCQC6NfFUk2/GlTtiEIjn5aPcRayaxKjHVeFn8lvkkpk= X-Received: by 2002:a63:fe17:: with SMTP id p23mr32165383pgh.103.1567547896259; Tue, 03 Sep 2019 14:58:16 -0700 (PDT) Date: Tue, 3 Sep 2019 14:57:58 -0700 In-Reply-To: <20190903215801.183193-1-oupton@google.com> Message-Id: <20190903215801.183193-6-oupton@google.com> Mime-Version: 1.0 References: <20190903215801.183193-1-oupton@google.com> X-Mailer: git-send-email 2.23.0.187.g17f5b7556c-goog Subject: [PATCH v3 5/8] KVM: nVMX: Check HOST_IA32_PERF_GLOBAL_CTRL on VM-entry From: Oliver Upton To: kvm@vger.kernel.org, Paolo Bonzini , " =?utf-8?b?UmFkaW0gS3LEjW3DocWZ?= " Cc: Jim Mattson , Peter Shier , Krish Sadhukhan , Sean Christopherson , Oliver Upton Sender: kvm-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: kvm@vger.kernel.org Add a consistency check on nested vm-entry for host's IA32_PERF_GLOBAL_CTRL from vmcs12. Per Intel's SDM Vol 3 26.2.2: If the "load IA32_PERF_GLOBAL_CTRL" VM-exit control is 1, bits reserved in the IA32_PERF_GLOBAL_CTRL MSR must be 0 in the field for that register" Suggested-by: Jim Mattson Co-developed-by: Krish Sadhukhan Signed-off-by: Krish Sadhukhan Signed-off-by: Oliver Upton --- arch/x86/kvm/vmx/nested.c | 6 ++++++ 1 file changed, 6 insertions(+) diff --git a/arch/x86/kvm/vmx/nested.c b/arch/x86/kvm/vmx/nested.c index 6c3aa3bcede3..e2baa9ca562f 100644 --- a/arch/x86/kvm/vmx/nested.c +++ b/arch/x86/kvm/vmx/nested.c @@ -2636,6 +2636,7 @@ static int nested_vmx_check_host_state(struct kvm_vcpu *vcpu, struct vmcs12 *vmcs12) { bool ia32e; + struct kvm_pmu *pmu = vcpu_to_pmu(vcpu); if (!nested_host_cr0_valid(vcpu, vmcs12->host_cr0) || !nested_host_cr4_valid(vcpu, vmcs12->host_cr4) || @@ -2650,6 +2651,11 @@ static int nested_vmx_check_host_state(struct kvm_vcpu *vcpu, !kvm_pat_valid(vmcs12->host_ia32_pat)) return -EINVAL; + if (vmcs12->vm_exit_controls & VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL && + !kvm_is_valid_perf_global_ctrl(pmu, + vmcs12->host_ia32_perf_global_ctrl)) + return -EINVAL; + ia32e = (vmcs12->vm_exit_controls & VM_EXIT_HOST_ADDR_SPACE_SIZE) != 0; From patchwork Tue Sep 3 21:57:59 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Oliver Upton X-Patchwork-Id: 11129051 Return-Path: Received: from mail.kernel.org (pdx-korg-mail-1.web.codeaurora.org [172.30.200.123]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id 041E413B1 for ; Tue, 3 Sep 2019 21:58:21 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.kernel.org (Postfix) with ESMTP id D819322DBF for ; Tue, 3 Sep 2019 21:58:20 +0000 (UTC) Authentication-Results: mail.kernel.org; dkim=pass (2048-bit key) header.d=google.com header.i=@google.com header.b="pRl3qA4Z" Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1727192AbfICV6T (ORCPT ); Tue, 3 Sep 2019 17:58:19 -0400 Received: from mail-qt1-f201.google.com ([209.85.160.201]:44888 "EHLO mail-qt1-f201.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1726858AbfICV6T (ORCPT ); Tue, 3 Sep 2019 17:58:19 -0400 Received: by mail-qt1-f201.google.com with SMTP id x11so20493453qtm.11 for ; Tue, 03 Sep 2019 14:58:19 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=20161025; h=date:in-reply-to:message-id:mime-version:references:subject:from:to :cc; bh=bN2YbEcyYMUiFznHgJcQvFVodagIFOKOSU42bIILepg=; b=pRl3qA4ZMjmFbFObq0gqUUl4J2eWLVoeFmgun4FSp3mOeCemDaiycinWuX3fRd0iLS Cqp5tUbz1GXemXeiCTEi+JE+PdCPCfmKN9y7Gl8/k+V+wlz4jel9ApRrdPsjeYKQyjF6 RTnb/9j73EzUDcDFmVxgpER6Pxn3FkdHPpIvFHM4uATVjfu4395U1L3Zm9Tfghuz30/x lmU13o3qxG7FauMv5TgLfipNWNuqiUeW8BzCLLSEhMj8B6j1AYv/CEdiH3/rRpl404qw WXw7ungU8pMt3vDwvchxhN54PjK3i25ncgPpSm7X3cPAD0KUYJa10fsTAz5eHOAet6L5 bYZQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:date:in-reply-to:message-id:mime-version :references:subject:from:to:cc; bh=bN2YbEcyYMUiFznHgJcQvFVodagIFOKOSU42bIILepg=; b=RhVC7UQ2yKL4KsepjYFreBM0IauIfFg37+qeZR1gxJsNeFUsRhPf0iFu8KpKbwWx3T ran22Y3uXX8UJ2NfrRCMCpdYfYHFnpwC8+pTOmGEDs4Ni1JKfo1OepmSshuKJfDvM2vN w5VEGQoQlviuxaSt4Xn8ag+zdAc+/cW4SoSNGUDW0CUXeJC5C6SywPwBYDhCHvxW3c49 BK1+8GIl/eb+kJFBAzKGbyT8Rk7HvM7y4U7JNJ+tpQpP7j/z3glaXDg831lnZd1GhhXY WH3k1EMh85kw75vOqG5Vmdqa/d0v/apOjIar7boLBGrvLCZPN13xJ0giGTJX57skobpd o9Kw== X-Gm-Message-State: APjAAAVJW0Lb3gFrST7hp6AL1EJBTCYbHagdjHxFRL0Kid2Nh84ouWb2 SSCEL1qXu39BNju7l7p373sAZDua02uKydXJ4jGgoJk5revw5ql5RCbbFSAaquRMftyXXSbFguy qxHGscvPxDsCNfDIFTodb/Y07eJuJuLZUHo4OVBfl3yivw/jzg4xf+9+Lew== X-Google-Smtp-Source: APXvYqy+v161gVUZVluXDv4fXiJJtfgSAzr3L/+aD0m495I1evxelGTWrRAtTXi0neFkDQzQMS6kb9PLdWw= X-Received: by 2002:a37:a544:: with SMTP id o65mr34522857qke.252.1567547898569; Tue, 03 Sep 2019 14:58:18 -0700 (PDT) Date: Tue, 3 Sep 2019 14:57:59 -0700 In-Reply-To: <20190903215801.183193-1-oupton@google.com> Message-Id: <20190903215801.183193-7-oupton@google.com> Mime-Version: 1.0 References: <20190903215801.183193-1-oupton@google.com> X-Mailer: git-send-email 2.23.0.187.g17f5b7556c-goog Subject: [PATCH v3 6/8] KVM: nVMX: Expose load IA32_PERF_GLOBAL_CTRL vm control if supported From: Oliver Upton To: kvm@vger.kernel.org, Paolo Bonzini , " =?utf-8?b?UmFkaW0gS3LEjW3DocWZ?= " Cc: Jim Mattson , Peter Shier , Krish Sadhukhan , Sean Christopherson , Oliver Upton Sender: kvm-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: kvm@vger.kernel.org The "load IA32_PERF_GLOBAL_CTRL" bit for VM-entry and VM-exit should only be exposed to the guest if IA32_PERF_GLOBAL_CTRL is a valid MSR. Create a new helper to allow pmu_refresh() to update the VM-entry and VM-exit controls to ensure PMU values are initialized when performing the is_valid_msr() check. Suggested-by: Jim Mattson Co-developed-by: Krish Sadhukhan Signed-off-by: Krish Sadhukhan Signed-off-by: Oliver Upton --- arch/x86/kvm/vmx/pmu_intel.c | 3 +++ arch/x86/kvm/vmx/vmx.c | 21 +++++++++++++++++++++ arch/x86/kvm/vmx/vmx.h | 1 + 3 files changed, 25 insertions(+) diff --git a/arch/x86/kvm/vmx/pmu_intel.c b/arch/x86/kvm/vmx/pmu_intel.c index 963766d631ad..2dc7be724321 100644 --- a/arch/x86/kvm/vmx/pmu_intel.c +++ b/arch/x86/kvm/vmx/pmu_intel.c @@ -16,6 +16,7 @@ #include "cpuid.h" #include "lapic.h" #include "pmu.h" +#include "vmx.h" static struct kvm_event_hw_type_mapping intel_arch_events[] = { /* Index must match CPUID 0x0A.EBX bit vector */ @@ -314,6 +315,8 @@ static void intel_pmu_refresh(struct kvm_vcpu *vcpu) (boot_cpu_has(X86_FEATURE_HLE) || boot_cpu_has(X86_FEATURE_RTM)) && (entry->ebx & (X86_FEATURE_HLE|X86_FEATURE_RTM))) pmu->reserved_bits ^= HSW_IN_TX|HSW_IN_TX_CHECKPOINTED; + + nested_vmx_pmu_entry_exit_ctls_update(vcpu); } static void intel_pmu_init(struct kvm_vcpu *vcpu) diff --git a/arch/x86/kvm/vmx/vmx.c b/arch/x86/kvm/vmx/vmx.c index 570a233e272b..5b0664bff23b 100644 --- a/arch/x86/kvm/vmx/vmx.c +++ b/arch/x86/kvm/vmx/vmx.c @@ -6417,6 +6417,27 @@ void vmx_update_host_rsp(struct vcpu_vmx *vmx, unsigned long host_rsp) } } +void nested_vmx_pmu_entry_exit_ctls_update(struct kvm_vcpu *vcpu) +{ + struct vcpu_vmx *vmx; + + if (!nested_vmx_allowed(vcpu)) + return; + + vmx = to_vmx(vcpu); + if (intel_pmu_ops.is_valid_msr(vcpu, MSR_CORE_PERF_GLOBAL_CTRL)) { + vmx->nested.msrs.entry_ctls_high |= + VM_ENTRY_LOAD_IA32_PERF_GLOBAL_CTRL; + vmx->nested.msrs.exit_ctls_high |= + VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL; + } else { + vmx->nested.msrs.entry_ctls_high &= + ~VM_ENTRY_LOAD_IA32_PERF_GLOBAL_CTRL; + vmx->nested.msrs.exit_ctls_high &= + ~VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL; + } +} + bool __vmx_vcpu_run(struct vcpu_vmx *vmx, unsigned long *regs, bool launched); static void vmx_vcpu_run(struct kvm_vcpu *vcpu) diff --git a/arch/x86/kvm/vmx/vmx.h b/arch/x86/kvm/vmx/vmx.h index 82d0bc3a4d52..e06884cf88ad 100644 --- a/arch/x86/kvm/vmx/vmx.h +++ b/arch/x86/kvm/vmx/vmx.h @@ -331,6 +331,7 @@ void vmx_set_virtual_apic_mode(struct kvm_vcpu *vcpu); struct shared_msr_entry *find_msr_entry(struct vcpu_vmx *vmx, u32 msr); void pt_update_intercept_for_msr(struct vcpu_vmx *vmx); void vmx_update_host_rsp(struct vcpu_vmx *vmx, unsigned long host_rsp); +void nested_vmx_pmu_entry_exit_ctls_update(struct kvm_vcpu *vcpu); #define POSTED_INTR_ON 0 #define POSTED_INTR_SN 1 From patchwork Tue Sep 3 21:58:00 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Oliver Upton X-Patchwork-Id: 11129053 Return-Path: Received: from mail.kernel.org (pdx-korg-mail-1.web.codeaurora.org [172.30.200.123]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id 67EFC13B1 for ; Tue, 3 Sep 2019 21:58:23 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.kernel.org (Postfix) with ESMTP id 4804022CF7 for ; Tue, 3 Sep 2019 21:58:23 +0000 (UTC) Authentication-Results: mail.kernel.org; dkim=pass (2048-bit key) header.d=google.com header.i=@google.com header.b="jrwzcDhS" Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1727056AbfICV6W (ORCPT ); Tue, 3 Sep 2019 17:58:22 -0400 Received: from mail-pf1-f201.google.com ([209.85.210.201]:55505 "EHLO mail-pf1-f201.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1727257AbfICV6V (ORCPT ); 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Tue, 03 Sep 2019 14:58:20 -0700 (PDT) Date: Tue, 3 Sep 2019 14:58:00 -0700 In-Reply-To: <20190903215801.183193-1-oupton@google.com> Message-Id: <20190903215801.183193-8-oupton@google.com> Mime-Version: 1.0 References: <20190903215801.183193-1-oupton@google.com> X-Mailer: git-send-email 2.23.0.187.g17f5b7556c-goog Subject: [kvm-unit-tests PATCH v3 7/8] x86: VMX: Make guest_state_test_main() check state from nested VM From: Oliver Upton To: kvm@vger.kernel.org, Paolo Bonzini , " =?utf-8?b?UmFkaW0gS3LEjW3DocWZ?= " Cc: Jim Mattson , Peter Shier , Krish Sadhukhan , Sean Christopherson , Oliver Upton Sender: kvm-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: kvm@vger.kernel.org The current tests for guest state do not yet check the validity of loaded state from within the nested VM. Introduce the load_state_test_data struct to share data with the nested VM. Signed-off-by: Oliver Upton --- x86/vmx_tests.c | 23 ++++++++++++++++++++--- 1 file changed, 20 insertions(+), 3 deletions(-) diff --git a/x86/vmx_tests.c b/x86/vmx_tests.c index f035f24a771a..b72a27583793 100644 --- a/x86/vmx_tests.c +++ b/x86/vmx_tests.c @@ -5017,13 +5017,28 @@ static void test_entry_msr_load(void) test_vmx_valid_controls(false); } +static struct load_state_test_data { + u32 msr; + u64 exp; + bool enabled; +} load_state_test_data; + static void guest_state_test_main(void) { + u64 obs; + struct load_state_test_data *data = &load_state_test_data; + while (1) { - if (vmx_get_test_stage() != 2) - vmcall(); - else + if (vmx_get_test_stage() == 2) break; + + if (data->enabled) { + obs = rdmsr(obs); + report("Guest state is 0x%lx (expected 0x%lx)", + data->exp == obs, obs, data->exp); + } + + vmcall(); } asm volatile("fnop"); @@ -6854,7 +6869,9 @@ static void test_pat(u32 field, const char * field_name, u32 ctrl_field, u64 i, val; u32 j; int error; + struct load_state_test_data *data = &load_state_test_data; + data->enabled = false; vmcs_clear_bits(ctrl_field, ctrl_bit); if (field == GUEST_PAT) { vmx_set_test_stage(1); From patchwork Tue Sep 3 21:58:01 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Oliver Upton X-Patchwork-Id: 11129055 Return-Path: Received: from mail.kernel.org (pdx-korg-mail-1.web.codeaurora.org [172.30.200.123]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id CD9631398 for ; Tue, 3 Sep 2019 21:58:25 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.kernel.org (Postfix) with ESMTP id A5B8822DBF for ; Tue, 3 Sep 2019 21:58:25 +0000 (UTC) Authentication-Results: mail.kernel.org; dkim=pass (2048-bit key) header.d=google.com header.i=@google.com header.b="kjRIvuf3" Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1727168AbfICV6Y (ORCPT ); Tue, 3 Sep 2019 17:58:24 -0400 Received: from mail-pf1-f202.google.com ([209.85.210.202]:38546 "EHLO mail-pf1-f202.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1727223AbfICV6X (ORCPT ); Tue, 3 Sep 2019 17:58:23 -0400 Received: by mail-pf1-f202.google.com with SMTP id b8so15070885pfd.5 for ; Tue, 03 Sep 2019 14:58:23 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=20161025; h=date:in-reply-to:message-id:mime-version:references:subject:from:to :cc; bh=JeYG/CdRS4FJjwc/zJdCeh9ANv77iaZ4013EMkx3oLc=; b=kjRIvuf3TT05qpCoJZz3m6GnD21RCJMM3Bd/+ZtkPvMqD7S9TnY4qRRFUyUtc0y0Yb vAaiAiHIqIG5AnEbhg/cTGb5Xnmbn27A3xkto0sEXBAODg1vUEwCfZTSjejXrYNEVOaU c2x5q1ca5I8YQwyw7guhXlPBFaqecwNLkfuufT29fT8J2lK/xCJBTlTSWoDmUzgyKXdI 6/LnNL6AoodzxyvI4uYB0aun9vV+CuymkhbJPGEV7fxZ0nLnU321QykHleBqQcs1Wm1/ 489HG81/2W12AY7feeipSnNnVyJR+8qBsRM3naE3mkbb0NiX0WRRaZxZSt3hyBpeiYkF plpg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:date:in-reply-to:message-id:mime-version :references:subject:from:to:cc; bh=JeYG/CdRS4FJjwc/zJdCeh9ANv77iaZ4013EMkx3oLc=; b=uMoPblCS5z0lUP5ZlqovCsvaUWZH+ywqvun3fO46nFE7FHi54P96SZTE9v29uPtzDt 1GGMDIMJnoVgn3Mhy4JFK0e40Xcvh7wITWF5zb2MGuF8dbuLQGkBRw0+I9bLuYxmYPJA pl/bjopDLLGvQPqdcDOUyKbY0uXBQc0k4v/T5KdOdkchn6BY9+NlHXIs3/B7G/pD2rM0 tbSlK8hHxjr0GNHdvKxiR7kGnDcqN8BpvYZLG1j/E9HlJBzlI76H0zkvhBvWtVpCq8CY 0tJKG388GLANCNitqsthsvTwOYZXy/SgScuiX9hoMlnHKJJxwo0AU4NWPE9ksUICESmd iopQ== X-Gm-Message-State: APjAAAUqzWdxkKERbt8v6icJmNWbNMCcN0vXG6liFTb0KhC+QC+BtSHr svxG7wgEwCX54L7P5WpIkWlJR3YFRKpZzaeMS/LcZwHWaNJgTzm3+usXUo6KrxLhrI4Z13IYEGr YpVIbj2joFynjo7HhHy3ehTd39PHd3JAFKQJse/WxtWM1QpCCuFlIUagtiQ== X-Google-Smtp-Source: APXvYqzQfbtzpiE1Fxt81iHH3MXI0nVspsJZ78h0qdIHqnX78tz5Y224aXK2JaiOpic/zakYJROit9XfpW4= X-Received: by 2002:a63:3805:: with SMTP id f5mr31966106pga.272.1567547902783; Tue, 03 Sep 2019 14:58:22 -0700 (PDT) Date: Tue, 3 Sep 2019 14:58:01 -0700 In-Reply-To: <20190903215801.183193-1-oupton@google.com> Message-Id: <20190903215801.183193-9-oupton@google.com> Mime-Version: 1.0 References: <20190903215801.183193-1-oupton@google.com> X-Mailer: git-send-email 2.23.0.187.g17f5b7556c-goog Subject: [kvm-unit-tests PATCH v3 8/8] x86: VMX: Add tests for nested "load IA32_PERF_GLOBAL_CTRL" From: Oliver Upton To: kvm@vger.kernel.org, Paolo Bonzini , " =?utf-8?b?UmFkaW0gS3LEjW3DocWZ?= " Cc: Jim Mattson , Peter Shier , Krish Sadhukhan , Sean Christopherson , Oliver Upton Sender: kvm-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: kvm@vger.kernel.org Tests to verify that KVM performs the correct checks on Host/Guest state at VM-entry, as described in SDM 26.3.1.1 "Checks on Guest Control Registers, Debug Registers, and MSRs" and SDM 26.2.2 "Checks on Host Control Registers and MSRs". Test that KVM does the following: If the "load IA32_PERF_GLOBAL_CTRL" VM-entry control is 1, the reserved bits of the IA32_PERF_GLOBAL_CTRL MSR must be 0 in the GUEST_IA32_PERF_GLOBAL_CTRL VMCS field. Otherwise, the VM-entry should fail with an exit reason of "VM-entry failure due to invalid guest state" (33). On a successful VM-entry, the correct value should be observed when the nested VM performs an RDMSR on IA32_PERF_GLOBAL_CTRL. If the "load IA32_PERF_GLOBAL_CTRL" VM-exit control is 1, the reserved bits of the IA32_PERF_GLOBAL_CTRL MSR must be 0 in the HOST_IA32_PERF_GLOBAL_CTRL VMCS field. Otherwise, the VM-entry should fail with a VM-instruction error of "VM entry with invalid host-state field(s)" (8). On a successful VM-exit, the correct value should be observed when L1 performs an RDMSR on IA32_PERF_GLOBAL_CTRL. Suggested-by: Jim Mattson Co-developed-by: Krish Sadhukhan Signed-off-by: Krish Sadhukhan Signed-off-by: Oliver Upton --- x86/vmx_tests.c | 199 +++++++++++++++++++++++++++++++++++++++++++++++- 1 file changed, 197 insertions(+), 2 deletions(-) diff --git a/x86/vmx_tests.c b/x86/vmx_tests.c index b72a27583793..73c46eba6be9 100644 --- a/x86/vmx_tests.c +++ b/x86/vmx_tests.c @@ -5033,7 +5033,7 @@ static void guest_state_test_main(void) break; if (data->enabled) { - obs = rdmsr(obs); + obs = rdmsr(data->msr); report("Guest state is 0x%lx (expected 0x%lx)", data->exp == obs, obs, data->exp); } @@ -6854,6 +6854,200 @@ static void test_host_efer(void) test_efer(HOST_EFER, "HOST_EFER", EXI_CONTROLS, EXI_LOAD_EFER); } +union cpuid10_eax { + struct { + unsigned int version_id:8; + unsigned int num_counters:8; + unsigned int bit_width:8; + unsigned int mask_length:8; + } split; + unsigned int full; +}; + +union cpuid10_edx { + struct { + unsigned int num_counters_fixed:5; + unsigned int bit_width_fixed:8; + unsigned int reserved:19; + } split; + unsigned int full; +}; + +static bool valid_pgc(u64 val) +{ + struct cpuid id; + union cpuid10_eax eax; + union cpuid10_edx edx; + u64 mask; + + id = cpuid(0xA); + eax.full = id.a; + edx.full = id.d; + mask = ~(((1ull << eax.split.num_counters) - 1) | + (((1ull << edx.split.num_counters_fixed) - 1) << 32)); + + return !(val & mask); +} + +static void test_pgc_vmlaunch(u32 xerror, bool xfail, bool host) +{ + u32 inst_err; + u64 guest_rip, inst_len, obs; + bool success; + struct load_state_test_data *data = &load_state_test_data; + + if (host) { + success = vmlaunch_succeeds(); + obs = rdmsr(data->msr); + if (data->enabled && success) + report("Host state is 0x%lx (expected 0x%lx)", + data->exp == obs, obs, data->exp); + } else { + if (xfail) + enter_guest_with_invalid_guest_state(); + else + enter_guest(); + success = VMX_VMCALL == (vmcs_read(EXI_REASON) & 0xff); + guest_rip = vmcs_read(GUEST_RIP); + inst_len = vmcs_read(EXI_INST_LEN); + if (success) + vmcs_write(GUEST_RIP, guest_rip + inst_len); + } + if (!success) { + inst_err = vmcs_read(VMX_INST_ERROR); + report("vmlaunch failed, VMX Inst Error is %d (expected %d)", + xerror == inst_err, inst_err, xerror); + } else { + report("vmlaunch succeeded", success != xfail); + } +} + +/* + * test_load_pgc is a generic function for testing the + * "load IA32_PERF_GLOBAL_CTRL" VM-{entry,exit} control. This test function + * will test the provided ctrl_val disabled and enabled. + * + * @nr - VMCS field number corresponding to the Host/Guest state field + * @name - Name of the above VMCS field for printing in test report + * @ctrl_nr - VMCS field number corresponding to the VM-{entry,exit} control + * @ctrl_val - Bit to set on the ctrl field. + */ +static void test_load_pgc(u32 nr, const char *name, u32 ctrl_nr, + const char *ctrl_name, u64 ctrl_val) +{ + u64 ctrl_saved = vmcs_read(ctrl_nr); + u64 pgc_saved = vmcs_read(nr); + u64 i, val; + bool host = nr == HOST_PERF_GLOBAL_CTRL; + struct load_state_test_data *data = &load_state_test_data; + + data->msr = MSR_CORE_PERF_GLOBAL_CTRL; + msr_bmp_init(); + if (!host) { + vmx_set_test_stage(1); + test_set_guest(guest_state_test_main); + } + vmcs_write(ctrl_nr, ctrl_saved & ~ctrl_val); + data->enabled = false; + report_prefix_pushf("\"load IA32_PERF_GLOBAL_CTRL\"=0 on %s", + ctrl_name); + for (i = 0; i < 64; i++) { + val = 1ull << i; + vmcs_write(nr, val); + report_prefix_pushf("%s = 0x%lx", name, val); + /* + * If the "load IA32_PERF_GLOBAL_CTRL" bit is 0 then + * the {HOST,GUEST}_IA32_PERF_GLOBAL_CTRL field is ignored, + * thus setting reserved bits in this field does not cause + * vmlaunch to fail. + */ + test_pgc_vmlaunch(0, false, host); + report_prefix_pop(); + } + report_prefix_pop(); + + vmcs_write(ctrl_nr, ctrl_saved | ctrl_val); + data->enabled = true; + report_prefix_pushf("\"load IA32_PERF_GLOBAL_CTRL\"=1 on %s", + ctrl_name); + for (i = 0; i < 64; i++) { + val = 1ull << i; + data->exp = val; + vmcs_write(nr, val); + report_prefix_pushf("%s = 0x%lx", name, val); + if (valid_pgc(val)) { + test_pgc_vmlaunch(0, false, host); + } else { + /* + * [SDM 30.4] + * + * Invalid host state fields result in an VM + * instruction error with error number 8 + * (VMXERR_ENTRY_INVALID_HOST_STATE_FIELD) + */ + if (host) { + test_pgc_vmlaunch( + VMXERR_ENTRY_INVALID_HOST_STATE_FIELD, + true, host); + /* + * [SDM 26.1] + * + * If a VM-Entry fails according to one of + * the guest-state checks, the exit reason on the VMCS + * will be set to reason number 33 (VMX_FAIL_STATE) + */ + } else { + test_pgc_vmlaunch( + 0, + true, host); + TEST_ASSERT_EQ( + VMX_ENTRY_FAILURE | VMX_FAIL_STATE, + vmcs_read(EXI_REASON)); + } + } + report_prefix_pop(); + } + + report_prefix_pop(); + + if (nr == GUEST_PERF_GLOBAL_CTRL) { + /* + * Let the guest finish execution + */ + vmx_set_test_stage(2); + vmcs_write(ctrl_nr, ctrl_saved); + vmcs_write(nr, pgc_saved); + enter_guest(); + } + + vmcs_write(ctrl_nr, ctrl_saved); + vmcs_write(nr, pgc_saved); +} + +static void test_load_host_pgc(void) +{ + if (!(ctrl_exit_rev.clr & EXI_LOAD_PERF)) { + printf("\"load IA32_PERF_GLOBAL_CTRL\" " + "exit control not supported\n"); + return; + } + + test_load_pgc(HOST_PERF_GLOBAL_CTRL, "HOST_PERF_GLOBAL_CTRL", + EXI_CONTROLS, "EXI_CONTROLS", EXI_LOAD_PERF); +} + + +static void test_load_guest_pgc(void) +{ + if (!(ctrl_enter_rev.clr & ENT_LOAD_PERF)) { + printf("\"load IA32_PERF_GLOBAL_CTRL\" " + "entry control not supported\n"); + } + + test_load_pgc(GUEST_PERF_GLOBAL_CTRL, "GUEST_PERF_GLOBAL_CTRL", + ENT_CONTROLS, "ENT_CONTROLS", ENT_LOAD_PERF); +} + /* * PAT values higher than 8 are uninteresting since they're likely lumped * in with "8". We only test values above 8 one bit at a time, @@ -7147,6 +7341,7 @@ static void vmx_host_state_area_test(void) test_sysenter_field(HOST_SYSENTER_EIP, "HOST_SYSENTER_EIP"); test_host_efer(); + test_load_host_pgc(); test_load_host_pat(); test_host_segment_regs(); test_host_desc_tables(); @@ -8587,7 +8782,6 @@ static int invalid_msr_entry_failure(struct vmentry_failure *failure) return VMX_TEST_VMEXIT; } - #define TEST(name) { #name, .v2 = name } /* name/init/guest_main/exit_handler/syscall_handler/guest_regs */ @@ -8637,6 +8831,7 @@ struct vmx_test vmx_tests[] = { TEST(vmx_host_state_area_test), TEST(vmx_guest_state_area_test), TEST(vmentry_movss_shadow_test), + TEST(test_load_guest_pgc), /* APICv tests */ TEST(vmx_eoi_bitmap_ioapic_scan_test), TEST(vmx_hlt_with_rvi_test),