From patchwork Fri Sep 6 08:31:47 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Xiang Zheng X-Patchwork-Id: 11134773 Return-Path: Received: from mail.kernel.org (pdx-korg-mail-1.web.codeaurora.org [172.30.200.123]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id 86D0B1599 for ; Fri, 6 Sep 2019 08:34:51 +0000 (UTC) Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id 6A62120842 for ; Fri, 6 Sep 2019 08:34:51 +0000 (UTC) DMARC-Filter: OpenDMARC Filter v1.3.2 mail.kernel.org 6A62120842 Authentication-Results: mail.kernel.org; dmarc=none (p=none dis=none) header.from=huawei.com Authentication-Results: mail.kernel.org; spf=pass smtp.mailfrom=qemu-devel-bounces+patchwork-qemu-devel=patchwork.kernel.org@nongnu.org Received: from localhost ([::1]:53528 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1i69hh-0003lm-T3 for patchwork-qemu-devel@patchwork.kernel.org; Fri, 06 Sep 2019 04:34:49 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:50207) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1i69gP-0001zd-1P for qemu-devel@nongnu.org; Fri, 06 Sep 2019 04:33:30 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1i69gN-0005br-Bf for qemu-devel@nongnu.org; Fri, 06 Sep 2019 04:33:28 -0400 Received: from szxga07-in.huawei.com ([45.249.212.35]:51114 helo=huawei.com) by eggs.gnu.org with esmtps (TLS1.0:DHE_RSA_AES_256_CBC_SHA1:32) (Exim 4.71) (envelope-from ) id 1i69gI-0005WM-Tp; Fri, 06 Sep 2019 04:33:23 -0400 Received: from DGGEMS403-HUB.china.huawei.com (unknown [172.30.72.58]) by Forcepoint Email with ESMTP id B1284F9680A2F91B9579; Fri, 6 Sep 2019 16:33:15 +0800 (CST) Received: from HGHY1z004218071.china.huawei.com (10.177.29.32) by DGGEMS403-HUB.china.huawei.com (10.3.19.203) with Microsoft SMTP Server id 14.3.439.0; Fri, 6 Sep 2019 16:33:08 +0800 From: Xiang Zheng To: , , , , , , , , , , , , , , , , Date: Fri, 6 Sep 2019 16:31:47 +0800 Message-ID: <20190906083152.25716-2-zhengxiang9@huawei.com> X-Mailer: git-send-email 2.15.1.windows.2 In-Reply-To: <20190906083152.25716-1-zhengxiang9@huawei.com> References: <20190906083152.25716-1-zhengxiang9@huawei.com> MIME-Version: 1.0 X-Originating-IP: [10.177.29.32] X-CFilter-Loop: Reflected X-detected-operating-system: by eggs.gnu.org: GNU/Linux 2.2.x-3.x [generic] X-Received-From: 45.249.212.35 Subject: [Qemu-devel] [PATCH v18 1/6] hw/arm/virt: Introduce RAS platform version and RAS machine option X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: wanghaibin.wang@huawei.com, zhengxiang9@huawei.com Errors-To: qemu-devel-bounces+patchwork-qemu-devel=patchwork.kernel.org@nongnu.org Sender: "Qemu-devel" From: Dongjiu Geng Support RAS Virtualization feature since version 4.2, disable it by default in the old versions. Also add a machine option which allows user to enable it explicitly. Signed-off-by: Dongjiu Geng Signed-off-by: Xiang Zheng --- hw/arm/virt.c | 33 +++++++++++++++++++++++++++++++++ include/hw/arm/virt.h | 2 ++ 2 files changed, 35 insertions(+) diff --git a/hw/arm/virt.c b/hw/arm/virt.c index d74538b021..e0451433c8 100644 --- a/hw/arm/virt.c +++ b/hw/arm/virt.c @@ -1783,6 +1783,20 @@ static void virt_set_its(Object *obj, bool value, Error **errp) vms->its = value; } +static bool virt_get_ras(Object *obj, Error **errp) +{ + VirtMachineState *vms = VIRT_MACHINE(obj); + + return vms->ras; +} + +static void virt_set_ras(Object *obj, bool value, Error **errp) +{ + VirtMachineState *vms = VIRT_MACHINE(obj); + + vms->ras = value; +} + static char *virt_get_gic_version(Object *obj, Error **errp) { VirtMachineState *vms = VIRT_MACHINE(obj); @@ -2026,6 +2040,19 @@ static void virt_instance_init(Object *obj) "Valid values are none and smmuv3", NULL); + if (vmc->no_ras) { + vms->ras = false; + } else { + /* Default disallows RAS instantiation */ + vms->ras = false; + object_property_add_bool(obj, "ras", virt_get_ras, + virt_set_ras, NULL); + object_property_set_description(obj, "ras", + "Set on/off to enable/disable " + "RAS instantiation", + NULL); + } + vms->irqmap = a15irqmap; virt_flash_create(vms); @@ -2058,8 +2085,14 @@ DEFINE_VIRT_MACHINE_AS_LATEST(4, 2) static void virt_machine_4_1_options(MachineClass *mc) { + VirtMachineClass *vmc = VIRT_MACHINE_CLASS(OBJECT_CLASS(mc)); + virt_machine_4_2_options(mc); compat_props_add(mc->compat_props, hw_compat_4_1, hw_compat_4_1_len); + /* Disable memory recovery feature for 4.1 as RAS support was + * introduced with 4.2. + */ + vmc->no_ras = true; } DEFINE_VIRT_MACHINE(4, 1) diff --git a/include/hw/arm/virt.h b/include/hw/arm/virt.h index a72094204e..04ab42ca42 100644 --- a/include/hw/arm/virt.h +++ b/include/hw/arm/virt.h @@ -103,6 +103,7 @@ typedef struct { bool disallow_affinity_adjustment; bool no_its; bool no_pmu; + bool no_ras; bool claim_edge_triggered_timers; bool smbios_old_sys_ver; bool no_highmem_ecam; @@ -119,6 +120,7 @@ typedef struct { bool highmem_ecam; bool its; bool virt; + bool ras; int32_t gic_version; VirtIOMMUType iommu; struct arm_boot_info bootinfo; From patchwork Fri Sep 6 08:31:48 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Xiang Zheng X-Patchwork-Id: 11134775 Return-Path: Received: from mail.kernel.org (pdx-korg-mail-1.web.codeaurora.org [172.30.200.123]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id 531591731 for ; Fri, 6 Sep 2019 08:34:54 +0000 (UTC) Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id 36ED720842 for ; Fri, 6 Sep 2019 08:34:54 +0000 (UTC) DMARC-Filter: OpenDMARC Filter v1.3.2 mail.kernel.org 36ED720842 Authentication-Results: mail.kernel.org; dmarc=none (p=none dis=none) header.from=huawei.com Authentication-Results: mail.kernel.org; spf=pass smtp.mailfrom=qemu-devel-bounces+patchwork-qemu-devel=patchwork.kernel.org@nongnu.org Received: from localhost ([::1]:53530 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1i69hk-0003py-Pn for patchwork-qemu-devel@patchwork.kernel.org; Fri, 06 Sep 2019 04:34:52 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:50234) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1i69gP-00020k-Vr for qemu-devel@nongnu.org; Fri, 06 Sep 2019 04:33:31 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1i69gO-0005cU-Av for qemu-devel@nongnu.org; Fri, 06 Sep 2019 04:33:29 -0400 Received: from szxga07-in.huawei.com ([45.249.212.35]:51110 helo=huawei.com) by eggs.gnu.org with esmtps (TLS1.0:DHE_RSA_AES_256_CBC_SHA1:32) (Exim 4.71) (envelope-from ) id 1i69gI-0005WN-TR; Fri, 06 Sep 2019 04:33:23 -0400 Received: from DGGEMS403-HUB.china.huawei.com (unknown [172.30.72.58]) by Forcepoint Email with ESMTP id 9E2F6B0146111930E6C7; Fri, 6 Sep 2019 16:33:15 +0800 (CST) Received: from HGHY1z004218071.china.huawei.com (10.177.29.32) by DGGEMS403-HUB.china.huawei.com (10.3.19.203) with Microsoft SMTP Server id 14.3.439.0; Fri, 6 Sep 2019 16:33:09 +0800 From: Xiang Zheng To: , , , , , , , , , , , , , , , , Date: Fri, 6 Sep 2019 16:31:48 +0800 Message-ID: <20190906083152.25716-3-zhengxiang9@huawei.com> X-Mailer: git-send-email 2.15.1.windows.2 In-Reply-To: <20190906083152.25716-1-zhengxiang9@huawei.com> References: <20190906083152.25716-1-zhengxiang9@huawei.com> MIME-Version: 1.0 X-Originating-IP: [10.177.29.32] X-CFilter-Loop: Reflected X-detected-operating-system: by eggs.gnu.org: GNU/Linux 2.2.x-3.x [generic] X-Received-From: 45.249.212.35 Subject: [Qemu-devel] [PATCH v18 2/6] docs: APEI GHES generation and CPER record description X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: wanghaibin.wang@huawei.com, zhengxiang9@huawei.com Errors-To: qemu-devel-bounces+patchwork-qemu-devel=patchwork.kernel.org@nongnu.org Sender: "Qemu-devel" From: Dongjiu Geng Add APEI/GHES detailed design document Signed-off-by: Dongjiu Geng Signed-off-by: Xiang Zheng --- docs/specs/acpi_hest_ghes.txt | 88 +++++++++++++++++++++++++++++++++++ 1 file changed, 88 insertions(+) create mode 100644 docs/specs/acpi_hest_ghes.txt diff --git a/docs/specs/acpi_hest_ghes.txt b/docs/specs/acpi_hest_ghes.txt new file mode 100644 index 0000000000..690d4b2bd0 --- /dev/null +++ b/docs/specs/acpi_hest_ghes.txt @@ -0,0 +1,88 @@ +APEI tables generating and CPER record +============================= + +Copyright (C) 2019 Huawei Corporation. + +Design Details: +------------------- + + etc/acpi/tables etc/hardware_errors + ==================== ========================================== ++ +--------------------------+ +-----------------------+ +| | HEST | | address | +--------------+ +| +--------------------------+ | registers | | Error Status | +| | GHES1 | | +---------------------+ | Data Block 1 | +| +--------------------------+ +--------->| |error_block_address1 |----------->| +------------+ +| | ................. | | | +---------------------+ | | CPER | +| | error_status_address-----+-+ +------->| |error_block_address2 |--------+ | | CPER | +| | ................. | | | +---------------------+ | | | .... | +| | read_ack_register--------+-+ | | | .............. | | | | CPER | +| | read_ack_preserve | | | +-----------------------+ | | +------------+ +| | read_ack_write | | | +----->| |error_block_addressN |------+ | | Error Status | ++ +--------------------------+ | | | | +---------------------+ | | | Data Block 2 | +| | GHES2 | +-+-+----->| |read_ack_register1 | | +-->| +------------+ ++ +--------------------------+ | | | +---------------------+ | | | CPER | +| | ................. | | | +--->| |read_ack_register2 | | | | CPER | +| | error_status_address-----+---+ | | | +---------------------+ | | | .... | +| | ................. | | | | | ............. | | | | CPER | +| | read_ack_register--------+-----+-+ | +---------------------+ | +-+------------+ +| | read_ack_preserve | | +->| |read_ack_registerN | | | |.......... | +| | read_ack_write | | | | +---------------------+ | | +------------+ ++ +--------------------------| | | | | Error Status | +| | ............... | | | | | Data Block N | ++ +--------------------------+ | | +---->| +------------+ +| | GHESN | | | | | CPER | ++ +--------------------------+ | | | | CPER | +| | ................. | | | | | .... | +| | error_status_address-----+-----+ | | | CPER | +| | ................. | | +-+------------+ +| | read_ack_register--------+---------+ +| | read_ack_preserve | +| | read_ack_write | ++ +--------------------------+ + +(1) QEMU generates the ACPI HEST table. This table goes in the current + "etc/acpi/tables" fw_cfg blob. Each error source has different + notification types. + +(2) A new fw_cfg blob called "etc/hardware_errors" is introduced. QEMU + also need to populate this blob. The "etc/hardwre_errors" fw_cfg blob + contains an address registers table and an Error Status Data Block table. + +(3) The address registers table contains N Error Block Address entries + and N Read Ack Register entries, the size for each entry is 8-byte. + The Error Status Data Block table contains N Error Status Data Block + entries, the size for each entry is 4096(0x1000) bytes. The total size + for "etc/hardware_errors" fw_cfg blob is (N * 8 * 2 + N * 4096) bytes. + N is the kinds of hardware error sources. + +(4) QEMU generates the ACPI linker/loader script for the firmware, the + firmware pre-allocates memory for "etc/acpi/tables", "etc/hardware_errors" + and copies blobs content there. + +(5) QEMU generates N ADD_POINTER commands, which patch address in the + "error_status_address" fields of the HEST table with a pointer to the + corresponding "address registers" in "etc/hardware_errors" blob. + +(6) QEMU generates N ADD_POINTER commands, which patch address in the + "read_ack_register" fields of the HEST table with a pointer to the + corresponding "address registers" in "etc/hardware_errors" blob. + +(7) QEMU generates N ADD_POINTER commands for the firmware, which patch + address in the " error_block_address" fields with a pointer to the + respective "Error Status Data Block" in "etc/hardware_errors" blob. + +(8) QEMU defines a third and write-only fw_cfg blob which is called + "etc/hardware_errors_addr". Through that blob, the firmware can send back + the guest-side allocation addresses to QEMU. The "etc/hardware_errors_addr" + blob contains a 8-byte entry. QEMU generates a single WRITE_POINTER commands + for the firmware, the firmware will write back the start address of + "etc/hardware_errors" blob to fw_cfg file "etc/hardware_errors_addr". + +(9) When QEMU gets SIGBUS from the kernel, QEMU formats the CPER right into + guest memory, and then injects whatever interrupt (or assert whatever GPIO + line) as a notification which is necessary for notifying the guest. + +(10) This notification (in virtual hardware) will be handled by guest kernel, + guest APEI driver will read the CPER which is recorded by QEMU and do the + recovery. From patchwork Fri Sep 6 08:31:49 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Xiang Zheng X-Patchwork-Id: 11134785 Return-Path: Received: from mail.kernel.org (pdx-korg-mail-1.web.codeaurora.org [172.30.200.123]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id C93C615E6 for ; Fri, 6 Sep 2019 08:39:06 +0000 (UTC) Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id 9BA1820842 for ; Fri, 6 Sep 2019 08:39:06 +0000 (UTC) DMARC-Filter: OpenDMARC Filter v1.3.2 mail.kernel.org 9BA1820842 Authentication-Results: mail.kernel.org; dmarc=none (p=none dis=none) header.from=huawei.com Authentication-Results: mail.kernel.org; spf=pass smtp.mailfrom=qemu-devel-bounces+patchwork-qemu-devel=patchwork.kernel.org@nongnu.org Received: from localhost ([::1]:53574 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1i69lp-0008SE-Qn for patchwork-qemu-devel@patchwork.kernel.org; Fri, 06 Sep 2019 04:39:05 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:50285) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1i69gV-00027i-9u for qemu-devel@nongnu.org; Fri, 06 Sep 2019 04:33:37 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1i69gS-0005f7-K0 for qemu-devel@nongnu.org; Fri, 06 Sep 2019 04:33:35 -0400 Received: from szxga05-in.huawei.com ([45.249.212.191]:2264 helo=huawei.com) by eggs.gnu.org with esmtps (TLS1.0:DHE_RSA_AES_256_CBC_SHA1:32) (Exim 4.71) (envelope-from ) id 1i69gJ-0005YP-Md; Fri, 06 Sep 2019 04:33:24 -0400 Received: from DGGEMS403-HUB.china.huawei.com (unknown [172.30.72.59]) by Forcepoint Email with ESMTP id E391D2DB891BF27C23D7; Fri, 6 Sep 2019 16:33:20 +0800 (CST) Received: from HGHY1z004218071.china.huawei.com (10.177.29.32) by DGGEMS403-HUB.china.huawei.com (10.3.19.203) with Microsoft SMTP Server id 14.3.439.0; Fri, 6 Sep 2019 16:33:10 +0800 From: Xiang Zheng To: , , , , , , , , , , , , , , , , Date: Fri, 6 Sep 2019 16:31:49 +0800 Message-ID: <20190906083152.25716-4-zhengxiang9@huawei.com> X-Mailer: git-send-email 2.15.1.windows.2 In-Reply-To: <20190906083152.25716-1-zhengxiang9@huawei.com> References: <20190906083152.25716-1-zhengxiang9@huawei.com> MIME-Version: 1.0 X-Originating-IP: [10.177.29.32] X-CFilter-Loop: Reflected X-detected-operating-system: by eggs.gnu.org: GNU/Linux 2.2.x-3.x [generic] X-Received-From: 45.249.212.191 Subject: [Qemu-devel] [PATCH v18 3/6] ACPI: Add APEI GHES table generation support X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: wanghaibin.wang@huawei.com, zhengxiang9@huawei.com Errors-To: qemu-devel-bounces+patchwork-qemu-devel=patchwork.kernel.org@nongnu.org Sender: "Qemu-devel" From: Dongjiu Geng This patch implements APEI GHES Table generation via fw_cfg blobs. Now it only supports ARMv8 SEA, a type of GHESv2 error source. Afterwards, we can extend the supported types if needed. For the CPER section, currently it is memory section because kernel mainly wants userspace to handle the memory errors. This patch follows the spec ACPI 6.2 to build the Hardware Error Source table. For more detailed information, please refer to document: docs/specs/acpi_hest_ghes.txt Suggested-by: Laszlo Ersek Signed-off-by: Dongjiu Geng Signed-off-by: Xiang Zheng --- default-configs/arm-softmmu.mak | 1 + hw/acpi/Kconfig | 4 + hw/acpi/Makefile.objs | 1 + hw/acpi/acpi_ghes.c | 210 ++++++++++++++++++++++++++++++++ hw/acpi/aml-build.c | 2 + hw/arm/virt-acpi-build.c | 12 ++ include/hw/acpi/acpi_ghes.h | 103 ++++++++++++++++ include/hw/acpi/aml-build.h | 1 + 8 files changed, 334 insertions(+) create mode 100644 hw/acpi/acpi_ghes.c create mode 100644 include/hw/acpi/acpi_ghes.h diff --git a/default-configs/arm-softmmu.mak b/default-configs/arm-softmmu.mak index 1f2e0e7fde..5722f3130e 100644 --- a/default-configs/arm-softmmu.mak +++ b/default-configs/arm-softmmu.mak @@ -40,3 +40,4 @@ CONFIG_FSL_IMX25=y CONFIG_FSL_IMX7=y CONFIG_FSL_IMX6UL=y CONFIG_SEMIHOSTING=y +CONFIG_ACPI_APEI=y diff --git a/hw/acpi/Kconfig b/hw/acpi/Kconfig index 7c59cf900b..2c4d0b9826 100644 --- a/hw/acpi/Kconfig +++ b/hw/acpi/Kconfig @@ -23,6 +23,10 @@ config ACPI_NVDIMM bool depends on ACPI +config ACPI_APEI + bool + depends on ACPI + config ACPI_PCI bool depends on ACPI && PCI diff --git a/hw/acpi/Makefile.objs b/hw/acpi/Makefile.objs index 9bb2101e3b..93fd8e8f64 100644 --- a/hw/acpi/Makefile.objs +++ b/hw/acpi/Makefile.objs @@ -5,6 +5,7 @@ common-obj-$(CONFIG_ACPI_CPU_HOTPLUG) += cpu_hotplug.o common-obj-$(CONFIG_ACPI_MEMORY_HOTPLUG) += memory_hotplug.o common-obj-$(CONFIG_ACPI_CPU_HOTPLUG) += cpu.o common-obj-$(CONFIG_ACPI_NVDIMM) += nvdimm.o +common-obj-$(CONFIG_ACPI_APEI) += acpi_ghes.o common-obj-$(CONFIG_ACPI_VMGENID) += vmgenid.o common-obj-$(call lnot,$(CONFIG_ACPI_X86)) += acpi-stub.o diff --git a/hw/acpi/acpi_ghes.c b/hw/acpi/acpi_ghes.c new file mode 100644 index 0000000000..20c45179ff --- /dev/null +++ b/hw/acpi/acpi_ghes.c @@ -0,0 +1,210 @@ +/* Support for generating APEI tables and record CPER for Guests + * + * Copyright (C) 2019 Huawei Corporation. + * + * Author: Dongjiu Geng + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + + * You should have received a copy of the GNU General Public License along + * with this program; if not, see . + */ + +#include "qemu/osdep.h" +#include "hw/acpi/acpi.h" +#include "hw/acpi/aml-build.h" +#include "hw/acpi/acpi_ghes.h" +#include "hw/nvram/fw_cfg.h" +#include "sysemu/sysemu.h" +#include "qemu/error-report.h" + +/* Hardware Error Notification + * ACPI 4.0: 17.3.2.7 Hardware Error Notification + */ +static void acpi_ghes_build_notify(GArray *table, const uint8_t type, + uint8_t length, uint16_t config_write_enable, + uint32_t poll_interval, uint32_t vector, + uint32_t polling_threshold_value, + uint32_t polling_threshold_window, + uint32_t error_threshold_value, + uint32_t error_threshold_window) +{ + /* Type */ + build_append_int_noprefix(table, type, 1); + /* Length */ + build_append_int_noprefix(table, length, 1); + /* Configuration Write Enable */ + build_append_int_noprefix(table, config_write_enable, 2); + /* Poll Interval */ + build_append_int_noprefix(table, poll_interval, 4); + /* Vector */ + build_append_int_noprefix(table, vector, 4); + /* Switch To Polling Threshold Value */ + build_append_int_noprefix(table, polling_threshold_value, 4); + /* Switch To Polling Threshold Window */ + build_append_int_noprefix(table, polling_threshold_window, 4); + /* Error Threshold Value */ + build_append_int_noprefix(table, error_threshold_value, 4); + /* Error Threshold Window */ + build_append_int_noprefix(table, error_threshold_window, 4); +} + +/* Build table for the hardware error fw_cfg blob */ +void acpi_ghes_build_error_table(GArray *hardware_errors, BIOSLinker *linker) +{ + int i, error_status_block_offset; + + /* + * | +--------------------------+ + * | | error_block_address | + * | | .......... | + * | +--------------------------+ + * | | read_ack_register | + * | | ........... | + * | +--------------------------+ + * | | Error Status Data Block | + * | | ........ | + * | +--------------------------+ + */ + + /* Build error_block_address */ + build_append_int_noprefix(hardware_errors, 0, + ACPI_GHES_ADDRESS_SIZE * ACPI_GHES_ERROR_SOURCE_COUNT); + + /* Build read_ack_register */ + for (i = 0; i < ACPI_GHES_ERROR_SOURCE_COUNT; i++) { + /* Initialize the value of read_ack_register to 1, so GHES can be + * writeable in the first time. + * ACPI 6.2: 18.3.2.8 Generic Hardware Error Source version 2 + * (GHESv2 - Type 10) + */ + build_append_int_noprefix(hardware_errors, 1, ACPI_GHES_ADDRESS_SIZE); + } + + /* Build Error Status Data Block */ + build_append_int_noprefix(hardware_errors, 0, + ACPI_GHES_MAX_RAW_DATA_LENGTH * ACPI_GHES_ERROR_SOURCE_COUNT); + + /* Allocate guest memory for the hardware error fw_cfg blob */ + bios_linker_loader_alloc(linker, ACPI_GHES_ERRORS_FW_CFG_FILE, + hardware_errors, 1, false); + + /* Generic Error Status Block offset in the hardware error fw_cfg blob */ + error_status_block_offset = ACPI_GHES_ADDRESS_SIZE * 2 * + ACPI_GHES_ERROR_SOURCE_COUNT; + + for (i = 0; i < ACPI_GHES_ERROR_SOURCE_COUNT; i++) { + /* Patch address of Error Status Data Block into + * the error_block_address of hardware_errors fw_cfg blob + */ + bios_linker_loader_add_pointer(linker, + ACPI_GHES_ERRORS_FW_CFG_FILE, ACPI_GHES_ADDRESS_SIZE * i, + ACPI_GHES_ADDRESS_SIZE, ACPI_GHES_ERRORS_FW_CFG_FILE, + error_status_block_offset + i * ACPI_GHES_MAX_RAW_DATA_LENGTH); + } + + /* Write address of hardware_errors fw_cfg blob into the + * hardware_errors_addr fw_cfg blob. + */ + bios_linker_loader_write_pointer(linker, ACPI_GHES_DATA_ADDR_FW_CFG_FILE, + 0, ACPI_GHES_ADDRESS_SIZE, ACPI_GHES_ERRORS_FW_CFG_FILE, 0); +} + +/* Build Hardware Error Source Table */ +void acpi_ghes_build_hest(GArray *table_data, GArray *hardware_errors, + BIOSLinker *linker) +{ + uint32_t i, hest_start = table_data->len; + + /* Reserve Hardware Error Source Table header size */ + acpi_data_push(table_data, sizeof(AcpiTableHeader)); + + /* Error Source Count */ + build_append_int_noprefix(table_data, ACPI_GHES_ERROR_SOURCE_COUNT, 4); + + /* Generic Hardware Error Source version 2(GHESv2 - Type 10) */ + for (i = 0; i < ACPI_GHES_ERROR_SOURCE_COUNT; i++) { + /* Type */ + build_append_int_noprefix(table_data, + ACPI_GHES_SOURCE_GENERIC_ERROR_V2, 2); + /* Source Id */ + build_append_int_noprefix(table_data, i, 2); + /* Related Source Id */ + build_append_int_noprefix(table_data, 0xffff, 2); + /* Flags */ + build_append_int_noprefix(table_data, 0, 1); + /* Enabled */ + build_append_int_noprefix(table_data, 1, 1); + + /* Number of Records To Pre-allocate */ + build_append_int_noprefix(table_data, 1, 4); + /* Max Sections Per Record */ + build_append_int_noprefix(table_data, 1, 4); + /* Max Raw Data Length */ + build_append_int_noprefix(table_data, ACPI_GHES_MAX_RAW_DATA_LENGTH, 4); + + /* Error Status Address */ + build_append_gas(table_data, AML_SYSTEM_MEMORY, 0x40, 0, + 4 /* QWord access */, 0); + bios_linker_loader_add_pointer(linker, ACPI_BUILD_TABLE_FILE, + ACPI_GHES_ERROR_STATUS_ADDRESS_OFFSET(hest_start, i), + ACPI_GHES_ADDRESS_SIZE, ACPI_GHES_ERRORS_FW_CFG_FILE, + i * ACPI_GHES_ADDRESS_SIZE); + + if (i == 0) { + /* Notification Structure + * Now only enable ARMv8 SEA notification type + */ + acpi_ghes_build_notify(table_data, ACPI_GHES_NOTIFY_SEA, 28, 0, + 0, 0, 0, 0, 0, 0); + } else { + g_assert_not_reached(); + } + + /* Error Status Block Length */ + build_append_int_noprefix(table_data, ACPI_GHES_MAX_RAW_DATA_LENGTH, 4); + + /* Read Ack Register + * ACPI 6.1: 18.3.2.8 Generic Hardware Error Source + * version 2 (GHESv2 - Type 10) + */ + build_append_gas(table_data, AML_SYSTEM_MEMORY, 0x40, 0, + 4 /* QWord access */, 0); + bios_linker_loader_add_pointer(linker, ACPI_BUILD_TABLE_FILE, + ACPI_GHES_READ_ACK_REGISTER_ADDRESS_OFFSET(hest_start, i), + ACPI_GHES_ADDRESS_SIZE, ACPI_GHES_ERRORS_FW_CFG_FILE, + (ACPI_GHES_ERROR_SOURCE_COUNT + i) * ACPI_GHES_ADDRESS_SIZE); + + /* Read Ack Preserve */ + build_append_int_noprefix(table_data, 0xfffffffffffffffe, 8); + /* Read Ack Write */ + build_append_int_noprefix(table_data, 0x1, 8); + } + + build_header(linker, table_data, (void *)(table_data->data + hest_start), + "HEST", table_data->len - hest_start, 1, NULL, "GHES"); +} + +static AcpiGhesState ges; +void acpi_ghes_add_fw_cfg(FWCfgState *s, GArray *hardware_error) +{ + + size_t size = 2 * ACPI_GHES_ADDRESS_SIZE + ACPI_GHES_MAX_RAW_DATA_LENGTH; + size_t request_block_size = ACPI_GHES_ERROR_SOURCE_COUNT * size; + + /* Create a read-only fw_cfg file for GHES */ + fw_cfg_add_file(s, ACPI_GHES_ERRORS_FW_CFG_FILE, hardware_error->data, + request_block_size); + + /* Create a read-write fw_cfg file for Address */ + fw_cfg_add_file_callback(s, ACPI_GHES_DATA_ADDR_FW_CFG_FILE, NULL, NULL, + NULL, &ges.ghes_addr_le, sizeof(ges.ghes_addr_le), false); +} diff --git a/hw/acpi/aml-build.c b/hw/acpi/aml-build.c index 78aee1a2f9..bfdb84c517 100644 --- a/hw/acpi/aml-build.c +++ b/hw/acpi/aml-build.c @@ -1578,6 +1578,7 @@ void acpi_build_tables_init(AcpiBuildTables *tables) tables->table_data = g_array_new(false, true /* clear */, 1); tables->tcpalog = g_array_new(false, true /* clear */, 1); tables->vmgenid = g_array_new(false, true /* clear */, 1); + tables->hardware_errors = g_array_new(false, true /* clear */, 1); tables->linker = bios_linker_loader_init(); } @@ -1588,6 +1589,7 @@ void acpi_build_tables_cleanup(AcpiBuildTables *tables, bool mfre) g_array_free(tables->table_data, true); g_array_free(tables->tcpalog, mfre); g_array_free(tables->vmgenid, mfre); + g_array_free(tables->hardware_errors, mfre); } /* diff --git a/hw/arm/virt-acpi-build.c b/hw/arm/virt-acpi-build.c index 6cdf156cf5..c74e178aa0 100644 --- a/hw/arm/virt-acpi-build.c +++ b/hw/arm/virt-acpi-build.c @@ -46,6 +46,7 @@ #include "sysemu/reset.h" #include "kvm_arm.h" #include "migration/vmstate.h" +#include "hw/acpi/acpi_ghes.h" #define ARM_SPI_BASE 32 #define ACPI_POWER_BUTTON_DEVICE "PWRB" @@ -796,6 +797,13 @@ void virt_acpi_build(VirtMachineState *vms, AcpiBuildTables *tables) acpi_add_table(table_offsets, tables_blob); build_spcr(tables_blob, tables->linker, vms); + if (vms->ras) { + acpi_add_table(table_offsets, tables_blob); + acpi_ghes_build_error_table(tables->hardware_errors, tables->linker); + acpi_ghes_build_hest(tables_blob, tables->hardware_errors, + tables->linker); + } + if (ms->numa_state->num_nodes > 0) { acpi_add_table(table_offsets, tables_blob); build_srat(tables_blob, tables->linker, vms); @@ -913,6 +921,10 @@ void virt_acpi_setup(VirtMachineState *vms) fw_cfg_add_file(vms->fw_cfg, ACPI_BUILD_TPMLOG_FILE, tables.tcpalog->data, acpi_data_len(tables.tcpalog)); + if (vms->ras) { + acpi_ghes_add_fw_cfg(vms->fw_cfg, tables.hardware_errors); + } + build_state->rsdp_mr = acpi_add_rom_blob(virt_acpi_build_update, build_state, tables.rsdp, ACPI_BUILD_RSDP_FILE, 0); diff --git a/include/hw/acpi/acpi_ghes.h b/include/hw/acpi/acpi_ghes.h new file mode 100644 index 0000000000..69747ba3d7 --- /dev/null +++ b/include/hw/acpi/acpi_ghes.h @@ -0,0 +1,103 @@ +/* Support for generating APEI tables and record CPER for Guests + * + * Copyright (C) 2019 Huawei Corporation. + * + * Author: Dongjiu Geng + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + + * You should have received a copy of the GNU General Public License along + * with this program; if not, see . + */ + +#ifndef ACPI_GHES_H +#define ACPI_GHES_H + +#include "hw/acpi/bios-linker-loader.h" + +#define ACPI_GHES_ERRORS_FW_CFG_FILE "etc/hardware_errors" +#define ACPI_GHES_DATA_ADDR_FW_CFG_FILE "etc/hardware_errors_addr" + +/* The size of Address field in Generic Address Structure, + * ACPI 2.0/3.0: 5.2.3.1 Generic Address Structure. + */ +#define ACPI_GHES_ADDRESS_SIZE 8 + +/* The max size in bytes for one error block */ +#define ACPI_GHES_MAX_RAW_DATA_LENGTH 0x1000 + +/* Now only support ARMv8 SEA notification type error source + */ +#define ACPI_GHES_ERROR_SOURCE_COUNT 1 + +/* + * Generic Hardware Error Source version 2 + */ +#define ACPI_GHES_SOURCE_GENERIC_ERROR_V2 10 + +/* + * Values for Hardware Error Notification Type field + */ +enum AcpiGhesNotifyType { + ACPI_GHES_NOTIFY_POLLED = 0, /* Polled */ + ACPI_GHES_NOTIFY_EXTERNAL = 1, /* External Interrupt */ + ACPI_GHES_NOTIFY_LOCAL = 2, /* Local Interrupt */ + ACPI_GHES_NOTIFY_SCI = 3, /* SCI */ + ACPI_GHES_NOTIFY_NMI = 4, /* NMI */ + ACPI_GHES_NOTIFY_CMCI = 5, /* CMCI, ACPI 5.0: 18.3.2.7, Table 18-290 */ + ACPI_GHES_NOTIFY_MCE = 6, /* MCE, ACPI 5.0: 18.3.2.7, Table 18-290 */ + /* GPIO-Signal, ACPI 6.0: 18.3.2.7, Table 18-332 */ + ACPI_GHES_NOTIFY_GPIO = 7, + /* ARMv8 SEA, ACPI 6.1: 18.3.2.9, Table 18-345 */ + ACPI_GHES_NOTIFY_SEA = 8, + /* ARMv8 SEI, ACPI 6.1: 18.3.2.9, Table 18-345 */ + ACPI_GHES_NOTIFY_SEI = 9, + /* External Interrupt - GSIV, ACPI 6.1: 18.3.2.9, Table 18-345 */ + ACPI_GHES_NOTIFY_GSIV = 10, + /* Software Delegated Exception, ACPI 6.2: 18.3.2.9, Table 18-383 */ + ACPI_GHES_NOTIFY_SDEI = 11, + ACPI_GHES_NOTIFY_RESERVED = 12 /* 12 and greater are reserved */ +}; + +/* + * | +--------------------------+ 0 + * | | Header | + * | +--------------------------+ 40---+- + * | | ................. | | + * | | error_status_address-----+ 60 | + * | | ................. | | + * | | read_ack_register--------+ 104 92 + * | | read_ack_preserve | | + * | | read_ack_write | | + * + +--------------------------+ 132--+- + * + * From above GHES definition, the error status address offset is 60; + * the Read ack register offset is 104, the whole size of GHESv2 is 92 + */ + +/* The error status address offset in GHES */ +#define ACPI_GHES_ERROR_STATUS_ADDRESS_OFFSET(start_addr, n) (start_addr + \ + 60 + offsetof(struct AcpiGenericAddress, address) + n * 92) + +/* The read Ack register offset in GHES */ +#define ACPI_GHES_READ_ACK_REGISTER_ADDRESS_OFFSET(start_addr, n) (start_addr +\ + 104 + offsetof(struct AcpiGenericAddress, address) + n * 92) + +typedef struct AcpiGhesState { + uint64_t ghes_addr_le; +} AcpiGhesState; + +void acpi_ghes_build_hest(GArray *table_data, GArray *hardware_error, + BIOSLinker *linker); + +void acpi_ghes_build_error_table(GArray *hardware_errors, BIOSLinker *linker); +void acpi_ghes_add_fw_cfg(FWCfgState *s, GArray *hardware_errors); +#endif diff --git a/include/hw/acpi/aml-build.h b/include/hw/acpi/aml-build.h index 991cf05134..2cc61712fd 100644 --- a/include/hw/acpi/aml-build.h +++ b/include/hw/acpi/aml-build.h @@ -220,6 +220,7 @@ struct AcpiBuildTables { GArray *rsdp; GArray *tcpalog; GArray *vmgenid; + GArray *hardware_errors; BIOSLinker *linker; } AcpiBuildTables; From patchwork Fri Sep 6 08:31:50 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Xiang Zheng X-Patchwork-Id: 11134781 Return-Path: Received: from mail.kernel.org (pdx-korg-mail-1.web.codeaurora.org [172.30.200.123]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id 6D79513B1 for ; Fri, 6 Sep 2019 08:37:08 +0000 (UTC) Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id 5054F20842 for ; Fri, 6 Sep 2019 08:37:08 +0000 (UTC) DMARC-Filter: OpenDMARC Filter v1.3.2 mail.kernel.org 5054F20842 Authentication-Results: mail.kernel.org; dmarc=none (p=none dis=none) header.from=huawei.com Authentication-Results: mail.kernel.org; spf=pass smtp.mailfrom=qemu-devel-bounces+patchwork-qemu-devel=patchwork.kernel.org@nongnu.org Received: from localhost ([::1]:53560 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1i69jv-0006ef-Fy for patchwork-qemu-devel@patchwork.kernel.org; Fri, 06 Sep 2019 04:37:07 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:50204) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1i69gO-0001zO-RS for qemu-devel@nongnu.org; Fri, 06 Sep 2019 04:33:30 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1i69gM-0005bU-SK for qemu-devel@nongnu.org; Fri, 06 Sep 2019 04:33:28 -0400 Received: from szxga07-in.huawei.com ([45.249.212.35]:51330 helo=huawei.com) by eggs.gnu.org with esmtps (TLS1.0:DHE_RSA_AES_256_CBC_SHA1:32) (Exim 4.71) (envelope-from ) id 1i69gI-0005YD-Kb; Fri, 06 Sep 2019 04:33:22 -0400 Received: from DGGEMS403-HUB.china.huawei.com (unknown [172.30.72.58]) by Forcepoint Email with ESMTP id AF3E2BC4DD8F5A5EE6DC; Fri, 6 Sep 2019 16:33:20 +0800 (CST) Received: from HGHY1z004218071.china.huawei.com (10.177.29.32) by DGGEMS403-HUB.china.huawei.com (10.3.19.203) with Microsoft SMTP Server id 14.3.439.0; Fri, 6 Sep 2019 16:33:11 +0800 From: Xiang Zheng To: , , , , , , , , , , , , , , , , Date: Fri, 6 Sep 2019 16:31:50 +0800 Message-ID: <20190906083152.25716-5-zhengxiang9@huawei.com> X-Mailer: git-send-email 2.15.1.windows.2 In-Reply-To: <20190906083152.25716-1-zhengxiang9@huawei.com> References: <20190906083152.25716-1-zhengxiang9@huawei.com> MIME-Version: 1.0 X-Originating-IP: [10.177.29.32] X-CFilter-Loop: Reflected X-detected-operating-system: by eggs.gnu.org: GNU/Linux 2.2.x-3.x [generic] X-Received-From: 45.249.212.35 Subject: [Qemu-devel] [PATCH v18 4/6] KVM: Move hwpoison page related functions into include/sysemu/kvm_int.h X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: wanghaibin.wang@huawei.com, zhengxiang9@huawei.com Errors-To: qemu-devel-bounces+patchwork-qemu-devel=patchwork.kernel.org@nongnu.org Sender: "Qemu-devel" From: Dongjiu Geng kvm_hwpoison_page_add() and kvm_unpoison_all() will both be used by X86 and ARM platforms, so moving them into "include/sysemu/kvm_int.h" to avoid duplicate code. Signed-off-by: Dongjiu Geng Signed-off-by: Xiang Zheng --- accel/kvm/kvm-all.c | 33 +++++++++++++++++++++++++++++++++ include/sysemu/kvm_int.h | 23 +++++++++++++++++++++++ target/arm/kvm.c | 3 +++ target/i386/kvm.c | 34 ---------------------------------- 4 files changed, 59 insertions(+), 34 deletions(-) diff --git a/accel/kvm/kvm-all.c b/accel/kvm/kvm-all.c index b09bad0804..c6c052ba57 100644 --- a/accel/kvm/kvm-all.c +++ b/accel/kvm/kvm-all.c @@ -821,6 +821,39 @@ int kvm_vm_check_extension(KVMState *s, unsigned int extension) return ret; } +typedef struct HWPoisonPage { + ram_addr_t ram_addr; + QLIST_ENTRY(HWPoisonPage) list; +} HWPoisonPage; + +static QLIST_HEAD(, HWPoisonPage) hwpoison_page_list = + QLIST_HEAD_INITIALIZER(hwpoison_page_list); + +void kvm_unpoison_all(void *param) +{ + HWPoisonPage *page, *next_page; + + QLIST_FOREACH_SAFE(page, &hwpoison_page_list, list, next_page) { + QLIST_REMOVE(page, list); + qemu_ram_remap(page->ram_addr, TARGET_PAGE_SIZE); + g_free(page); + } +} + +void kvm_hwpoison_page_add(ram_addr_t ram_addr) +{ + HWPoisonPage *page; + + QLIST_FOREACH(page, &hwpoison_page_list, list) { + if (page->ram_addr == ram_addr) { + return; + } + } + page = g_new(HWPoisonPage, 1); + page->ram_addr = ram_addr; + QLIST_INSERT_HEAD(&hwpoison_page_list, page, list); +} + static uint32_t adjust_ioeventfd_endianness(uint32_t val, uint32_t size) { #if defined(HOST_WORDS_BIGENDIAN) != defined(TARGET_WORDS_BIGENDIAN) diff --git a/include/sysemu/kvm_int.h b/include/sysemu/kvm_int.h index 72b2d1b3ae..3ad49f9a28 100644 --- a/include/sysemu/kvm_int.h +++ b/include/sysemu/kvm_int.h @@ -41,4 +41,27 @@ typedef struct KVMMemoryListener { void kvm_memory_listener_register(KVMState *s, KVMMemoryListener *kml, AddressSpace *as, int as_id); +/** + * kvm_hwpoison_page_add: + * + * Parameters: + * @ram_addr: the address in the RAM for the poisoned page + * + * Add a poisoned page to the list + * + * Return: None. + */ +void kvm_hwpoison_page_add(ram_addr_t ram_addr); + +/** + * kvm_unpoison_all: + * + * Parameters: + * @param: some data may be passed to this function + * + * Free and remove all the poisoned pages in the list + * + * Return: None. + */ +void kvm_unpoison_all(void *param); #endif diff --git a/target/arm/kvm.c b/target/arm/kvm.c index b2eaa50b8d..3a110be7b8 100644 --- a/target/arm/kvm.c +++ b/target/arm/kvm.c @@ -20,6 +20,7 @@ #include "sysemu/sysemu.h" #include "sysemu/kvm.h" #include "sysemu/kvm_int.h" +#include "sysemu/reset.h" #include "kvm_arm.h" #include "cpu.h" #include "trace.h" @@ -195,6 +196,8 @@ int kvm_arch_init(MachineState *ms, KVMState *s) cap_has_mp_state = kvm_check_extension(s, KVM_CAP_MP_STATE); + qemu_register_reset(kvm_unpoison_all, NULL); + return 0; } diff --git a/target/i386/kvm.c b/target/i386/kvm.c index 8023c679ea..4f9f3682ee 100644 --- a/target/i386/kvm.c +++ b/target/i386/kvm.c @@ -476,40 +476,6 @@ uint32_t kvm_arch_get_supported_msr_feature(KVMState *s, uint32_t index) return msr_data.entries[0].data; } - -typedef struct HWPoisonPage { - ram_addr_t ram_addr; - QLIST_ENTRY(HWPoisonPage) list; -} HWPoisonPage; - -static QLIST_HEAD(, HWPoisonPage) hwpoison_page_list = - QLIST_HEAD_INITIALIZER(hwpoison_page_list); - -static void kvm_unpoison_all(void *param) -{ - HWPoisonPage *page, *next_page; - - QLIST_FOREACH_SAFE(page, &hwpoison_page_list, list, next_page) { - QLIST_REMOVE(page, list); - qemu_ram_remap(page->ram_addr, TARGET_PAGE_SIZE); - g_free(page); - } -} - -static void kvm_hwpoison_page_add(ram_addr_t ram_addr) -{ - HWPoisonPage *page; - - QLIST_FOREACH(page, &hwpoison_page_list, list) { - if (page->ram_addr == ram_addr) { - return; - } - } - page = g_new(HWPoisonPage, 1); - page->ram_addr = ram_addr; - QLIST_INSERT_HEAD(&hwpoison_page_list, page, list); -} - static int kvm_get_mce_cap_supported(KVMState *s, uint64_t *mce_cap, int *max_banks) { From patchwork Fri Sep 6 08:31:51 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Xiang Zheng X-Patchwork-Id: 11134777 Return-Path: Received: from mail.kernel.org (pdx-korg-mail-1.web.codeaurora.org [172.30.200.123]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id A5F6713B1 for ; Fri, 6 Sep 2019 08:35:08 +0000 (UTC) Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id 8A53D20842 for ; Fri, 6 Sep 2019 08:35:08 +0000 (UTC) DMARC-Filter: OpenDMARC Filter v1.3.2 mail.kernel.org 8A53D20842 Authentication-Results: mail.kernel.org; dmarc=none (p=none dis=none) header.from=huawei.com Authentication-Results: mail.kernel.org; spf=pass smtp.mailfrom=qemu-devel-bounces+patchwork-qemu-devel=patchwork.kernel.org@nongnu.org Received: from localhost ([::1]:53532 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1i69hz-00049z-2x for patchwork-qemu-devel@patchwork.kernel.org; Fri, 06 Sep 2019 04:35:07 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:50238) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1i69gQ-00021A-7w for qemu-devel@nongnu.org; Fri, 06 Sep 2019 04:33:31 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1i69gO-0005cl-NV for qemu-devel@nongnu.org; Fri, 06 Sep 2019 04:33:30 -0400 Received: from szxga05-in.huawei.com ([45.249.212.191]:2263 helo=huawei.com) by eggs.gnu.org with esmtps (TLS1.0:DHE_RSA_AES_256_CBC_SHA1:32) (Exim 4.71) (envelope-from ) id 1i69gJ-0005YN-OX; Fri, 06 Sep 2019 04:33:24 -0400 Received: from DGGEMS403-HUB.china.huawei.com (unknown [172.30.72.59]) by Forcepoint Email with ESMTP id DA4513714BE49AC749E6; Fri, 6 Sep 2019 16:33:20 +0800 (CST) Received: from HGHY1z004218071.china.huawei.com (10.177.29.32) by DGGEMS403-HUB.china.huawei.com (10.3.19.203) with Microsoft SMTP Server id 14.3.439.0; Fri, 6 Sep 2019 16:33:12 +0800 From: Xiang Zheng To: , , , , , , , , , , , , , , , , Date: Fri, 6 Sep 2019 16:31:51 +0800 Message-ID: <20190906083152.25716-6-zhengxiang9@huawei.com> X-Mailer: git-send-email 2.15.1.windows.2 In-Reply-To: <20190906083152.25716-1-zhengxiang9@huawei.com> References: <20190906083152.25716-1-zhengxiang9@huawei.com> MIME-Version: 1.0 X-Originating-IP: [10.177.29.32] X-CFilter-Loop: Reflected X-detected-operating-system: by eggs.gnu.org: GNU/Linux 2.2.x-3.x [generic] X-Received-From: 45.249.212.191 Subject: [Qemu-devel] [PATCH v18 5/6] target-arm: kvm64: inject synchronous External Abort X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: wanghaibin.wang@huawei.com, zhengxiang9@huawei.com Errors-To: qemu-devel-bounces+patchwork-qemu-devel=patchwork.kernel.org@nongnu.org Sender: "Qemu-devel" From: Dongjiu Geng Introduce kvm_inject_arm_sea() function in which we will setup the type of exception and the syndrome information in order to inject a virtual synchronous external abort. When switching to guest, it will jump to the synchronous external abort vector table entry. The ESR_ELx.DFSC is set to synchronous external abort(0x10), and ESR_ELx.FnV is set to not valid(0x1), which will tell guest that FAR is not valid and hold an UNKNOWN value. These values will be set to KVM register structures through KVM_SET_ONE_REG IOCTL. Signed-off-by: Dongjiu Geng Signed-off-by: Xiang Zheng --- target/arm/helper.c | 2 +- target/arm/internals.h | 5 +++-- target/arm/kvm64.c | 34 ++++++++++++++++++++++++++++++++++ target/arm/tlb_helper.c | 2 +- 4 files changed, 39 insertions(+), 4 deletions(-) diff --git a/target/arm/helper.c b/target/arm/helper.c index 507026c915..a13baeb085 100644 --- a/target/arm/helper.c +++ b/target/arm/helper.c @@ -3005,7 +3005,7 @@ static uint64_t do_ats_write(CPUARMState *env, uint64_t value, * Report exception with ESR indicating a fault due to a * translation table walk for a cache maintenance instruction. */ - syn = syn_data_abort_no_iss(current_el == target_el, + syn = syn_data_abort_no_iss(current_el == target_el, 0, fi.ea, 1, fi.s1ptw, 1, fsc); env->exception.vaddress = value; env->exception.fsr = fsr; diff --git a/target/arm/internals.h b/target/arm/internals.h index 232d963875..98cde702ad 100644 --- a/target/arm/internals.h +++ b/target/arm/internals.h @@ -451,13 +451,14 @@ static inline uint32_t syn_insn_abort(int same_el, int ea, int s1ptw, int fsc) | ARM_EL_IL | (ea << 9) | (s1ptw << 7) | fsc; } -static inline uint32_t syn_data_abort_no_iss(int same_el, +static inline uint32_t syn_data_abort_no_iss(int same_el, int fnv, int ea, int cm, int s1ptw, int wnr, int fsc) { return (EC_DATAABORT << ARM_EL_EC_SHIFT) | (same_el << ARM_EL_EC_SHIFT) | ARM_EL_IL - | (ea << 9) | (cm << 8) | (s1ptw << 7) | (wnr << 6) | fsc; + | (fnv << 10) | (ea << 9) | (cm << 8) | (s1ptw << 7) + | (wnr << 6) | fsc; } static inline uint32_t syn_data_abort_with_iss(int same_el, diff --git a/target/arm/kvm64.c b/target/arm/kvm64.c index 28f6db57d5..bf6edaa3f6 100644 --- a/target/arm/kvm64.c +++ b/target/arm/kvm64.c @@ -710,6 +710,40 @@ int kvm_arm_cpreg_level(uint64_t regidx) return KVM_PUT_RUNTIME_STATE; } +/* Inject synchronous external abort */ +static void kvm_inject_arm_sea(CPUState *c) +{ + ARMCPU *cpu = ARM_CPU(c); + CPUARMState *env = &cpu->env; + CPUClass *cc = CPU_GET_CLASS(c); + uint32_t esr; + bool same_el; + + /** + * Set the exception type to synchronous data abort + * and the target exception Level to EL1. + */ + c->exception_index = EXCP_DATA_ABORT; + env->exception.target_el = 1; + + /* + * Set the DFSC to synchronous external abort and set FnV to not valid, + * this will tell guest the FAR_ELx is UNKNOWN for this abort. + */ + + /* This exception comes from lower or current exception level. */ + same_el = arm_current_el(env) == env->exception.target_el; + esr = syn_data_abort_no_iss(same_el, 1, 0, 0, 0, 0, 0x10); + + env->exception.syndrome = esr; + + /** + * The vcpu thread already hold BQL, so no need hold again when + * calling do_interrupt + */ + cc->do_interrupt(c); +} + #define AARCH64_CORE_REG(x) (KVM_REG_ARM64 | KVM_REG_SIZE_U64 | \ KVM_REG_ARM_CORE | KVM_REG_ARM_CORE_REG(x)) diff --git a/target/arm/tlb_helper.c b/target/arm/tlb_helper.c index 5feb312941..499672ebbc 100644 --- a/target/arm/tlb_helper.c +++ b/target/arm/tlb_helper.c @@ -33,7 +33,7 @@ static inline uint32_t merge_syn_data_abort(uint32_t template_syn, * ISV field. */ if (!(template_syn & ARM_EL_ISV) || target_el != 2 || s1ptw) { - syn = syn_data_abort_no_iss(same_el, + syn = syn_data_abort_no_iss(same_el, 0, ea, 0, s1ptw, is_write, fsc); } else { /* From patchwork Fri Sep 6 08:31:52 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Xiang Zheng X-Patchwork-Id: 11134783 Return-Path: Received: from mail.kernel.org (pdx-korg-mail-1.web.codeaurora.org [172.30.200.123]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id 6216415E6 for ; Fri, 6 Sep 2019 08:38:08 +0000 (UTC) Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id 343AF20842 for ; Fri, 6 Sep 2019 08:38:08 +0000 (UTC) DMARC-Filter: OpenDMARC Filter v1.3.2 mail.kernel.org 343AF20842 Authentication-Results: mail.kernel.org; dmarc=none (p=none dis=none) header.from=huawei.com Authentication-Results: mail.kernel.org; spf=pass smtp.mailfrom=qemu-devel-bounces+patchwork-qemu-devel=patchwork.kernel.org@nongnu.org Received: from localhost ([::1]:53568 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1i69kt-0007Y9-7o for patchwork-qemu-devel@patchwork.kernel.org; Fri, 06 Sep 2019 04:38:07 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:50270) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1i69gS-000242-S5 for qemu-devel@nongnu.org; Fri, 06 Sep 2019 04:33:35 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1i69gQ-0005dl-7y for qemu-devel@nongnu.org; Fri, 06 Sep 2019 04:33:32 -0400 Received: from szxga07-in.huawei.com ([45.249.212.35]:51342 helo=huawei.com) by eggs.gnu.org with esmtps (TLS1.0:DHE_RSA_AES_256_CBC_SHA1:32) (Exim 4.71) (envelope-from ) id 1i69gI-0005YF-PJ; Fri, 06 Sep 2019 04:33:23 -0400 Received: from DGGEMS403-HUB.china.huawei.com (unknown [172.30.72.58]) by Forcepoint Email with ESMTP id BA96F2422365D44913A1; Fri, 6 Sep 2019 16:33:20 +0800 (CST) Received: from HGHY1z004218071.china.huawei.com (10.177.29.32) by DGGEMS403-HUB.china.huawei.com (10.3.19.203) with Microsoft SMTP Server id 14.3.439.0; Fri, 6 Sep 2019 16:33:13 +0800 From: Xiang Zheng To: , , , , , , , , , , , , , , , , Date: Fri, 6 Sep 2019 16:31:52 +0800 Message-ID: <20190906083152.25716-7-zhengxiang9@huawei.com> X-Mailer: git-send-email 2.15.1.windows.2 In-Reply-To: <20190906083152.25716-1-zhengxiang9@huawei.com> References: <20190906083152.25716-1-zhengxiang9@huawei.com> MIME-Version: 1.0 X-Originating-IP: [10.177.29.32] X-CFilter-Loop: Reflected X-detected-operating-system: by eggs.gnu.org: GNU/Linux 2.2.x-3.x [generic] X-Received-From: 45.249.212.35 Subject: [Qemu-devel] [PATCH v18 6/6] target-arm: kvm64: handle SIGBUS signal from kernel or KVM X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: wanghaibin.wang@huawei.com, zhengxiang9@huawei.com Errors-To: qemu-devel-bounces+patchwork-qemu-devel=patchwork.kernel.org@nongnu.org Sender: "Qemu-devel" From: Dongjiu Geng Add a SIGBUS signal handler. In this handler, it checks the SIGBUS type, translates the host VA delivered by host to guest PA, then fills this PA to guest APEI GHES memory, then notifies guest according to the SIGBUS type. If guest accesses the poisoned memory, it generates Synchronous External Abort(SEA). Then host kernel gets an APEI notification and calls memory_failure() to unmapped the affected page in stage 2, finally returns to guest. Guest continues to access PG_hwpoison page, it will trap to KVM as stage2 fault, then a SIGBUS_MCEERR_AR synchronous signal is delivered to Qemu, Qemu records this error address into guest APEI GHES memory and notifes guest using Synchronous-External-Abort(SEA). Suggested-by: James Morse Signed-off-by: Dongjiu Geng Signed-off-by: Xiang Zheng --- hw/acpi/acpi_ghes.c | 252 ++++++++++++++++++++++++++++++++++++ include/hw/acpi/acpi_ghes.h | 40 ++++++ include/sysemu/kvm.h | 2 +- target/arm/kvm64.c | 39 ++++++ 4 files changed, 332 insertions(+), 1 deletion(-) diff --git a/hw/acpi/acpi_ghes.c b/hw/acpi/acpi_ghes.c index 20c45179ff..2d17c88045 100644 --- a/hw/acpi/acpi_ghes.c +++ b/hw/acpi/acpi_ghes.c @@ -26,6 +26,168 @@ #include "sysemu/sysemu.h" #include "qemu/error-report.h" +/* Total size for Generic Error Status Block + * ACPI 6.2: 18.3.2.7.1 Generic Error Data, + * Table 18-380 Generic Error Status Block + */ +#define ACPI_GHES_GESB_SIZE 20 +/* The offset of Data Length in Generic Error Status Block */ +#define ACPI_GHES_GESB_DATA_LENGTH_OFFSET 12 + +/* Record the value of data length for each error status block to avoid getting + * this value from guest. + */ +static uint32_t acpi_ghes_data_length[ACPI_GHES_ERROR_SOURCE_COUNT]; + +/* Generic Error Data Entry + * ACPI 6.1: 18.3.2.7.1 Generic Error Data + */ +static void acpi_ghes_generic_error_data(GArray *table, QemuUUID section_type, + uint32_t error_severity, uint16_t revision, + uint8_t validation_bits, uint8_t flags, + uint32_t error_data_length, QemuUUID fru_id, + uint8_t *fru_text, uint64_t time_stamp) +{ + QemuUUID uuid_le; + + /* Section Type */ + uuid_le = qemu_uuid_bswap(section_type); + g_array_append_vals(table, uuid_le.data, ARRAY_SIZE(uuid_le.data)); + + /* Error Severity */ + build_append_int_noprefix(table, error_severity, 4); + /* Revision */ + build_append_int_noprefix(table, revision, 2); + /* Validation Bits */ + build_append_int_noprefix(table, validation_bits, 1); + /* Flags */ + build_append_int_noprefix(table, flags, 1); + /* Error Data Length */ + build_append_int_noprefix(table, error_data_length, 4); + + /* FRU Id */ + uuid_le = qemu_uuid_bswap(fru_id); + g_array_append_vals(table, uuid_le.data, ARRAY_SIZE(uuid_le.data)); + + /* FRU Text */ + g_array_append_vals(table, fru_text, 20); + /* Timestamp */ + build_append_int_noprefix(table, time_stamp, 8); +} + +/* Generic Error Status Block + * ACPI 6.1: 18.3.2.7.1 Generic Error Data + */ +static void acpi_ghes_generic_error_status(GArray *table, uint32_t block_status, + uint32_t raw_data_offset, uint32_t raw_data_length, + uint32_t data_length, uint32_t error_severity) +{ + /* Block Status */ + build_append_int_noprefix(table, block_status, 4); + /* Raw Data Offset */ + build_append_int_noprefix(table, raw_data_offset, 4); + /* Raw Data Length */ + build_append_int_noprefix(table, raw_data_length, 4); + /* Data Length */ + build_append_int_noprefix(table, data_length, 4); + /* Error Severity */ + build_append_int_noprefix(table, error_severity, 4); +} + +/* UEFI 2.6: N.2.5 Memory Error Section */ +static void acpi_ghes_build_append_mem_cper(GArray *table, + uint64_t error_physical_addr) +{ + /* + * Memory Error Record + */ + + /* Validation Bits */ + build_append_int_noprefix(table, + (1UL << 14) | /* Type Valid */ + (1UL << 1) /* Physical Address Valid */, + 8); + /* Error Status */ + build_append_int_noprefix(table, 0, 8); + /* Physical Address */ + build_append_int_noprefix(table, error_physical_addr, 8); + /* Skip all the detailed information normally found in such a record */ + build_append_int_noprefix(table, 0, 48); + /* Memory Error Type */ + build_append_int_noprefix(table, 0 /* Unknown error */, 1); + /* Skip all the detailed information normally found in such a record */ + build_append_int_noprefix(table, 0, 7); +} + +static int acpi_ghes_record_mem_error(uint64_t error_block_address, + uint64_t error_physical_addr, + uint32_t data_length) +{ + GArray *block; + uint64_t current_block_length; + /* Memory Error Section Type */ + QemuUUID mem_section_id_le = UEFI_CPER_SEC_PLATFORM_MEM; + QemuUUID fru_id = {0}; + uint8_t fru_text[20] = {0}; + + /* Generic Error Status Block + * | +---------------------+ + * | | block_status | + * | +---------------------+ + * | | raw_data_offset | + * | +---------------------+ + * | | raw_data_length | + * | +---------------------+ + * | | data_length | + * | +---------------------+ + * | | error_severity | + * | +---------------------+ + */ + block = g_array_new(false, true /* clear */, 1); + + /* The current whole length of the generic error status block */ + current_block_length = ACPI_GHES_GESB_SIZE + data_length; + + /* This is the length if adding a new generic error data entry*/ + data_length += ACPI_GHES_DATA_LENGTH; + data_length += ACPI_GHES_MEM_CPER_LENGTH; + + /* Check whether it will run out of the preallocated memory if adding a new + * generic error data entry + */ + if ((data_length + ACPI_GHES_GESB_SIZE) > ACPI_GHES_MAX_RAW_DATA_LENGTH) { + error_report("Record CPER out of boundary!!!"); + return ACPI_GHES_CPER_FAIL; + } + + /* Build the new generic error status block header */ + acpi_ghes_generic_error_status(block, cpu_to_le32(ACPI_GEBS_UNCORRECTABLE), + 0, 0, cpu_to_le32(data_length), cpu_to_le32(ACPI_CPER_SEV_RECOVERABLE)); + + /* Write back above generic error status block header to guest memory */ + cpu_physical_memory_write(error_block_address, block->data, + block->len); + + /* Add a new generic error data entry */ + + data_length = block->len; + /* Build this new generic error data entry header */ + acpi_ghes_generic_error_data(block, mem_section_id_le, + cpu_to_le32(ACPI_CPER_SEV_RECOVERABLE), cpu_to_le32(0x300), 0, 0, + cpu_to_le32(ACPI_GHES_MEM_CPER_LENGTH), fru_id, fru_text, 0); + + /* Build the memory section CPER for above new generic error data entry */ + acpi_ghes_build_append_mem_cper(block, error_physical_addr); + + /* Write back above this new generic error data entry to guest memory */ + cpu_physical_memory_write(error_block_address + current_block_length, + block->data + data_length, block->len - data_length); + + g_array_free(block, true); + + return ACPI_GHES_CPER_OK; +} + /* Hardware Error Notification * ACPI 4.0: 17.3.2.7 Hardware Error Notification */ @@ -208,3 +370,93 @@ void acpi_ghes_add_fw_cfg(FWCfgState *s, GArray *hardware_error) fw_cfg_add_file_callback(s, ACPI_GHES_DATA_ADDR_FW_CFG_FILE, NULL, NULL, NULL, &ges.ghes_addr_le, sizeof(ges.ghes_addr_le), false); } + +bool acpi_ghes_record_errors(uint32_t notify, uint64_t physical_address) +{ + uint64_t error_block_addr, read_ack_register_addr, read_ack_register = 0; + int loop = 0; + uint64_t start_addr = le64_to_cpu(ges.ghes_addr_le); + bool ret = ACPI_GHES_CPER_FAIL; + uint8_t source_id; + const uint8_t error_source_id[] = { 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0, 0xff, 0xff, 0xff}; + + /* + * | +---------------------+ ges.ghes_addr_le + * | |error_block_address0 | + * | +---------------------+ --+-- + * | | ............. | ACPI_GHES_ADDRESS_SIZE + * | +---------------------+ --+-- + * | |error_block_addressN | + * | +---------------------+ + * | | read_ack_register0 | + * | +---------------------+ --+-- + * | | ............. | ACPI_GHES_ADDRESS_SIZE + * | +---------------------+ --+-- + * | | read_ack_registerN | + * | +---------------------+ --+-- + * | | CPER | | + * | | .... | ACPI_GHES_MAX_RAW_DATA_LENGT + * | | CPER | | + * | +---------------------+ --+-- + * | | .......... | + * | +---------------------+ + * | | CPER | + * | | .... | + * | | CPER | + * | +---------------------+ + */ + if (physical_address && notify < ACPI_GHES_NOTIFY_RESERVED) { + /* Find and check the source id for this new CPER */ + source_id = error_source_id[notify]; + if (source_id != 0xff) { + start_addr += source_id * ACPI_GHES_ADDRESS_SIZE; + } else { + goto out; + } + + cpu_physical_memory_read(start_addr, &error_block_addr, + ACPI_GHES_ADDRESS_SIZE); + + read_ack_register_addr = start_addr + + ACPI_GHES_ERROR_SOURCE_COUNT * ACPI_GHES_ADDRESS_SIZE; +retry: + cpu_physical_memory_read(read_ack_register_addr, + &read_ack_register, ACPI_GHES_ADDRESS_SIZE); + + /* zero means OSPM does not acknowledge the error */ + if (!read_ack_register) { + if (loop < 3) { + usleep(100 * 1000); + loop++; + goto retry; + } else { + error_report("OSPM does not acknowledge previous error," + " so can not record CPER for current error, forcibly" + " acknowledge previous error to avoid blocking next time" + " CPER record! Exit"); + read_ack_register = 1; + cpu_physical_memory_write(read_ack_register_addr, + &read_ack_register, ACPI_GHES_ADDRESS_SIZE); + } + } else { + if (error_block_addr) { + read_ack_register = 0; + /* Clear the Read Ack Register, OSPM will write it to 1 when + * acknowledge this error. + */ + cpu_physical_memory_write(read_ack_register_addr, + &read_ack_register, ACPI_GHES_ADDRESS_SIZE); + ret = acpi_ghes_record_mem_error(error_block_addr, + physical_address, acpi_ghes_data_length[source_id]); + if (ret == ACPI_GHES_CPER_OK) { + acpi_ghes_data_length[source_id] += + (ACPI_GHES_DATA_LENGTH + ACPI_GHES_MEM_CPER_LENGTH); + } + } + } + } + +out: + return ret; +} diff --git a/include/hw/acpi/acpi_ghes.h b/include/hw/acpi/acpi_ghes.h index 69747ba3d7..96f932c207 100644 --- a/include/hw/acpi/acpi_ghes.h +++ b/include/hw/acpi/acpi_ghes.h @@ -34,6 +34,35 @@ /* The max size in bytes for one error block */ #define ACPI_GHES_MAX_RAW_DATA_LENGTH 0x1000 +/* The total size of Generic Error Data Entry + * ACPI 6.1/6.2: 18.3.2.7.1 Generic Error Data, + * Table 18-343 Generic Error Data Entry + */ +#define ACPI_GHES_DATA_LENGTH 72 + +/* The memory section CPER size, + * UEFI 2.6: N.2.5 Memory Error Section + */ +#define ACPI_GHES_MEM_CPER_LENGTH 80 + +#define ACPI_GHES_CPER_OK 1 +#define ACPI_GHES_CPER_FAIL 0 + +/* + * Masks for block_status flags above + */ +#define ACPI_GEBS_UNCORRECTABLE 1 + +/* + * Values for error_severity field above + */ +enum AcpiGenericErrorSeverity { + ACPI_CPER_SEV_RECOVERABLE, + ACPI_CPER_SEV_FATAL, + ACPI_CPER_SEV_CORRECTED, + ACPI_CPER_SEV_NONE, +}; + /* Now only support ARMv8 SEA notification type error source */ #define ACPI_GHES_ERROR_SOURCE_COUNT 1 @@ -67,6 +96,16 @@ enum AcpiGhesNotifyType { ACPI_GHES_NOTIFY_RESERVED = 12 /* 12 and greater are reserved */ }; +#define UUID_BE(a, b, c, d0, d1, d2, d3, d4, d5, d6, d7) \ + {{{ ((a) >> 24) & 0xff, ((a) >> 16) & 0xff, ((a) >> 8) & 0xff, (a) & 0xff, \ + ((b) >> 8) & 0xff, (b) & 0xff, \ + ((c) >> 8) & 0xff, (c) & 0xff, \ + (d0), (d1), (d2), (d3), (d4), (d5), (d6), (d7) } } } + +#define UEFI_CPER_SEC_PLATFORM_MEM \ + UUID_BE(0xA5BC1114, 0x6F64, 0x4EDE, 0xB8, 0x63, 0x3E, 0x83, \ + 0xED, 0x7C, 0x83, 0xB1) + /* * | +--------------------------+ 0 * | | Header | @@ -100,4 +139,5 @@ void acpi_ghes_build_hest(GArray *table_data, GArray *hardware_error, void acpi_ghes_build_error_table(GArray *hardware_errors, BIOSLinker *linker); void acpi_ghes_add_fw_cfg(FWCfgState *s, GArray *hardware_errors); +bool acpi_ghes_record_errors(uint32_t notify, uint64_t error_physical_addr); #endif diff --git a/include/sysemu/kvm.h b/include/sysemu/kvm.h index 909bcd77cf..5f57e4ed43 100644 --- a/include/sysemu/kvm.h +++ b/include/sysemu/kvm.h @@ -378,7 +378,7 @@ bool kvm_vcpu_id_is_valid(int vcpu_id); /* Returns VCPU ID to be used on KVM_CREATE_VCPU ioctl() */ unsigned long kvm_arch_vcpu_id(CPUState *cpu); -#ifdef TARGET_I386 +#if defined(TARGET_I386) || defined(TARGET_AARCH64) #define KVM_HAVE_MCE_INJECTION 1 void kvm_arch_on_sigbus_vcpu(CPUState *cpu, int code, void *addr); #endif diff --git a/target/arm/kvm64.c b/target/arm/kvm64.c index bf6edaa3f6..186d855522 100644 --- a/target/arm/kvm64.c +++ b/target/arm/kvm64.c @@ -28,6 +28,8 @@ #include "kvm_arm.h" #include "hw/boards.h" #include "internals.h" +#include "hw/acpi/acpi.h" +#include "hw/acpi/acpi_ghes.h" static bool have_guest_debug; @@ -1070,6 +1072,43 @@ int kvm_arch_get_registers(CPUState *cs) return ret; } +void kvm_arch_on_sigbus_vcpu(CPUState *c, int code, void *addr) +{ + ram_addr_t ram_addr; + hwaddr paddr; + + assert(code == BUS_MCEERR_AR || code == BUS_MCEERR_AO); + + if (acpi_enabled && addr && + object_property_get_bool(qdev_get_machine(), "ras", NULL)) { + ram_addr = qemu_ram_addr_from_host(addr); + if (ram_addr != RAM_ADDR_INVALID && + kvm_physical_memory_addr_from_host(c->kvm_state, addr, &paddr)) { + kvm_hwpoison_page_add(ram_addr); + /* Asynchronous signal will be masked by main thread, so + * only handle synchronous signal. + */ + if (code == BUS_MCEERR_AR) { + kvm_cpu_synchronize_state(c); + if (ACPI_GHES_CPER_FAIL != + acpi_ghes_record_errors(ACPI_GHES_NOTIFY_SEA, paddr)) { + kvm_inject_arm_sea(c); + } else { + fprintf(stderr, "failed to record the error\n"); + } + } + return; + } + fprintf(stderr, "Hardware memory error for memory used by " + "QEMU itself instead of guest system!\n"); + } + + if (code == BUS_MCEERR_AR) { + fprintf(stderr, "Hardware memory error!\n"); + exit(1); + } +} + /* C6.6.29 BRK instruction */ static const uint32_t brk_insn = 0xd4200000;