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Fri, 6 Sep 2019 19:11:43 +0000 From: "Moger, Babu" To: ssg.sos.staff , "ehabkost@redhat.com" , "marcel.apfelbaum@gmail.com" , "mst@redhat.com" , "pbonzini@redhat.com" , "rth@twiddle.net" , "eblake@redhat.com" , "armbru@redhat.com" , "imammedo@redhat.com" Thread-Topic: [RFC 2 PATCH 01/16] numa: Split the numa functionality Thread-Index: AQHVZObrnLDTbxd9bUifE1lwjy5LPg== Date: Fri, 6 Sep 2019 19:11:43 +0000 Message-ID: <156779710184.21957.13351592831416903368.stgit@localhost.localdomain> References: <156779689013.21957.1631551572950676212.stgit@localhost.localdomain> In-Reply-To: <156779689013.21957.1631551572950676212.stgit@localhost.localdomain> Accept-Language: en-US Content-Language: en-US X-MS-Has-Attach: X-MS-TNEF-Correlator: x-clientproxiedby: SN4PR0401CA0009.namprd04.prod.outlook.com (2603:10b6:803:21::19) To DM5PR12MB2471.namprd12.prod.outlook.com (2603:10b6:4:b5::10) authentication-results: spf=none (sender IP is ) smtp.mailfrom=Babu.Moger@amd.com; x-ms-exchange-messagesentrepresentingtype: 1 x-originating-ip: [165.204.78.1] x-ms-publictraffictype: Email x-ms-office365-filtering-correlation-id: 88a7dc72-dd9c-4a9c-4aef-08d732fe0ddd x-ms-office365-filtering-ht: Tenant x-microsoft-antispam: BCL:0; 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DIR:OUT; SFP:1101; SCL:1; SRVR:DM5PR12MB1145; H:DM5PR12MB2471.namprd12.prod.outlook.com; FPR:; SPF:None; LANG:en; PTR:InfoNoRecords; A:1; MX:1; received-spf: None (protection.outlook.com: amd.com does not designate permitted sender hosts) x-ms-exchange-senderadcheck: 1 x-microsoft-antispam-message-info: snComlcKZ6V0zX9isGmMPx/7KVtPNbtRN6B8baGfb6DedYFRrVU39wvAd0enfuo6InRXDpXUg7g+dXlVdk/J9uHjPxa8QVe7WI2zA6uTQ/6JRRs0fY2ivpDExyi3ZdpZ9F23bNbyRsDQESUCqZFBSvNoIDelE0JT6c0/kW2EZoW3pgUqVoKx8gi9xn+eSXx/WyafkIlIFR5YyLSwaePvkttkTiWl0dGco/obMOk7MVkwzwttwsSg1Z500PyJ0lzSjfGkNCGjlmm0zUmilEmGCcETDl2B3ms7vlJ+SOWhGwtWml7Z3/lynPPH/GwSLY+ovuXm5TnHc1WKxyF2VVebT4WRLE66Va1MCR4W+ow/2tH41vOyYAUbiyAJOAUo4Ee+EZObGNrYZXSWItZzrU6p/T/HS28ZPLYS0Riw2PPQdmY= Content-ID: <91D5F778E86AEB43B30783D33CC5C9E0@namprd12.prod.outlook.com> MIME-Version: 1.0 X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-Network-Message-Id: 88a7dc72-dd9c-4a9c-4aef-08d732fe0ddd X-MS-Exchange-CrossTenant-originalarrivaltime: 06 Sep 2019 19:11:43.6660 (UTC) X-MS-Exchange-CrossTenant-fromentityheader: Hosted X-MS-Exchange-CrossTenant-id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-mailboxtype: HOSTED X-MS-Exchange-CrossTenant-userprincipalname: rgCdITV5mHNMCirgQEn8v8l+GO4yB6a/7gcX2OMib16a+MLv6IaEj1HMUTnIrECW X-MS-Exchange-Transport-CrossTenantHeadersStamped: DM5PR12MB1145 X-detected-operating-system: by eggs.gnu.org: Windows 7 or 8 [fuzzy] X-Received-From: 40.107.75.75 Subject: [Qemu-devel] [RFC 2 PATCH 01/16] numa: Split the numa functionality X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: "qemu-devel@nongnu.org" Errors-To: qemu-devel-bounces+patchwork-qemu-devel=patchwork.kernel.org@nongnu.org Sender: "Qemu-devel" To support new epyc mode, we need to know the number of numa nodes in advance to generate apic id correctly. So, split the numa initialization into two. The function parse_numa initializes numa_info and updates nb_numa_nodes. And then parse_numa_node does the numa node initialization. Signed-off-by: Babu Moger --- hw/core/numa.c | 106 +++++++++++++++++++++++++++++++++++-------------- include/sysemu/numa.h | 2 + vl.c | 2 + 3 files changed, 80 insertions(+), 30 deletions(-) diff --git a/hw/core/numa.c b/hw/core/numa.c index a11431483c..27fa6b5e1d 100644 --- a/hw/core/numa.c +++ b/hw/core/numa.c @@ -55,14 +55,10 @@ bool have_numa_distance; NodeInfo numa_info[MAX_NODES]; -static void parse_numa_node(MachineState *ms, NumaNodeOptions *node, +static void parse_numa_info(MachineState *ms, NumaNodeOptions *node, Error **errp) { - Error *err = NULL; uint16_t nodenr; - uint16List *cpus = NULL; - MachineClass *mc = MACHINE_GET_CLASS(ms); - unsigned int max_cpus = ms->smp.max_cpus; if (node->has_nodeid) { nodenr = node->nodeid; @@ -81,29 +77,6 @@ static void parse_numa_node(MachineState *ms, NumaNodeOptions *node, return; } - if (!mc->cpu_index_to_instance_props || !mc->get_default_cpu_node_id) { - error_setg(errp, "NUMA is not supported by this machine-type"); - return; - } - for (cpus = node->cpus; cpus; cpus = cpus->next) { - CpuInstanceProperties props; - if (cpus->value >= max_cpus) { - error_setg(errp, - "CPU index (%" PRIu16 ")" - " should be smaller than maxcpus (%d)", - cpus->value, max_cpus); - return; - } - props = mc->cpu_index_to_instance_props(ms, cpus->value); - props.node_id = nodenr; - props.has_node_id = true; - machine_set_cpu_numa_node(ms, &props, &err); - if (err) { - error_propagate(errp, err); - return; - } - } - have_memdevs = have_memdevs ? : node->has_memdev; have_mem = have_mem ? : node->has_mem; if ((node->has_mem && have_memdevs) || (node->has_memdev && have_mem)) { @@ -177,7 +150,7 @@ void set_numa_options(MachineState *ms, NumaOptions *object, Error **errp) switch (object->type) { case NUMA_OPTIONS_TYPE_NODE: - parse_numa_node(ms, &object->u.node, &err); + parse_numa_info(ms, &object->u.node, &err); if (err) { goto end; } @@ -242,6 +215,73 @@ end: return 0; } +void set_numa_node_options(MachineState *ms, NumaOptions *object, Error **errp) +{ + MachineClass *mc = MACHINE_GET_CLASS(ms); + NumaNodeOptions *node = &object->u.node; + unsigned int max_cpus = ms->smp.max_cpus; + uint16List *cpus = NULL; + Error *err = NULL; + uint16_t nodenr; + + if (node->has_nodeid) { + nodenr = node->nodeid; + } else { + error_setg(errp, "NUMA node information is not available"); + } + + if (!mc->cpu_index_to_instance_props || !mc->get_default_cpu_node_id) { + error_setg(errp, "NUMA is not supported by this machine-type"); + return; + } + + for (cpus = node->cpus; cpus; cpus = cpus->next) { + CpuInstanceProperties props; + if (cpus->value >= max_cpus) { + error_setg(errp, + "CPU index (%" PRIu16 ")" + " should be smaller than maxcpus (%d)", + cpus->value, max_cpus); + return; + } + props = mc->cpu_index_to_instance_props(ms, cpus->value); + props.node_id = nodenr; + props.has_node_id = true; + machine_set_cpu_numa_node(ms, &props, &err); + if (err) { + error_propagate(errp, err); + return; + } + } +} + +static int parse_numa_node(void *opaque, QemuOpts *opts, Error **errp) +{ + NumaOptions *object = NULL; + MachineState *ms = MACHINE(opaque); + Error *err = NULL; + Visitor *v = opts_visitor_new(opts); + + visit_type_NumaOptions(v, NULL, &object, &err); + visit_free(v); + if (err) { + goto end; + } + + if (object->type == NUMA_OPTIONS_TYPE_NODE) { + set_numa_node_options(ms, object, &err); + } + +end: + qapi_free_NumaOptions(object); + if (err) { + error_propagate(errp, err); + return -1; + } + + return 0; +} + /* If all node pair distances are symmetric, then only distances * in one direction are enough. If there is even one asymmetric * pair, though, then all distances must be provided. The @@ -368,7 +408,7 @@ void numa_complete_configuration(MachineState *ms) if (ms->ram_slots > 0 && nb_numa_nodes == 0 && mc->auto_enable_numa_with_memhp) { NumaNodeOptions node = { }; - parse_numa_node(ms, &node, &error_abort); + parse_numa_info(ms, &node, &error_abort); } assert(max_numa_nodeid <= MAX_NODES); @@ -448,6 +488,12 @@ void parse_numa_opts(MachineState *ms) qemu_opts_foreach(qemu_find_opts("numa"), parse_numa, ms, &error_fatal); } +void parse_numa_node_opts(MachineState *ms) +{ + qemu_opts_foreach(qemu_find_opts("numa"), parse_numa_node, + ms, &error_fatal); +} + void numa_cpu_pre_plug(const CPUArchId *slot, DeviceState *dev, Error **errp) { int node_id = object_property_get_int(OBJECT(dev), "node-id", &error_abort); diff --git a/include/sysemu/numa.h b/include/sysemu/numa.h index 01a263eba2..ca109adaa6 100644 --- a/include/sysemu/numa.h +++ b/include/sysemu/numa.h @@ -24,7 +24,9 @@ struct NumaNodeMem { extern NodeInfo numa_info[MAX_NODES]; void set_numa_options(MachineState *ms, NumaOptions *object, Error **errp); +void set_numa_node_options(MachineState *ms, NumaOptions *object, Error **errp); void parse_numa_opts(MachineState *ms); +void parse_numa_node_opts(MachineState *ms); void numa_complete_configuration(MachineState *ms); void query_numa_node_mem(NumaNodeMem node_mem[]); extern QemuOptsList qemu_numa_opts; diff --git a/vl.c b/vl.c index b426b32134..711d2ae5da 100644 --- a/vl.c +++ b/vl.c @@ -4339,6 +4339,8 @@ int main(int argc, char **argv, char **envp) } parse_numa_opts(current_machine); + parse_numa_node_opts(current_machine); + /* do monitor/qmp handling at preconfig state if requested */ main_loop(); From patchwork Fri Sep 6 19:11:50 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Babu Moger X-Patchwork-Id: 11135855 Return-Path: Received: from mail.kernel.org (pdx-korg-mail-1.web.codeaurora.org [172.30.200.123]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id 2EF7513BD for ; Fri, 6 Sep 2019 19:13:33 +0000 (UTC) Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id EA7902070C for ; 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Fri, 6 Sep 2019 19:11:50 +0000 From: "Moger, Babu" To: ssg.sos.staff , "ehabkost@redhat.com" , "marcel.apfelbaum@gmail.com" , "mst@redhat.com" , "pbonzini@redhat.com" , "rth@twiddle.net" , "eblake@redhat.com" , "armbru@redhat.com" , "imammedo@redhat.com" Thread-Topic: [RFC 2 PATCH 02/16] hw/i386: Rename X86CPUTopoInfo structure to X86CPUTopoIDs Thread-Index: AQHVZObvrlEVZxaTa0i09SKpSAN3jw== Date: Fri, 6 Sep 2019 19:11:50 +0000 Message-ID: <156779710892.21957.12320825183231112713.stgit@localhost.localdomain> References: <156779689013.21957.1631551572950676212.stgit@localhost.localdomain> In-Reply-To: <156779689013.21957.1631551572950676212.stgit@localhost.localdomain> Accept-Language: en-US Content-Language: en-US X-MS-Has-Attach: X-MS-TNEF-Correlator: x-clientproxiedby: SN6PR06CA0010.namprd06.prod.outlook.com (2603:10b6:805:8e::23) To DM5PR12MB2471.namprd12.prod.outlook.com (2603:10b6:4:b5::10) authentication-results: spf=none (sender IP is ) smtp.mailfrom=Babu.Moger@amd.com; x-ms-exchange-messagesentrepresentingtype: 1 x-originating-ip: [165.204.78.1] x-ms-publictraffictype: Email x-ms-office365-filtering-correlation-id: 10270f50-ba88-4771-0275-08d732fe121c x-ms-office365-filtering-ht: Tenant x-microsoft-antispam: BCL:0; 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DIR:OUT; SFP:1101; SCL:1; SRVR:DM5PR12MB1145; H:DM5PR12MB2471.namprd12.prod.outlook.com; FPR:; SPF:None; LANG:en; PTR:InfoNoRecords; A:1; MX:1; received-spf: None (protection.outlook.com: amd.com does not designate permitted sender hosts) x-ms-exchange-senderadcheck: 1 x-microsoft-antispam-message-info: rwEaJr/bcyusb3I3cbdFUQJ4AFTuvbBMrDUCloKZsUstEIxx04dwu7Z6KPUaFvRaGSjhwU2CnjDUVb7LFf/6s9RR8CWNrh9KPxR/I1G4MYi4oLNz+jMp98hK29t5qnu2KYTI+dWvtAW32fmNNOnVXI5BsLd8zgnY3buTft43QuVt54zrjhs7QHWlI1Uv4LdLRTXCAxWSwm4t8t0VgXAnOKScJK+3dEFDSLCj6lmcnXn/6Tf3eEIOUcLLa2c4vdEjSpcpUwyiWR3HcvfTcYevJy5fqhM3ubPa6M4jyXonBfoMZ9dqcQEjlhDCU3L3iiLHj5DtW3TE6hmGn8EfZ83RtcdQh2072jvr4cSFN+ktFAcpFMwZuBS0VIbEBK/ZjvWTUCRfJx8LhymEaiVuusJxNFktu++0hw1uQR47ZsrryDo= Content-ID: MIME-Version: 1.0 X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-Network-Message-Id: 10270f50-ba88-4771-0275-08d732fe121c X-MS-Exchange-CrossTenant-originalarrivaltime: 06 Sep 2019 19:11:50.5280 (UTC) X-MS-Exchange-CrossTenant-fromentityheader: Hosted X-MS-Exchange-CrossTenant-id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-mailboxtype: HOSTED X-MS-Exchange-CrossTenant-userprincipalname: yOHgIKtZY32lisAnrUznQDzIxjaAjfH+WY4EBlY2Gg8eRSXIxSmHE23W6oeON913 X-MS-Exchange-Transport-CrossTenantHeadersStamped: DM5PR12MB1145 X-detected-operating-system: by eggs.gnu.org: Windows 7 or 8 [fuzzy] X-Received-From: 40.107.75.49 Subject: [Qemu-devel] [RFC 2 PATCH 02/16] hw/i386: Rename X86CPUTopoInfo structure to X86CPUTopoIDs X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: "qemu-devel@nongnu.org" Errors-To: qemu-devel-bounces+patchwork-qemu-devel=patchwork.kernel.org@nongnu.org Sender: "Qemu-devel" Rename few data structures related to X86 topology. X86CPUTopoIDs will have individual arch ids. Next patch introduces X86CPUTopoInfo which will have all topology information(like cores, threads etc..). Adds node_id and ccx_id. This will be required to support new epyc mode mode. There is no functional change. Signed-off-by: Babu Moger Reviewed-by: Eduardo Habkost --- hw/i386/pc.c | 60 ++++++++++++++++++++++---------------------- include/hw/i386/topology.h | 42 ++++++++++++++++--------------- 2 files changed, 52 insertions(+), 50 deletions(-) diff --git a/hw/i386/pc.c b/hw/i386/pc.c index 549c437050..ada445f8f3 100644 --- a/hw/i386/pc.c +++ b/hw/i386/pc.c @@ -2379,7 +2379,7 @@ static void pc_cpu_pre_plug(HotplugHandler *hotplug_dev, int idx; CPUState *cs; CPUArchId *cpu_slot; - X86CPUTopoInfo topo; + X86CPUTopoIDs topo_ids; X86CPU *cpu = X86_CPU(dev); CPUX86State *env = &cpu->env; MachineState *ms = MACHINE(hotplug_dev); @@ -2432,12 +2432,12 @@ static void pc_cpu_pre_plug(HotplugHandler *hotplug_dev, return; } - topo.pkg_id = cpu->socket_id; - topo.die_id = cpu->die_id; - topo.core_id = cpu->core_id; - topo.smt_id = cpu->thread_id; + topo_ids.pkg_id = cpu->socket_id; + topo_ids.die_id = cpu->die_id; + topo_ids.core_id = cpu->core_id; + topo_ids.smt_id = cpu->thread_id; cpu->apic_id = apicid_from_topo_ids(pcms->smp_dies, smp_cores, - smp_threads, &topo); + smp_threads, &topo_ids); } cpu_slot = pc_find_cpu_slot(MACHINE(pcms), cpu->apic_id, &idx); @@ -2445,11 +2445,11 @@ static void pc_cpu_pre_plug(HotplugHandler *hotplug_dev, MachineState *ms = MACHINE(pcms); x86_topo_ids_from_apicid(cpu->apic_id, pcms->smp_dies, - smp_cores, smp_threads, &topo); + smp_cores, smp_threads, &topo_ids); error_setg(errp, "Invalid CPU [socket: %u, die: %u, core: %u, thread: %u] with" " APIC ID %" PRIu32 ", valid index range 0:%d", - topo.pkg_id, topo.die_id, topo.core_id, topo.smt_id, + topo_ids.pkg_id, topo_ids.die_id, topo_ids.core_id, topo_ids.smt_id, cpu->apic_id, ms->possible_cpus->len - 1); return; } @@ -2467,34 +2467,34 @@ static void pc_cpu_pre_plug(HotplugHandler *hotplug_dev, * once -smp refactoring is complete and there will be CPU private * CPUState::nr_cores and CPUState::nr_threads fields instead of globals */ x86_topo_ids_from_apicid(cpu->apic_id, pcms->smp_dies, - smp_cores, smp_threads, &topo); - if (cpu->socket_id != -1 && cpu->socket_id != topo.pkg_id) { + smp_cores, smp_threads, &topo_ids); + if (cpu->socket_id != -1 && cpu->socket_id != topo_ids.pkg_id) { error_setg(errp, "property socket-id: %u doesn't match set apic-id:" - " 0x%x (socket-id: %u)", cpu->socket_id, cpu->apic_id, topo.pkg_id); + " 0x%x (socket-id: %u)", cpu->socket_id, cpu->apic_id, topo_ids.pkg_id); return; } - cpu->socket_id = topo.pkg_id; + cpu->socket_id = topo_ids.pkg_id; - if (cpu->die_id != -1 && cpu->die_id != topo.die_id) { + if (cpu->die_id != -1 && cpu->die_id != topo_ids.die_id) { error_setg(errp, "property die-id: %u doesn't match set apic-id:" - " 0x%x (die-id: %u)", cpu->die_id, cpu->apic_id, topo.die_id); + " 0x%x (die-id: %u)", cpu->die_id, cpu->apic_id, topo_ids.die_id); return; } - cpu->die_id = topo.die_id; + cpu->die_id = topo_ids.die_id; - if (cpu->core_id != -1 && cpu->core_id != topo.core_id) { + if (cpu->core_id != -1 && cpu->core_id != topo_ids.core_id) { error_setg(errp, "property core-id: %u doesn't match set apic-id:" - " 0x%x (core-id: %u)", cpu->core_id, cpu->apic_id, topo.core_id); + " 0x%x (core-id: %u)", cpu->core_id, cpu->apic_id, topo_ids.core_id); return; } - cpu->core_id = topo.core_id; + cpu->core_id = topo_ids.core_id; - if (cpu->thread_id != -1 && cpu->thread_id != topo.smt_id) { + if (cpu->thread_id != -1 && cpu->thread_id != topo_ids.smt_id) { error_setg(errp, "property thread-id: %u doesn't match set apic-id:" - " 0x%x (thread-id: %u)", cpu->thread_id, cpu->apic_id, topo.smt_id); + " 0x%x (thread-id: %u)", cpu->thread_id, cpu->apic_id, topo_ids.smt_id); return; } - cpu->thread_id = topo.smt_id; + cpu->thread_id = topo_ids.smt_id; if (hyperv_feat_enabled(cpu, HYPERV_FEAT_VPINDEX) && !kvm_hv_vpindex_settable()) { @@ -2840,14 +2840,14 @@ pc_cpu_index_to_props(MachineState *ms, unsigned cpu_index) static int64_t pc_get_default_cpu_node_id(const MachineState *ms, int idx) { - X86CPUTopoInfo topo; + X86CPUTopoIDs topo_ids; PCMachineState *pcms = PC_MACHINE(ms); assert(idx < ms->possible_cpus->len); x86_topo_ids_from_apicid(ms->possible_cpus->cpus[idx].arch_id, pcms->smp_dies, ms->smp.cores, - ms->smp.threads, &topo); - return topo.pkg_id % nb_numa_nodes; + ms->smp.threads, &topo_ids); + return topo_ids.pkg_id % nb_numa_nodes; } static const CPUArchIdList *pc_possible_cpu_arch_ids(MachineState *ms) @@ -2869,22 +2869,22 @@ static const CPUArchIdList *pc_possible_cpu_arch_ids(MachineState *ms) sizeof(CPUArchId) * max_cpus); ms->possible_cpus->len = max_cpus; for (i = 0; i < ms->possible_cpus->len; i++) { - X86CPUTopoInfo topo; + X86CPUTopoIDs topo_ids; ms->possible_cpus->cpus[i].type = ms->cpu_type; ms->possible_cpus->cpus[i].vcpus_count = 1; ms->possible_cpus->cpus[i].arch_id = x86_cpu_apic_id_from_index(pcms, i); x86_topo_ids_from_apicid(ms->possible_cpus->cpus[i].arch_id, pcms->smp_dies, ms->smp.cores, - ms->smp.threads, &topo); + ms->smp.threads, &topo_ids); ms->possible_cpus->cpus[i].props.has_socket_id = true; - ms->possible_cpus->cpus[i].props.socket_id = topo.pkg_id; + ms->possible_cpus->cpus[i].props.socket_id = topo_ids.pkg_id; ms->possible_cpus->cpus[i].props.has_die_id = true; - ms->possible_cpus->cpus[i].props.die_id = topo.die_id; + ms->possible_cpus->cpus[i].props.die_id = topo_ids.die_id; ms->possible_cpus->cpus[i].props.has_core_id = true; - ms->possible_cpus->cpus[i].props.core_id = topo.core_id; + ms->possible_cpus->cpus[i].props.core_id = topo_ids.core_id; ms->possible_cpus->cpus[i].props.has_thread_id = true; - ms->possible_cpus->cpus[i].props.thread_id = topo.smt_id; + ms->possible_cpus->cpus[i].props.thread_id = topo_ids.smt_id; } return ms->possible_cpus; } diff --git a/include/hw/i386/topology.h b/include/hw/i386/topology.h index 4ff5b2da6c..0637743cdf 100644 --- a/include/hw/i386/topology.h +++ b/include/hw/i386/topology.h @@ -45,12 +45,14 @@ */ typedef uint32_t apic_id_t; -typedef struct X86CPUTopoInfo { +typedef struct X86CPUTopoIDs { unsigned pkg_id; unsigned die_id; unsigned core_id; unsigned smt_id; -} X86CPUTopoInfo; + unsigned node_id; + unsigned ccx_id; +} X86CPUTopoIDs; /* Return the bit width needed for 'count' IDs */ @@ -122,12 +124,12 @@ static inline unsigned apicid_pkg_offset(unsigned nr_dies, static inline apic_id_t apicid_from_topo_ids(unsigned nr_dies, unsigned nr_cores, unsigned nr_threads, - const X86CPUTopoInfo *topo) + const X86CPUTopoIDs *topo_ids) { - return (topo->pkg_id << apicid_pkg_offset(nr_dies, nr_cores, nr_threads)) | - (topo->die_id << apicid_die_offset(nr_dies, nr_cores, nr_threads)) | - (topo->core_id << apicid_core_offset(nr_dies, nr_cores, nr_threads)) | - topo->smt_id; + return (topo_ids->pkg_id << apicid_pkg_offset(nr_dies, nr_cores, nr_threads)) | + (topo_ids->die_id << apicid_die_offset(nr_dies, nr_cores, nr_threads)) | + (topo_ids->core_id << apicid_core_offset(nr_dies, nr_cores, nr_threads)) | + topo_ids->smt_id; } /* Calculate thread/core/package IDs for a specific topology, @@ -137,12 +139,12 @@ static inline void x86_topo_ids_from_idx(unsigned nr_dies, unsigned nr_cores, unsigned nr_threads, unsigned cpu_index, - X86CPUTopoInfo *topo) + X86CPUTopoIDs *topo_ids) { - topo->pkg_id = cpu_index / (nr_dies * nr_cores * nr_threads); - topo->die_id = cpu_index / (nr_cores * nr_threads) % nr_dies; - topo->core_id = cpu_index / nr_threads % nr_cores; - topo->smt_id = cpu_index % nr_threads; + topo_ids->pkg_id = cpu_index / (nr_dies * nr_cores * nr_threads); + topo_ids->die_id = cpu_index / (nr_cores * nr_threads) % nr_dies; + topo_ids->core_id = cpu_index / nr_threads % nr_cores; + topo_ids->smt_id = cpu_index % nr_threads; } /* Calculate thread/core/package IDs for a specific topology, @@ -152,17 +154,17 @@ static inline void x86_topo_ids_from_apicid(apic_id_t apicid, unsigned nr_dies, unsigned nr_cores, unsigned nr_threads, - X86CPUTopoInfo *topo) + X86CPUTopoIDs *topo_ids) { - topo->smt_id = apicid & + topo_ids->smt_id = apicid & ~(0xFFFFFFFFUL << apicid_smt_width(nr_dies, nr_cores, nr_threads)); - topo->core_id = + topo_ids->core_id = (apicid >> apicid_core_offset(nr_dies, nr_cores, nr_threads)) & ~(0xFFFFFFFFUL << apicid_core_width(nr_dies, nr_cores, nr_threads)); - topo->die_id = + topo_ids->die_id = (apicid >> apicid_die_offset(nr_dies, nr_cores, nr_threads)) & ~(0xFFFFFFFFUL << apicid_die_width(nr_dies, nr_cores, nr_threads)); - topo->pkg_id = apicid >> apicid_pkg_offset(nr_dies, nr_cores, nr_threads); + topo_ids->pkg_id = apicid >> apicid_pkg_offset(nr_dies, nr_cores, nr_threads); } /* Make APIC ID for the CPU 'cpu_index' @@ -174,9 +176,9 @@ static inline apic_id_t x86_apicid_from_cpu_idx(unsigned nr_dies, unsigned nr_threads, unsigned cpu_index) { - X86CPUTopoInfo topo; - x86_topo_ids_from_idx(nr_dies, nr_cores, nr_threads, cpu_index, &topo); - return apicid_from_topo_ids(nr_dies, nr_cores, nr_threads, &topo); + X86CPUTopoIDs topo_ids; + x86_topo_ids_from_idx(nr_dies, nr_cores, nr_threads, cpu_index, &topo_ids); + return apicid_from_topo_ids(nr_dies, nr_cores, nr_threads, &topo_ids); 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Fri, 6 Sep 2019 19:11:57 +0000 From: "Moger, Babu" To: ssg.sos.staff , "ehabkost@redhat.com" , "marcel.apfelbaum@gmail.com" , "mst@redhat.com" , "pbonzini@redhat.com" , "rth@twiddle.net" , "eblake@redhat.com" , "armbru@redhat.com" , "imammedo@redhat.com" Thread-Topic: [RFC 2 PATCH 03/16] hw/i386: Introduce X86CPUTopoInfo to contain topology info Thread-Index: AQHVZObziLA3l0FNIkGr1sRRrqiJ3Q== Date: Fri, 6 Sep 2019 19:11:57 +0000 Message-ID: <156779711572.21957.10722611828264773686.stgit@localhost.localdomain> References: <156779689013.21957.1631551572950676212.stgit@localhost.localdomain> In-Reply-To: <156779689013.21957.1631551572950676212.stgit@localhost.localdomain> Accept-Language: en-US Content-Language: en-US X-MS-Has-Attach: X-MS-TNEF-Correlator: x-clientproxiedby: SN4PR0401CA0010.namprd04.prod.outlook.com (2603:10b6:803:21::20) To DM5PR12MB2471.namprd12.prod.outlook.com (2603:10b6:4:b5::10) authentication-results: spf=none (sender IP is ) smtp.mailfrom=Babu.Moger@amd.com; x-ms-exchange-messagesentrepresentingtype: 1 x-originating-ip: [165.204.78.1] x-ms-publictraffictype: Email x-ms-office365-filtering-correlation-id: b6da3d73-6267-48e9-742b-08d732fe1622 x-ms-office365-filtering-ht: Tenant x-microsoft-antispam: BCL:0; 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DIR:OUT; SFP:1101; SCL:1; SRVR:DM5PR12MB1179; H:DM5PR12MB2471.namprd12.prod.outlook.com; FPR:; SPF:None; LANG:en; PTR:InfoNoRecords; MX:1; A:1; received-spf: None (protection.outlook.com: amd.com does not designate permitted sender hosts) x-ms-exchange-senderadcheck: 1 x-microsoft-antispam-message-info: 5UdIfzb3w4RAnHMdLVY2xqhur+FxCziGESGE75PjqNmifNaOY/gpd+e9KG6WcJRVTrNWrgQ6c5DkmYcZN35SrDPb0r0XZ2919W11zRTOSDhPUWi/UYgXNvD3bWzyRrtna+k9b9m3zex7uyile9eexc4urWqykaCOebErJyqVdG5+GG+1/TQfUfZW8FiLW/T4quXisQJkEQYbZ+4Hmy7HHV1VdJtPALHmF2Q4gbN6zLguM5vrMLaKoJs0nGon/fhJnBGNN1Ds2qaJVP//An1mbhnmzjPh14juZsUny/VW5NsAm6WcxfTjscEynT7Cw0n0pF3WDXaPVvywfGQaqtgHeQZyzhkOGQG+jLV3MK2lWweUjRx9nGLYVKnw5NK+hfQLCF964jL0DRbwkMEGeRLgn+mprEGMEOo7qdwXS5FC9HA= Content-ID: MIME-Version: 1.0 X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-Network-Message-Id: b6da3d73-6267-48e9-742b-08d732fe1622 X-MS-Exchange-CrossTenant-originalarrivaltime: 06 Sep 2019 19:11:57.4760 (UTC) X-MS-Exchange-CrossTenant-fromentityheader: Hosted X-MS-Exchange-CrossTenant-id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-mailboxtype: HOSTED X-MS-Exchange-CrossTenant-userprincipalname: iazF9OP1NqVq2TvrDjWeOUIIcdP80YmQQEZWHIQAYPSRaWsWeMMSYadU8Sewttv5 X-MS-Exchange-Transport-CrossTenantHeadersStamped: DM5PR12MB1179 X-detected-operating-system: by eggs.gnu.org: Windows 7 or 8 [fuzzy] X-Received-From: 40.107.82.45 Subject: [Qemu-devel] [RFC 2 PATCH 03/16] hw/i386: Introduce X86CPUTopoInfo to contain topology info X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: "qemu-devel@nongnu.org" Errors-To: qemu-devel-bounces+patchwork-qemu-devel=patchwork.kernel.org@nongnu.org Sender: "Qemu-devel" This is an effort to re-arrange few data structure for better readability. Add X86CPUTopoInfo which will have all the topology informations required to build the cpu topology. There is no functional changes. Signed-off-by: Babu Moger --- hw/i386/pc.c | 40 +++++++++++++++++++++++++++------------- include/hw/i386/topology.h | 40 ++++++++++++++++++++++++++-------------- 2 files changed, 53 insertions(+), 27 deletions(-) diff --git a/hw/i386/pc.c b/hw/i386/pc.c index ada445f8f3..95aab8e5e7 100644 --- a/hw/i386/pc.c +++ b/hw/i386/pc.c @@ -930,11 +930,15 @@ static uint32_t x86_cpu_apic_id_from_index(PCMachineState *pcms, { MachineState *ms = MACHINE(pcms); PCMachineClass *pcmc = PC_MACHINE_GET_CLASS(pcms); + X86CPUTopoInfo topo_info; uint32_t correct_id; static bool warned; - correct_id = x86_apicid_from_cpu_idx(pcms->smp_dies, ms->smp.cores, - ms->smp.threads, cpu_index); + topo_info.nr_dies = pcms->smp_dies; + topo_info.nr_cores = ms->smp.cores; + topo_info.nr_threads = ms->smp.threads; + + correct_id = x86_apicid_from_cpu_idx(&topo_info, cpu_index); if (pcmc->compat_apic_id_mode) { if (cpu_index != correct_id && !warned && !qtest_enabled()) { error_report("APIC IDs set in compatibility mode, " @@ -2386,6 +2390,7 @@ static void pc_cpu_pre_plug(HotplugHandler *hotplug_dev, PCMachineState *pcms = PC_MACHINE(hotplug_dev); unsigned int smp_cores = ms->smp.cores; unsigned int smp_threads = ms->smp.threads; + X86CPUTopoInfo topo_info; if(!object_dynamic_cast(OBJECT(cpu), ms->cpu_type)) { error_setg(errp, "Invalid CPU type, expected cpu type: '%s'", @@ -2393,6 +2398,10 @@ static void pc_cpu_pre_plug(HotplugHandler *hotplug_dev, return; } + topo_info.nr_dies = pcms->smp_dies; + topo_info.nr_cores = smp_cores; + topo_info.nr_threads = smp_threads; + env->nr_dies = pcms->smp_dies; /* @@ -2436,16 +2445,14 @@ static void pc_cpu_pre_plug(HotplugHandler *hotplug_dev, topo_ids.die_id = cpu->die_id; topo_ids.core_id = cpu->core_id; topo_ids.smt_id = cpu->thread_id; - cpu->apic_id = apicid_from_topo_ids(pcms->smp_dies, smp_cores, - smp_threads, &topo_ids); + cpu->apic_id = apicid_from_topo_ids(&topo_info, &topo_ids); } cpu_slot = pc_find_cpu_slot(MACHINE(pcms), cpu->apic_id, &idx); if (!cpu_slot) { MachineState *ms = MACHINE(pcms); - x86_topo_ids_from_apicid(cpu->apic_id, pcms->smp_dies, - smp_cores, smp_threads, &topo_ids); + x86_topo_ids_from_apicid(cpu->apic_id, &topo_info, &topo_ids); error_setg(errp, "Invalid CPU [socket: %u, die: %u, core: %u, thread: %u] with" " APIC ID %" PRIu32 ", valid index range 0:%d", @@ -2466,8 +2473,7 @@ static void pc_cpu_pre_plug(HotplugHandler *hotplug_dev, /* TODO: move socket_id/core_id/thread_id checks into x86_cpu_realizefn() * once -smp refactoring is complete and there will be CPU private * CPUState::nr_cores and CPUState::nr_threads fields instead of globals */ - x86_topo_ids_from_apicid(cpu->apic_id, pcms->smp_dies, - smp_cores, smp_threads, &topo_ids); + x86_topo_ids_from_apicid(cpu->apic_id, &topo_info, &topo_ids); if (cpu->socket_id != -1 && cpu->socket_id != topo_ids.pkg_id) { error_setg(errp, "property socket-id: %u doesn't match set apic-id:" " 0x%x (socket-id: %u)", cpu->socket_id, cpu->apic_id, topo_ids.pkg_id); @@ -2842,19 +2848,28 @@ static int64_t pc_get_default_cpu_node_id(const MachineState *ms, int idx) { X86CPUTopoIDs topo_ids; PCMachineState *pcms = PC_MACHINE(ms); + X86CPUTopoInfo topo_info; + + topo_info.nr_dies = pcms->smp_dies; + topo_info.nr_cores = ms->smp.cores; + topo_info.nr_threads = ms->smp.threads; assert(idx < ms->possible_cpus->len); x86_topo_ids_from_apicid(ms->possible_cpus->cpus[idx].arch_id, - pcms->smp_dies, ms->smp.cores, - ms->smp.threads, &topo_ids); + &topo_info, &topo_ids); return topo_ids.pkg_id % nb_numa_nodes; } static const CPUArchIdList *pc_possible_cpu_arch_ids(MachineState *ms) { PCMachineState *pcms = PC_MACHINE(ms); - int i; unsigned int max_cpus = ms->smp.max_cpus; + X86CPUTopoInfo topo_info; + int i; + + topo_info.nr_dies = pcms->smp_dies; + topo_info.nr_cores = ms->smp.cores; + topo_info.nr_threads = ms->smp.threads; if (ms->possible_cpus) { /* @@ -2875,8 +2890,7 @@ static const CPUArchIdList *pc_possible_cpu_arch_ids(MachineState *ms) ms->possible_cpus->cpus[i].vcpus_count = 1; ms->possible_cpus->cpus[i].arch_id = x86_cpu_apic_id_from_index(pcms, i); x86_topo_ids_from_apicid(ms->possible_cpus->cpus[i].arch_id, - pcms->smp_dies, ms->smp.cores, - ms->smp.threads, &topo_ids); + &topo_info, &topo_ids); ms->possible_cpus->cpus[i].props.has_socket_id = true; ms->possible_cpus->cpus[i].props.socket_id = topo_ids.pkg_id; ms->possible_cpus->cpus[i].props.has_die_id = true; diff --git a/include/hw/i386/topology.h b/include/hw/i386/topology.h index 0637743cdf..906017e8e3 100644 --- a/include/hw/i386/topology.h +++ b/include/hw/i386/topology.h @@ -54,6 +54,14 @@ typedef struct X86CPUTopoIDs { unsigned ccx_id; } X86CPUTopoIDs; +typedef struct X86CPUTopoInfo { + unsigned numa_nodes; + unsigned nr_sockets; + unsigned nr_dies; + unsigned nr_cores; + unsigned nr_threads; +} X86CPUTopoInfo; + /* Return the bit width needed for 'count' IDs */ static unsigned apicid_bitwidth_for_count(unsigned count) @@ -121,11 +129,13 @@ static inline unsigned apicid_pkg_offset(unsigned nr_dies, * * The caller must make sure core_id < nr_cores and smt_id < nr_threads. */ -static inline apic_id_t apicid_from_topo_ids(unsigned nr_dies, - unsigned nr_cores, - unsigned nr_threads, +static inline apic_id_t apicid_from_topo_ids(X86CPUTopoInfo *topo_info, const X86CPUTopoIDs *topo_ids) { + unsigned nr_dies = topo_info->nr_dies; + unsigned nr_cores = topo_info->nr_cores; + unsigned nr_threads = topo_info->nr_threads; + return (topo_ids->pkg_id << apicid_pkg_offset(nr_dies, nr_cores, nr_threads)) | (topo_ids->die_id << apicid_die_offset(nr_dies, nr_cores, nr_threads)) | (topo_ids->core_id << apicid_core_offset(nr_dies, nr_cores, nr_threads)) | @@ -135,12 +145,14 @@ static inline apic_id_t apicid_from_topo_ids(unsigned nr_dies, /* Calculate thread/core/package IDs for a specific topology, * based on (contiguous) CPU index */ -static inline void x86_topo_ids_from_idx(unsigned nr_dies, - unsigned nr_cores, - unsigned nr_threads, +static inline void x86_topo_ids_from_idx(X86CPUTopoInfo *topo_info, unsigned cpu_index, X86CPUTopoIDs *topo_ids) { + unsigned nr_dies = topo_info->nr_dies; + unsigned nr_cores = topo_info->nr_cores; + unsigned nr_threads = topo_info->nr_threads; + topo_ids->pkg_id = cpu_index / (nr_dies * nr_cores * nr_threads); topo_ids->die_id = cpu_index / (nr_cores * nr_threads) % nr_dies; topo_ids->core_id = cpu_index / nr_threads % nr_cores; @@ -151,11 +163,13 @@ static inline void x86_topo_ids_from_idx(unsigned nr_dies, * based on APIC ID */ static inline void x86_topo_ids_from_apicid(apic_id_t apicid, - unsigned nr_dies, - unsigned nr_cores, - unsigned nr_threads, + X86CPUTopoInfo *topo_info, X86CPUTopoIDs *topo_ids) { + unsigned nr_dies = topo_info->nr_dies; + unsigned nr_cores = topo_info->nr_cores; + unsigned nr_threads = topo_info->nr_threads; + topo_ids->smt_id = apicid & ~(0xFFFFFFFFUL << apicid_smt_width(nr_dies, nr_cores, nr_threads)); topo_ids->core_id = @@ -171,14 +185,12 @@ static inline void x86_topo_ids_from_apicid(apic_id_t apicid, * * 'cpu_index' is a sequential, contiguous ID for the CPU. */ -static inline apic_id_t x86_apicid_from_cpu_idx(unsigned nr_dies, - unsigned nr_cores, - unsigned nr_threads, +static inline apic_id_t x86_apicid_from_cpu_idx(X86CPUTopoInfo *topo_info, unsigned cpu_index) { X86CPUTopoIDs topo_ids; - x86_topo_ids_from_idx(nr_dies, nr_cores, nr_threads, cpu_index, &topo_ids); - return apicid_from_topo_ids(nr_dies, nr_cores, nr_threads, &topo_ids); + x86_topo_ids_from_idx(topo_info, cpu_index, &topo_ids); + return apicid_from_topo_ids(topo_info, &topo_ids); } #endif /* HW_I386_TOPOLOGY_H */ From patchwork Fri Sep 6 19:12:04 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Babu Moger X-Patchwork-Id: 11135857 Return-Path: Received: from mail.kernel.org (pdx-korg-mail-1.web.codeaurora.org [172.30.200.123]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id 089F316B1 for ; Fri, 6 Sep 2019 19:14:10 +0000 (UTC) Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id D48A42070C for ; Fri, 6 Sep 2019 19:14:09 +0000 (UTC) Authentication-Results: mail.kernel.org; dkim=fail reason="signature verification failed" (1024-bit key) header.d=amdcloud.onmicrosoft.com header.i=@amdcloud.onmicrosoft.com header.b="x0Fxmn0A" DMARC-Filter: OpenDMARC Filter v1.3.2 mail.kernel.org D48A42070C Authentication-Results: mail.kernel.org; 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Fri, 6 Sep 2019 19:12:05 +0000 From: "Moger, Babu" To: ssg.sos.staff , "ehabkost@redhat.com" , "marcel.apfelbaum@gmail.com" , "mst@redhat.com" , "pbonzini@redhat.com" , "rth@twiddle.net" , "eblake@redhat.com" , "armbru@redhat.com" , "imammedo@redhat.com" Thread-Topic: [RFC 2 PATCH 04/16] machine: Add SMP Sockets in CpuTopology Thread-Index: AQHVZOb49iqY+dEK7EqEIoezGv+ilw== Date: Fri, 6 Sep 2019 19:12:04 +0000 Message-ID: <156779712350.21957.6312199085335942636.stgit@localhost.localdomain> References: <156779689013.21957.1631551572950676212.stgit@localhost.localdomain> In-Reply-To: <156779689013.21957.1631551572950676212.stgit@localhost.localdomain> Accept-Language: en-US Content-Language: en-US X-MS-Has-Attach: X-MS-TNEF-Correlator: x-clientproxiedby: SN6PR06CA0020.namprd06.prod.outlook.com (2603:10b6:805:8e::33) To DM5PR12MB2471.namprd12.prod.outlook.com (2603:10b6:4:b5::10) authentication-results: spf=none (sender IP is ) smtp.mailfrom=Babu.Moger@amd.com; x-ms-exchange-messagesentrepresentingtype: 1 x-originating-ip: [165.204.78.1] x-ms-publictraffictype: Email x-ms-office365-filtering-correlation-id: 85efdba0-9553-4088-e743-08d732fe1acd x-ms-office365-filtering-ht: Tenant x-microsoft-antispam: BCL:0; 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DIR:OUT; SFP:1101; SCL:1; SRVR:DM5PR12MB1145; H:DM5PR12MB2471.namprd12.prod.outlook.com; FPR:; SPF:None; LANG:en; PTR:InfoNoRecords; A:1; MX:1; received-spf: None (protection.outlook.com: amd.com does not designate permitted sender hosts) x-ms-exchange-senderadcheck: 1 x-microsoft-antispam-message-info: ud8EE0DthP2RVzUiAMqhWIKwxOjxhIBJvQMABzXR7XZGzO7HewpsmvJw/p8LSa2nTDNCLZB3fWr2A93m7GjAhRI6A8+puYvXiBgEqLl319Ur/hCDzkJ46QPR1o7sMGJFGY/R0X2K6hDH66As1wkPaT9eLA2IYP1O9sLhLgAOWn3W+VmeN55sUYnNh6Zn50PnwBqo0ris2n3xL8/oOF8flg/VZTbGL1gmaMzLHdSG67WMpXKYXRioQOnW2SjL3pzPMT8y4LgmaSkkQSJ15KgMkOj87cnDNy5eotHLEo6S5AML3L3vK9CLt4K0afya9Lj+4eB7WsULgq2gF1MP00dv7qNqw0vyY0SmwPtZkIgehPXmevmH9UGb7fVaHRkwHKc3vCEHg8/ztg0yEa2NLnL0Cm8Zfa42RVm6zO7xAnn+aDM= Content-ID: MIME-Version: 1.0 X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-Network-Message-Id: 85efdba0-9553-4088-e743-08d732fe1acd X-MS-Exchange-CrossTenant-originalarrivaltime: 06 Sep 2019 19:12:05.0147 (UTC) X-MS-Exchange-CrossTenant-fromentityheader: Hosted X-MS-Exchange-CrossTenant-id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-mailboxtype: HOSTED X-MS-Exchange-CrossTenant-userprincipalname: GWbzz1MIzG3R4RJYmRd/bYZMXymqKNHn2x4su72qRppMWkBieDk5QmtybT0ZWXg0 X-MS-Exchange-Transport-CrossTenantHeadersStamped: DM5PR12MB1145 X-detected-operating-system: by eggs.gnu.org: Windows 7 or 8 [fuzzy] X-Received-From: 40.107.75.85 Subject: [Qemu-devel] [RFC 2 PATCH 04/16] machine: Add SMP Sockets in CpuTopology X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: "qemu-devel@nongnu.org" Errors-To: qemu-devel-bounces+patchwork-qemu-devel=patchwork.kernel.org@nongnu.org Sender: "Qemu-devel" Store the smp Sockets in CpuTopology. Socket information is required to build the cpu topology in new epyc mode. Signed-off-by: Babu Moger Reviewed-by: Eduardo Habkost --- hw/core/machine.c | 1 + hw/i386/pc.c | 1 + include/hw/boards.h | 2 ++ vl.c | 1 + 4 files changed, 5 insertions(+) diff --git a/hw/core/machine.c b/hw/core/machine.c index c58a8e594e..4034b7e903 100644 --- a/hw/core/machine.c +++ b/hw/core/machine.c @@ -795,6 +795,7 @@ static void smp_parse(MachineState *ms, QemuOpts *opts) ms->smp.cpus = cpus; ms->smp.cores = cores; ms->smp.threads = threads; + ms->smp.sockets = sockets; } if (ms->smp.cpus > 1) { diff --git a/hw/i386/pc.c b/hw/i386/pc.c index 95aab8e5e7..9e1c3f9f57 100644 --- a/hw/i386/pc.c +++ b/hw/i386/pc.c @@ -1609,6 +1609,7 @@ void pc_smp_parse(MachineState *ms, QemuOpts *opts) ms->smp.cpus = cpus; ms->smp.cores = cores; ms->smp.threads = threads; + ms->smp.sockets = sockets; pcms->smp_dies = dies; } diff --git a/include/hw/boards.h b/include/hw/boards.h index a71d1a53a5..12eb5032a5 100644 --- a/include/hw/boards.h +++ b/include/hw/boards.h @@ -245,12 +245,14 @@ typedef struct DeviceMemoryState { * @cpus: the number of present logical processors on the machine * @cores: the number of cores in one package * @threads: the number of threads in one core + * @sockets: the number of sockets on the machine * @max_cpus: the maximum number of logical processors on the machine */ typedef struct CpuTopology { unsigned int cpus; unsigned int cores; unsigned int threads; + unsigned int sockets; unsigned int max_cpus; } CpuTopology; diff --git a/vl.c b/vl.c index 711d2ae5da..473a688779 100644 --- a/vl.c +++ b/vl.c @@ -3981,6 +3981,7 @@ int main(int argc, char **argv, char **envp) current_machine->smp.max_cpus = machine_class->default_cpus; current_machine->smp.cores = 1; current_machine->smp.threads = 1; + current_machine->smp.sockets = 1; machine_class->smp_parse(current_machine, qemu_opts_find(qemu_find_opts("smp-opts"), NULL)); From patchwork Fri Sep 6 19:12:11 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Babu Moger X-Patchwork-Id: 11135859 Return-Path: Received: from mail.kernel.org (pdx-korg-mail-1.web.codeaurora.org [172.30.200.123]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id 4FF9A16B1 for ; Fri, 6 Sep 2019 19:16:05 +0000 (UTC) Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id 1603020644 for ; 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Fri, 6 Sep 2019 19:12:11 +0000 From: "Moger, Babu" To: ssg.sos.staff , "ehabkost@redhat.com" , "marcel.apfelbaum@gmail.com" , "mst@redhat.com" , "pbonzini@redhat.com" , "rth@twiddle.net" , "eblake@redhat.com" , "armbru@redhat.com" , "imammedo@redhat.com" Thread-Topic: [RFC 2 PATCH 05/16] hw/i386: Simplify topology Offset/width Calculation Thread-Index: AQHVZOb89qmGH/MzAkO4cTQpzupvOA== Date: Fri, 6 Sep 2019 19:12:11 +0000 Message-ID: <156779713027.21957.5884599223662351252.stgit@localhost.localdomain> References: <156779689013.21957.1631551572950676212.stgit@localhost.localdomain> In-Reply-To: <156779689013.21957.1631551572950676212.stgit@localhost.localdomain> Accept-Language: en-US Content-Language: en-US X-MS-Has-Attach: X-MS-TNEF-Correlator: x-clientproxiedby: SN4PR0601CA0015.namprd06.prod.outlook.com (2603:10b6:803:2f::25) To DM5PR12MB2471.namprd12.prod.outlook.com (2603:10b6:4:b5::10) authentication-results: spf=none (sender IP is ) smtp.mailfrom=Babu.Moger@amd.com; x-ms-exchange-messagesentrepresentingtype: 1 x-originating-ip: [165.204.78.1] x-ms-publictraffictype: Email x-ms-office365-filtering-correlation-id: c7641158-64bb-4190-3b93-08d732fe1ec7 x-ms-office365-filtering-ht: Tenant x-microsoft-antispam: BCL:0; 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DIR:OUT; SFP:1101; SCL:1; SRVR:DM5PR12MB1145; H:DM5PR12MB2471.namprd12.prod.outlook.com; FPR:; SPF:None; LANG:en; PTR:InfoNoRecords; A:1; MX:1; received-spf: None (protection.outlook.com: amd.com does not designate permitted sender hosts) x-ms-exchange-senderadcheck: 1 x-microsoft-antispam-message-info: Pk2AoBckym3iYEZaiGZIEvUZALThVcF/HzIrb4cDSd71qmqWAynwBGHvoLc47FxB6Y8khMlVKj1SwjE7QsF50GdcpVyg5lRnUt3i9PeYFtq7lY7JwPbTD2GXQdkO0dd33bqOPBTs9fJOo3Mnl0nUrY502V+Fb4kq8CmnqDsvB5IgKCgQYf5vWbjt1u/ulpQtupjmtswJAP7umVrfwIguSGPRp/UpUHWQkUx0xEIBEioCwaCcqYoi0UM/ymP1IziIUggVYbYOjwMdt/ZnOibdJZjRIo0kYp4UOGuXJL0msShEABjjC0ZmTD7wp7ZTMgS2Q26mFYEr3LnskkvtUvjnUM1Mr79qH76LdJ2sl+dsnUxpTaAse9i2tIY59D9T9sjt3FheJD4Q3lVRKDCGEjTRs+ePu/BRZUYTfD9Nqu86tHQ= Content-ID: <9E22E9CBBC317849A6482A2B7F00F961@namprd12.prod.outlook.com> MIME-Version: 1.0 X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-Network-Message-Id: c7641158-64bb-4190-3b93-08d732fe1ec7 X-MS-Exchange-CrossTenant-originalarrivaltime: 06 Sep 2019 19:12:11.6929 (UTC) X-MS-Exchange-CrossTenant-fromentityheader: Hosted X-MS-Exchange-CrossTenant-id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-mailboxtype: HOSTED X-MS-Exchange-CrossTenant-userprincipalname: AMLEvSU0+QPGJnzYed0rawAxwV7SiOSeI3avgf4dSEK4xpJHhf7XKnZWVjcZlPbo X-MS-Exchange-Transport-CrossTenantHeadersStamped: DM5PR12MB1145 X-detected-operating-system: by eggs.gnu.org: Windows 7 or 8 [fuzzy] X-Received-From: 40.107.69.45 Subject: [Qemu-devel] [RFC 2 PATCH 05/16] hw/i386: Simplify topology Offset/width Calculation X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: "qemu-devel@nongnu.org" Errors-To: qemu-devel-bounces+patchwork-qemu-devel=patchwork.kernel.org@nongnu.org Sender: "Qemu-devel" Some parameters are unnecessarily passed for offset/width calculation. Remove those parameters from function prototypes. No functional change. Signed-off-by: Babu Moger --- include/hw/i386/topology.h | 45 ++++++++++++++++++-------------------------- target/i386/cpu.c | 12 ++++-------- 2 files changed, 22 insertions(+), 35 deletions(-) diff --git a/include/hw/i386/topology.h b/include/hw/i386/topology.h index 906017e8e3..fb10863a66 100644 --- a/include/hw/i386/topology.h +++ b/include/hw/i386/topology.h @@ -73,46 +73,37 @@ static unsigned apicid_bitwidth_for_count(unsigned count) /* Bit width of the SMT_ID (thread ID) field on the APIC ID */ -static inline unsigned apicid_smt_width(unsigned nr_dies, - unsigned nr_cores, - unsigned nr_threads) +static inline unsigned apicid_smt_width(unsigned nr_threads) { return apicid_bitwidth_for_count(nr_threads); } /* Bit width of the Core_ID field */ -static inline unsigned apicid_core_width(unsigned nr_dies, - unsigned nr_cores, - unsigned nr_threads) +static inline unsigned apicid_core_width(unsigned nr_cores) { return apicid_bitwidth_for_count(nr_cores); } /* Bit width of the Die_ID field */ -static inline unsigned apicid_die_width(unsigned nr_dies, - unsigned nr_cores, - unsigned nr_threads) +static inline unsigned apicid_die_width(unsigned nr_dies) { return apicid_bitwidth_for_count(nr_dies); } /* Bit offset of the Core_ID field */ -static inline unsigned apicid_core_offset(unsigned nr_dies, - unsigned nr_cores, - unsigned nr_threads) +static inline unsigned apicid_core_offset(unsigned nr_threads) { - return apicid_smt_width(nr_dies, nr_cores, nr_threads); + return apicid_smt_width(nr_threads); } /* Bit offset of the Die_ID field */ -static inline unsigned apicid_die_offset(unsigned nr_dies, - unsigned nr_cores, - unsigned nr_threads) +static inline unsigned apicid_die_offset(unsigned nr_cores, + unsigned nr_threads) { - return apicid_core_offset(nr_dies, nr_cores, nr_threads) + - apicid_core_width(nr_dies, nr_cores, nr_threads); + return apicid_core_offset(nr_threads) + + apicid_core_width(nr_cores); } /* Bit offset of the Pkg_ID (socket ID) field @@ -121,8 +112,8 @@ static inline unsigned apicid_pkg_offset(unsigned nr_dies, unsigned nr_cores, unsigned nr_threads) { - return apicid_die_offset(nr_dies, nr_cores, nr_threads) + - apicid_die_width(nr_dies, nr_cores, nr_threads); + return apicid_die_offset(nr_cores, nr_threads) + + apicid_die_width(nr_dies); } /* Make APIC ID for the CPU based on Pkg_ID, Core_ID, SMT_ID @@ -137,8 +128,8 @@ static inline apic_id_t apicid_from_topo_ids(X86CPUTopoInfo *topo_info, unsigned nr_threads = topo_info->nr_threads; return (topo_ids->pkg_id << apicid_pkg_offset(nr_dies, nr_cores, nr_threads)) | - (topo_ids->die_id << apicid_die_offset(nr_dies, nr_cores, nr_threads)) | - (topo_ids->core_id << apicid_core_offset(nr_dies, nr_cores, nr_threads)) | + (topo_ids->die_id << apicid_die_offset(nr_cores, nr_threads)) | + (topo_ids->core_id << apicid_core_offset(nr_threads)) | topo_ids->smt_id; } @@ -171,13 +162,13 @@ static inline void x86_topo_ids_from_apicid(apic_id_t apicid, unsigned nr_threads = topo_info->nr_threads; topo_ids->smt_id = apicid & - ~(0xFFFFFFFFUL << apicid_smt_width(nr_dies, nr_cores, nr_threads)); + ~(0xFFFFFFFFUL << apicid_smt_width(nr_threads)); topo_ids->core_id = - (apicid >> apicid_core_offset(nr_dies, nr_cores, nr_threads)) & - ~(0xFFFFFFFFUL << apicid_core_width(nr_dies, nr_cores, nr_threads)); + (apicid >> apicid_core_offset(nr_threads)) & + ~(0xFFFFFFFFUL << apicid_core_width(nr_cores)); topo_ids->die_id = - (apicid >> apicid_die_offset(nr_dies, nr_cores, nr_threads)) & - ~(0xFFFFFFFFUL << apicid_die_width(nr_dies, nr_cores, nr_threads)); + (apicid >> apicid_die_offset(nr_cores, nr_threads)) & + ~(0xFFFFFFFFUL << apicid_die_width(nr_dies)); topo_ids->pkg_id = apicid >> apicid_pkg_offset(nr_dies, nr_cores, nr_threads); } diff --git a/target/i386/cpu.c b/target/i386/cpu.c index 19751e37a7..6d7f9b6b8b 100644 --- a/target/i386/cpu.c +++ b/target/i386/cpu.c @@ -4260,8 +4260,7 @@ void cpu_x86_cpuid(CPUX86State *env, uint32_t index, uint32_t count, eax, ebx, ecx, edx); break; case 3: /* L3 cache info */ - die_offset = apicid_die_offset(env->nr_dies, - cs->nr_cores, cs->nr_threads); + die_offset = apicid_die_offset(cs->nr_cores, cs->nr_threads); if (cpu->enable_l3_cache) { encode_cache_cpuid4(env->cache_info_cpuid4.l3_cache, (1 << die_offset), cs->nr_cores, @@ -4346,8 +4345,7 @@ void cpu_x86_cpuid(CPUX86State *env, uint32_t index, uint32_t count, switch (count) { case 0: - *eax = apicid_core_offset(env->nr_dies, - cs->nr_cores, cs->nr_threads); + *eax = apicid_core_offset(cs->nr_threads); *ebx = cs->nr_threads; *ecx |= CPUID_TOPOLOGY_LEVEL_SMT; break; @@ -4377,14 +4375,12 @@ void cpu_x86_cpuid(CPUX86State *env, uint32_t index, uint32_t count, *edx = cpu->apic_id; switch (count) { case 0: - *eax = apicid_core_offset(env->nr_dies, cs->nr_cores, - cs->nr_threads); + *eax = apicid_core_offset(cs->nr_threads); *ebx = cs->nr_threads; *ecx |= CPUID_TOPOLOGY_LEVEL_SMT; break; case 1: - *eax = apicid_die_offset(env->nr_dies, cs->nr_cores, - cs->nr_threads); + *eax = apicid_die_offset(cs->nr_cores, cs->nr_threads); *ebx = cs->nr_cores * cs->nr_threads; *ecx |= CPUID_TOPOLOGY_LEVEL_CORE; break; From patchwork Fri Sep 6 19:12:18 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Babu Moger X-Patchwork-Id: 11135867 Return-Path: Received: from mail.kernel.org (pdx-korg-mail-1.web.codeaurora.org [172.30.200.123]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id 291971398 for ; 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Fri, 6 Sep 2019 19:12:18 +0000 Received: from DM5PR12MB2471.namprd12.prod.outlook.com ([fe80::6c7c:4b6d:f136:1bf8]) by DM5PR12MB2471.namprd12.prod.outlook.com ([fe80::6c7c:4b6d:f136:1bf8%3]) with mapi id 15.20.2220.022; Fri, 6 Sep 2019 19:12:18 +0000 From: "Moger, Babu" To: ssg.sos.staff , "ehabkost@redhat.com" , "marcel.apfelbaum@gmail.com" , "mst@redhat.com" , "pbonzini@redhat.com" , "rth@twiddle.net" , "eblake@redhat.com" , "armbru@redhat.com" , "imammedo@redhat.com" Thread-Topic: [RFC 2 PATCH 06/16] hw/core: Add core complex id in X86CPU topology Thread-Index: AQHVZOcAvXBgYAx8v0mIeU+F8XEfTA== Date: Fri, 6 Sep 2019 19:12:18 +0000 Message-ID: <156779713686.21957.6192568272184346850.stgit@localhost.localdomain> References: <156779689013.21957.1631551572950676212.stgit@localhost.localdomain> In-Reply-To: <156779689013.21957.1631551572950676212.stgit@localhost.localdomain> Accept-Language: en-US Content-Language: en-US X-MS-Has-Attach: X-MS-TNEF-Correlator: x-clientproxiedby: SN6PR06CA0002.namprd06.prod.outlook.com (2603:10b6:805:8e::15) To DM5PR12MB2471.namprd12.prod.outlook.com (2603:10b6:4:b5::10) authentication-results: spf=none (sender IP is ) smtp.mailfrom=Babu.Moger@amd.com; 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DIR:OUT; SFP:1101; SCL:1; SRVR:DM5PR12MB1145; H:DM5PR12MB2471.namprd12.prod.outlook.com; FPR:; SPF:None; LANG:en; PTR:InfoNoRecords; A:1; MX:1; received-spf: None (protection.outlook.com: amd.com does not designate permitted sender hosts) x-ms-exchange-senderadcheck: 1 x-microsoft-antispam-message-info: m2tiSjboBFbv3l0lFPUCa/vb4cUjZpuoaPFUwMPciTyb79LhXzDrYHfDTLCK/WIyEgyk8r3c78XzNGPr4jvdRy8OKCtKkGExVruvh7M1//4Xzvyj27zbgu+CA+fAhm0YsMVfdzQ/+ZxoEVAFQuJDxZLOPqUsHgD5fsymfJWShiXmMWQ7Uz40xxOQVvTHqw2CL8tN3Gl52DRelDeJ8B8ZPaOxLMzolN+YPrD2zxqWzd3OLRRMkf8fW+UzL6LrDKEWKbDESne7DKb5nQolX/4tzqJGdj5ImMcPGRuh5PQFXeg/zTVhBoPSvHeu7DrECTgGbk0QWiqlv2mbQahO/tTfByuChICN6GBNsptXsrki18Ynn1MGI51ZmG8N+ykTUIPQElrzu3y6xt/w7QpSg2WCOd2nOqGkrzhxcwRW946hDUk= Content-ID: MIME-Version: 1.0 X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-Network-Message-Id: 3b0ad94e-efe7-46c0-b1cc-08d732fe22cb X-MS-Exchange-CrossTenant-originalarrivaltime: 06 Sep 2019 19:12:18.4350 (UTC) X-MS-Exchange-CrossTenant-fromentityheader: Hosted X-MS-Exchange-CrossTenant-id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-mailboxtype: HOSTED X-MS-Exchange-CrossTenant-userprincipalname: WsiGtlpk94F3QX445J1WKikjCVLFB1FVDZV0fY+0Q0Yi/tHto8cIM0K5kuqrwqwH X-MS-Exchange-Transport-CrossTenantHeadersStamped: DM5PR12MB1145 X-detected-operating-system: by eggs.gnu.org: Windows 7 or 8 [fuzzy] X-Received-From: 2a01:111:f400:fe4d::610 Subject: [Qemu-devel] [RFC 2 PATCH 06/16] hw/core: Add core complex id in X86CPU topology X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: "qemu-devel@nongnu.org" Errors-To: qemu-devel-bounces+patchwork-qemu-devel=patchwork.kernel.org@nongnu.org Sender: "Qemu-devel" Introduce cpu core complex id(ccx_id) in x86CPU topology. Each CCX can have upto 4 cores and share same L3 cache. This information is required to build the topology in new apyc mode. Signed-off-by: Babu Moger --- hw/core/machine-hmp-cmds.c | 3 +++ hw/core/machine.c | 13 +++++++++++++ hw/i386/pc.c | 10 ++++++++++ include/hw/i386/topology.h | 1 + qapi/machine.json | 4 +++- target/i386/cpu.c | 2 ++ target/i386/cpu.h | 1 + 7 files changed, 33 insertions(+), 1 deletion(-) diff --git a/hw/core/machine-hmp-cmds.c b/hw/core/machine-hmp-cmds.c index 1f66bda346..6c534779af 100644 --- a/hw/core/machine-hmp-cmds.c +++ b/hw/core/machine-hmp-cmds.c @@ -89,6 +89,9 @@ void hmp_hotpluggable_cpus(Monitor *mon, const QDict *qdict) if (c->has_die_id) { monitor_printf(mon, " die-id: \"%" PRIu64 "\"\n", c->die_id); } + if (c->has_ccx_id) { + monitor_printf(mon, " ccx-id: \"%" PRIu64 "\"\n", c->ccx_id); + } if (c->has_core_id) { monitor_printf(mon, " core-id: \"%" PRIu64 "\"\n", c->core_id); } diff --git a/hw/core/machine.c b/hw/core/machine.c index 4034b7e903..9a8586cf30 100644 --- a/hw/core/machine.c +++ b/hw/core/machine.c @@ -694,6 +694,11 @@ void machine_set_cpu_numa_node(MachineState *machine, return; } + if (props->has_ccx_id && !slot->props.has_ccx_id) { + error_setg(errp, "ccx-id is not supported"); + return; + } + /* skip slots with explicit mismatch */ if (props->has_thread_id && props->thread_id != slot->props.thread_id) { continue; @@ -707,6 +712,10 @@ void machine_set_cpu_numa_node(MachineState *machine, continue; } + if (props->has_ccx_id && props->ccx_id != slot->props.ccx_id) { + continue; + } + if (props->has_socket_id && props->socket_id != slot->props.socket_id) { continue; } @@ -1041,6 +1050,10 @@ static char *cpu_slot_to_string(const CPUArchId *cpu) if (cpu->props.has_die_id) { g_string_append_printf(s, "die-id: %"PRId64, cpu->props.die_id); } + + if (cpu->props.has_ccx_id) { + g_string_append_printf(s, "ccx-id: %"PRId64, cpu->props.ccx_id); + } if (cpu->props.has_core_id) { if (s->len) { g_string_append_printf(s, ", "); diff --git a/hw/i386/pc.c b/hw/i386/pc.c index 9e1c3f9f57..f71389ad9f 100644 --- a/hw/i386/pc.c +++ b/hw/i386/pc.c @@ -2444,6 +2444,7 @@ static void pc_cpu_pre_plug(HotplugHandler *hotplug_dev, topo_ids.pkg_id = cpu->socket_id; topo_ids.die_id = cpu->die_id; + topo_ids.ccx_id = cpu->ccx_id; topo_ids.core_id = cpu->core_id; topo_ids.smt_id = cpu->thread_id; cpu->apic_id = apicid_from_topo_ids(&topo_info, &topo_ids); @@ -2489,6 +2490,13 @@ static void pc_cpu_pre_plug(HotplugHandler *hotplug_dev, } cpu->die_id = topo_ids.die_id; + if (cpu->ccx_id != -1 && cpu->ccx_id != topo_ids.ccx_id) { + error_setg(errp, "property ccx-id: %u doesn't match set apic-id:" + " 0x%x (ccx-id: %u)", cpu->ccx_id, cpu->apic_id, topo_ids.ccx_id); + return; + } + cpu->ccx_id = topo_ids.ccx_id; + if (cpu->core_id != -1 && cpu->core_id != topo_ids.core_id) { error_setg(errp, "property core-id: %u doesn't match set apic-id:" " 0x%x (core-id: %u)", cpu->core_id, cpu->apic_id, topo_ids.core_id); @@ -2896,6 +2904,8 @@ static const CPUArchIdList *pc_possible_cpu_arch_ids(MachineState *ms) ms->possible_cpus->cpus[i].props.socket_id = topo_ids.pkg_id; ms->possible_cpus->cpus[i].props.has_die_id = true; ms->possible_cpus->cpus[i].props.die_id = topo_ids.die_id; + ms->possible_cpus->cpus[i].props.has_ccx_id = true; + ms->possible_cpus->cpus[i].props.ccx_id = topo_ids.ccx_id; ms->possible_cpus->cpus[i].props.has_core_id = true; ms->possible_cpus->cpus[i].props.core_id = topo_ids.core_id; ms->possible_cpus->cpus[i].props.has_thread_id = true; diff --git a/include/hw/i386/topology.h b/include/hw/i386/topology.h index fb10863a66..5a61d53f05 100644 --- a/include/hw/i386/topology.h +++ b/include/hw/i386/topology.h @@ -170,6 +170,7 @@ static inline void x86_topo_ids_from_apicid(apic_id_t apicid, (apicid >> apicid_die_offset(nr_cores, nr_threads)) & ~(0xFFFFFFFFUL << apicid_die_width(nr_dies)); topo_ids->pkg_id = apicid >> apicid_pkg_offset(nr_dies, nr_cores, nr_threads); + topo_ids->ccx_id = 0; } /* Make APIC ID for the CPU 'cpu_index' diff --git a/qapi/machine.json b/qapi/machine.json index 6db8a7e2ec..bb7627e698 100644 --- a/qapi/machine.json +++ b/qapi/machine.json @@ -597,9 +597,10 @@ # @node-id: NUMA node ID the CPU belongs to # @socket-id: socket number within node/board the CPU belongs to # @die-id: die number within node/board the CPU belongs to (Since 4.1) +# @ccx-id: core complex number within node/board the CPU belongs to (Since 4.1) # @core-id: core number within die the CPU belongs to# @thread-id: thread number within core the CPU belongs to # -# Note: currently there are 5 properties that could be present +# Note: currently there are 6 properties that could be present # but management should be prepared to pass through other # properties with device_add command to allow for future # interface extension. This also requires the filed names to be kept in @@ -611,6 +612,7 @@ 'data': { '*node-id': 'int', '*socket-id': 'int', '*die-id': 'int', + '*ccx-id': 'int', '*core-id': 'int', '*thread-id': 'int' } diff --git a/target/i386/cpu.c b/target/i386/cpu.c index 6d7f9b6b8b..ca02bc21ec 100644 --- a/target/i386/cpu.c +++ b/target/i386/cpu.c @@ -5811,12 +5811,14 @@ static Property x86_cpu_properties[] = { DEFINE_PROP_INT32("thread-id", X86CPU, thread_id, 0), DEFINE_PROP_INT32("core-id", X86CPU, core_id, 0), DEFINE_PROP_INT32("die-id", X86CPU, die_id, 0), + DEFINE_PROP_INT32("ccx-id", X86CPU, ccx_id, 0), DEFINE_PROP_INT32("socket-id", X86CPU, socket_id, 0), #else DEFINE_PROP_UINT32("apic-id", X86CPU, apic_id, UNASSIGNED_APIC_ID), DEFINE_PROP_INT32("thread-id", X86CPU, thread_id, -1), DEFINE_PROP_INT32("core-id", X86CPU, core_id, -1), DEFINE_PROP_INT32("die-id", X86CPU, die_id, -1), + DEFINE_PROP_INT32("ccx-id", X86CPU, ccx_id, -1), DEFINE_PROP_INT32("socket-id", X86CPU, socket_id, -1), #endif DEFINE_PROP_INT32("node-id", X86CPU, node_id, CPU_UNSET_NUMA_NODE_ID), diff --git a/target/i386/cpu.h b/target/i386/cpu.h index 8b3dc5533e..db940cdb2a 100644 --- a/target/i386/cpu.h +++ b/target/i386/cpu.h @@ -1508,6 +1508,7 @@ struct X86CPU { int32_t node_id; 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Fri, 6 Sep 2019 19:12:25 +0000 From: "Moger, Babu" To: ssg.sos.staff , "ehabkost@redhat.com" , "marcel.apfelbaum@gmail.com" , "mst@redhat.com" , "pbonzini@redhat.com" , "rth@twiddle.net" , "eblake@redhat.com" , "armbru@redhat.com" , "imammedo@redhat.com" Thread-Topic: [RFC 2 PATCH 07/16] hw/386: Add new epyc mode topology decoding functions Thread-Index: AQHVZOcEityrOa9ypkyXmr/sF3Gefg== Date: Fri, 6 Sep 2019 19:12:25 +0000 Message-ID: <156779714362.21957.2682347975717100335.stgit@localhost.localdomain> References: <156779689013.21957.1631551572950676212.stgit@localhost.localdomain> In-Reply-To: <156779689013.21957.1631551572950676212.stgit@localhost.localdomain> Accept-Language: en-US Content-Language: en-US X-MS-Has-Attach: X-MS-TNEF-Correlator: x-clientproxiedby: SN4PR0601CA0004.namprd06.prod.outlook.com (2603:10b6:803:2f::14) To DM5PR12MB2471.namprd12.prod.outlook.com (2603:10b6:4:b5::10) authentication-results: spf=none (sender IP is ) smtp.mailfrom=Babu.Moger@amd.com; x-ms-exchange-messagesentrepresentingtype: 1 x-originating-ip: [165.204.78.1] x-ms-publictraffictype: Email x-ms-office365-filtering-correlation-id: ff7bec2b-4285-43ab-bc84-08d732fe26c2 x-ms-office365-filtering-ht: Tenant x-microsoft-antispam: BCL:0; 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DIR:OUT; SFP:1101; SCL:1; SRVR:DM5PR12MB1179; H:DM5PR12MB2471.namprd12.prod.outlook.com; FPR:; SPF:None; LANG:en; PTR:InfoNoRecords; MX:1; A:1; received-spf: None (protection.outlook.com: amd.com does not designate permitted sender hosts) x-ms-exchange-senderadcheck: 1 x-microsoft-antispam-message-info: Tfq2H2jLhZ01g6EHT0dOPv61CPb55dDzSMN+KuMEVPOj4nRn6Rv9nAmjtochp5eRe+et5oCbtwIMMIdCF7q3Vo8aOqE7vw0eareFxsWqZAzyekliUL0/KurvO/mzQiniqjHwjRyotXplRHiU3vp5LNZSQ7L0Pr+eE5sQ4NZwidpqLaaJtAK6LMI33+skwSTL9mSk1qmtW9CbPGNDaQ+eaOThelIiWYanTWlVdX9SwITy54P4IHVeUEBPh14hQY8kIpzvgxITBjZeLDF2HvwHyfelM0xBdsgpoT/AFu3YgRMuUrHrCnKWu2sZjQ1EyT0tAngTuBZM+bgpONZmFMAbsKRQTn/2V7shajMXEfrU23ewWBfUxAwuGh0XzKcI4Eep20cUKAqHJxfQNxXF6gP54hB0Qb4VEOKEilNhnP8aPR0= Content-ID: MIME-Version: 1.0 X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-Network-Message-Id: ff7bec2b-4285-43ab-bc84-08d732fe26c2 X-MS-Exchange-CrossTenant-originalarrivaltime: 06 Sep 2019 19:12:25.1411 (UTC) X-MS-Exchange-CrossTenant-fromentityheader: Hosted X-MS-Exchange-CrossTenant-id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-mailboxtype: HOSTED X-MS-Exchange-CrossTenant-userprincipalname: gENzf0u0WsQ66HBiYHdb3LA0uHtvsUOYvOugkGmxtzSqQ2yLCRcUx1PgFQZETd/5 X-MS-Exchange-Transport-CrossTenantHeadersStamped: DM5PR12MB1179 X-detected-operating-system: by eggs.gnu.org: Windows 7 or 8 [fuzzy] X-Received-From: 40.107.82.50 Subject: [Qemu-devel] [RFC 2 PATCH 07/16] hw/386: Add new epyc mode topology decoding functions X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: "qemu-devel@nongnu.org" Errors-To: qemu-devel-bounces+patchwork-qemu-devel=patchwork.kernel.org@nongnu.org Sender: "Qemu-devel" These functions add support for building new epyc mode topology given smp details like numa nodes, cores, threads and sockets. Subsequent patches will use these functions to build the topology. The topology details are available in Processor Programming Reference (PPR) for AMD Family 17h Model 01h, Revision B1 Processors. It is available at https://www.amd.com/en/support/tech-docs Signed-off-by: Babu Moger --- include/hw/i386/topology.h | 174 ++++++++++++++++++++++++++++++++++++++++++++ 1 file changed, 174 insertions(+) diff --git a/include/hw/i386/topology.h b/include/hw/i386/topology.h index 5a61d53f05..6fd4184f07 100644 --- a/include/hw/i386/topology.h +++ b/include/hw/i386/topology.h @@ -62,6 +62,22 @@ typedef struct X86CPUTopoInfo { unsigned nr_threads; } X86CPUTopoInfo; +/* + * Definitions used for building CPUID Leaf 0x8000001D and 0x8000001E + * Please refer to the AMD64 Architecture Programmer’s Manual Volume 3. + * Define the constants to build the cpu topology. Right now, TOPOEXT + * feature is enabled only on EPYC. So, these constants are based on + * EPYC supported configurations. We may need to handle the cases if + * these values change in future. + */ + +/* Maximum core complexes in a node */ +#define MAX_CCX 2 +/* Maximum cores in a core complex */ +#define MAX_CORES_IN_CCX 4 +/* Maximum cores in a node */ +#define MAX_CORES_IN_NODE 8 + /* Return the bit width needed for 'count' IDs */ static unsigned apicid_bitwidth_for_count(unsigned count) @@ -116,6 +132,164 @@ static inline unsigned apicid_pkg_offset(unsigned nr_dies, apicid_die_width(nr_dies); } +/* Bit offset of the CCX_ID field */ +static inline unsigned apicid_ccx_offset(unsigned nr_cores, + unsigned nr_threads) +{ + return apicid_core_offset(nr_threads) + + apicid_core_width(nr_cores); +} + +/* Bit width of the Die_ID field */ +static inline unsigned apicid_ccx_width(unsigned nr_ccxs) +{ + return apicid_bitwidth_for_count(nr_ccxs); +} + +/* Bit offset of the node_id field */ +static inline unsigned apicid_node_offset(unsigned nr_ccxs, + unsigned nr_cores, + unsigned nr_threads) +{ + return apicid_ccx_offset(nr_cores, nr_threads) + + apicid_ccx_width(nr_ccxs); +} + +/* Bit width of the node_id field */ +static inline unsigned apicid_node_width(unsigned nr_nodes) +{ + return apicid_bitwidth_for_count(nr_nodes); +} + +/* Bit offset of the node_id field */ +static inline unsigned apicid_pkg_offset_epyc(unsigned nr_nodes, + unsigned nr_ccxs, + unsigned nr_cores, + unsigned nr_threads) +{ + return apicid_node_offset(nr_ccxs, nr_cores, nr_threads) + + apicid_node_width(nr_nodes); +} + +/* + * Figure out the number of nodes required to build this config. + * Max cores in a nodes is 8 + */ +static inline int nodes_in_pkg(X86CPUTopoInfo *topo_info) +{ + /* + * Create a config with user given (nr_nodes > 1) numa node config, + * else go with a standard configuration + */ + if (topo_info->numa_nodes > 1) { + return DIV_ROUND_UP(topo_info->numa_nodes, topo_info->nr_sockets); + } else { + return DIV_ROUND_UP(topo_info->nr_cores, MAX_CORES_IN_NODE); + } +} + +/* + * Decide the number of cores in a core complex with the given nr_cores using + * following set constants MAX_CCX, MAX_CORES_IN_CCX, MAX_CORES_IN_DIE and + * MAX_NODES_PER_SOCKET. Maintain symmetry as much as possible + * L3 cache is shared across all cores in a core complex. So, this will also + * tell us how many cores are sharing the L3 cache. + */ +static inline int cores_in_ccx(X86CPUTopoInfo *topo_info) +{ + int nodes; + + /* Get the number of nodes required to build this config */ + nodes = nodes_in_pkg(topo_info); + + /* + * Divide the cores accros all the core complexes + * Return rounded up value + */ + return DIV_ROUND_UP(topo_info->nr_cores, nodes * MAX_CCX); +} + +/* + * Make APIC ID for the CPU based on Pkg_ID, Core_ID, SMT_ID + * + * The caller must make sure core_id < nr_cores and smt_id < nr_threads. + */ +static inline apic_id_t x86_apicid_from_topo_ids_epyc(X86CPUTopoInfo *topo_info, + const X86CPUTopoIDs *topo_ids) +{ + unsigned nr_ccxs = MAX_CCX; + unsigned nr_nodes = nodes_in_pkg(topo_info); + unsigned nr_cores = MAX_CORES_IN_CCX; + unsigned nr_threads = topo_info->nr_threads; + + return (topo_ids->pkg_id << apicid_pkg_offset_epyc(nr_nodes, nr_ccxs, + nr_cores, nr_threads)) | + (topo_ids->node_id << apicid_node_offset(nr_ccxs, nr_cores, + nr_threads)) | + (topo_ids->ccx_id << apicid_ccx_offset(nr_cores, nr_threads)) | + (topo_ids->core_id << apicid_core_offset(nr_threads)) | + topo_ids->smt_id; +} + +static inline void x86_topo_ids_from_idx_epyc(X86CPUTopoInfo *topo_info, + unsigned cpu_index, + X86CPUTopoIDs *topo_ids) +{ + unsigned nr_cores = topo_info->nr_cores; + unsigned nr_threads = topo_info->nr_threads; + unsigned core_index = cpu_index / nr_threads % nr_cores; + unsigned ccx_cores = cores_in_ccx(topo_info); + + topo_ids->smt_id = cpu_index % nr_threads; + topo_ids->core_id = core_index % ccx_cores; /* core id inside the ccx */ + topo_ids->ccx_id = (core_index % (ccx_cores * MAX_CCX)) / ccx_cores; + topo_ids->node_id = core_index / (ccx_cores * MAX_CCX); + topo_ids->pkg_id = cpu_index / (nr_cores * nr_threads); +} + +/* + * Calculate thread/core/package IDs for a specific topology, + * based on APIC ID + */ +static inline void x86_topo_ids_from_apicid_epyc(apic_id_t apicid, + X86CPUTopoInfo *topo_info, + X86CPUTopoIDs *topo_ids) +{ + unsigned nr_nodes = nodes_in_pkg(topo_info); + unsigned nr_cores = MAX_CORES_IN_CCX; + unsigned nr_threads = topo_info->nr_threads; + unsigned nr_ccxs = MAX_CCX; + + topo_ids->smt_id = apicid & + ~(0xFFFFFFFFUL << apicid_smt_width(nr_threads)); + + topo_ids->core_id = (apicid >> apicid_core_offset(nr_threads)) & + ~(0xFFFFFFFFUL << apicid_core_width(nr_cores)); + + topo_ids->ccx_id = (apicid >> apicid_ccx_offset(nr_cores, nr_threads)) & + ~(0xFFFFFFFFUL << apicid_ccx_width(nr_ccxs)); + + topo_ids->node_id = (apicid >> apicid_node_offset(nr_ccxs, nr_cores, + nr_threads)) & + ~(0xFFFFFFFFUL << apicid_node_width(nr_nodes)); + + topo_ids->pkg_id = apicid >> apicid_pkg_offset_epyc(nr_nodes, nr_ccxs, + nr_cores, nr_threads); +} + +/* + * Make APIC ID for the CPU 'cpu_index' + * + * 'cpu_index' is a sequential, contiguous ID for the CPU. + */ +static inline apic_id_t x86_apicid_from_cpu_idx_epyc(X86CPUTopoInfo *topo_info, + unsigned cpu_index) +{ + X86CPUTopoIDs topo_ids; + x86_topo_ids_from_idx_epyc(topo_info, cpu_index, &topo_ids); + return x86_apicid_from_topo_ids_epyc(topo_info, &topo_ids); +} + /* Make APIC ID for the CPU based on Pkg_ID, Core_ID, SMT_ID * * The caller must make sure core_id < nr_cores and smt_id < nr_threads. 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Fri, 6 Sep 2019 19:12:33 +0000 From: "Moger, Babu" To: ssg.sos.staff , "ehabkost@redhat.com" , "marcel.apfelbaum@gmail.com" , "mst@redhat.com" , "pbonzini@redhat.com" , "rth@twiddle.net" , "eblake@redhat.com" , "armbru@redhat.com" , "imammedo@redhat.com" Thread-Topic: [RFC 2 PATCH 08/16] i386: Cleanup and use the new epyc mode topology functions Thread-Index: AQHVZOcJUr5O2hUIukO4Iv4t3TEIVA== Date: Fri, 6 Sep 2019 19:12:33 +0000 Message-ID: <156779715031.21957.17374671669134234845.stgit@localhost.localdomain> References: <156779689013.21957.1631551572950676212.stgit@localhost.localdomain> In-Reply-To: <156779689013.21957.1631551572950676212.stgit@localhost.localdomain> Accept-Language: en-US Content-Language: en-US X-MS-Has-Attach: X-MS-TNEF-Correlator: x-clientproxiedby: SN4PR0201CA0043.namprd02.prod.outlook.com (2603:10b6:803:2e::29) To DM5PR12MB2471.namprd12.prod.outlook.com (2603:10b6:4:b5::10) authentication-results: spf=none (sender IP is ) smtp.mailfrom=Babu.Moger@amd.com; x-ms-exchange-messagesentrepresentingtype: 1 x-originating-ip: [165.204.78.1] x-ms-publictraffictype: Email x-ms-office365-filtering-correlation-id: 82f0a3e5-b343-4ba6-0a78-08d732fe2ad9 x-ms-office365-filtering-ht: Tenant x-microsoft-antispam: BCL:0; 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Signed-off-by: Babu Moger --- target/i386/cpu.c | 171 +++++++++++++++-------------------------------------- 1 file changed, 48 insertions(+), 123 deletions(-) diff --git a/target/i386/cpu.c b/target/i386/cpu.c index ca02bc21ec..f25491a029 100644 --- a/target/i386/cpu.c +++ b/target/i386/cpu.c @@ -28,6 +28,7 @@ #include "sysemu/kvm.h" #include "sysemu/hvf.h" #include "sysemu/cpus.h" +#include "sysemu/numa.h" #include "kvm_i386.h" #include "sev_i386.h" @@ -338,67 +339,19 @@ static void encode_cache_cpuid80000006(CPUCacheInfo *l2, } } -/* - * Definitions used for building CPUID Leaf 0x8000001D and 0x8000001E - * Please refer to the AMD64 Architecture Programmer’s Manual Volume 3. - * Define the constants to build the cpu topology. Right now, TOPOEXT - * feature is enabled only on EPYC. So, these constants are based on - * EPYC supported configurations. We may need to handle the cases if - * these values change in future. - */ -/* Maximum core complexes in a node */ -#define MAX_CCX 2 -/* Maximum cores in a core complex */ -#define MAX_CORES_IN_CCX 4 -/* Maximum cores in a node */ -#define MAX_CORES_IN_NODE 8 -/* Maximum nodes in a socket */ -#define MAX_NODES_PER_SOCKET 4 - -/* - * Figure out the number of nodes required to build this config. - * Max cores in a node is 8 - */ -static int nodes_in_socket(int nr_cores) -{ - int nodes; - - nodes = DIV_ROUND_UP(nr_cores, MAX_CORES_IN_NODE); - - /* Hardware does not support config with 3 nodes, return 4 in that case */ - return (nodes == 3) ? 4 : nodes; -} - -/* - * Decide the number of cores in a core complex with the given nr_cores using - * following set constants MAX_CCX, MAX_CORES_IN_CCX, MAX_CORES_IN_NODE and - * MAX_NODES_PER_SOCKET. Maintain symmetry as much as possible - * L3 cache is shared across all cores in a core complex. So, this will also - * tell us how many cores are sharing the L3 cache. - */ -static int cores_in_core_complex(int nr_cores) -{ - int nodes; - - /* Check if we can fit all the cores in one core complex */ - if (nr_cores <= MAX_CORES_IN_CCX) { - return nr_cores; - } - /* Get the number of nodes required to build this config */ - nodes = nodes_in_socket(nr_cores); - - /* - * Divide the cores accros all the core complexes - * Return rounded up value - */ - return DIV_ROUND_UP(nr_cores, nodes * MAX_CCX); -} - /* Encode cache info for CPUID[8000001D] */ -static void encode_cache_cpuid8000001d(CPUCacheInfo *cache, CPUState *cs, - uint32_t *eax, uint32_t *ebx, - uint32_t *ecx, uint32_t *edx) +static void encode_cache_cpuid8000001d(CPUCacheInfo *cache, + uint32_t *eax, uint32_t *ebx, + uint32_t *ecx, uint32_t *edx) { + MachineState *ms = MACHINE(qdev_get_machine()); + X86CPUTopoInfo topo_info = { + .numa_nodes = nb_numa_nodes, + .nr_sockets = ms->smp.sockets, + .nr_cores = ms->smp.cores, + .nr_threads = ms->smp.threads, + }; + uint32_t l3_cores; assert(cache->size == cache->line_size * cache->associativity * cache->partitions * cache->sets); @@ -408,10 +361,10 @@ static void encode_cache_cpuid8000001d(CPUCacheInfo *cache, CPUState *cs, /* L3 is shared among multiple cores */ if (cache->level == 3) { - l3_cores = cores_in_core_complex(cs->nr_cores); - *eax |= ((l3_cores * cs->nr_threads) - 1) << 14; + l3_cores = cores_in_ccx(&topo_info); + *eax |= ((l3_cores * topo_info.nr_threads) - 1) << 14; } else { - *eax |= ((cs->nr_threads - 1) << 14); + *eax |= ((topo_info.nr_threads - 1) << 14); } assert(cache->line_size > 0); @@ -431,56 +384,28 @@ static void encode_cache_cpuid8000001d(CPUCacheInfo *cache, CPUState *cs, (cache->complex_indexing ? CACHE_COMPLEX_IDX : 0); } -/* Data structure to hold the configuration info for a given core index */ -struct core_topology { - /* core complex id of the current core index */ - int ccx_id; - /* - * Adjusted core index for this core in the topology - * This can be 0,1,2,3 with max 4 cores in a core complex - */ - int core_id; - /* Node id for this core index */ - int node_id; - /* Number of nodes in this config */ - int num_nodes; -}; - -/* - * Build the configuration closely match the EPYC hardware. Using the EPYC - * hardware configuration values (MAX_CCX, MAX_CORES_IN_CCX, MAX_CORES_IN_NODE) - * right now. This could change in future. - * nr_cores : Total number of cores in the config - * core_id : Core index of the current CPU - * topo : Data structure to hold all the config info for this core index - */ -static void build_core_topology(int nr_cores, int core_id, - struct core_topology *topo) -{ - int nodes, cores_in_ccx; - - /* First get the number of nodes required */ - nodes = nodes_in_socket(nr_cores); - - cores_in_ccx = cores_in_core_complex(nr_cores); - - topo->node_id = core_id / (cores_in_ccx * MAX_CCX); - topo->ccx_id = (core_id % (cores_in_ccx * MAX_CCX)) / cores_in_ccx; - topo->core_id = core_id % cores_in_ccx; - topo->num_nodes = nodes; -} - /* Encode cache info for CPUID[8000001E] */ -static void encode_topo_cpuid8000001e(CPUState *cs, X86CPU *cpu, - uint32_t *eax, uint32_t *ebx, - uint32_t *ecx, uint32_t *edx) +static void encode_topo_cpuid8000001e(CPUX86State *env, + uint32_t *eax, uint32_t *ebx, + uint32_t *ecx, uint32_t *edx) { - struct core_topology topo = {0}; - unsigned long nodes; - int shift; + X86CPUTopoIDs topo_ids = { 0 }; + unsigned long nodes, shift; + X86CPU *cpu = env_archcpu(env); + CPUState *cs = env_cpu(env); + MachineState *ms = MACHINE(qdev_get_machine()); + X86CPUTopoInfo topo_info = { + .numa_nodes = nb_numa_nodes, + .nr_sockets = ms->smp.sockets, + .nr_cores = ms->smp.cores, + .nr_threads = ms->smp.threads, + }; + + nodes = nodes_in_pkg(&topo_info); + x86_topo_ids_from_idx_epyc(&topo_info, cs->cpu_index, &topo_ids); - build_core_topology(cs->nr_cores, cpu->core_id, &topo); *eax = cpu->apic_id; + /* * CPUID_Fn8000001E_EBX * 31:16 Reserved @@ -496,11 +421,12 @@ static void encode_topo_cpuid8000001e(CPUState *cs, X86CPU *cpu, * 3 Core complex id * 1:0 Core id */ - if (cs->nr_threads - 1) { - *ebx = ((cs->nr_threads - 1) << 8) | (topo.node_id << 3) | - (topo.ccx_id << 2) | topo.core_id; + if (topo_info.nr_threads - 1) { + *ebx = ((topo_info.nr_threads - 1) << 8) | (topo_ids.node_id << 3) | + (topo_ids.ccx_id << 2) | topo_ids.core_id; } else { - *ebx = (topo.node_id << 4) | (topo.ccx_id << 3) | topo.core_id; + *ebx = (topo_ids.node_id << 4) | (topo_ids.ccx_id << 3) | + topo_ids.core_id; } /* * CPUID_Fn8000001E_ECX @@ -510,9 +436,8 @@ static void encode_topo_cpuid8000001e(CPUState *cs, X86CPU *cpu, * 2 Socket id * 1:0 Node id */ - if (topo.num_nodes <= 4) { - *ecx = ((topo.num_nodes - 1) << 8) | (cpu->socket_id << 2) | - topo.node_id; + if (nodes <= 4) { + *ecx = ((nodes - 1) << 8) | (topo_ids.pkg_id << 2) | topo_ids.node_id; } else { /* * Node id fix up. Actual hardware supports up to 4 nodes. But with @@ -527,12 +452,12 @@ static void encode_topo_cpuid8000001e(CPUState *cs, X86CPU *cpu, * number of nodes. find_last_bit returns last set bit(0 based). Left * shift(+1) the socket id to represent all the nodes. */ - nodes = topo.num_nodes - 1; + nodes = nodes - 1; shift = find_last_bit(&nodes, 8); - *ecx = ((topo.num_nodes - 1) << 8) | (cpu->socket_id << (shift + 1)) | - topo.node_id; + *ecx = (nodes << 8) | (topo_ids.pkg_id << (shift + 1)) | topo_ids.node_id; } *edx = 0; + } /* @@ -4580,19 +4505,19 @@ void cpu_x86_cpuid(CPUX86State *env, uint32_t index, uint32_t count, } switch (count) { case 0: /* L1 dcache info */ - encode_cache_cpuid8000001d(env->cache_info_amd.l1d_cache, cs, + encode_cache_cpuid8000001d(env->cache_info_amd.l1d_cache, eax, ebx, ecx, edx); break; case 1: /* L1 icache info */ - encode_cache_cpuid8000001d(env->cache_info_amd.l1i_cache, cs, + encode_cache_cpuid8000001d(env->cache_info_amd.l1i_cache, eax, ebx, ecx, edx); break; case 2: /* L2 cache info */ - encode_cache_cpuid8000001d(env->cache_info_amd.l2_cache, cs, + encode_cache_cpuid8000001d(env->cache_info_amd.l2_cache, eax, ebx, ecx, edx); break; case 3: /* L3 cache info */ - encode_cache_cpuid8000001d(env->cache_info_amd.l3_cache, cs, + encode_cache_cpuid8000001d(env->cache_info_amd.l3_cache, eax, ebx, ecx, edx); break; default: /* end of info */ @@ -4602,7 +4527,7 @@ void cpu_x86_cpuid(CPUX86State *env, uint32_t index, uint32_t count, break; case 0x8000001E: assert(cpu->core_id <= 255); - encode_topo_cpuid8000001e(cs, cpu, + encode_topo_cpuid8000001e(env, eax, ebx, ecx, edx); break; case 0xC0000000: From patchwork Fri Sep 6 19:12:40 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Babu Moger X-Patchwork-Id: 11135869 Return-Path: Received: from mail.kernel.org (pdx-korg-mail-1.web.codeaurora.org [172.30.200.123]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id BA27815E6 for ; Fri, 6 Sep 2019 19:20:14 +0000 (UTC) Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id 90AB32070C for ; Fri, 6 Sep 2019 19:20:12 +0000 (UTC) Authentication-Results: mail.kernel.org; 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Fri, 6 Sep 2019 19:12:40 +0000 From: "Moger, Babu" To: ssg.sos.staff , "ehabkost@redhat.com" , "marcel.apfelbaum@gmail.com" , "mst@redhat.com" , "pbonzini@redhat.com" , "rth@twiddle.net" , "eblake@redhat.com" , "armbru@redhat.com" , "imammedo@redhat.com" Thread-Topic: [RFC 2 PATCH 09/16] hw/i386: Introduce initialize_topo_info function Thread-Index: AQHVZOcNbGFqs/bz/0O7j4JtAjT1Xg== Date: Fri, 6 Sep 2019 19:12:40 +0000 Message-ID: <156779715852.21957.5495116804345322435.stgit@localhost.localdomain> References: <156779689013.21957.1631551572950676212.stgit@localhost.localdomain> In-Reply-To: <156779689013.21957.1631551572950676212.stgit@localhost.localdomain> Accept-Language: en-US Content-Language: en-US X-MS-Has-Attach: X-MS-TNEF-Correlator: x-clientproxiedby: SN4PR0601CA0007.namprd06.prod.outlook.com (2603:10b6:803:2f::17) To DM5PR12MB2471.namprd12.prod.outlook.com (2603:10b6:4:b5::10) authentication-results: spf=none (sender IP is ) smtp.mailfrom=Babu.Moger@amd.com; x-ms-exchange-messagesentrepresentingtype: 1 x-originating-ip: [165.204.78.1] x-ms-publictraffictype: Email x-ms-office365-filtering-correlation-id: e05cdf22-8d6d-4824-e73a-08d732fe2fac x-ms-office365-filtering-ht: Tenant x-microsoft-antispam: BCL:0; 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No functional change. Signed-off-by: Babu Moger Reviewed-by: Eduardo Habkost --- hw/i386/pc.c | 29 +++++++++++++++++------------ 1 file changed, 17 insertions(+), 12 deletions(-) diff --git a/hw/i386/pc.c b/hw/i386/pc.c index f71389ad9f..504e1ab083 100644 --- a/hw/i386/pc.c +++ b/hw/i386/pc.c @@ -918,6 +918,17 @@ bool e820_get_entry(int idx, uint32_t type, uint64_t *address, uint64_t *length) return false; } +static inline void initialize_topo_info(X86CPUTopoInfo *topo_info, + PCMachineState *pcms, + const MachineState *ms) +{ + topo_info->nr_dies = pcms->smp_dies; + topo_info->nr_cores = ms->smp.cores; + topo_info->nr_threads = ms->smp.threads; + topo_info->nr_sockets = ms->smp.sockets; + topo_info->numa_nodes = nb_numa_nodes; +} + /* Calculates initial APIC ID for a specific CPU index * * Currently we need to be able to calculate the APIC ID from the CPU index @@ -934,9 +945,7 @@ static uint32_t x86_cpu_apic_id_from_index(PCMachineState *pcms, uint32_t correct_id; static bool warned; - topo_info.nr_dies = pcms->smp_dies; - topo_info.nr_cores = ms->smp.cores; - topo_info.nr_threads = ms->smp.threads; + initialize_topo_info(&topo_info, pcms, ms); correct_id = x86_apicid_from_cpu_idx(&topo_info, cpu_index); if (pcmc->compat_apic_id_mode) { @@ -2399,9 +2408,7 @@ static void pc_cpu_pre_plug(HotplugHandler *hotplug_dev, return; } - topo_info.nr_dies = pcms->smp_dies; - topo_info.nr_cores = smp_cores; - topo_info.nr_threads = smp_threads; + initialize_topo_info(&topo_info, pcms, ms); env->nr_dies = pcms->smp_dies; @@ -2859,9 +2866,7 @@ static int64_t pc_get_default_cpu_node_id(const MachineState *ms, int idx) PCMachineState *pcms = PC_MACHINE(ms); X86CPUTopoInfo topo_info; - topo_info.nr_dies = pcms->smp_dies; - topo_info.nr_cores = ms->smp.cores; - topo_info.nr_threads = ms->smp.threads; + initialize_topo_info(&topo_info, pcms, ms); assert(idx < ms->possible_cpus->len); x86_topo_ids_from_apicid(ms->possible_cpus->cpus[idx].arch_id, @@ -2876,9 +2881,6 @@ static const CPUArchIdList *pc_possible_cpu_arch_ids(MachineState *ms) X86CPUTopoInfo topo_info; int i; - topo_info.nr_dies = pcms->smp_dies; - topo_info.nr_cores = ms->smp.cores; - topo_info.nr_threads = ms->smp.threads; if (ms->possible_cpus) { /* @@ -2891,6 +2893,9 @@ static const CPUArchIdList *pc_possible_cpu_arch_ids(MachineState *ms) ms->possible_cpus = g_malloc0(sizeof(CPUArchIdList) + sizeof(CPUArchId) * max_cpus); + + initialize_topo_info(&topo_info, pcms, ms); + ms->possible_cpus->len = max_cpus; for (i = 0; i < ms->possible_cpus->len; i++) { X86CPUTopoIDs topo_ids; From patchwork Fri Sep 6 19:12:48 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Babu Moger X-Patchwork-Id: 11135877 Return-Path: Received: from mail.kernel.org (pdx-korg-mail-1.web.codeaurora.org [172.30.200.123]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id BEDA11398 for ; Fri, 6 Sep 2019 19:23:39 +0000 (UTC) Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id 9164E20838 for ; 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Fri, 6 Sep 2019 19:12:48 +0000 From: "Moger, Babu" To: ssg.sos.staff , "ehabkost@redhat.com" , "marcel.apfelbaum@gmail.com" , "mst@redhat.com" , "pbonzini@redhat.com" , "rth@twiddle.net" , "eblake@redhat.com" , "armbru@redhat.com" , "imammedo@redhat.com" Thread-Topic: [RFC 2 PATCH 10/16] hw/i386: Introduce apicid_from_cpu_idx in PCMachineState Thread-Index: AQHVZOcSApWPC/FakEeb0y+1mx+yAw== Date: Fri, 6 Sep 2019 19:12:48 +0000 Message-ID: <156779716561.21957.7845498562538992402.stgit@localhost.localdomain> References: <156779689013.21957.1631551572950676212.stgit@localhost.localdomain> In-Reply-To: <156779689013.21957.1631551572950676212.stgit@localhost.localdomain> Accept-Language: en-US Content-Language: en-US X-MS-Has-Attach: X-MS-TNEF-Correlator: x-clientproxiedby: SN4PR0601CA0020.namprd06.prod.outlook.com (2603:10b6:803:2f::30) To DM5PR12MB2471.namprd12.prod.outlook.com (2603:10b6:4:b5::10) authentication-results: spf=none (sender IP is ) smtp.mailfrom=Babu.Moger@amd.com; x-ms-exchange-messagesentrepresentingtype: 1 x-originating-ip: [165.204.78.1] x-ms-publictraffictype: Email x-ms-office365-filtering-correlation-id: b079fc1a-0f2b-4734-367d-08d732fe33ee x-ms-office365-filtering-ht: Tenant x-microsoft-antispam: BCL:0; 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DIR:OUT; SFP:1101; SCL:1; SRVR:DM5PR12MB1145; H:DM5PR12MB2471.namprd12.prod.outlook.com; FPR:; SPF:None; LANG:en; PTR:InfoNoRecords; A:1; MX:1; received-spf: None (protection.outlook.com: amd.com does not designate permitted sender hosts) x-ms-exchange-senderadcheck: 1 x-microsoft-antispam-message-info: 2qKJHO0Or4hk7upgUBqQkr1SVP9IuLgjBOsdujBhI4PTynTNUs4weEWsWwga8tudzvypN7rlOn7iW1/W7g4gUACTBIombwaVepDDwUyqobBTU9GMNKiSMSyF8CTokR9y3Kv6UQLDKtKMzbM3/QtSnqB6wXwdoGDIqDCuePca687TL8vxuZGN+sb0E8JlN5s2EDvyj0SESAg01WKNwneZR5gftXW5Gvw56FdKPS6T9zj/jPbRpxWKW7NNycmPs9KvVAY4ILk7aoo7+L8r34n4x+bn+XVumcjidYDZJG2il+PvRThIoDDHcPncyCRBaHUQLxl96VGWuV5jP1DQLiAH5U5duOZrCPWarWxieKTJ3x/8lZxlg81bk+MEVMqeASQB4TO6hCZLqWZ+ttPYc6777tRSSYslYk2p0xdvXlob2r8= Content-ID: <2205F9627BE0F9409A6F5DEF4D240172@namprd12.prod.outlook.com> MIME-Version: 1.0 X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-Network-Message-Id: b079fc1a-0f2b-4734-367d-08d732fe33ee X-MS-Exchange-CrossTenant-originalarrivaltime: 06 Sep 2019 19:12:48.4128 (UTC) X-MS-Exchange-CrossTenant-fromentityheader: Hosted X-MS-Exchange-CrossTenant-id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-mailboxtype: HOSTED X-MS-Exchange-CrossTenant-userprincipalname: HjFmlwqHx1wgfSGSTPmPHSweZdBxRYPzs15oFh9SsQd08I9mUvQkKj/YZ650kNE+ X-MS-Exchange-Transport-CrossTenantHeadersStamped: DM5PR12MB1145 X-detected-operating-system: by eggs.gnu.org: Windows 7 or 8 [fuzzy] X-Received-From: 40.107.75.82 Subject: [Qemu-devel] [RFC 2 PATCH 10/16] hw/i386: Introduce apicid_from_cpu_idx in PCMachineState X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: "qemu-devel@nongnu.org" Errors-To: qemu-devel-bounces+patchwork-qemu-devel=patchwork.kernel.org@nongnu.org Sender: "Qemu-devel" Add function pointers in PCMachineState to handle apic id specific functionalities. This will be used to initialize with correct handlers based on mode selected. x86_apicid_from_cpu_idx will be default handler. Signed-off-by: Babu Moger --- hw/i386/pc.c | 5 ++++- include/hw/i386/pc.h | 4 ++++ 2 files changed, 8 insertions(+), 1 deletion(-) diff --git a/hw/i386/pc.c b/hw/i386/pc.c index 504e1ab083..69a6b82186 100644 --- a/hw/i386/pc.c +++ b/hw/i386/pc.c @@ -947,7 +947,7 @@ static uint32_t x86_cpu_apic_id_from_index(PCMachineState *pcms, initialize_topo_info(&topo_info, pcms, ms); - correct_id = x86_apicid_from_cpu_idx(&topo_info, cpu_index); + correct_id = pcms->apicid_from_cpu_idx(&topo_info, cpu_index); if (pcmc->compat_apic_id_mode) { if (cpu_index != correct_id && !warned && !qtest_enabled()) { error_report("APIC IDs set in compatibility mode, " @@ -2828,6 +2828,9 @@ static void pc_machine_initfn(Object *obj) pcms->pit_enabled = true; pcms->smp_dies = 1; + /* Initialize the apic id related handlers */ + pcms->apicid_from_cpu_idx = x86_apicid_from_cpu_idx; + pc_system_flash_create(pcms); } diff --git a/include/hw/i386/pc.h b/include/hw/i386/pc.h index 859b64c51d..6cefefdd57 100644 --- a/include/hw/i386/pc.h +++ b/include/hw/i386/pc.h @@ -17,6 +17,7 @@ #include "hw/mem/pc-dimm.h" #include "hw/mem/nvdimm.h" #include "hw/acpi/acpi_dev_interface.h" +#include "hw/i386/topology.h" #define HPET_INTCAP "hpet-intcap" @@ -66,6 +67,9 @@ struct PCMachineState { uint64_t numa_nodes; uint64_t *node_mem; + /* Apic id specific handlers */ + uint32_t (*apicid_from_cpu_idx)(X86CPUTopoInfo *topo_info, unsigned cpu_index); + /* Address space used by IOAPIC device. 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Fri, 6 Sep 2019 19:12:56 +0000 From: "Moger, Babu" To: ssg.sos.staff , "ehabkost@redhat.com" , "marcel.apfelbaum@gmail.com" , "mst@redhat.com" , "pbonzini@redhat.com" , "rth@twiddle.net" , "eblake@redhat.com" , "armbru@redhat.com" , "imammedo@redhat.com" Thread-Topic: [RFC 2 PATCH 11/16] Introduce-topo_ids_from_apicid-handler Thread-Index: AQHVZOcWMrF/C1DABUG5/VPpbi5v/g== Date: Fri, 6 Sep 2019 19:12:55 +0000 Message-ID: <156779717413.21957.2843856950982088519.stgit@localhost.localdomain> References: <156779689013.21957.1631551572950676212.stgit@localhost.localdomain> In-Reply-To: <156779689013.21957.1631551572950676212.stgit@localhost.localdomain> Accept-Language: en-US Content-Language: en-US X-MS-Has-Attach: X-MS-TNEF-Correlator: x-clientproxiedby: SN6PR06CA0004.namprd06.prod.outlook.com (2603:10b6:805:8e::17) To DM5PR12MB2471.namprd12.prod.outlook.com (2603:10b6:4:b5::10) authentication-results: spf=none (sender IP is ) smtp.mailfrom=Babu.Moger@amd.com; x-ms-exchange-messagesentrepresentingtype: 1 x-originating-ip: [165.204.78.1] x-ms-publictraffictype: Email x-ms-office365-filtering-correlation-id: 52c459a6-c936-484c-2a5e-08d732fe38ec x-ms-office365-filtering-ht: Tenant x-microsoft-antispam: BCL:0; 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DIR:OUT; SFP:1101; SCL:1; SRVR:DM5PR12MB1145; H:DM5PR12MB2471.namprd12.prod.outlook.com; FPR:; SPF:None; LANG:en; PTR:InfoNoRecords; A:1; MX:1; received-spf: None (protection.outlook.com: amd.com does not designate permitted sender hosts) x-ms-exchange-senderadcheck: 1 x-microsoft-antispam-message-info: kty3Ft8Kz0yM/SXq7XwHjNf4QgKNDsz3+wfT5BintZe4NWV0ArlVLiRywmrpQK3Sq8wqvJXOq5m74ad7VL6EiU34WZs3015S252AZoCre+d/vpMDBSDmSu9UG9tP5z9pDcuCROW6G5nIUjwDsTwooSJ0UwXfcMY5rwiB4+LJqigWRE+TB0ca8bzmHptVyAE56JHtDR1gPDYVlBWhXDn1ZDVi1tdGbGKxM2CpyCca/HUcoYUKWX2MX/OhyUgsY0tmWtWBcQeFqqMG+elyvgQ+pbwcG7ZHjagYI+AbLY3RfOZxsnywFH8xqC/nixe6DbFbMyRODRHEDJooE+dE9sEVvchk/Mn9M98UGXVbRf/Y4wQKDmsqOquhsQOHpaiqImqXTZPpd0MsRZ8jvLRK6WRTi25UfNwSyvkogh2kv9C14So= Content-ID: <24A7FDFEAC85D043A764D1EDE8FDB395@namprd12.prod.outlook.com> MIME-Version: 1.0 X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-Network-Message-Id: 52c459a6-c936-484c-2a5e-08d732fe38ec X-MS-Exchange-CrossTenant-originalarrivaltime: 06 Sep 2019 19:12:55.9854 (UTC) X-MS-Exchange-CrossTenant-fromentityheader: Hosted X-MS-Exchange-CrossTenant-id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-mailboxtype: HOSTED X-MS-Exchange-CrossTenant-userprincipalname: Yc5awS5aUURPfVnE7PHFWKQXPn3yZIrneLBObX67lknTY+lKcIZDeeQzCpbK4gdH X-MS-Exchange-Transport-CrossTenantHeadersStamped: DM5PR12MB1145 X-detected-operating-system: by eggs.gnu.org: Windows 7 or 8 [fuzzy] X-Received-From: 40.107.70.77 Subject: [Qemu-devel] [RFC 2 PATCH 11/16] Introduce-topo_ids_from_apicid-handler X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: "qemu-devel@nongnu.org" Errors-To: qemu-devel-bounces+patchwork-qemu-devel=patchwork.kernel.org@nongnu.org Sender: "Qemu-devel" hw/i386: Introduce topo_ids_from_apicid handler PCMachineState Add function pointer topo_ids_from_apicid in PCMachineState. Initialize with correct handler based on mode selected. x86_apicid_from_cpu_idx will be the default handler. Signed-off-by: Babu Moger --- hw/i386/pc.c | 13 +++++++------ include/hw/i386/pc.h | 2 ++ 2 files changed, 9 insertions(+), 6 deletions(-) diff --git a/hw/i386/pc.c b/hw/i386/pc.c index 69a6b82186..c88de09350 100644 --- a/hw/i386/pc.c +++ b/hw/i386/pc.c @@ -2461,7 +2461,7 @@ static void pc_cpu_pre_plug(HotplugHandler *hotplug_dev, if (!cpu_slot) { MachineState *ms = MACHINE(pcms); - x86_topo_ids_from_apicid(cpu->apic_id, &topo_info, &topo_ids); + pcms->topo_ids_from_apicid(cpu->apic_id, &topo_info, &topo_ids); error_setg(errp, "Invalid CPU [socket: %u, die: %u, core: %u, thread: %u] with" " APIC ID %" PRIu32 ", valid index range 0:%d", @@ -2482,7 +2482,7 @@ static void pc_cpu_pre_plug(HotplugHandler *hotplug_dev, /* TODO: move socket_id/core_id/thread_id checks into x86_cpu_realizefn() * once -smp refactoring is complete and there will be CPU private * CPUState::nr_cores and CPUState::nr_threads fields instead of globals */ - x86_topo_ids_from_apicid(cpu->apic_id, &topo_info, &topo_ids); + pcms->topo_ids_from_apicid(cpu->apic_id, &topo_info, &topo_ids); if (cpu->socket_id != -1 && cpu->socket_id != topo_ids.pkg_id) { error_setg(errp, "property socket-id: %u doesn't match set apic-id:" " 0x%x (socket-id: %u)", cpu->socket_id, cpu->apic_id, topo_ids.pkg_id); @@ -2830,6 +2830,7 @@ static void pc_machine_initfn(Object *obj) /* Initialize the apic id related handlers */ pcms->apicid_from_cpu_idx = x86_apicid_from_cpu_idx; + pcms->topo_ids_from_apicid = x86_topo_ids_from_apicid; pc_system_flash_create(pcms); } @@ -2872,8 +2873,8 @@ static int64_t pc_get_default_cpu_node_id(const MachineState *ms, int idx) initialize_topo_info(&topo_info, pcms, ms); assert(idx < ms->possible_cpus->len); - x86_topo_ids_from_apicid(ms->possible_cpus->cpus[idx].arch_id, - &topo_info, &topo_ids); + pcms->topo_ids_from_apicid(ms->possible_cpus->cpus[idx].arch_id, + &topo_info, &topo_ids); return topo_ids.pkg_id % nb_numa_nodes; } @@ -2906,8 +2907,8 @@ static const CPUArchIdList *pc_possible_cpu_arch_ids(MachineState *ms) ms->possible_cpus->cpus[i].type = ms->cpu_type; ms->possible_cpus->cpus[i].vcpus_count = 1; ms->possible_cpus->cpus[i].arch_id = x86_cpu_apic_id_from_index(pcms, i); - x86_topo_ids_from_apicid(ms->possible_cpus->cpus[i].arch_id, - &topo_info, &topo_ids); + pcms->topo_ids_from_apicid(ms->possible_cpus->cpus[i].arch_id, + &topo_info, &topo_ids); ms->possible_cpus->cpus[i].props.has_socket_id = true; ms->possible_cpus->cpus[i].props.socket_id = topo_ids.pkg_id; ms->possible_cpus->cpus[i].props.has_die_id = true; diff --git a/include/hw/i386/pc.h b/include/hw/i386/pc.h index 6cefefdd57..9a40f123d0 100644 --- a/include/hw/i386/pc.h +++ b/include/hw/i386/pc.h @@ -69,6 +69,8 @@ struct PCMachineState { /* Apic id specific handlers */ uint32_t (*apicid_from_cpu_idx)(X86CPUTopoInfo *topo_info, unsigned cpu_index); + void (*topo_ids_from_apicid)(apic_id_t apicid, X86CPUTopoInfo *topo_info, + X86CPUTopoIDs *topo_ids); /* Address space used by IOAPIC device. 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Fri, 6 Sep 2019 19:13:02 +0000 From: "Moger, Babu" To: ssg.sos.staff , "ehabkost@redhat.com" , "marcel.apfelbaum@gmail.com" , "mst@redhat.com" , "pbonzini@redhat.com" , "rth@twiddle.net" , "eblake@redhat.com" , "armbru@redhat.com" , "imammedo@redhat.com" Thread-Topic: [RFC 2 PATCH 12/16] hw/i386: Introduce apic_id_from_topo_ids handler in PCMachineState Thread-Index: AQHVZOcaItEosya+MEKaCAT2nutfDg== Date: Fri, 6 Sep 2019 19:13:02 +0000 Message-ID: <156779718115.21957.699621482515468870.stgit@localhost.localdomain> References: <156779689013.21957.1631551572950676212.stgit@localhost.localdomain> In-Reply-To: <156779689013.21957.1631551572950676212.stgit@localhost.localdomain> Accept-Language: en-US Content-Language: en-US X-MS-Has-Attach: X-MS-TNEF-Correlator: x-clientproxiedby: SN4PR0601CA0009.namprd06.prod.outlook.com (2603:10b6:803:2f::19) To DM5PR12MB2471.namprd12.prod.outlook.com (2603:10b6:4:b5::10) authentication-results: spf=none (sender IP is ) smtp.mailfrom=Babu.Moger@amd.com; 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DIR:OUT; SFP:1101; SCL:1; SRVR:DM5PR12MB1145; H:DM5PR12MB2471.namprd12.prod.outlook.com; FPR:; SPF:None; LANG:en; PTR:InfoNoRecords; A:1; MX:1; received-spf: None (protection.outlook.com: amd.com does not designate permitted sender hosts) x-ms-exchange-senderadcheck: 1 x-microsoft-antispam-message-info: kgSQG/Qk4jKYR/QNAy0AqByZ8ycEyWXe9GvO2qbUMc3C0mVwEgFw8Qd8EP4397uB2zwK6zPj5d6USgcjbG/eTJJuWwzuZEgx9SdTCYq7lKnnDpp2G65vxUUpv32b40YHhHR6oqucc7fw4h/5084KtJJJJrqdexNI+jIkMQd/dF/xATWsZKBhD/9Y77K6fCQXhOq/rINFd5UXXVwYjurHJXQiYckVJHIUl2/msGKoxOG1jPMnskx7qLKUGoAfu/9LlS9WxSdnKob30WMmcBqeU7oyrpPuYAH0yPzIsI5WiPVNlGTMNXEjNXfkIziLmYOpu+RLuGCuLN6jKUHlqd48CkmHENSL0z3/HUeX3OAf63dPksRRp0xoy7u2UItCR5h7WhcpC4fkuC1UYd3OIz8Q8QZyxPJGXOa9xtIoJ5TTh+k= Content-ID: <72118726988BF64CBE69A5D1E53A9C88@namprd12.prod.outlook.com> MIME-Version: 1.0 X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-Network-Message-Id: 87a6f11a-352c-4c8d-6856-08d732fe3d2c X-MS-Exchange-CrossTenant-originalarrivaltime: 06 Sep 2019 19:13:02.6886 (UTC) X-MS-Exchange-CrossTenant-fromentityheader: Hosted X-MS-Exchange-CrossTenant-id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-mailboxtype: HOSTED X-MS-Exchange-CrossTenant-userprincipalname: uNBLapWs3Pw8W2qdNj5ejbwmU7RWAbSZ1HSQxxqzwGpVzzIDxEULwB7UopaFSx/Y X-MS-Exchange-Transport-CrossTenantHeadersStamped: DM5PR12MB1145 X-detected-operating-system: by eggs.gnu.org: Windows 7 or 8 [fuzzy] X-Received-From: 2a01:111:f400:fe4d::62a Subject: [Qemu-devel] [RFC 2 PATCH 12/16] hw/i386: Introduce apic_id_from_topo_ids handler in PCMachineState X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: "qemu-devel@nongnu.org" Errors-To: qemu-devel-bounces+patchwork-qemu-devel=patchwork.kernel.org@nongnu.org Sender: "Qemu-devel" Add function pointer apic_id_from_topo_ids in PCMachineState. Initialize with correct handler based on the mode selected. Also rename the handler apicid_from_topo_ids to x86_apicid_from_topo_ids for consistency. x86_apicid_from_topo_ids will be the default handler. Signed-off-by: Babu Moger --- hw/i386/pc.c | 3 ++- include/hw/i386/pc.h | 2 ++ include/hw/i386/topology.h | 4 ++-- 3 files changed, 6 insertions(+), 3 deletions(-) diff --git a/hw/i386/pc.c b/hw/i386/pc.c index c88de09350..959bd3821b 100644 --- a/hw/i386/pc.c +++ b/hw/i386/pc.c @@ -2454,7 +2454,7 @@ static void pc_cpu_pre_plug(HotplugHandler *hotplug_dev, topo_ids.ccx_id = cpu->ccx_id; topo_ids.core_id = cpu->core_id; topo_ids.smt_id = cpu->thread_id; - cpu->apic_id = apicid_from_topo_ids(&topo_info, &topo_ids); + cpu->apic_id = pcms->apicid_from_topo_ids(&topo_info, &topo_ids); } cpu_slot = pc_find_cpu_slot(MACHINE(pcms), cpu->apic_id, &idx); @@ -2831,6 +2831,7 @@ static void pc_machine_initfn(Object *obj) /* Initialize the apic id related handlers */ pcms->apicid_from_cpu_idx = x86_apicid_from_cpu_idx; pcms->topo_ids_from_apicid = x86_topo_ids_from_apicid; + pcms->apicid_from_topo_ids = x86_apicid_from_topo_ids; pc_system_flash_create(pcms); } diff --git a/include/hw/i386/pc.h b/include/hw/i386/pc.h index 9a40f123d0..d6f1189997 100644 --- a/include/hw/i386/pc.h +++ b/include/hw/i386/pc.h @@ -71,6 +71,8 @@ struct PCMachineState { uint32_t (*apicid_from_cpu_idx)(X86CPUTopoInfo *topo_info, unsigned cpu_index); void (*topo_ids_from_apicid)(apic_id_t apicid, X86CPUTopoInfo *topo_info, X86CPUTopoIDs *topo_ids); + apic_id_t (*apicid_from_topo_ids)(X86CPUTopoInfo *topo_info, + const X86CPUTopoIDs *topo_ids); /* Address space used by IOAPIC device. All IOAPIC interrupts * will be translated to MSI messages in the address space. */ diff --git a/include/hw/i386/topology.h b/include/hw/i386/topology.h index 6fd4184f07..740e66970d 100644 --- a/include/hw/i386/topology.h +++ b/include/hw/i386/topology.h @@ -294,7 +294,7 @@ static inline apic_id_t x86_apicid_from_cpu_idx_epyc(X86CPUTopoInfo *topo_info, * * The caller must make sure core_id < nr_cores and smt_id < nr_threads. */ -static inline apic_id_t apicid_from_topo_ids(X86CPUTopoInfo *topo_info, +static inline apic_id_t x86_apicid_from_topo_ids(X86CPUTopoInfo *topo_info, const X86CPUTopoIDs *topo_ids) { unsigned nr_dies = topo_info->nr_dies; @@ -356,7 +356,7 @@ static inline apic_id_t x86_apicid_from_cpu_idx(X86CPUTopoInfo *topo_info, { X86CPUTopoIDs topo_ids; x86_topo_ids_from_idx(topo_info, cpu_index, &topo_ids); - return apicid_from_topo_ids(topo_info, &topo_ids); + return x86_apicid_from_topo_ids(topo_info, &topo_ids); } #endif /* HW_I386_TOPOLOGY_H */ From patchwork Fri Sep 6 19:13:09 2019 Content-Type: text/plain; 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Fri, 6 Sep 2019 19:13:09 +0000 Received: from DM5PR12MB2471.namprd12.prod.outlook.com ([fe80::6c7c:4b6d:f136:1bf8]) by DM5PR12MB2471.namprd12.prod.outlook.com ([fe80::6c7c:4b6d:f136:1bf8%3]) with mapi id 15.20.2220.022; Fri, 6 Sep 2019 19:13:09 +0000 From: "Moger, Babu" To: ssg.sos.staff , "ehabkost@redhat.com" , "marcel.apfelbaum@gmail.com" , "mst@redhat.com" , "pbonzini@redhat.com" , "rth@twiddle.net" , "eblake@redhat.com" , "armbru@redhat.com" , "imammedo@redhat.com" Thread-Topic: [RFC 2 PATCH 13/16] machine: Add new epyc property in PCMachineState Thread-Index: AQHVZOceIuce90DAyEeExN49RF5ewg== Date: Fri, 6 Sep 2019 19:13:09 +0000 Message-ID: <156779718791.21957.9675425538561156773.stgit@localhost.localdomain> References: <156779689013.21957.1631551572950676212.stgit@localhost.localdomain> In-Reply-To: <156779689013.21957.1631551572950676212.stgit@localhost.localdomain> Accept-Language: en-US Content-Language: en-US X-MS-Has-Attach: X-MS-TNEF-Correlator: x-clientproxiedby: SN6PR06CA0032.namprd06.prod.outlook.com (2603:10b6:805:8e::45) To DM5PR12MB2471.namprd12.prod.outlook.com (2603:10b6:4:b5::10) authentication-results: spf=none (sender IP is ) smtp.mailfrom=Babu.Moger@amd.com; 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DIR:OUT; SFP:1101; SCL:1; SRVR:DM5PR12MB1179; H:DM5PR12MB2471.namprd12.prod.outlook.com; FPR:; SPF:None; LANG:en; PTR:InfoNoRecords; MX:1; A:1; received-spf: None (protection.outlook.com: amd.com does not designate permitted sender hosts) x-ms-exchange-senderadcheck: 1 x-microsoft-antispam-message-info: ZjMoGxUnGZD2toZVCYgyQouS/3nMU4pnp2RbSAnbtzftKEwHPjoosfbiZvpwXfVrU8JoPUHCJLQTuFRHzRw7prG6TQ0nI2lxbGNahuqBrYsBztPRCLYe/2PNeSknSRCmuvQ2ArIkIHLiOJxe1i0AOw1227JOdkW5VY6QcoEyXLgSeYu2YCmIBZTnF/eGXl16ViwzeIMpgio5epZdGuu5CmLUMygMy7lr/BDf4rGOmEPjfYXw9Lo5qf2IvnQORRJjDO8wk3D5FMye1eLPABI2TKqDUDq317y7S073rm7GZespRojFiVhVsbZqoqEu28mBwiyWDleMO1LpNNv/GXKHAiK4nc/Mc50sfXURYMkeVd4AbQf1n74qUkq5Fi/vMpo4/24dnO3G3GIy+CMPDW94JkljJtb9sl6izF1XCIP/fr8= Content-ID: <709F257EA469B94A9F057026B129A31C@namprd12.prod.outlook.com> MIME-Version: 1.0 X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-Network-Message-Id: 183874bd-4453-4508-a1d3-08d732fe4131 X-MS-Exchange-CrossTenant-originalarrivaltime: 06 Sep 2019 19:13:09.4997 (UTC) X-MS-Exchange-CrossTenant-fromentityheader: Hosted X-MS-Exchange-CrossTenant-id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-mailboxtype: HOSTED X-MS-Exchange-CrossTenant-userprincipalname: DeEQMjyzcpsb2Ou9CVYnvi5dUWnh367HcEy/Scv1B5mTvZnLQhG5dp7kf7n7PcSl X-MS-Exchange-Transport-CrossTenantHeadersStamped: DM5PR12MB1179 X-detected-operating-system: by eggs.gnu.org: Windows 7 or 8 [fuzzy] X-Received-From: 2a01:111:f400:fe50::60b Subject: [Qemu-devel] [RFC 2 PATCH 13/16] machine: Add new epyc property in PCMachineState X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: "qemu-devel@nongnu.org" Errors-To: qemu-devel-bounces+patchwork-qemu-devel=patchwork.kernel.org@nongnu.org Sender: "Qemu-devel" Adds new epyc property in PCMachineState and also in MachineState. This property will be used to initialize the mode specific handlers to generate apic ids. Signed-off-by: Babu Moger --- hw/i386/pc.c | 23 +++++++++++++++++++++++ include/hw/boards.h | 2 ++ include/hw/i386/pc.h | 1 + 3 files changed, 26 insertions(+) diff --git a/hw/i386/pc.c b/hw/i386/pc.c index 959bd3821b..14760523a9 100644 --- a/hw/i386/pc.c +++ b/hw/i386/pc.c @@ -2810,6 +2810,22 @@ static void pc_machine_set_pit(Object *obj, bool value, Error **errp) pcms->pit_enabled = value; } +static bool pc_machine_get_epyc(Object *obj, Error **errp) +{ + PCMachineState *pcms = PC_MACHINE(obj); + + return pcms->epyc; +} + +static void pc_machine_set_epyc(Object *obj, bool value, Error **errp) +{ + PCMachineState *pcms = PC_MACHINE(obj); + MachineState *ms = MACHINE(pcms); + + pcms->epyc = value; + ms->epyc = value; +} + static void pc_machine_initfn(Object *obj) { PCMachineState *pcms = PC_MACHINE(obj); @@ -3015,6 +3031,13 @@ static void pc_machine_class_init(ObjectClass *oc, void *data) object_class_property_add_bool(oc, PC_MACHINE_PIT, pc_machine_get_pit, pc_machine_set_pit, &error_abort); + + object_class_property_add_bool(oc, "epyc", + pc_machine_get_epyc, pc_machine_set_epyc, &error_abort); + + object_class_property_set_description(oc, "epyc", + "Set on/off to use epyc mode", &error_abort); + } static const TypeInfo pc_machine_info = { diff --git a/include/hw/boards.h b/include/hw/boards.h index 12eb5032a5..0001d42e50 100644 --- a/include/hw/boards.h +++ b/include/hw/boards.h @@ -299,6 +299,8 @@ struct MachineState { AccelState *accelerator; CPUArchIdList *possible_cpus; CpuTopology smp; + bool epyc; + struct NVDIMMState *nvdimms_state; }; diff --git a/include/hw/i386/pc.h b/include/hw/i386/pc.h index d6f1189997..cf9e7b0045 100644 --- a/include/hw/i386/pc.h +++ b/include/hw/i386/pc.h @@ -68,6 +68,7 @@ struct PCMachineState { uint64_t *node_mem; /* Apic id specific handlers */ + bool epyc; uint32_t (*apicid_from_cpu_idx)(X86CPUTopoInfo *topo_info, unsigned cpu_index); void (*topo_ids_from_apicid)(apic_id_t apicid, X86CPUTopoInfo *topo_info, X86CPUTopoIDs *topo_ids); From patchwork Fri Sep 6 19:13:16 2019 Content-Type: text/plain; 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Fri, 6 Sep 2019 19:13:16 +0000 Received: from DM5PR12MB2471.namprd12.prod.outlook.com ([fe80::6c7c:4b6d:f136:1bf8]) by DM5PR12MB2471.namprd12.prod.outlook.com ([fe80::6c7c:4b6d:f136:1bf8%3]) with mapi id 15.20.2220.022; Fri, 6 Sep 2019 19:13:16 +0000 From: "Moger, Babu" To: ssg.sos.staff , "ehabkost@redhat.com" , "marcel.apfelbaum@gmail.com" , "mst@redhat.com" , "pbonzini@redhat.com" , "rth@twiddle.net" , "eblake@redhat.com" , "armbru@redhat.com" , "imammedo@redhat.com" Thread-Topic: [RFC 2 PATCH 14/16] hw/i386: Introduce epyc mode function handlers Thread-Index: AQHVZOciXVA3YS7qJ0mAH+PEaBeSRA== Date: Fri, 6 Sep 2019 19:13:16 +0000 Message-ID: <156779719472.21957.5262347241826039177.stgit@localhost.localdomain> References: <156779689013.21957.1631551572950676212.stgit@localhost.localdomain> In-Reply-To: <156779689013.21957.1631551572950676212.stgit@localhost.localdomain> Accept-Language: en-US Content-Language: en-US X-MS-Has-Attach: X-MS-TNEF-Correlator: x-clientproxiedby: SN4PR0601CA0021.namprd06.prod.outlook.com (2603:10b6:803:2f::31) To DM5PR12MB2471.namprd12.prod.outlook.com (2603:10b6:4:b5::10) authentication-results: spf=none (sender IP is ) smtp.mailfrom=Babu.Moger@amd.com; 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DIR:OUT; SFP:1101; SCL:1; SRVR:DM5PR12MB1179; H:DM5PR12MB2471.namprd12.prod.outlook.com; FPR:; SPF:None; LANG:en; PTR:InfoNoRecords; MX:1; A:1; received-spf: None (protection.outlook.com: amd.com does not designate permitted sender hosts) x-ms-exchange-senderadcheck: 1 x-microsoft-antispam-message-info: v9umr7Yv8E8KMzw/ga2DYDltLZGruSzMXPIycZU/lbj4S4XBPPkUhvqrc3Frp3oxdgzyFKTQucnZJPoaibSv+u9CuZuhRh8p/u2bvFMbxExnAwWtZw+D+LLbqX82O/QRwLx2NZuESSiF7dCVZsOF9LfA3cir+Q/66Tpr55Ugj++IhF2s7g2IgDy5+XyRq+lYyWHL5+dBHRxTF4pce1stBOVMf8K2FBVnvuyhqdxjRUlJoNSi1j4x1pyWGDUcyaqTqHAzndffpVf57FAnIT+6OAmPdx5RSFjiut5235LtYXVdEoS9wPcdJHeVS/2cYkUmQ855P65oTwWPbXMCBPMMTUpbSjP3wyrCheN2dDaG+EDcRnsxrKlXYDVrRNMMyatCwPHcsDoIkr2tfauRiApF7rfy4LLhXsFf6x1kQ0mYYlk= Content-ID: <501A89B664746F4DB8CD4E6AAA31D1E9@namprd12.prod.outlook.com> MIME-Version: 1.0 X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-Network-Message-Id: 42680ee2-8cea-41d0-4f38-08d732fe4549 X-MS-Exchange-CrossTenant-originalarrivaltime: 06 Sep 2019 19:13:16.3048 (UTC) X-MS-Exchange-CrossTenant-fromentityheader: Hosted X-MS-Exchange-CrossTenant-id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-mailboxtype: HOSTED X-MS-Exchange-CrossTenant-userprincipalname: f08dujvAehgPEU/7qnnMFwrJOWusgIxXxURNhEpBPjvG+H93GYtYi8RGGTVLVUyk X-MS-Exchange-Transport-CrossTenantHeadersStamped: DM5PR12MB1179 X-detected-operating-system: by eggs.gnu.org: Windows 7 or 8 [fuzzy] X-Received-From: 2a01:111:f400:fe50::62f Subject: [Qemu-devel] [RFC 2 PATCH 14/16] hw/i386: Introduce epyc mode function handlers X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: "qemu-devel@nongnu.org" Errors-To: qemu-devel-bounces+patchwork-qemu-devel=patchwork.kernel.org@nongnu.org Sender: "Qemu-devel" Introduce following handlers for new epyc mode. x86_apicid_from_cpu_idx_epyc: Generate apicid from cpu index. x86_topo_ids_from_apicid_epyc: Generate topo ids from apic id. x86_apicid_from_topo_ids_epyci: Generate apicid from topo ids. Signed-off-by: Babu Moger --- hw/i386/pc.c | 5 +++++ 1 file changed, 5 insertions(+) diff --git a/hw/i386/pc.c b/hw/i386/pc.c index 14760523a9..59c7c4d8b2 100644 --- a/hw/i386/pc.c +++ b/hw/i386/pc.c @@ -2824,6 +2824,11 @@ static void pc_machine_set_epyc(Object *obj, bool value, Error **errp) pcms->epyc = value; ms->epyc = value; + if (pcms->epyc) { + pcms->apicid_from_cpu_idx = x86_apicid_from_cpu_idx_epyc; + pcms->topo_ids_from_apicid = x86_topo_ids_from_apicid_epyc; + pcms->apicid_from_topo_ids = x86_apicid_from_topo_ids_epyc; + } } static void pc_machine_initfn(Object *obj) From patchwork Fri Sep 6 19:13:22 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Babu Moger X-Patchwork-Id: 11135909 Return-Path: Received: from mail.kernel.org (pdx-korg-mail-1.web.codeaurora.org [172.30.200.123]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id 300C81398 for ; Fri, 6 Sep 2019 19:28:08 +0000 (UTC) Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id 0730C20838 for ; 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Fri, 6 Sep 2019 19:13:22 +0000 From: "Moger, Babu" To: ssg.sos.staff , "ehabkost@redhat.com" , "marcel.apfelbaum@gmail.com" , "mst@redhat.com" , "pbonzini@redhat.com" , "rth@twiddle.net" , "eblake@redhat.com" , "armbru@redhat.com" , "imammedo@redhat.com" Thread-Topic: [RFC 2 PATCH 15/16] i386: Fix pkg_id offset for epyc mode Thread-Index: AQHVZOcmbebOiftiVUCaGUSkVpMtgg== Date: Fri, 6 Sep 2019 19:13:22 +0000 Message-ID: <156779720146.21957.9036938076017885210.stgit@localhost.localdomain> References: <156779689013.21957.1631551572950676212.stgit@localhost.localdomain> In-Reply-To: <156779689013.21957.1631551572950676212.stgit@localhost.localdomain> Accept-Language: en-US Content-Language: en-US X-MS-Has-Attach: X-MS-TNEF-Correlator: x-clientproxiedby: SN4PR0601CA0020.namprd06.prod.outlook.com (2603:10b6:803:2f::30) To DM5PR12MB2471.namprd12.prod.outlook.com (2603:10b6:4:b5::10) authentication-results: spf=none (sender IP is ) smtp.mailfrom=Babu.Moger@amd.com; x-ms-exchange-messagesentrepresentingtype: 1 x-originating-ip: [165.204.78.1] x-ms-publictraffictype: Email x-ms-office365-filtering-correlation-id: 56c4b1fe-1041-4e74-2a9f-08d732fe493b x-ms-office365-filtering-ht: Tenant x-microsoft-antispam: BCL:0; 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DIR:OUT; SFP:1101; SCL:1; SRVR:DM5PR12MB1930; H:DM5PR12MB2471.namprd12.prod.outlook.com; FPR:; SPF:None; LANG:en; PTR:InfoNoRecords; MX:1; A:1; received-spf: None (protection.outlook.com: amd.com does not designate permitted sender hosts) x-ms-exchange-senderadcheck: 1 x-microsoft-antispam-message-info: XX3W+epJzeSzFIZqPNwN2Vm5N0+PuNFSlfK5QUIlPX2J3UMjRBD5xYDY/BEebGKPnXZxdrkf3EioaanjXsPGhaOHw49pYf54640Lp9hLseSdhVhYq39H5ZljZPZ/5hiWKKhXHautA+UD6J94j5K6YQRaoGcqFrmYkuLXCWrpJtUuVxAq19JOYNOCyrlwii+HZy/+Ao32PrqME/SkWhpTfM4gEflQNlx9sAtOuPGNBXMnJhYgSg2+e2iVSDU/zjaVW0QB1q5zGlBjze9csk6LcnAeb5vgLXjoxlQ9DUJtiTgk6t6rhz1mthmcc1BNO4FrbBubzFjeubbsJoQ8fDHcebDH9k2mJNk9c/htUHvm0pOfcFH+qVhhBaDC/90jJz0PALRgxs97EQlFIyjQJEsU7VghZmmtMMYqKdfCdB7rNBM= Content-ID: <751AC802B34CAE449F8922185A98C7FF@namprd12.prod.outlook.com> MIME-Version: 1.0 X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-Network-Message-Id: 56c4b1fe-1041-4e74-2a9f-08d732fe493b X-MS-Exchange-CrossTenant-originalarrivaltime: 06 Sep 2019 19:13:22.8690 (UTC) X-MS-Exchange-CrossTenant-fromentityheader: Hosted X-MS-Exchange-CrossTenant-id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-mailboxtype: HOSTED X-MS-Exchange-CrossTenant-userprincipalname: jUlccFwgLfO13YmOfIGzuRT9/2UvRPrRVpYBP0hhPg5BuZP7ZMWGWqwWowmmqt6k X-MS-Exchange-Transport-CrossTenantHeadersStamped: DM5PR12MB1930 X-detected-operating-system: by eggs.gnu.org: Windows 7 or 8 [fuzzy] X-Received-From: 40.107.71.70 Subject: [Qemu-devel] [RFC 2 PATCH 15/16] i386: Fix pkg_id offset for epyc mode X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: "qemu-devel@nongnu.org" Errors-To: qemu-devel-bounces+patchwork-qemu-devel=patchwork.kernel.org@nongnu.org Sender: "Qemu-devel" Signed-off-by: Babu Moger --- target/i386/cpu.c | 24 +++++++++++++++++++----- 1 file changed, 19 insertions(+), 5 deletions(-) diff --git a/target/i386/cpu.c b/target/i386/cpu.c index f25491a029..f8b1fc5c07 100644 --- a/target/i386/cpu.c +++ b/target/i386/cpu.c @@ -4094,9 +4094,10 @@ void cpu_x86_cpuid(CPUX86State *env, uint32_t index, uint32_t count, uint32_t *eax, uint32_t *ebx, uint32_t *ecx, uint32_t *edx) { + MachineState *ms = MACHINE(qdev_get_machine()); X86CPU *cpu = env_archcpu(env); CPUState *cs = env_cpu(env); - uint32_t die_offset; + uint32_t die_offset, pkg_offset; uint32_t limit; uint32_t signature[3]; @@ -4119,6 +4120,21 @@ void cpu_x86_cpuid(CPUX86State *env, uint32_t index, uint32_t count, index = env->cpuid_level; } + if (ms->epyc) { + X86CPUTopoInfo topo_info = { + .numa_nodes = nb_numa_nodes, + .nr_sockets = ms->smp.sockets, + .nr_cores = ms->smp.cores, + .nr_threads = ms->smp.threads, + }; + unsigned nodes = nodes_in_pkg(&topo_info); + pkg_offset = apicid_pkg_offset_epyc(nodes, MAX_CCX, MAX_CORES_IN_CCX, + cs->nr_threads); + } else { + pkg_offset = apicid_pkg_offset(env->nr_dies, cs->nr_cores, + cs->nr_threads); + } + switch(index) { case 0: *eax = env->cpuid_level; @@ -4275,8 +4291,7 @@ void cpu_x86_cpuid(CPUX86State *env, uint32_t index, uint32_t count, *ecx |= CPUID_TOPOLOGY_LEVEL_SMT; break; case 1: - *eax = apicid_pkg_offset(env->nr_dies, - cs->nr_cores, cs->nr_threads); + *eax = pkg_offset; *ebx = cs->nr_cores * cs->nr_threads; *ecx |= CPUID_TOPOLOGY_LEVEL_CORE; break; @@ -4310,8 +4325,7 @@ void cpu_x86_cpuid(CPUX86State *env, uint32_t index, uint32_t count, *ecx |= CPUID_TOPOLOGY_LEVEL_CORE; break; case 2: - *eax = apicid_pkg_offset(env->nr_dies, cs->nr_cores, - cs->nr_threads); + *eax = pkg_offset; *ebx = env->nr_dies * cs->nr_cores * cs->nr_threads; *ecx |= CPUID_TOPOLOGY_LEVEL_DIE; break; From patchwork Fri Sep 6 19:13:29 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Babu Moger X-Patchwork-Id: 11135873 Return-Path: Received: from mail.kernel.org (pdx-korg-mail-1.web.codeaurora.org [172.30.200.123]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id CFC9615E6 for ; Fri, 6 Sep 2019 19:23:18 +0000 (UTC) Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id A689820838 for ; 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Fri, 6 Sep 2019 19:13:29 +0000 From: "Moger, Babu" To: ssg.sos.staff , "ehabkost@redhat.com" , "marcel.apfelbaum@gmail.com" , "mst@redhat.com" , "pbonzini@redhat.com" , "rth@twiddle.net" , "eblake@redhat.com" , "armbru@redhat.com" , "imammedo@redhat.com" Thread-Topic: [RFC 2 PATCH 16/16] hw/core: Fix up the machine_set_cpu_numa_node for epyc Thread-Index: AQHVZOcq5DENcdpQ5EuQmZjh98ITLw== Date: Fri, 6 Sep 2019 19:13:29 +0000 Message-ID: <156779720803.21957.8389712174989601936.stgit@localhost.localdomain> References: <156779689013.21957.1631551572950676212.stgit@localhost.localdomain> In-Reply-To: <156779689013.21957.1631551572950676212.stgit@localhost.localdomain> Accept-Language: en-US Content-Language: en-US X-MS-Has-Attach: X-MS-TNEF-Correlator: x-clientproxiedby: SN1PR12CA0082.namprd12.prod.outlook.com (2603:10b6:802:21::17) To DM5PR12MB2471.namprd12.prod.outlook.com (2603:10b6:4:b5::10) authentication-results: spf=none (sender IP is ) smtp.mailfrom=Babu.Moger@amd.com; x-ms-exchange-messagesentrepresentingtype: 1 x-originating-ip: [165.204.78.1] x-ms-publictraffictype: Email x-ms-office365-filtering-correlation-id: 1f7e3218-fe2d-4c6f-8d16-08d732fe4d25 x-ms-office365-filtering-ht: Tenant x-microsoft-antispam: BCL:0; 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DIR:OUT; SFP:1101; SCL:1; SRVR:DM5PR12MB1145; H:DM5PR12MB2471.namprd12.prod.outlook.com; FPR:; SPF:None; LANG:en; PTR:InfoNoRecords; A:1; MX:1; received-spf: None (protection.outlook.com: amd.com does not designate permitted sender hosts) x-ms-exchange-senderadcheck: 1 x-microsoft-antispam-message-info: 7Vv6gNO/CrEZ4v1xI45DXm3EIBMNyYSwztSZ69oEPpdNfG+3Z9aDJ/BNhjSSKAIFOuxDkoF2ZKO3L2EIpZnl0K5WgBblUveMUOgyZpv7EwfaMbGfjwREGhjJCIKFVswTIR3YH2jsubKw4F+X3hq+WEqXEoPy7DjMRDLqWSddow0IE9aRIT5//8kF+Y3YJ77JSaL7efDdNG+jJ6dTY+kNMGQZJBPM4DcTABT1pgI77VvoKjXPeFV9Gzw4vWgElkX0HI4ps9pfHMYt09I8+jONuhgTvDbxq6NVCfT1bP8Y+dAzGnBT39eUjSq9HQIRjK0a13NYBizgd4A6ZyjllBMz+APPSX2otGPlVd/dDTwf2MvRmQn75R68Aob6UrJvi2duko1sLzGB261olxEXvtwkkjhyUJ3b8Z8C6RoLKkNHRCM= Content-ID: MIME-Version: 1.0 X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-Network-Message-Id: 1f7e3218-fe2d-4c6f-8d16-08d732fe4d25 X-MS-Exchange-CrossTenant-originalarrivaltime: 06 Sep 2019 19:13:29.4512 (UTC) X-MS-Exchange-CrossTenant-fromentityheader: Hosted X-MS-Exchange-CrossTenant-id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-mailboxtype: HOSTED X-MS-Exchange-CrossTenant-userprincipalname: LaAgdygmr9HRTs6tnhnw1ej2q+XPWi0yI5O7y78IHRxKbrMUHINe0bjlkDh7jQx7 X-MS-Exchange-Transport-CrossTenantHeadersStamped: DM5PR12MB1145 X-detected-operating-system: by eggs.gnu.org: Windows 7 or 8 [fuzzy] X-Received-From: 40.107.70.62 Subject: [Qemu-devel] [RFC 2 PATCH 16/16] hw/core: Fix up the machine_set_cpu_numa_node for epyc X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: "qemu-devel@nongnu.org" Errors-To: qemu-devel-bounces+patchwork-qemu-devel=patchwork.kernel.org@nongnu.org Sender: "Qemu-devel" Current topology id match will not work for epyc mode when setting the node id. In epyc mode, ids like smt_id, thread_id, core_id, ccx_id, socket_id can be same for more than one CPUs with across two numa nodes. For example, we can have two CPUs with following ids on two different node. 1. smt_id=0, thread_id=0, core_id=0, ccx_id=0, socket_id=0, node_id=0 2. smt_id=0, thread_id=0, core_id=0, ccx_id=0, socket_id=0, node_id=1 The function machine_set_cpu_numa_node will fail to find a match to assign the node. Added new function machine_set_cpu_numa_node_epyc to set the node_id directly in epyc mode. Signed-off-by: Babu Moger --- hw/core/machine.c | 24 ++++++++++++++++++++++++ hw/core/numa.c | 6 +++++- include/hw/boards.h | 4 ++++ 3 files changed, 33 insertions(+), 1 deletion(-) diff --git a/hw/core/machine.c b/hw/core/machine.c index 9a8586cf30..6bceefc6f3 100644 --- a/hw/core/machine.c +++ b/hw/core/machine.c @@ -741,6 +741,30 @@ void machine_set_cpu_numa_node(MachineState *machine, } } +void machine_set_cpu_numa_node_epyc(MachineState *machine, + const CpuInstanceProperties *props, + unsigned index, + Error **errp) +{ + MachineClass *mc = MACHINE_GET_CLASS(machine); + CPUArchId *slot; + + if (!mc->possible_cpu_arch_ids) { + error_setg(errp, "mapping of CPUs to NUMA node is not supported"); + return; + } + + /* disabling node mapping is not supported, forbid it */ + assert(props->has_node_id); + + /* force board to initialize possible_cpus if it hasn't been done yet */ + mc->possible_cpu_arch_ids(machine); + + slot = &machine->possible_cpus->cpus[index]; + slot->props.node_id = props->node_id; + slot->props.has_node_id = props->has_node_id; +} + static void smp_parse(MachineState *ms, QemuOpts *opts) { if (opts) { diff --git a/hw/core/numa.c b/hw/core/numa.c index 27fa6b5e1d..a9e835aea6 100644 --- a/hw/core/numa.c +++ b/hw/core/numa.c @@ -247,7 +247,11 @@ void set_numa_node_options(MachineState *ms, NumaOptions *object, Error **errp) props = mc->cpu_index_to_instance_props(ms, cpus->value); props.node_id = nodenr; props.has_node_id = true; - machine_set_cpu_numa_node(ms, &props, &err); + if (ms->epyc) { + machine_set_cpu_numa_node_epyc(ms, &props, cpus->value, &err); + } else { + machine_set_cpu_numa_node(ms, &props, &err); + } if (err) { error_propagate(errp, err); return; diff --git a/include/hw/boards.h b/include/hw/boards.h index 0001d42e50..ec1b1c5a85 100644 --- a/include/hw/boards.h +++ b/include/hw/boards.h @@ -74,6 +74,10 @@ HotpluggableCPUList *machine_query_hotpluggable_cpus(MachineState *machine); void machine_set_cpu_numa_node(MachineState *machine, const CpuInstanceProperties *props, Error **errp); +void machine_set_cpu_numa_node_epyc(MachineState *machine, + const CpuInstanceProperties *props, + unsigned index, + Error **errp); void machine_class_allow_dynamic_sysbus_dev(MachineClass *mc, const char *type);