From patchwork Mon Sep 9 10:21:00 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Tony W Wang-oc X-Patchwork-Id: 11137661 Return-Path: Received: from mail.kernel.org (pdx-korg-mail-1.web.codeaurora.org [172.30.200.123]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id 905C476 for ; Mon, 9 Sep 2019 10:36:32 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.kernel.org (Postfix) with ESMTP id 7804121920 for ; Mon, 9 Sep 2019 10:36:32 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1729132AbfIIKgb convert rfc822-to-8bit (ORCPT ); Mon, 9 Sep 2019 06:36:31 -0400 Received: from ZXSHCAS2.zhaoxin.com ([203.148.12.82]:59195 "EHLO ZXSHCAS2.zhaoxin.com" rhost-flags-OK-FAIL-OK-FAIL) by vger.kernel.org with ESMTP id S1728964AbfIIKga (ORCPT ); Mon, 9 Sep 2019 06:36:30 -0400 Received: from zxbjmbx2.zhaoxin.com (10.29.252.164) by ZXSHCAS2.zhaoxin.com (10.28.252.162) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.1261.35; Mon, 9 Sep 2019 18:21:00 +0800 Received: from zxbjmbx1.zhaoxin.com (10.29.252.163) by zxbjmbx2.zhaoxin.com (10.29.252.164) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.1261.35; Mon, 9 Sep 2019 18:21:00 +0800 Received: from zxbjmbx1.zhaoxin.com ([fe80::b41a:737:a784:b70d]) by zxbjmbx1.zhaoxin.com ([fe80::b41a:737:a784:b70d%16]) with mapi id 15.01.1261.035; Mon, 9 Sep 2019 18:21:00 +0800 From: Tony W Wang-oc To: "tony.luck@intel.com" , "Borislav Petkov (bp@alien8.de)" , "tglx@linutronix.de" , "mingo@redhat.com" , "hpa@zytor.com" , "x86@kernel.org" , "linux-edac@vger.kernel.org" , "linux-kernel@vger.kernel.org" , "yazen.ghannam@amd.com" , "vishal.l.verma@intel.com" , "qiuxu.zhuo@intel.com" CC: David Wang , "Cooper Yan(BJ-RD)" , "Qiyuan Wang(BJ-RD)" , "Herry Yang(BJ-RD)" Subject: [PATCH v1 1/4] x86/mce: Add Zhaoxin MCE support Thread-Topic: [PATCH v1 1/4] x86/mce: Add Zhaoxin MCE support Thread-Index: AdVm9wIO3kejlR5fSyK15L215x15mg== Date: Mon, 9 Sep 2019 10:21:00 +0000 Message-ID: <9ab728a082834a29abb26f6e7bc6263d@zhaoxin.com> Accept-Language: en-US, zh-CN Content-Language: zh-CN X-MS-Has-Attach: X-MS-TNEF-Correlator: x-originating-ip: [10.32.64.75] MIME-Version: 1.0 Sender: linux-edac-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-edac@vger.kernel.org All Zhaoxin newer CPUs support MCE that compatible with Intel's "Machine-Check Architecture", so add support for Zhaoxin MCE in mce/core.c. Signed-off-by: Tony W Wang-oc --- arch/x86/kernel/cpu/mce/core.c | 30 ++++++++++++++++++++++++------ 1 file changed, 24 insertions(+), 6 deletions(-) diff --git a/arch/x86/kernel/cpu/mce/core.c b/arch/x86/kernel/cpu/mce/core.c index 743370e..3f878f6 100644 --- a/arch/x86/kernel/cpu/mce/core.c +++ b/arch/x86/kernel/cpu/mce/core.c @@ -488,8 +488,9 @@ int mce_usable_address(struct mce *m) if (!(m->status & MCI_STATUS_ADDRV)) return 0; - /* Checks after this one are Intel-specific: */ - if (boot_cpu_data.x86_vendor != X86_VENDOR_INTEL) + /* Checks after this one are Intel/Zhaoxin-specific: */ + if (boot_cpu_data.x86_vendor != X86_VENDOR_INTEL && + boot_cpu_data.x86_vendor != X86_VENDOR_ZHAOXIN) return 1; if (!(m->status & MCI_STATUS_MISCV)) @@ -510,7 +511,8 @@ bool mce_is_memory_error(struct mce *m) if (m->cpuvendor == X86_VENDOR_AMD || m->cpuvendor == X86_VENDOR_HYGON) { return amd_mce_is_memory_error(m); - } else if (m->cpuvendor == X86_VENDOR_INTEL) { + } else if (m->cpuvendor == X86_VENDOR_INTEL || + m->cpuvendor == X86_VENDOR_ZHAOXIN) { /* * Intel SDM Volume 3B - 15.9.2 Compound Error Codes * @@ -1697,6 +1699,21 @@ static int __mcheck_cpu_apply_quirks(struct cpuinfo_x86 *c) if (c->x86 == 6 && c->x86_model == 45) quirk_no_way_out = quirk_sandybridge_ifu; } + + if (c->x86_vendor == X86_VENDOR_ZHAOXIN) { + /* + * All newer Zhaoxin CPUs support MCE broadcasting. Enable + * synchronization with a one second timeout. + */ + if ((c->x86 == 6 && c->x86_model == 0x19 && + (c->x86_stepping > 3 && c->x86_stepping < 8)) || + (c->x86 == 6 && c->x86_model == 0x1f) || + c->x86 > 6) { + if (cfg->monarch_timeout < 0) + cfg->monarch_timeout = USEC_PER_SEC; + } + } + if (cfg->monarch_timeout < 0) cfg->monarch_timeout = 0; if (cfg->bootlog != 0) @@ -2014,15 +2031,16 @@ static void mce_disable_error_reporting(void) static void vendor_disable_error_reporting(void) { /* - * Don't clear on Intel or AMD or Hygon CPUs. Some of these MSRs - * are socket-wide. + * Don't clear on Intel or AMD or Hygon or Zhaoxin CPUs. Some of these + * MSRs are socket-wide. * Disabling them for just a single offlined CPU is bad, since it will * inhibit reporting for all shared resources on the socket like the * last level cache (LLC), the integrated memory controller (iMC), etc. */ if (boot_cpu_data.x86_vendor == X86_VENDOR_INTEL || boot_cpu_data.x86_vendor == X86_VENDOR_HYGON || - boot_cpu_data.x86_vendor == X86_VENDOR_AMD) + boot_cpu_data.x86_vendor == X86_VENDOR_AMD || + boot_cpu_data.x86_vendor == X86_VENDOR_ZHAOXIN) return; mce_disable_error_reporting(); From patchwork Mon Sep 9 10:21:14 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Tony W Wang-oc X-Patchwork-Id: 11137665 Return-Path: Received: from mail.kernel.org (pdx-korg-mail-1.web.codeaurora.org [172.30.200.123]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id 778DB1709 for ; Mon, 9 Sep 2019 10:36:43 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.kernel.org (Postfix) with ESMTP id 5EE512086D for ; Mon, 9 Sep 2019 10:36:43 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1728964AbfIIKgf convert rfc822-to-8bit (ORCPT ); Mon, 9 Sep 2019 06:36:35 -0400 Received: from ZXSHCAS2.zhaoxin.com ([203.148.12.82]:59195 "EHLO ZXSHCAS2.zhaoxin.com" rhost-flags-OK-FAIL-OK-FAIL) by vger.kernel.org with ESMTP id S1728945AbfIIKgc (ORCPT ); Mon, 9 Sep 2019 06:36:32 -0400 Received: from zxbjmbx3.zhaoxin.com (10.29.252.165) by ZXSHCAS2.zhaoxin.com (10.28.252.162) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.1261.35; Mon, 9 Sep 2019 18:21:15 +0800 Received: from zxbjmbx1.zhaoxin.com (10.29.252.163) by zxbjmbx3.zhaoxin.com (10.29.252.165) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.1261.35; Mon, 9 Sep 2019 18:21:14 +0800 Received: from zxbjmbx1.zhaoxin.com ([fe80::b41a:737:a784:b70d]) by zxbjmbx1.zhaoxin.com ([fe80::b41a:737:a784:b70d%16]) with mapi id 15.01.1261.035; Mon, 9 Sep 2019 18:21:14 +0800 From: Tony W Wang-oc To: "tony.luck@intel.com" , "Borislav Petkov (bp@alien8.de)" , "tglx@linutronix.de" , "mingo@redhat.com" , "hpa@zytor.com" , "x86@kernel.org" , "linux-edac@vger.kernel.org" , "linux-kernel@vger.kernel.org" , "yazen.ghannam@amd.com" , "vishal.l.verma@intel.com" , "qiuxu.zhuo@intel.com" CC: David Wang , "Cooper Yan(BJ-RD)" , "Qiyuan Wang(BJ-RD)" , "Herry Yang(BJ-RD)" Subject: [PATCH v1 2/4] x86/mce: Make 4 functions non-static Thread-Topic: [PATCH v1 2/4] x86/mce: Make 4 functions non-static Thread-Index: AdVm9wPzkra93/0kREu4L4PJi6UVog== Date: Mon, 9 Sep 2019 10:21:14 +0000 Message-ID: <54f39a2e51be4ae6bed875d1fa38e0be@zhaoxin.com> Accept-Language: en-US, zh-CN Content-Language: zh-CN X-MS-Has-Attach: X-MS-TNEF-Correlator: x-originating-ip: [10.32.64.75] MIME-Version: 1.0 Sender: linux-edac-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-edac@vger.kernel.org These functions are declared static and cannot be used in others .c source file. this commit removes the static attribute and adds the declaration to the header for these functions. Signed-off-by: Tony W Wang-oc --- arch/x86/kernel/cpu/mce/intel.c | 8 ++++---- arch/x86/kernel/cpu/mce/internal.h | 8 ++++++++ 2 files changed, 12 insertions(+), 4 deletions(-) diff --git a/arch/x86/kernel/cpu/mce/intel.c b/arch/x86/kernel/cpu/mce/intel.c index 88cd959..eee4b12 100644 --- a/arch/x86/kernel/cpu/mce/intel.c +++ b/arch/x86/kernel/cpu/mce/intel.c @@ -423,7 +423,7 @@ void cmci_disable_bank(int bank) raw_spin_unlock_irqrestore(&cmci_discover_lock, flags); } -static void intel_init_cmci(void) +void intel_init_cmci(void) { int banks; @@ -442,7 +442,7 @@ static void intel_init_cmci(void) cmci_recheck(); } -static void intel_init_lmce(void) +void intel_init_lmce(void) { u64 val; @@ -455,7 +455,7 @@ static void intel_init_lmce(void) wrmsrl(MSR_IA32_MCG_EXT_CTL, val | MCG_EXT_CTL_LMCE_EN); } -static void intel_clear_lmce(void) +void intel_clear_lmce(void) { u64 val; @@ -467,7 +467,7 @@ static void intel_clear_lmce(void) wrmsrl(MSR_IA32_MCG_EXT_CTL, val); } -static void intel_ppin_init(struct cpuinfo_x86 *c) +void intel_ppin_init(struct cpuinfo_x86 *c) { unsigned long long val; diff --git a/arch/x86/kernel/cpu/mce/internal.h b/arch/x86/kernel/cpu/mce/internal.h index 43031db..55d1f0a 100644 --- a/arch/x86/kernel/cpu/mce/internal.h +++ b/arch/x86/kernel/cpu/mce/internal.h @@ -45,11 +45,19 @@ unsigned long cmci_intel_adjust_timer(unsigned long interval); bool mce_intel_cmci_poll(void); void mce_intel_hcpu_update(unsigned long cpu); void cmci_disable_bank(int bank); +void intel_init_cmci(void); +void intel_init_lmce(void); +void intel_clear_lmce(void); +void intel_ppin_init(struct cpuinfo_x86 *c); #else # define cmci_intel_adjust_timer mce_adjust_timer_default static inline bool mce_intel_cmci_poll(void) { return false; } static inline void mce_intel_hcpu_update(unsigned long cpu) { } static inline void cmci_disable_bank(int bank) { } +static inline void intel_init_cmci(void) { } +static inline void intel_init_lmce(void) { } +static inline void intel_clear_lmce(void) { } +static inline void intel_ppin_init(struct cpuinfo_x86 *c) { } #endif void mce_timer_kick(unsigned long interval); From patchwork Mon Sep 9 10:21:22 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Tony W Wang-oc X-Patchwork-Id: 11137659 Return-Path: Received: from mail.kernel.org (pdx-korg-mail-1.web.codeaurora.org [172.30.200.123]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id 1419F76 for ; Mon, 9 Sep 2019 10:36:30 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.kernel.org (Postfix) with ESMTP id F020F21A4C for ; Mon, 9 Sep 2019 10:36:29 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1728970AbfIIKg3 convert rfc822-to-8bit (ORCPT ); Mon, 9 Sep 2019 06:36:29 -0400 Received: from ZXSHCAS1.zhaoxin.com ([203.148.12.81]:6752 "EHLO ZXSHCAS1.zhaoxin.com" rhost-flags-OK-FAIL-OK-FAIL) by vger.kernel.org with ESMTP id S1728945AbfIIKg2 (ORCPT ); Mon, 9 Sep 2019 06:36:28 -0400 X-Greylist: delayed 902 seconds by postgrey-1.27 at vger.kernel.org; Mon, 09 Sep 2019 06:36:28 EDT Received: from zxbjmbx2.zhaoxin.com (10.29.252.164) by ZXSHCAS1.zhaoxin.com (10.28.252.161) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.1261.35; Mon, 9 Sep 2019 18:21:23 +0800 Received: from zxbjmbx1.zhaoxin.com (10.29.252.163) by zxbjmbx2.zhaoxin.com (10.29.252.164) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.1261.35; Mon, 9 Sep 2019 18:21:23 +0800 Received: from zxbjmbx1.zhaoxin.com ([fe80::b41a:737:a784:b70d]) by zxbjmbx1.zhaoxin.com ([fe80::b41a:737:a784:b70d%16]) with mapi id 15.01.1261.035; Mon, 9 Sep 2019 18:21:23 +0800 From: Tony W Wang-oc To: "tony.luck@intel.com" , "Borislav Petkov (bp@alien8.de)" , "tglx@linutronix.de" , "mingo@redhat.com" , "hpa@zytor.com" , "x86@kernel.org" , "linux-edac@vger.kernel.org" , "linux-kernel@vger.kernel.org" , "yazen.ghannam@amd.com" , "vishal.l.verma@intel.com" , "qiuxu.zhuo@intel.com" CC: David Wang , "Cooper Yan(BJ-RD)" , "Qiyuan Wang(BJ-RD)" , "Herry Yang(BJ-RD)" Subject: [PATCH v1 3/4] x86/mce: Add Zhaoxin CMCI support Thread-Topic: [PATCH v1 3/4] x86/mce: Add Zhaoxin CMCI support Thread-Index: AdVm9rhzHHwSHU0OR4CG5KfkCNKupA== Date: Mon, 9 Sep 2019 10:21:22 +0000 Message-ID: <29e895912c2f4989937fa33d59e55dd9@zhaoxin.com> Accept-Language: en-US, zh-CN Content-Language: zh-CN X-MS-Has-Attach: X-MS-TNEF-Correlator: x-originating-ip: [10.32.64.75] MIME-Version: 1.0 Sender: linux-edac-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-edac@vger.kernel.org All Zhaoxin newer CPUs support CMCI that compatible with Intel's "Machine-Check Architecture", so add support for Zhaoxin CMCI in mce/core.c and mce/intel.c. Signed-off-by: Tony W Wang-oc --- arch/x86/include/asm/mce.h | 6 ++++++ arch/x86/kernel/cpu/mce/core.c | 25 +++++++++++++++++++++++++ arch/x86/kernel/cpu/mce/intel.c | 3 ++- 3 files changed, 33 insertions(+), 1 deletion(-) diff --git a/arch/x86/include/asm/mce.h b/arch/x86/include/asm/mce.h index dc2d4b2..0986a11 100644 --- a/arch/x86/include/asm/mce.h +++ b/arch/x86/include/asm/mce.h @@ -350,4 +350,10 @@ umc_normaddr_to_sysaddr(u64 norm_addr, u16 nid, u8 umc, u64 *sys_addr) { return static inline void mce_hygon_feature_init(struct cpuinfo_x86 *c) { return mce_amd_feature_init(c); } +#ifdef CONFIG_CPU_SUP_ZHAOXIN +void mce_zhaoxin_feature_init(struct cpuinfo_x86 *c); +#else +static inline void mce_zhaoxin_feature_init(struct cpuinfo_x86 *c) { } +#endif + #endif /* _ASM_X86_MCE_H */ diff --git a/arch/x86/kernel/cpu/mce/core.c b/arch/x86/kernel/cpu/mce/core.c index 3f878f6..a3b07ca 100644 --- a/arch/x86/kernel/cpu/mce/core.c +++ b/arch/x86/kernel/cpu/mce/core.c @@ -1777,6 +1777,27 @@ static void mce_centaur_feature_init(struct cpuinfo_x86 *c) } } +void mce_zhaoxin_feature_init(struct cpuinfo_x86 *c) +{ + struct mce_bank *mce_banks = this_cpu_ptr(mce_banks_array); + + /* + * These CPUs bank8 SVAD error may be triggered unexpected when + * bringup virtual machine. it is not hardware bug. Always disable + * bank8 SVAD error by default. + */ + if ((c->x86 == 6 && c->x86_model == 0x19 && + (c->x86_stepping > 3 && c->x86_stepping < 8)) || + (c->x86 == 6 && c->x86_model == 0x1f) || + (c->x86 == 7 && c->x86_model == 0x1b)) { + if (this_cpu_read(mce_num_banks) > 8) + mce_banks[8].ctl = 0; + } + + intel_init_cmci(); + mce_adjust_timer = cmci_intel_adjust_timer; +} + static void __mcheck_cpu_init_vendor(struct cpuinfo_x86 *c) { switch (c->x86_vendor) { @@ -1798,6 +1819,10 @@ static void __mcheck_cpu_init_vendor(struct cpuinfo_x86 *c) mce_centaur_feature_init(c); break; + case X86_VENDOR_ZHAOXIN: + mce_zhaoxin_feature_init(c); + break; + default: break; } diff --git a/arch/x86/kernel/cpu/mce/intel.c b/arch/x86/kernel/cpu/mce/intel.c index eee4b12..b49cba7 100644 --- a/arch/x86/kernel/cpu/mce/intel.c +++ b/arch/x86/kernel/cpu/mce/intel.c @@ -85,7 +85,8 @@ static int cmci_supported(int *banks) * initialization is vendor keyed and this * makes sure none of the backdoors are entered otherwise. */ - if (boot_cpu_data.x86_vendor != X86_VENDOR_INTEL) + if (boot_cpu_data.x86_vendor != X86_VENDOR_INTEL && + boot_cpu_data.x86_vendor != X86_VENDOR_ZHAOXIN) return 0; if (!boot_cpu_has(X86_FEATURE_APIC) || lapic_get_maxlvt() < 6) return 0; From patchwork Mon Sep 9 10:21:32 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Tony W Wang-oc X-Patchwork-Id: 11137663 Return-Path: Received: from mail.kernel.org (pdx-korg-mail-1.web.codeaurora.org [172.30.200.123]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id EE75A1709 for ; Mon, 9 Sep 2019 10:36:38 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.kernel.org (Postfix) with ESMTP id D654221A4C for ; Mon, 9 Sep 2019 10:36:38 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1728945AbfIIKgi convert rfc822-to-8bit (ORCPT ); Mon, 9 Sep 2019 06:36:38 -0400 Received: from ZXSHCAS1.zhaoxin.com ([203.148.12.81]:6766 "EHLO ZXSHCAS1.zhaoxin.com" rhost-flags-OK-FAIL-OK-FAIL) by vger.kernel.org with ESMTP id S1729535AbfIIKgh (ORCPT ); Mon, 9 Sep 2019 06:36:37 -0400 Received: from zxbjmbx3.zhaoxin.com (10.29.252.165) by ZXSHCAS1.zhaoxin.com (10.28.252.161) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.1261.35; Mon, 9 Sep 2019 18:21:33 +0800 Received: from zxbjmbx1.zhaoxin.com (10.29.252.163) by zxbjmbx3.zhaoxin.com (10.29.252.165) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.1261.35; Mon, 9 Sep 2019 18:21:33 +0800 Received: from zxbjmbx1.zhaoxin.com ([fe80::b41a:737:a784:b70d]) by zxbjmbx1.zhaoxin.com ([fe80::b41a:737:a784:b70d%16]) with mapi id 15.01.1261.035; Mon, 9 Sep 2019 18:21:33 +0800 From: Tony W Wang-oc To: "tony.luck@intel.com" , "Borislav Petkov (bp@alien8.de)" , "tglx@linutronix.de" , "mingo@redhat.com" , "hpa@zytor.com" , "x86@kernel.org" , "linux-edac@vger.kernel.org" , "linux-kernel@vger.kernel.org" , "yazen.ghannam@amd.com" , "vishal.l.verma@intel.com" , "qiuxu.zhuo@intel.com" CC: David Wang , "Cooper Yan(BJ-RD)" , "Qiyuan Wang(BJ-RD)" , "Herry Yang(BJ-RD)" Subject: [PATCH v1 4/4] x86/mce: Add Zhaoxin LMCE support Thread-Topic: [PATCH v1 4/4] x86/mce: Add Zhaoxin LMCE support Thread-Index: AdVm9sekXcvxySmaQUuiHvxrjjCjsg== Date: Mon, 9 Sep 2019 10:21:32 +0000 Message-ID: <8eec2a65dd5a4957aa5d0e6600302963@zhaoxin.com> Accept-Language: en-US, zh-CN Content-Language: zh-CN X-MS-Has-Attach: X-MS-TNEF-Correlator: x-originating-ip: [10.32.64.75] MIME-Version: 1.0 Sender: linux-edac-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-edac@vger.kernel.org Zhaoxin newer CPUs support LMCE that compatible with Intel's "Machine-Check Architecture", so add support for Zhaoxin LMCE in mce/core.c. Signed-off-by: Tony W Wang-oc --- arch/x86/include/asm/mce.h | 2 ++ arch/x86/kernel/cpu/mce/core.c | 25 +++++++++++++++++++++++-- 2 files changed, 25 insertions(+), 2 deletions(-) diff --git a/arch/x86/include/asm/mce.h b/arch/x86/include/asm/mce.h index 0986a11..01840ec 100644 --- a/arch/x86/include/asm/mce.h +++ b/arch/x86/include/asm/mce.h @@ -352,8 +352,10 @@ static inline void mce_hygon_feature_init(struct cpuinfo_x86 *c) { return mce_am #ifdef CONFIG_CPU_SUP_ZHAOXIN void mce_zhaoxin_feature_init(struct cpuinfo_x86 *c); +void mce_zhaoxin_feature_clear(struct cpuinfo_x86 *c); #else static inline void mce_zhaoxin_feature_init(struct cpuinfo_x86 *c) { } +static inline void mce_zhaoxin_feature_clear(struct cpuinfo_x86 *c) { } #endif #endif /* _ASM_X86_MCE_H */ diff --git a/arch/x86/kernel/cpu/mce/core.c b/arch/x86/kernel/cpu/mce/core.c index a3b07ca..857570f 100644 --- a/arch/x86/kernel/cpu/mce/core.c +++ b/arch/x86/kernel/cpu/mce/core.c @@ -1129,6 +1129,17 @@ static bool __mc_check_crashing_cpu(int cpu) u64 mcgstatus; mcgstatus = mce_rdmsrl(MSR_IA32_MCG_STATUS); + + if (boot_cpu_data.x86_vendor == X86_VENDOR_ZHAOXIN) { + if (mcgstatus & MCG_STATUS_LMCES) { + return false; + } else { + if (mcgstatus & MCG_STATUS_RIPV) + mce_wrmsrl(MSR_IA32_MCG_STATUS, 0); + return true; + } + } + if (mcgstatus & MCG_STATUS_RIPV) { mce_wrmsrl(MSR_IA32_MCG_STATUS, 0); return true; @@ -1279,9 +1290,10 @@ void do_machine_check(struct pt_regs *regs, long error_code) /* * Check if this MCE is signaled to only this logical processor, - * on Intel only. + * on Intel, Zhaoxin only. */ - if (m.cpuvendor == X86_VENDOR_INTEL) + if (m.cpuvendor == X86_VENDOR_INTEL || + m.cpuvendor == X86_VENDOR_ZHAOXIN) lmce = m.mcgstatus & MCG_STATUS_LMCES; /* @@ -1795,9 +1807,15 @@ void mce_zhaoxin_feature_init(struct cpuinfo_x86 *c) } intel_init_cmci(); + intel_init_lmce(); mce_adjust_timer = cmci_intel_adjust_timer; } +void mce_zhaoxin_feature_clear(struct cpuinfo_x86 *c) +{ + intel_clear_lmce(); +} + static void __mcheck_cpu_init_vendor(struct cpuinfo_x86 *c) { switch (c->x86_vendor) { @@ -1834,6 +1852,9 @@ static void __mcheck_cpu_clear_vendor(struct cpuinfo_x86 *c) case X86_VENDOR_INTEL: mce_intel_feature_clear(c); break; + case X86_VENDOR_ZHAOXIN: + mce_zhaoxin_feature_clear(c); + break; default: break; }