From patchwork Tue Sep 10 09:56:07 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Beata Michalska X-Patchwork-Id: 11139123 Return-Path: Received: from mail.kernel.org (pdx-korg-mail-1.web.codeaurora.org [172.30.200.123]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id EB7C476 for ; Tue, 10 Sep 2019 09:57:46 +0000 (UTC) Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id C14922067B for ; Tue, 10 Sep 2019 09:57:46 +0000 (UTC) Authentication-Results: mail.kernel.org; dkim=fail reason="signature verification failed" (2048-bit key) header.d=linaro.org header.i=@linaro.org header.b="MHABNx7D" DMARC-Filter: OpenDMARC Filter v1.3.2 mail.kernel.org C14922067B Authentication-Results: mail.kernel.org; dmarc=fail (p=none dis=none) header.from=linaro.org Authentication-Results: mail.kernel.org; spf=pass smtp.mailfrom=qemu-devel-bounces+patchwork-qemu-devel=patchwork.kernel.org@nongnu.org Received: from localhost ([::1]:37058 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1i7cu9-0001ND-P8 for patchwork-qemu-devel@patchwork.kernel.org; Tue, 10 Sep 2019 05:57:45 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:50766) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1i7ct0-0008P8-PW for qemu-devel@nongnu.org; Tue, 10 Sep 2019 05:56:35 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1i7csz-0002Xf-LQ for qemu-devel@nongnu.org; Tue, 10 Sep 2019 05:56:34 -0400 Received: from mail-wr1-x444.google.com ([2a00:1450:4864:20::444]:33382) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1i7csz-0002X6-Fs for qemu-devel@nongnu.org; Tue, 10 Sep 2019 05:56:33 -0400 Received: by mail-wr1-x444.google.com with SMTP id u16so18897042wrr.0 for ; Tue, 10 Sep 2019 02:56:33 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=V8rbWEWlHyHd4UbRaLskqjLUrYsGkHiX8TMo3VrUG1s=; b=MHABNx7DC1/9SGQ/iNb/c4Dte1b/++/wKMVMg8NIdcJVi0cLj517karVPxy6+Oc4eA YObSxH1pfn7gVTBaVjWWJlOWpueDwr+CyvAfxdMqoPajh0Tl4DMj5TPNZeP9zXU1bF/5 keKzi/I/CGz6Uo9BCdEqly97R3w5TUXAzM2FwXQ8rzO784ExZV7E8XkzWZzldm2CMA2I xc7Aqf2x0jBsFjrvODEAA+pYfL1sOuwfpZSM+4olFXGDxm5d1eN3xjSr46Avrm7Jp1MW MIAOfVxbbK2pv8UEjFEYtnBzs9/oXpFlSyX2QVypvbhL4Cp+laFAYs8I7gfH4raERacn pNKA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=V8rbWEWlHyHd4UbRaLskqjLUrYsGkHiX8TMo3VrUG1s=; b=Ge7Iy8w/rLJg8Wq0kIDFdoL62X46ng1aMMKMhTTnvPmnYx6AYZ+ePnLHzx578BiBKw gB6shkkK3IgkYv9+MHBT5mwAV3eYfzEkXomoGj+RIvtHc/xTfoHXImiZ8LC84oyicI5C t7VijwlN4DVKWRMD3eAiJZC0Nzqm04sDQ7JPxO6FamgExezTL7O1nLq93SB00WrVf4CY AY9EwJ6vH3XiTyCw4r0DePn1ARq9S6kbjOT0ezgqjrEZUlQtD5ymcVRgVhb/Ia5YDBuY w7yoRPSLl7fvk3TFjnAcIk5mLlEYoFGvA3V8YdQtwCq/I2HNMhbqTJ5Tklf998zA23Gd qRZg== X-Gm-Message-State: APjAAAUHCjofJWVpLi7ti87N91pCM+DFxKZ5X/P4GxEp1UPoJZLqxJVD RK5qfC/wf53TToGUATEkltKn/ZVXjbrFcw== X-Google-Smtp-Source: APXvYqwg3AXsD02hm5Ty4zNk5Ux9pNgo/7utw4vI1Y476GoPt7vIaiHCepvkDYXDl1Sf4h3LfoArjA== X-Received: by 2002:adf:a4c8:: with SMTP id h8mr25265331wrb.293.1568109392396; Tue, 10 Sep 2019 02:56:32 -0700 (PDT) Received: from moi-XPS-13-9350.arm.com (host86-144-13-57.range86-144.btcentralplus.com. [86.144.13.57]) by smtp.gmail.com with ESMTPSA id e30sm32403540wra.48.2019.09.10.02.56.31 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 10 Sep 2019 02:56:31 -0700 (PDT) From: Beata Michalska To: qemu-devel@nongnu.org Date: Tue, 10 Sep 2019 11:56:07 +0200 Message-Id: <20190910095610.4546-2-beata.michalska@linaro.org> In-Reply-To: <20190910095610.4546-1-beata.michalska@linaro.org> References: <20190910095610.4546-1-beata.michalska@linaro.org> X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2a00:1450:4864:20::444 Subject: [Qemu-devel] [PATCH 1/4] tcg: cputlb: Add probe_read X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: peter.maydell@linaro.org, Beata Michalska , quintela@redhat.com, richard.henderson@linaro.org, dgilbert@redhat.com, shameerali.kolothum.thodi@huawei.com, eric.auger@redhat.com, qemu-arm@nongnu.org, pbonzini@redhat.com Errors-To: qemu-devel-bounces+patchwork-qemu-devel=patchwork.kernel.org@nongnu.org Sender: "Qemu-devel" Add probe_read alongside the write probing equivalent. Signed-off-by: Beata Michalska Reviewed-by: Alex Bennée --- include/exec/exec-all.h | 6 ++++++ 1 file changed, 6 insertions(+) diff --git a/include/exec/exec-all.h b/include/exec/exec-all.h index 81b02eb2fe..e1785700c3 100644 --- a/include/exec/exec-all.h +++ b/include/exec/exec-all.h @@ -319,6 +319,12 @@ static inline void *probe_write(CPUArchState *env, target_ulong addr, int size, return probe_access(env, addr, size, MMU_DATA_STORE, mmu_idx, retaddr); } +static inline void *probe_read(CPUArchState *env, target_ulong addr, int size, + int mmu_idx, uintptr_t retaddr) +{ + return probe_access(env, addr, size, MMU_DATA_LOAD, mmu_idx, retaddr); +} + #define CODE_GEN_ALIGN 16 /* must be >= of the size of a icache line */ /* Estimated block size for TB allocation. */ From patchwork Tue Sep 10 09:56:08 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Beata Michalska X-Patchwork-Id: 11139127 Return-Path: Received: from mail.kernel.org (pdx-korg-mail-1.web.codeaurora.org [172.30.200.123]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id 556D8112B for ; Tue, 10 Sep 2019 09:57:51 +0000 (UTC) Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id 2B1602067B for ; Tue, 10 Sep 2019 09:57:51 +0000 (UTC) Authentication-Results: mail.kernel.org; dkim=fail reason="signature verification failed" (2048-bit key) header.d=linaro.org header.i=@linaro.org header.b="TIUC3Oap" DMARC-Filter: OpenDMARC Filter v1.3.2 mail.kernel.org 2B1602067B Authentication-Results: mail.kernel.org; dmarc=fail (p=none dis=none) header.from=linaro.org Authentication-Results: mail.kernel.org; spf=pass smtp.mailfrom=qemu-devel-bounces+patchwork-qemu-devel=patchwork.kernel.org@nongnu.org Received: from localhost ([::1]:37066 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1i7cuE-0001RG-2w for patchwork-qemu-devel@patchwork.kernel.org; Tue, 10 Sep 2019 05:57:50 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:50807) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1i7ct2-0008PV-6z for qemu-devel@nongnu.org; Tue, 10 Sep 2019 05:56:37 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1i7ct0-0002YZ-LS for qemu-devel@nongnu.org; Tue, 10 Sep 2019 05:56:36 -0400 Received: from mail-wr1-x444.google.com ([2a00:1450:4864:20::444]:44193) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1i7ct0-0002Xu-El for qemu-devel@nongnu.org; Tue, 10 Sep 2019 05:56:34 -0400 Received: by mail-wr1-x444.google.com with SMTP id k6so6705762wrn.11 for ; Tue, 10 Sep 2019 02:56:34 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=RoTSf3FoUt1H5Iax7flIjVdUuQGEjtJhhUG2AX/tyZA=; b=TIUC3OapXpTIMyBTSXw88+5YYYiuOjpw1waPasSA4fHt+r/TNJVMo/TuA2CdVgkGWK vheZBRtKoBDwua/BvD0AXMts6HZn5fs+U0+yFUegR1CqEPuZO41/LC6830ZXnD9mjedF MoTa7yhdTLSGRS9lTlop/AE9gqJ1g2zO1otBYUj1iM/kkqioQBEGN6MJaj8aPkJ5turp r/OMIwJ+te7+zrDX2/9yArr6p9ah+olPSIgLCl/UL1Z1c2Tly+WOYgGKzubHW6V1Cswy 6/979aoGNH/eQzQdCO65TmZnNVc9GOymVLZU++aUhbSLwSTgj0EOl8lblSF6DyewzLP1 /cXw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=RoTSf3FoUt1H5Iax7flIjVdUuQGEjtJhhUG2AX/tyZA=; b=Rp8vyTlNhF8cbF/fKtCLWAc8mw3ZxBnka31RkJGbDucAULZh8e1Ycus9JufiLSo4k6 WAWqvXFxKiK/EYWB3+x02rSlTg/Ei2aTwejfKgLT33J1aJYR05hKiixhFNvfEid1uvwb zCQ2pd2q0SeF1Lk/VPS39UdhfV4mfz+p786BMLW2Mrew/jmP0pl3lYXCBN4ny0d4/4UG VCVBzRxDKdAfpcIHyQh+BmhfRUqBsW8CmdYRSvNUyICd0R0rwX+O5dLp+SrS39fnEMKx tCyUKqRNLmpdeUKLavwU363MgUpclzf6lovIBIhnozgDrcxkL5Rs1gTOdJ8Vk9+k7HHW lNPA== X-Gm-Message-State: APjAAAV1ao5IShZGn5WMw3mjInzax4gV/LLEkRaDa4CDazdO2ABGsxM8 8FujVDf3LWQmZ59wxlxx8Qg24L9UnjPGJQ== X-Google-Smtp-Source: APXvYqxgl61O7oVO/OotBN0CpMCtL2QHMBFHRdRDVtFlrcquprLroTVuH8pD9V6Qky9cqAemRAuC8A== X-Received: by 2002:adf:dd0b:: with SMTP id a11mr26928177wrm.42.1568109393331; Tue, 10 Sep 2019 02:56:33 -0700 (PDT) Received: from moi-XPS-13-9350.arm.com (host86-144-13-57.range86-144.btcentralplus.com. [86.144.13.57]) by smtp.gmail.com with ESMTPSA id e30sm32403540wra.48.2019.09.10.02.56.32 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 10 Sep 2019 02:56:32 -0700 (PDT) From: Beata Michalska To: qemu-devel@nongnu.org Date: Tue, 10 Sep 2019 11:56:08 +0200 Message-Id: <20190910095610.4546-3-beata.michalska@linaro.org> In-Reply-To: <20190910095610.4546-1-beata.michalska@linaro.org> References: <20190910095610.4546-1-beata.michalska@linaro.org> X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2a00:1450:4864:20::444 Subject: [Qemu-devel] [PATCH 2/4] Memory: Enable writeback for given memory region X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: peter.maydell@linaro.org, Beata Michalska , quintela@redhat.com, richard.henderson@linaro.org, dgilbert@redhat.com, shameerali.kolothum.thodi@huawei.com, eric.auger@redhat.com, qemu-arm@nongnu.org, pbonzini@redhat.com Errors-To: qemu-devel-bounces+patchwork-qemu-devel=patchwork.kernel.org@nongnu.org Sender: "Qemu-devel" Add an option to trigger memory writeback to sync given memory region with the corresponding backing store, case one is available. This extends the support for persistent memory, allowing syncing on-demand. Also, adding verification for msync support on host. Signed-off-by: Beata Michalska --- configure | 24 ++++++++++++++++++++++++ exec.c | 38 ++++++++++++++++++++++++++++++++++++++ include/exec/memory.h | 6 ++++++ include/exec/ram_addr.h | 6 ++++++ memory.c | 12 ++++++++++++ 5 files changed, 86 insertions(+) diff --git a/configure b/configure index 95134c0180..bdb7dc47e9 100755 --- a/configure +++ b/configure @@ -5081,6 +5081,26 @@ if compile_prog "" "" ; then fdatasync=yes fi +########################################## +# verify support for msyc + +msync=no +cat > $TMPC << EOF +#include +#include +int main(void) { +#if defined(_POSIX_MAPPED_FILES) && _POSIX_MAPPED_FILES > 0 \ +&& defined(_POSIX_SYNCHRONIZED_IO) && _POSIX_SYNCHRONIZED_IO > 0 +return msync(NULL,0, MS_SYNC); +#else +#error Not supported +#endif +} +EOF +if compile_prog "" "" ; then + msync=yes +fi + ########################################## # check if we have madvise @@ -6413,6 +6433,7 @@ echo "fdt support $fdt" echo "membarrier $membarrier" echo "preadv support $preadv" echo "fdatasync $fdatasync" +echo "msync $msync" echo "madvise $madvise" echo "posix_madvise $posix_madvise" echo "posix_memalign $posix_memalign" @@ -6952,6 +6973,9 @@ fi if test "$fdatasync" = "yes" ; then echo "CONFIG_FDATASYNC=y" >> $config_host_mak fi +if test "$msync" = "yes" ; then + echo "CONFIG_MSYNC=y" >> $config_host_mak +fi if test "$madvise" = "yes" ; then echo "CONFIG_MADVISE=y" >> $config_host_mak fi diff --git a/exec.c b/exec.c index 235d6bc883..5ed6908368 100644 --- a/exec.c +++ b/exec.c @@ -65,6 +65,8 @@ #include "exec/ram_addr.h" #include "exec/log.h" +#include "qemu/pmem.h" + #include "migration/vmstate.h" #include "qemu/range.h" @@ -2182,6 +2184,42 @@ int qemu_ram_resize(RAMBlock *block, ram_addr_t newsize, Error **errp) return 0; } +/* + * Trigger sync on the given ram block for range [start, start + length] + * with the backing store if available. + * @Note: this is supposed to be a SYNC op. + */ +void qemu_ram_writeback(RAMBlock *block, ram_addr_t start, ram_addr_t length) +{ + void *addr = ramblock_ptr(block, start); + + /* + * The requested range might spread up to the very end of the block + */ + if ((start + length) > block->used_length) { + error_report("%s: sync range outside the block boundires: " + "start: " RAM_ADDR_FMT " length: " RAM_ADDR_FMT + " block length: " RAM_ADDR_FMT " Narrowing down ..." , + __func__, start, length, block->used_length); + length = block->used_length - start; + } + +#ifdef CONFIG_LIBPMEM + /* The lack of support for pmem should not block the sync */ + if (ramblock_is_pmem(block)) { + pmem_persist(addr, length); + } else +#endif + if (block->fd >= 0) { +#ifdef CONFIG_MSYNC + msync((void *)((uintptr_t)addr & qemu_host_page_mask), + HOST_PAGE_ALIGN(length), MS_SYNC); +#else + qemu_fdatasync(block->fd); +#endif + } +} + /* Called with ram_list.mutex held */ static void dirty_memory_extend(ram_addr_t old_ram_size, ram_addr_t new_ram_size) diff --git a/include/exec/memory.h b/include/exec/memory.h index 2dd810259d..ff0d7937cf 100644 --- a/include/exec/memory.h +++ b/include/exec/memory.h @@ -1242,6 +1242,12 @@ void *memory_region_get_ram_ptr(MemoryRegion *mr); */ void memory_region_ram_resize(MemoryRegion *mr, ram_addr_t newsize, Error **errp); +/** + * memory_region_do_writeback: Trigger writeback for selected address range + * [addr, addr + size] + * + */ +void memory_region_do_writeback(MemoryRegion *mr, hwaddr addr, hwaddr size); /** * memory_region_set_log: Turn dirty logging on or off for a region. diff --git a/include/exec/ram_addr.h b/include/exec/ram_addr.h index a327a80cfe..d4bce81a03 100644 --- a/include/exec/ram_addr.h +++ b/include/exec/ram_addr.h @@ -180,6 +180,12 @@ void qemu_ram_free(RAMBlock *block); int qemu_ram_resize(RAMBlock *block, ram_addr_t newsize, Error **errp); +void qemu_ram_writeback(RAMBlock *block, ram_addr_t start, ram_addr_t length); + +/* Clear whole block of mem */ +#define qemu_ram_block_writeback(rb) \ + qemu_ram_writeback(rb, 0, rb->used_length) + #define DIRTY_CLIENTS_ALL ((1 << DIRTY_MEMORY_NUM) - 1) #define DIRTY_CLIENTS_NOCODE (DIRTY_CLIENTS_ALL & ~(1 << DIRTY_MEMORY_CODE)) diff --git a/memory.c b/memory.c index 61a254c3f9..436eb64737 100644 --- a/memory.c +++ b/memory.c @@ -2228,6 +2228,18 @@ void memory_region_ram_resize(MemoryRegion *mr, ram_addr_t newsize, Error **errp qemu_ram_resize(mr->ram_block, newsize, errp); } + +void memory_region_do_writeback(MemoryRegion *mr, hwaddr addr, hwaddr size) +{ + /* + * Might be extended case needed to cover + * different types of memory regions + */ + if (mr->ram_block && mr->dirty_log_mask) { + qemu_ram_writeback(mr->ram_block, addr, size); + } +} + /* * Call proper memory listeners about the change on the newly * added/removed CoalescedMemoryRange. From patchwork Tue Sep 10 09:56:09 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Beata Michalska X-Patchwork-Id: 11139131 Return-Path: Received: from mail.kernel.org (pdx-korg-mail-1.web.codeaurora.org [172.30.200.123]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id 208C076 for ; Tue, 10 Sep 2019 10:00:34 +0000 (UTC) Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id E81BB20872 for ; Tue, 10 Sep 2019 10:00:33 +0000 (UTC) Authentication-Results: mail.kernel.org; dkim=fail reason="signature verification failed" (2048-bit key) header.d=linaro.org header.i=@linaro.org header.b="sOgF04CL" DMARC-Filter: OpenDMARC Filter v1.3.2 mail.kernel.org E81BB20872 Authentication-Results: mail.kernel.org; dmarc=fail (p=none dis=none) header.from=linaro.org Authentication-Results: mail.kernel.org; spf=pass smtp.mailfrom=qemu-devel-bounces+patchwork-qemu-devel=patchwork.kernel.org@nongnu.org Received: from localhost ([::1]:37118 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1i7cwq-0003yb-GV for patchwork-qemu-devel@patchwork.kernel.org; Tue, 10 Sep 2019 06:00:32 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:50815) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1i7ct2-0008PX-Kl for qemu-devel@nongnu.org; Tue, 10 Sep 2019 05:56:37 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1i7ct1-0002ZE-Ja for qemu-devel@nongnu.org; Tue, 10 Sep 2019 05:56:36 -0400 Received: from mail-wr1-x443.google.com ([2a00:1450:4864:20::443]:41845) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1i7ct1-0002Yr-EW for qemu-devel@nongnu.org; Tue, 10 Sep 2019 05:56:35 -0400 Received: by mail-wr1-x443.google.com with SMTP id h7so17835486wrw.8 for ; Tue, 10 Sep 2019 02:56:35 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=H/RngVVAFC6u7kHobivBuj3t/ObQ9MDzihOX8Ue72qY=; b=sOgF04CL48muksHqhI07dFayZIhWRLSf/gA5sLdj76AxYXFgCzJYG5ATkmGXGL/AVk o2vSMPVxh/xYza11TbARaBim353aGDR1eXDWrUZri2cBSEYjpaXYwPTQwNWRBqr8qS4n 5ruJjwYa+YBQ4CgX6mUqNgPYwfs065pf50IHBQr17V6WvJQIe9WgoW6LIey9y/Xc7FW5 kpKFTvJSoJy+Na2037p6Wd0jMhWwRg9CVtH27nuidwcYr8Uj8cMZanF6rlYXCDYL3hJ9 v2cOBro0+ND8ih3Yc7b3Ch1+jJfZzfNOVjzTDb0aCjdsKsn9WGfsShn6L4XegJWImRVm zHZg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=H/RngVVAFC6u7kHobivBuj3t/ObQ9MDzihOX8Ue72qY=; b=rU9ZkDid0f8KMMotYIf4xxJA3TMftnO/l+Yn6BKAngjFoVQXb+yjoO7i6vpYU7qyeI /m6NuI35zMA+jZ09qQZ491zhNd7xf3ii75pnWbun8O/g1qv7PVwc1vcsfsWkp8DVO0/k CkWEbtcKj6Yr7V5vYBmWpgLPpS8DiA2nkRIWdTRt4p4XAfwPBUmPWokylNJLskNbgOtQ HveZqfrELtT5f1FMwqrZM+bhoKH1dQSzeLp6zypD5nQgmMqoZd4fw95O8MdLDWsHOUFn Ck9L2dSO3CxoODohz8edHBzDqbpbGWGOa4N1se6lEKi9ateJ1DgacFb0CRVjEfLXO+mV 3liw== X-Gm-Message-State: APjAAAXh8gv3oOOiI/wngCGvfHilKLVLHAiHWtbRf9zmhQsc7popLlE8 1fC5CRC0g5QjvmYxSURT2b5A5yoXg+Y= X-Google-Smtp-Source: APXvYqynw70k2L8t8RmowQsUvN0lBgXakfaLuEGPmfoG2F/QkQFiC2CaQbvl9xzj5KI2IW0HFQ+2Bw== X-Received: by 2002:adf:df8e:: with SMTP id z14mr26631987wrl.81.1568109394391; Tue, 10 Sep 2019 02:56:34 -0700 (PDT) Received: from moi-XPS-13-9350.arm.com (host86-144-13-57.range86-144.btcentralplus.com. [86.144.13.57]) by smtp.gmail.com with ESMTPSA id e30sm32403540wra.48.2019.09.10.02.56.33 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 10 Sep 2019 02:56:34 -0700 (PDT) From: Beata Michalska To: qemu-devel@nongnu.org Date: Tue, 10 Sep 2019 11:56:09 +0200 Message-Id: <20190910095610.4546-4-beata.michalska@linaro.org> In-Reply-To: <20190910095610.4546-1-beata.michalska@linaro.org> References: <20190910095610.4546-1-beata.michalska@linaro.org> X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2a00:1450:4864:20::443 Subject: [Qemu-devel] [PATCH 3/4] migration: ram: Switch to ram block writeback X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: peter.maydell@linaro.org, Beata Michalska , quintela@redhat.com, richard.henderson@linaro.org, dgilbert@redhat.com, shameerali.kolothum.thodi@huawei.com, eric.auger@redhat.com, qemu-arm@nongnu.org, pbonzini@redhat.com Errors-To: qemu-devel-bounces+patchwork-qemu-devel=patchwork.kernel.org@nongnu.org Sender: "Qemu-devel" Switch to ram block writeback for pmem migration. Signed-off-by: Beata Michalska Reviewed-by: Richard Henderson --- migration/ram.c | 5 +---- 1 file changed, 1 insertion(+), 4 deletions(-) diff --git a/migration/ram.c b/migration/ram.c index b01a37e7ca..8ea0bd63fc 100644 --- a/migration/ram.c +++ b/migration/ram.c @@ -33,7 +33,6 @@ #include "qemu/bitops.h" #include "qemu/bitmap.h" #include "qemu/main-loop.h" -#include "qemu/pmem.h" #include "xbzrle.h" #include "ram.h" #include "migration.h" @@ -4064,9 +4063,7 @@ static int ram_load_cleanup(void *opaque) RAMBlock *rb; RAMBLOCK_FOREACH_NOT_IGNORED(rb) { - if (ramblock_is_pmem(rb)) { - pmem_persist(rb->host, rb->used_length); - } + qemu_ram_block_writeback(rb); } xbzrle_load_cleanup(); From patchwork Tue Sep 10 09:56:10 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Beata Michalska X-Patchwork-Id: 11139143 Return-Path: Received: from mail.kernel.org (pdx-korg-mail-1.web.codeaurora.org [172.30.200.123]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id DF0961709 for ; Tue, 10 Sep 2019 10:03:42 +0000 (UTC) Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id B57D12067B for ; Tue, 10 Sep 2019 10:03:42 +0000 (UTC) Authentication-Results: mail.kernel.org; dkim=fail reason="signature verification failed" (2048-bit key) header.d=linaro.org header.i=@linaro.org header.b="jTgkrQt5" DMARC-Filter: OpenDMARC Filter v1.3.2 mail.kernel.org B57D12067B Authentication-Results: mail.kernel.org; dmarc=fail (p=none dis=none) header.from=linaro.org Authentication-Results: mail.kernel.org; spf=pass smtp.mailfrom=qemu-devel-bounces+patchwork-qemu-devel=patchwork.kernel.org@nongnu.org Received: from localhost ([::1]:37228 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1i7czt-0006Vk-Pr for patchwork-qemu-devel@patchwork.kernel.org; Tue, 10 Sep 2019 06:03:41 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:50845) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1i7ct4-0008Qx-7d for qemu-devel@nongnu.org; Tue, 10 Sep 2019 05:56:39 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1i7ct2-0002aB-NK for qemu-devel@nongnu.org; Tue, 10 Sep 2019 05:56:38 -0400 Received: from mail-wr1-x444.google.com ([2a00:1450:4864:20::444]:38987) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1i7ct2-0002ZQ-H0 for qemu-devel@nongnu.org; Tue, 10 Sep 2019 05:56:36 -0400 Received: by mail-wr1-x444.google.com with SMTP id t16so18858107wra.6 for ; Tue, 10 Sep 2019 02:56:36 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=/WkGeJeyqUUlCOczegoffHH2fd/jiOdQ19K334OwQps=; b=jTgkrQt59w/pre1I46EQAUjxt8DCKTxmaxlpcf9syvSBT7ompVeqAOzKH0CL6/6YL/ +5SZnkv0jxVYkEZf5z8vUXGR4Go+4f1h/LYWmnquSM8HLaGL7QClyAmgzbD0w+ODkcUV lej1x1+cOCrfqvT7VxAIw/q9E5BgylwNZkckZSvxTPUUkCLxqmROL+eFBTMmAWsTllnm wEbfljjujfsNug58Mchqlwf5aGpCSzxe68D80lN658zR7NJG7w9fKu6kfNF9Ck2Pq7fJ sEVOhLB292LEldEs+we1forGceN66iAbKkm5I84kDrtPLtXcwjA526is51RM4moyfhcm 3xQg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=/WkGeJeyqUUlCOczegoffHH2fd/jiOdQ19K334OwQps=; b=Zg/FDfbmV4UPlZyKPfsmD7lYHKp/1EaIOzpnzuOFln6Ey3GRs1Zy8uy3BX/ahgRKe2 lz63kyqxvWNwsB1Jb+m6ta+svvBSITCZw7AdxGH6buyT+NWVTpToN5qPiATuzwd0EmK5 1xzL57w8kaslimlGKbBe5F5jxonX24W/qwGzhaLL/Ci3YMTtSTI6jPegGhxNFwhNjdvI /WzcE951qv0lSt9KPNZHJw1S0HRPQ99QGxiyBWzXhnPG2L01tF9bp69xBF+X3bQ0ZP+f b3s4hN3VoHJwzl4EgX59inbnvIlLU10nfCHedNmb2n3tW2FgSqqAsZVihTSa5V0OAXc6 RNng== X-Gm-Message-State: APjAAAWX/tc1KVpspLPv3dE5oL/CeDu44isY75BylSLAwMnTyJnI6/Pg Wa84XaNsICCaUd41WEz76rBJoOZDkCo= X-Google-Smtp-Source: APXvYqx2OPSNgpET+wL+51IIk442Ef5L4Pb4tyGh6ETgD0zBrAEjyRSybWCowI1vjcXyTBglPJzS7w== X-Received: by 2002:a5d:678a:: with SMTP id v10mr24800537wru.145.1568109395309; Tue, 10 Sep 2019 02:56:35 -0700 (PDT) Received: from moi-XPS-13-9350.arm.com (host86-144-13-57.range86-144.btcentralplus.com. [86.144.13.57]) by smtp.gmail.com with ESMTPSA id e30sm32403540wra.48.2019.09.10.02.56.34 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 10 Sep 2019 02:56:34 -0700 (PDT) From: Beata Michalska To: qemu-devel@nongnu.org Date: Tue, 10 Sep 2019 11:56:10 +0200 Message-Id: <20190910095610.4546-5-beata.michalska@linaro.org> In-Reply-To: <20190910095610.4546-1-beata.michalska@linaro.org> References: <20190910095610.4546-1-beata.michalska@linaro.org> X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2a00:1450:4864:20::444 Subject: [Qemu-devel] [PATCH 4/4] target/arm: Add support for DC CVAP & DC CVADP ins X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: peter.maydell@linaro.org, Beata Michalska , quintela@redhat.com, richard.henderson@linaro.org, dgilbert@redhat.com, shameerali.kolothum.thodi@huawei.com, eric.auger@redhat.com, qemu-arm@nongnu.org, pbonzini@redhat.com Errors-To: qemu-devel-bounces+patchwork-qemu-devel=patchwork.kernel.org@nongnu.org Sender: "Qemu-devel" ARMv8.2 introduced support for Data Cache Clean instructions to PoP (point-of-persistence) - DC CVAP and PoDP (point-of-deep-persistence) - DV CVADP. Both specify conceptual points in a memory system where all writes that are to reach them are considered persistent. The support provided considers both to be actually the same so there is no distinction between the two. If none is available (there is no backing store for given memory) both will result in Data Cache Clean up to the point of coherency. Otherwise sync for the specified range shall be performed. Signed-off-by: Beata Michalska --- linux-user/elfload.c | 18 +++++++++++++++++- target/arm/cpu.h | 13 ++++++++++++- target/arm/cpu64.c | 1 + target/arm/helper.c | 24 ++++++++++++++++++++++++ target/arm/helper.h | 1 + target/arm/op_helper.c | 36 ++++++++++++++++++++++++++++++++++++ target/arm/translate-a64.c | 5 +++++ 7 files changed, 96 insertions(+), 2 deletions(-) diff --git a/linux-user/elfload.c b/linux-user/elfload.c index 3365e192eb..1ec00308d5 100644 --- a/linux-user/elfload.c +++ b/linux-user/elfload.c @@ -609,7 +609,12 @@ enum { ARM_HWCAP_A64_PACG = 1UL << 31, }; +enum { + ARM_HWCAP2_A64_DCPODP = 1 << 0, +}; + #define ELF_HWCAP get_elf_hwcap() +#define ELF_HWCAP2 get_elf_hwcap2() static uint32_t get_elf_hwcap(void) { @@ -644,12 +649,23 @@ static uint32_t get_elf_hwcap(void) GET_FEATURE_ID(aa64_jscvt, ARM_HWCAP_A64_JSCVT); GET_FEATURE_ID(aa64_sb, ARM_HWCAP_A64_SB); GET_FEATURE_ID(aa64_condm_4, ARM_HWCAP_A64_FLAGM); + GET_FEATURE_ID(aa64_dcpop, ARM_HWCAP_A64_DCPOP); -#undef GET_FEATURE_ID return hwcaps; } +static uint32_t get_elf_hwcap2(void) +{ + ARMCPU *cpu = ARM_CPU(thread_cpu); + uint32_t hwcaps = 0; + + GET_FEATURE_ID(aa64_dcpodp, ARM_HWCAP2_A64_DCPODP); + return hwcaps; +} + +#undef GET_FEATURE_ID + #endif /* not TARGET_AARCH64 */ #endif /* TARGET_ARM */ diff --git a/target/arm/cpu.h b/target/arm/cpu.h index 297ad5e47a..1713d76590 100644 --- a/target/arm/cpu.h +++ b/target/arm/cpu.h @@ -2229,7 +2229,8 @@ static inline uint64_t cpreg_to_kvm_id(uint32_t cpregid) #define ARM_CP_NZCV (ARM_CP_SPECIAL | 0x0300) #define ARM_CP_CURRENTEL (ARM_CP_SPECIAL | 0x0400) #define ARM_CP_DC_ZVA (ARM_CP_SPECIAL | 0x0500) -#define ARM_LAST_SPECIAL ARM_CP_DC_ZVA +#define ARM_CP_DC_CVAP (ARM_CP_SPECIAL | 0x0600) +#define ARM_LAST_SPECIAL ARM_CP_DC_CVAP #define ARM_CP_FPU 0x1000 #define ARM_CP_SVE 0x2000 #define ARM_CP_NO_GDB 0x4000 @@ -3572,6 +3573,16 @@ static inline bool isar_feature_aa64_frint(const ARMISARegisters *id) return FIELD_EX64(id->id_aa64isar1, ID_AA64ISAR1, FRINTTS) != 0; } +static inline bool isar_feature_aa64_dcpop(const ARMISARegisters *id) +{ + return FIELD_EX64(id->id_aa64isar1, ID_AA64ISAR1, DPB) != 0; +} + +static inline bool isar_feature_aa64_dcpodp(const ARMISARegisters *id) +{ + return (FIELD_EX64(id->id_aa64isar1, ID_AA64ISAR1, DPB) >> 1) != 0; +} + static inline bool isar_feature_aa64_fp16(const ARMISARegisters *id) { /* We always set the AdvSIMD and FP fields identically wrt FP16. */ diff --git a/target/arm/cpu64.c b/target/arm/cpu64.c index d7f5bf610a..20094f980d 100644 --- a/target/arm/cpu64.c +++ b/target/arm/cpu64.c @@ -331,6 +331,7 @@ static void aarch64_max_initfn(Object *obj) cpu->isar.id_aa64isar0 = t; t = cpu->isar.id_aa64isar1; + t = FIELD_DP64(t, ID_AA64ISAR1, DPB, 2); t = FIELD_DP64(t, ID_AA64ISAR1, JSCVT, 1); t = FIELD_DP64(t, ID_AA64ISAR1, FCMA, 1); t = FIELD_DP64(t, ID_AA64ISAR1, APA, 1); /* PAuth, architected only */ diff --git a/target/arm/helper.c b/target/arm/helper.c index 507026c915..99ae01b7e7 100644 --- a/target/arm/helper.c +++ b/target/arm/helper.c @@ -3843,6 +3843,22 @@ static CPAccessResult aa64_cacheop_access(CPUARMState *env, return CP_ACCESS_OK; } +static CPAccessResult aa64_cacheop_persist_access(CPUARMState *env, + const ARMCPRegInfo *ri, + bool isread) +{ + ARMCPU *cpu = env_archcpu(env); + /* + * Access is UNDEF if lacking implementation for either DC CVAP or DC CVADP + * DC CVAP -> CRm: 0xc + * DC CVADP -> CRm: 0xd + */ + return (ri->crm == 0xc && !cpu_isar_feature(aa64_dcpop, cpu)) || + (ri->crm == 0xd && !cpu_isar_feature(aa64_dcpodp, cpu)) + ? CP_ACCESS_TRAP_UNCATEGORIZED + : aa64_cacheop_access(env, ri, isread); +} + /* See: D4.7.2 TLB maintenance requirements and the TLB maintenance instructions * Page D4-1736 (DDI0487A.b) */ @@ -4251,6 +4267,14 @@ static const ARMCPRegInfo v8_cp_reginfo[] = { .opc0 = 1, .opc1 = 3, .crn = 7, .crm = 10, .opc2 = 1, .access = PL0_W, .type = ARM_CP_NOP, .accessfn = aa64_cacheop_access }, + { .name = "DC_CVAP", .state = ARM_CP_STATE_AA64, + .opc0 = 1, .opc1 = 3, .crn = 7, .crm = 12, .opc2 = 1, + .access = PL0_W, .type = ARM_CP_DC_CVAP, + .accessfn = aa64_cacheop_persist_access }, + { .name = "DC_CVADP", .state = ARM_CP_STATE_AA64, + .opc0 = 1, .opc1 = 3, .crn = 7, .crm = 13, .opc2 = 1, + .access = PL0_W, .type = ARM_CP_DC_CVAP, + .accessfn = aa64_cacheop_persist_access }, { .name = "DC_CSW", .state = ARM_CP_STATE_AA64, .opc0 = 1, .opc1 = 0, .crn = 7, .crm = 10, .opc2 = 2, .access = PL1_W, .type = ARM_CP_NOP }, diff --git a/target/arm/helper.h b/target/arm/helper.h index 1fb2cb5a77..a850364944 100644 --- a/target/arm/helper.h +++ b/target/arm/helper.h @@ -561,6 +561,7 @@ DEF_HELPER_FLAGS_3(crypto_sm4ekey, TCG_CALL_NO_RWG, void, ptr, ptr, ptr) DEF_HELPER_FLAGS_3(crc32, TCG_CALL_NO_RWG_SE, i32, i32, i32, i32) DEF_HELPER_FLAGS_3(crc32c, TCG_CALL_NO_RWG_SE, i32, i32, i32, i32) DEF_HELPER_2(dc_zva, void, env, i64) +DEF_HELPER_2(dc_cvap, void, env, i64) DEF_HELPER_FLAGS_2(neon_pmull_64_lo, TCG_CALL_NO_RWG_SE, i64, i64, i64) DEF_HELPER_FLAGS_2(neon_pmull_64_hi, TCG_CALL_NO_RWG_SE, i64, i64, i64) diff --git a/target/arm/op_helper.c b/target/arm/op_helper.c index 0fd4bd0238..75ebf6afa4 100644 --- a/target/arm/op_helper.c +++ b/target/arm/op_helper.c @@ -987,3 +987,39 @@ void HELPER(dc_zva)(CPUARMState *env, uint64_t vaddr_in) memset(g2h(vaddr), 0, blocklen); #endif } + +void HELPER(dc_cvap)(CPUARMState *env, uint64_t vaddr_in) +{ +#ifndef CONFIG_USER_ONLY + ARMCPU *cpu = env_archcpu(env); + /* CTR_EL0 System register -> DminLine, bits [19:16] */ + uint64_t dline_size = 4 << ((cpu->ctr >> 16) & 0xF); + uint64_t vaddr = vaddr_in & ~(dline_size - 1); + void *haddr; + int mem_idx = cpu_mmu_index(env, false); + + /* This won't be crossing page boundaries */ + haddr = probe_read(env, vaddr, dline_size, mem_idx, GETPC()); + if (haddr) { + + ram_addr_t offset; + MemoryRegion *mr; + + /* + * RCU critical section + ref counting, + * so that MR won't disappear behind the scene + */ + rcu_read_lock(); + mr = memory_region_from_host(haddr, &offset); + if (mr) { + memory_region_ref(mr); + } + rcu_read_unlock(); + + if (mr) { + memory_region_do_writeback(mr, offset, dline_size); + memory_region_unref(mr); + } + } +#endif +} diff --git a/target/arm/translate-a64.c b/target/arm/translate-a64.c index 2d6cd09634..21ea3631d6 100644 --- a/target/arm/translate-a64.c +++ b/target/arm/translate-a64.c @@ -1746,6 +1746,11 @@ static void handle_sys(DisasContext *s, uint32_t insn, bool isread, tcg_rt = cpu_reg(s, rt); gen_helper_dc_zva(cpu_env, tcg_rt); return; + case ARM_CP_DC_CVAP: + /* DC CVAP / DC CVADP */ + tcg_rt = cpu_reg(s, rt); + gen_helper_dc_cvap(cpu_env, tcg_rt); + return; default: break; }