From patchwork Thu Sep 12 13:26:04 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Tero Kristo X-Patchwork-Id: 11143035 Return-Path: Received: from mail.kernel.org (pdx-korg-mail-1.web.codeaurora.org [172.30.200.123]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id 062B81599 for ; Thu, 12 Sep 2019 13:26:29 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.kernel.org (Postfix) with ESMTP id CF71520CC7 for ; Thu, 12 Sep 2019 13:26:28 +0000 (UTC) Authentication-Results: mail.kernel.org; dkim=pass (1024-bit key) header.d=ti.com header.i=@ti.com header.b="XxLUX4Yt" Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1731840AbfILN02 (ORCPT ); Thu, 12 Sep 2019 09:26:28 -0400 Received: from lelv0142.ext.ti.com ([198.47.23.249]:38344 "EHLO lelv0142.ext.ti.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1732098AbfILN02 (ORCPT ); Thu, 12 Sep 2019 09:26:28 -0400 Received: from fllv0035.itg.ti.com ([10.64.41.0]) by lelv0142.ext.ti.com (8.15.2/8.15.2) with ESMTP id x8CDQLB7021179; Thu, 12 Sep 2019 08:26:21 -0500 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=ti.com; s=ti-com-17Q1; t=1568294781; bh=ZhhtgfHz1PpryANYuepNGwQFWlONDXmjaSxUGLbbF0g=; h=From:To:CC:Subject:Date:In-Reply-To:References; b=XxLUX4Yteuu2XXr6dA3aF5yRzFMY/r5k4y1Cvwcisk7dvn1rs2zxqkAJf094+UqUR VyYeH6wQ3cLiCjoOIu7eaK8noT9nlXSsvHl9KF5Y13hJ5I3Dgfx2HEaBHIeYyY8rBa x7mE12ul4RmeQu6rSSpg+fmCfSwcqe78xAO65xZw= Received: from DFLE112.ent.ti.com (dfle112.ent.ti.com [10.64.6.33]) by fllv0035.itg.ti.com (8.15.2/8.15.2) with ESMTP id x8CDQLDe070947; Thu, 12 Sep 2019 08:26:21 -0500 Received: from DFLE101.ent.ti.com (10.64.6.22) by DFLE112.ent.ti.com (10.64.6.33) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.1713.5; Thu, 12 Sep 2019 08:26:19 -0500 Received: from lelv0326.itg.ti.com (10.180.67.84) by DFLE101.ent.ti.com (10.64.6.22) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.1713.5 via Frontend Transport; Thu, 12 Sep 2019 08:26:19 -0500 Received: from sokoban.bb.dnainternet.fi (ileax41-snat.itg.ti.com [10.172.224.153]) by lelv0326.itg.ti.com (8.15.2/8.15.2) with ESMTP id x8CDQFvQ130575; Thu, 12 Sep 2019 08:26:18 -0500 From: Tero Kristo To: , , , CC: , Subject: [PATCHv3 01/10] clk: ti: clkctrl: fix setting up clkctrl clocks Date: Thu, 12 Sep 2019 16:26:04 +0300 Message-ID: <20190912132613.28093-2-t-kristo@ti.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20190912132613.28093-1-t-kristo@ti.com> References: <20190912132613.28093-1-t-kristo@ti.com> MIME-Version: 1.0 X-EXCLAIMER-MD-CONFIG: e1e8a2fd-e40a-4ac6-ac9b-f7e9cc9ee180 Sender: linux-clk-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-clk@vger.kernel.org Apply the proper register function for clkctrl clocks, so they get registered under the clk_hw_omap list also. This allows checking their type runtime. Signed-off-by: Tero Kristo --- drivers/clk/ti/clkctrl.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/clk/ti/clkctrl.c b/drivers/clk/ti/clkctrl.c index 975995eea15c..a914df2e9e1b 100644 --- a/drivers/clk/ti/clkctrl.c +++ b/drivers/clk/ti/clkctrl.c @@ -622,7 +622,7 @@ static void __init _ti_omap4_clkctrl_setup(struct device_node *node) init.ops = &omap4_clkctrl_clk_ops; hw->hw.init = &init; - clk = ti_clk_register(NULL, &hw->hw, init.name); + clk = ti_clk_register_omap_hw(NULL, &hw->hw, init.name); if (IS_ERR_OR_NULL(clk)) goto cleanup; From patchwork Thu Sep 12 13:26:05 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Tero Kristo X-Patchwork-Id: 11143029 Return-Path: Received: from mail.kernel.org (pdx-korg-mail-1.web.codeaurora.org [172.30.200.123]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id 82A6518A6 for ; Thu, 12 Sep 2019 13:26:26 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.kernel.org (Postfix) with ESMTP id 612AC20856 for ; Thu, 12 Sep 2019 13:26:26 +0000 (UTC) Authentication-Results: mail.kernel.org; dkim=pass (1024-bit key) header.d=ti.com header.i=@ti.com header.b="i8ULB+Ix" Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1732092AbfILN00 (ORCPT ); Thu, 12 Sep 2019 09:26:26 -0400 Received: from fllv0016.ext.ti.com ([198.47.19.142]:58626 "EHLO fllv0016.ext.ti.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1732093AbfILN0Z (ORCPT ); Thu, 12 Sep 2019 09:26:25 -0400 Received: from lelv0266.itg.ti.com ([10.180.67.225]) by fllv0016.ext.ti.com (8.15.2/8.15.2) with ESMTP id x8CDQLWI098812; Thu, 12 Sep 2019 08:26:22 -0500 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=ti.com; s=ti-com-17Q1; t=1568294782; bh=CA2p2SsjZBiZ+CVSDGSdF5T0f2itSmxPDgeQXhbNBGw=; h=From:To:CC:Subject:Date:In-Reply-To:References; b=i8ULB+Ix1oWkHXvDa0mX83DFG6PpwzNIxqizHnbem4PYzTeNpIsk0HziVdm52WNNu PQjnNkJnPBDvHUbYds7jlgu/KXHnHdT9D+XYkxM/I4biycl5UKdGoqJ7x0hc/JtnRU 81Fwomulf7qgS0fPGE6EKwRufGbUDh12qPtGi/g8= Received: from DFLE109.ent.ti.com (dfle109.ent.ti.com [10.64.6.30]) by lelv0266.itg.ti.com (8.15.2/8.15.2) with ESMTPS id x8CDQLuX015180 (version=TLSv1.2 cipher=AES256-GCM-SHA384 bits=256 verify=FAIL); Thu, 12 Sep 2019 08:26:21 -0500 Received: from DFLE112.ent.ti.com (10.64.6.33) by DFLE109.ent.ti.com (10.64.6.30) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.1713.5; Thu, 12 Sep 2019 08:26:21 -0500 Received: from lelv0326.itg.ti.com (10.180.67.84) by DFLE112.ent.ti.com (10.64.6.33) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.1713.5 via Frontend Transport; Thu, 12 Sep 2019 08:26:21 -0500 Received: from sokoban.bb.dnainternet.fi (ileax41-snat.itg.ti.com [10.172.224.153]) by lelv0326.itg.ti.com (8.15.2/8.15.2) with ESMTP id x8CDQFvR130575; Thu, 12 Sep 2019 08:26:20 -0500 From: Tero Kristo To: , , , CC: , Subject: [PATCHv3 02/10] clk: ti: clkctrl: convert to use bit helper macros instead of bitops Date: Thu, 12 Sep 2019 16:26:05 +0300 Message-ID: <20190912132613.28093-3-t-kristo@ti.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20190912132613.28093-1-t-kristo@ti.com> References: <20190912132613.28093-1-t-kristo@ti.com> MIME-Version: 1.0 X-EXCLAIMER-MD-CONFIG: e1e8a2fd-e40a-4ac6-ac9b-f7e9cc9ee180 Sender: linux-clk-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-clk@vger.kernel.org This improves the readibility of the code slightly, and makes modifying the flags bit simpler. Signed-off-by: Tero Kristo --- drivers/clk/ti/clkctrl.c | 8 ++++---- include/linux/clk/ti.h | 2 +- 2 files changed, 5 insertions(+), 5 deletions(-) diff --git a/drivers/clk/ti/clkctrl.c b/drivers/clk/ti/clkctrl.c index a914df2e9e1b..d904a9a7626a 100644 --- a/drivers/clk/ti/clkctrl.c +++ b/drivers/clk/ti/clkctrl.c @@ -24,7 +24,7 @@ #include #include "clock.h" -#define NO_IDLEST 0x1 +#define NO_IDLEST 0 #define OMAP4_MODULEMODE_MASK 0x3 @@ -158,7 +158,7 @@ static int _omap4_clkctrl_clk_enable(struct clk_hw *hw) ti_clk_ll_ops->clk_writel(val, &clk->enable_reg); - if (clk->flags & NO_IDLEST) + if (test_bit(NO_IDLEST, &clk->flags)) return 0; /* Wait until module is enabled */ @@ -187,7 +187,7 @@ static void _omap4_clkctrl_clk_disable(struct clk_hw *hw) ti_clk_ll_ops->clk_writel(val, &clk->enable_reg); - if (clk->flags & NO_IDLEST) + if (test_bit(NO_IDLEST, &clk->flags)) goto exit; /* Wait until module is disabled */ @@ -596,7 +596,7 @@ static void __init _ti_omap4_clkctrl_setup(struct device_node *node) if (reg_data->flags & CLKF_HW_SUP) hw->enable_bit = MODULEMODE_HWCTRL; if (reg_data->flags & CLKF_NO_IDLEST) - hw->flags |= NO_IDLEST; + set_bit(NO_IDLEST, &hw->flags); if (reg_data->clkdm_name) hw->clkdm_name = reg_data->clkdm_name; diff --git a/include/linux/clk/ti.h b/include/linux/clk/ti.h index 1e8ef96555ce..bb2c5af9082a 100644 --- a/include/linux/clk/ti.h +++ b/include/linux/clk/ti.h @@ -153,7 +153,7 @@ struct clk_hw_omap { u8 fixed_div; struct clk_omap_reg enable_reg; u8 enable_bit; - u8 flags; + unsigned long flags; struct clk_omap_reg clksel_reg; struct dpll_data *dpll_data; const char *clkdm_name; From patchwork Thu Sep 12 13:26:06 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Tero Kristo X-Patchwork-Id: 11143033 Return-Path: Received: from mail.kernel.org (pdx-korg-mail-1.web.codeaurora.org [172.30.200.123]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id B8A4C16B1 for ; Thu, 12 Sep 2019 13:26:28 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.kernel.org (Postfix) with ESMTP id 97B2920CC7 for ; Thu, 12 Sep 2019 13:26:28 +0000 (UTC) Authentication-Results: mail.kernel.org; dkim=pass (1024-bit key) header.d=ti.com header.i=@ti.com header.b="A8JSNdgo" Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1732100AbfILN02 (ORCPT ); Thu, 12 Sep 2019 09:26:28 -0400 Received: from fllv0015.ext.ti.com ([198.47.19.141]:59656 "EHLO fllv0015.ext.ti.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1732093AbfILN02 (ORCPT ); Thu, 12 Sep 2019 09:26:28 -0400 Received: from lelv0266.itg.ti.com ([10.180.67.225]) by fllv0015.ext.ti.com (8.15.2/8.15.2) with ESMTP id x8CDQOf6011927; Thu, 12 Sep 2019 08:26:24 -0500 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=ti.com; s=ti-com-17Q1; t=1568294784; bh=+qrcnaR3a/pZ4OviE1ZKc8IWLJlt6Yebqe6i5IEbb64=; h=From:To:CC:Subject:Date:In-Reply-To:References; b=A8JSNdgohFwtatBw+XFGPRUpp2hpxdX9Lq/w1OAb8zjFsNSw2NFg5fa9oTYnUyffx 1tc2kKk3P/zmQ8sg8AxTe2ZrKhzzWUymfUjvgYFUgLaDzllGjP1AdFR4RB0vu6ettW qzTflc3wR7sZDCpRiz2RJnIfKvtI/8xWJDLlnyZw= Received: from DLEE108.ent.ti.com (dlee108.ent.ti.com [157.170.170.38]) by lelv0266.itg.ti.com (8.15.2/8.15.2) with ESMTPS id x8CDQOKw015237 (version=TLSv1.2 cipher=AES256-GCM-SHA384 bits=256 verify=FAIL); Thu, 12 Sep 2019 08:26:24 -0500 Received: from DLEE110.ent.ti.com (157.170.170.21) by DLEE108.ent.ti.com (157.170.170.38) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.1713.5; Thu, 12 Sep 2019 08:26:23 -0500 Received: from lelv0326.itg.ti.com (10.180.67.84) by DLEE110.ent.ti.com (157.170.170.21) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.1713.5 via Frontend Transport; Thu, 12 Sep 2019 08:26:23 -0500 Received: from sokoban.bb.dnainternet.fi (ileax41-snat.itg.ti.com [10.172.224.153]) by lelv0326.itg.ti.com (8.15.2/8.15.2) with ESMTP id x8CDQFvS130575; Thu, 12 Sep 2019 08:26:21 -0500 From: Tero Kristo To: , , , CC: , Subject: [PATCHv3 03/10] clk: ti: clkctrl: add new exported API for checking standby info Date: Thu, 12 Sep 2019 16:26:06 +0300 Message-ID: <20190912132613.28093-4-t-kristo@ti.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20190912132613.28093-1-t-kristo@ti.com> References: <20190912132613.28093-1-t-kristo@ti.com> MIME-Version: 1.0 X-EXCLAIMER-MD-CONFIG: e1e8a2fd-e40a-4ac6-ac9b-f7e9cc9ee180 Sender: linux-clk-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-clk@vger.kernel.org Standby status is provided for certain clkctrl clocks to see if the given module has entered standby or not. This is mostly needed by remoteproc code to see if the remoteproc has entered standby and the clock can be turned off safely. Signed-off-by: Tero Kristo --- drivers/clk/ti/clkctrl.c | 33 +++++++++++++++++++++++++++++++++ include/linux/clk/ti.h | 1 + 2 files changed, 34 insertions(+) diff --git a/drivers/clk/ti/clkctrl.c b/drivers/clk/ti/clkctrl.c index d904a9a7626a..e3e0a66a6ce2 100644 --- a/drivers/clk/ti/clkctrl.c +++ b/drivers/clk/ti/clkctrl.c @@ -34,6 +34,9 @@ #define OMAP4_IDLEST_MASK (0x3 << 16) #define OMAP4_IDLEST_SHIFT 16 +#define OMAP4_STBYST_MASK BIT(18) +#define OMAP4_STBYST_SHIFT 18 + #define CLKCTRL_IDLEST_FUNCTIONAL 0x0 #define CLKCTRL_IDLEST_INTERFACE_IDLE 0x2 #define CLKCTRL_IDLEST_DISABLED 0x3 @@ -647,3 +650,33 @@ static void __init _ti_omap4_clkctrl_setup(struct device_node *node) } CLK_OF_DECLARE(ti_omap4_clkctrl_clock, "ti,clkctrl", _ti_omap4_clkctrl_setup); + +/** + * ti_clk_is_in_standby - Check if clkctrl clock is in standby or not + * @clk: clock to check standby status for + * + * Finds whether the provided clock is in standby mode or not. Returns + * true if the provided clock is a clkctrl type clock and it is in standby, + * false otherwise. + */ +u32 ti_clk_is_in_standby(struct clk *clk) +{ + struct clk_hw *hw; + struct clk_hw_omap *hwclk; + u32 val; + + hw = __clk_get_hw(clk); + + if (!omap2_clk_is_hw_omap(hw)) + return false; + + hwclk = to_clk_hw_omap(hw); + + val = ti_clk_ll_ops->clk_readl(&hwclk->enable_reg); + + if (val & OMAP4_STBYST_MASK) + return true; + + return false; +} +EXPORT_SYMBOL_GPL(ti_clk_is_in_standby); diff --git a/include/linux/clk/ti.h b/include/linux/clk/ti.h index bb2c5af9082a..3fb777f7103a 100644 --- a/include/linux/clk/ti.h +++ b/include/linux/clk/ti.h @@ -298,6 +298,7 @@ struct ti_clk_features { void ti_clk_setup_features(struct ti_clk_features *features); const struct ti_clk_features *ti_clk_get_features(void); +u32 ti_clk_is_in_standby(struct clk *clk); int omap3_noncore_dpll_save_context(struct clk_hw *hw); void omap3_noncore_dpll_restore_context(struct clk_hw *hw); From patchwork Thu Sep 12 13:26:07 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Tero Kristo X-Patchwork-Id: 11143041 Return-Path: Received: from mail.kernel.org (pdx-korg-mail-1.web.codeaurora.org [172.30.200.123]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id 3417716B1 for ; Thu, 12 Sep 2019 13:26:33 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.kernel.org (Postfix) with ESMTP id 081A620CC7 for ; Thu, 12 Sep 2019 13:26:33 +0000 (UTC) Authentication-Results: mail.kernel.org; dkim=pass (1024-bit key) header.d=ti.com header.i=@ti.com header.b="xa4D904r" Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1732102AbfILN0c (ORCPT ); Thu, 12 Sep 2019 09:26:32 -0400 Received: from fllv0016.ext.ti.com ([198.47.19.142]:58654 "EHLO fllv0016.ext.ti.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1732098AbfILN0c (ORCPT ); Thu, 12 Sep 2019 09:26:32 -0400 Received: from fllv0035.itg.ti.com ([10.64.41.0]) by fllv0016.ext.ti.com (8.15.2/8.15.2) with ESMTP id x8CDQPAX098827; Thu, 12 Sep 2019 08:26:25 -0500 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=ti.com; s=ti-com-17Q1; t=1568294785; bh=lAooCRUVMyzHhADwC9qZkva36ihXtVfNEPnWC8n4rlE=; h=From:To:CC:Subject:Date:In-Reply-To:References; b=xa4D904r3oRK+1nEn52YVgjGmPidk5ijrBjzLkWOvyTmR7rVxeOglRiNFtZfUcPFc HPEbt19lBHXtJ/NoV56yvBVtKc3/wNY/n/j01u64WRM2zrVt+CoYep2ufJ/VnCJRHa P4bf7EKEwNAjBr7i9XTJqKL56tnezMGyWOFxpW38= Received: from DFLE113.ent.ti.com (dfle113.ent.ti.com [10.64.6.34]) by fllv0035.itg.ti.com (8.15.2/8.15.2) with ESMTP id x8CDQPNl071069; Thu, 12 Sep 2019 08:26:25 -0500 Received: from DFLE114.ent.ti.com (10.64.6.35) by DFLE113.ent.ti.com (10.64.6.34) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.1713.5; Thu, 12 Sep 2019 08:26:25 -0500 Received: from lelv0326.itg.ti.com (10.180.67.84) by DFLE114.ent.ti.com (10.64.6.35) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.1713.5 via Frontend Transport; Thu, 12 Sep 2019 08:26:25 -0500 Received: from sokoban.bb.dnainternet.fi (ileax41-snat.itg.ti.com [10.172.224.153]) by lelv0326.itg.ti.com (8.15.2/8.15.2) with ESMTP id x8CDQFvT130575; Thu, 12 Sep 2019 08:26:23 -0500 From: Tero Kristo To: , , , CC: , Subject: [PATCHv3 04/10] dt-bindings: clk: add omap5 iva clkctrl definitions Date: Thu, 12 Sep 2019 16:26:07 +0300 Message-ID: <20190912132613.28093-5-t-kristo@ti.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20190912132613.28093-1-t-kristo@ti.com> References: <20190912132613.28093-1-t-kristo@ti.com> MIME-Version: 1.0 X-EXCLAIMER-MD-CONFIG: e1e8a2fd-e40a-4ac6-ac9b-f7e9cc9ee180 Sender: linux-clk-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-clk@vger.kernel.org OMAP5 device contains an IVA subsystem (Image and Video Accelerator.) IVA subsystem clkctrl definitions are currently missing, so add them. Signed-off-by: Tero Kristo --- include/dt-bindings/clock/omap5.h | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/include/dt-bindings/clock/omap5.h b/include/dt-bindings/clock/omap5.h index f3283957f48d..eb6d2fbe78f9 100644 --- a/include/dt-bindings/clock/omap5.h +++ b/include/dt-bindings/clock/omap5.h @@ -86,6 +86,10 @@ #define OMAP5_UART5_CLKCTRL OMAP5_CLKCTRL_INDEX(0x170) #define OMAP5_UART6_CLKCTRL OMAP5_CLKCTRL_INDEX(0x178) +/* iva clocks */ +#define OMAP5_IVA_CLKCTRL OMAP5_CLKCTRL_INDEX(0x20) +#define OMAP5_SL2IF_CLKCTRL OMAP5_CLKCTRL_INDEX(0x28) + /* dss clocks */ #define OMAP5_DSS_CORE_CLKCTRL OMAP5_CLKCTRL_INDEX(0x20) From patchwork Thu Sep 12 13:26:08 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Tero Kristo X-Patchwork-Id: 11143045 Return-Path: Received: from mail.kernel.org (pdx-korg-mail-1.web.codeaurora.org [172.30.200.123]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id 95F2F1599 for ; Thu, 12 Sep 2019 13:26:33 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.kernel.org (Postfix) with ESMTP id 73EE920830 for ; Thu, 12 Sep 2019 13:26:33 +0000 (UTC) Authentication-Results: mail.kernel.org; dkim=pass (1024-bit key) header.d=ti.com header.i=@ti.com header.b="ECsG4xE9" Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1732104AbfILN0d (ORCPT ); Thu, 12 Sep 2019 09:26:33 -0400 Received: from lelv0142.ext.ti.com ([198.47.23.249]:38374 "EHLO lelv0142.ext.ti.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1732101AbfILN0c (ORCPT ); Thu, 12 Sep 2019 09:26:32 -0400 Received: from fllv0035.itg.ti.com ([10.64.41.0]) by lelv0142.ext.ti.com (8.15.2/8.15.2) with ESMTP id x8CDQTcN021198; Thu, 12 Sep 2019 08:26:29 -0500 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=ti.com; s=ti-com-17Q1; t=1568294789; bh=+wJjCWfQrTgNasnwgKOhFijISSbGmcAqlzAKHLVv0jA=; h=From:To:CC:Subject:Date:In-Reply-To:References; b=ECsG4xE9qa8EpnYr69vNt/rPmogkYvgc/pY1gIz4ZraIoS+8WeYnKQOwWLW3A2O3J JjfWKpXLeILXPqhxojHMMtbuga/0aztd+qR5oa2CvMBwT1wPiSBSryYqBwoQqXJ103 LyNakZdnNiHwyDPlNInImxKRKlmK0/J+4x4yW+4A= Received: from DFLE110.ent.ti.com (dfle110.ent.ti.com [10.64.6.31]) by fllv0035.itg.ti.com (8.15.2/8.15.2) with ESMTP id x8CDQTgj071141; Thu, 12 Sep 2019 08:26:29 -0500 Received: from DFLE101.ent.ti.com (10.64.6.22) by DFLE110.ent.ti.com (10.64.6.31) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.1713.5; Thu, 12 Sep 2019 08:26:27 -0500 Received: from lelv0326.itg.ti.com (10.180.67.84) by DFLE101.ent.ti.com (10.64.6.22) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.1713.5 via Frontend Transport; Thu, 12 Sep 2019 08:26:27 -0500 Received: from sokoban.bb.dnainternet.fi (ileax41-snat.itg.ti.com [10.172.224.153]) by lelv0326.itg.ti.com (8.15.2/8.15.2) with ESMTP id x8CDQFvU130575; Thu, 12 Sep 2019 08:26:25 -0500 From: Tero Kristo To: , , , CC: , Subject: [PATCHv3 05/10] clk: ti: omap5: add IVA subsystem clkctrl data Date: Thu, 12 Sep 2019 16:26:08 +0300 Message-ID: <20190912132613.28093-6-t-kristo@ti.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20190912132613.28093-1-t-kristo@ti.com> References: <20190912132613.28093-1-t-kristo@ti.com> MIME-Version: 1.0 X-EXCLAIMER-MD-CONFIG: e1e8a2fd-e40a-4ac6-ac9b-f7e9cc9ee180 Sender: linux-clk-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-clk@vger.kernel.org Add clkctrl data for the IVA subsystem (Image and Video Accelerator.) Signed-off-by: Tero Kristo --- drivers/clk/ti/clk-54xx.c | 7 +++++++ 1 file changed, 7 insertions(+) diff --git a/drivers/clk/ti/clk-54xx.c b/drivers/clk/ti/clk-54xx.c index dafef7e70ba8..f63871dac600 100644 --- a/drivers/clk/ti/clk-54xx.c +++ b/drivers/clk/ti/clk-54xx.c @@ -286,6 +286,12 @@ static const struct omap_clkctrl_reg_data omap5_l4per_clkctrl_regs[] __initconst { 0 }, }; +static const struct omap_clkctrl_reg_data omap5_iva_clkctrl_regs[] __initconst = { + { OMAP5_IVA_CLKCTRL, NULL, CLKF_HW_SUP, "dpll_iva_h12x2_ck" }, + { OMAP5_SL2IF_CLKCTRL, NULL, CLKF_HW_SUP, "dpll_iva_h12x2_ck" }, + { 0 }, +}; + static const char * const omap5_dss_dss_clk_parents[] __initconst = { "dpll_per_h12x2_ck", NULL, @@ -469,6 +475,7 @@ const struct omap_clkctrl_data omap5_clkctrl_data[] __initconst = { { 0x4a008d20, omap5_l4cfg_clkctrl_regs }, { 0x4a008e20, omap5_l3instr_clkctrl_regs }, { 0x4a009020, omap5_l4per_clkctrl_regs }, + { 0x4a009220, omap5_iva_clkctrl_regs }, { 0x4a009420, omap5_dss_clkctrl_regs }, { 0x4a009620, omap5_l3init_clkctrl_regs }, { 0x4ae07920, omap5_wkupaon_clkctrl_regs }, From patchwork Thu Sep 12 13:26:09 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Tero Kristo X-Patchwork-Id: 11143049 Return-Path: Received: from mail.kernel.org (pdx-korg-mail-1.web.codeaurora.org [172.30.200.123]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id 7218316B1 for ; Thu, 12 Sep 2019 13:26:34 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.kernel.org (Postfix) with ESMTP id 507B520CC7 for ; Thu, 12 Sep 2019 13:26:34 +0000 (UTC) Authentication-Results: mail.kernel.org; dkim=pass (1024-bit key) header.d=ti.com header.i=@ti.com header.b="gesj7+IM" Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1732106AbfILN0e (ORCPT ); Thu, 12 Sep 2019 09:26:34 -0400 Received: from lelv0142.ext.ti.com ([198.47.23.249]:38376 "EHLO lelv0142.ext.ti.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1732098AbfILN0d (ORCPT ); Thu, 12 Sep 2019 09:26:33 -0400 Received: from fllv0034.itg.ti.com ([10.64.40.246]) by lelv0142.ext.ti.com (8.15.2/8.15.2) with ESMTP id x8CDQTon021204; Thu, 12 Sep 2019 08:26:29 -0500 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=ti.com; s=ti-com-17Q1; t=1568294789; bh=Atr2gt17DIkZ/xfyFREBQcV4wJqdHAnuRyN2OSnVshc=; h=From:To:CC:Subject:Date:In-Reply-To:References; b=gesj7+IM71PTBUrqbvzBK+1wWWWeQ/1AQHo8VfwFkMSAHH9yUc+aYyn4Sy8aVahyd nng9IC2Ew9vcTgS8bxXZ+lwyqD8L4nWJO3t8c6qavVaIO8Zv7ZcxoGYzVT/ZmpduZv liI9uI3cSHCdWBAZMU7hyvKGgMpJYxxNBnt3BJsA= Received: from DFLE108.ent.ti.com (dfle108.ent.ti.com [10.64.6.29]) by fllv0034.itg.ti.com (8.15.2/8.15.2) with ESMTPS id x8CDQTmb011681 (version=TLSv1.2 cipher=AES256-GCM-SHA384 bits=256 verify=FAIL); Thu, 12 Sep 2019 08:26:29 -0500 Received: from DFLE113.ent.ti.com (10.64.6.34) by DFLE108.ent.ti.com (10.64.6.29) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.1713.5; Thu, 12 Sep 2019 08:26:29 -0500 Received: from lelv0326.itg.ti.com (10.180.67.84) by DFLE113.ent.ti.com (10.64.6.34) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.1713.5 via Frontend Transport; Thu, 12 Sep 2019 08:26:29 -0500 Received: from sokoban.bb.dnainternet.fi (ileax41-snat.itg.ti.com [10.172.224.153]) by lelv0326.itg.ti.com (8.15.2/8.15.2) with ESMTP id x8CDQFvV130575; Thu, 12 Sep 2019 08:26:27 -0500 From: Tero Kristo To: , , , CC: , Subject: [PATCHv3 06/10] clk: ti: dra7xx: Drop idlest polling from IPU & DSP clkctrl clocks Date: Thu, 12 Sep 2019 16:26:09 +0300 Message-ID: <20190912132613.28093-7-t-kristo@ti.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20190912132613.28093-1-t-kristo@ti.com> References: <20190912132613.28093-1-t-kristo@ti.com> MIME-Version: 1.0 X-EXCLAIMER-MD-CONFIG: e1e8a2fd-e40a-4ac6-ac9b-f7e9cc9ee180 Sender: linux-clk-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-clk@vger.kernel.org The IPU and DSP remote processor cores and their corresponding MMUs on DRA7 SoCs have hardreset lines associated with them and are controlled by a PRCM reset line each. Any clkctrl enable/disable operations cannot be checked for module enabled/disabled status independent of the reset operation, and this causes some unwanted timeouts in the kernel and unbalanced states for these clocks. These details should be handled by the driver integration code itself. Add the CLKF_NO_IDLEST flag to both the IPU and DSP clkctrl clocks so that these module status checks are skipped. Signed-off-by: Tero Kristo --- drivers/clk/ti/clk-7xx.c | 8 ++++---- 1 file changed, 4 insertions(+), 4 deletions(-) diff --git a/drivers/clk/ti/clk-7xx.c b/drivers/clk/ti/clk-7xx.c index b57fe09b428b..94e69cdc2bd2 100644 --- a/drivers/clk/ti/clk-7xx.c +++ b/drivers/clk/ti/clk-7xx.c @@ -25,7 +25,7 @@ static const struct omap_clkctrl_reg_data dra7_mpu_clkctrl_regs[] __initconst = }; static const struct omap_clkctrl_reg_data dra7_dsp1_clkctrl_regs[] __initconst = { - { DRA7_DSP1_MMU0_DSP1_CLKCTRL, NULL, CLKF_HW_SUP, "dpll_dsp_m2_ck" }, + { DRA7_DSP1_MMU0_DSP1_CLKCTRL, NULL, CLKF_HW_SUP | CLKF_NO_IDLEST, "dpll_dsp_m2_ck" }, { 0 }, }; @@ -41,7 +41,7 @@ static const struct omap_clkctrl_bit_data dra7_mmu_ipu1_bit_data[] __initconst = }; static const struct omap_clkctrl_reg_data dra7_ipu1_clkctrl_regs[] __initconst = { - { DRA7_IPU1_MMU_IPU1_CLKCTRL, dra7_mmu_ipu1_bit_data, CLKF_HW_SUP, "ipu1-clkctrl:0000:24" }, + { DRA7_IPU1_MMU_IPU1_CLKCTRL, dra7_mmu_ipu1_bit_data, CLKF_HW_SUP | CLKF_NO_IDLEST, "ipu1-clkctrl:0000:24" }, { 0 }, }; @@ -137,7 +137,7 @@ static const struct omap_clkctrl_reg_data dra7_ipu_clkctrl_regs[] __initconst = }; static const struct omap_clkctrl_reg_data dra7_dsp2_clkctrl_regs[] __initconst = { - { DRA7_DSP2_MMU0_DSP2_CLKCTRL, NULL, CLKF_HW_SUP, "dpll_dsp_m2_ck" }, + { DRA7_DSP2_MMU0_DSP2_CLKCTRL, NULL, CLKF_HW_SUP | CLKF_NO_IDLEST, "dpll_dsp_m2_ck" }, { 0 }, }; @@ -164,7 +164,7 @@ static const struct omap_clkctrl_reg_data dra7_l3main1_clkctrl_regs[] __initcons }; static const struct omap_clkctrl_reg_data dra7_ipu2_clkctrl_regs[] __initconst = { - { DRA7_IPU2_MMU_IPU2_CLKCTRL, NULL, CLKF_HW_SUP, "dpll_core_h22x2_ck" }, + { DRA7_IPU2_MMU_IPU2_CLKCTRL, NULL, CLKF_HW_SUP | CLKF_NO_IDLEST, "dpll_core_h22x2_ck" }, { 0 }, }; From patchwork Thu Sep 12 13:26:10 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Tero Kristo X-Patchwork-Id: 11143053 Return-Path: Received: from mail.kernel.org (pdx-korg-mail-1.web.codeaurora.org [172.30.200.123]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id 839041599 for ; Thu, 12 Sep 2019 13:26:35 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.kernel.org (Postfix) with ESMTP id 61E9020856 for ; Thu, 12 Sep 2019 13:26:35 +0000 (UTC) Authentication-Results: mail.kernel.org; dkim=pass (1024-bit key) header.d=ti.com header.i=@ti.com header.b="btVwRm+W" Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1732108AbfILN0f (ORCPT ); Thu, 12 Sep 2019 09:26:35 -0400 Received: from lelv0143.ext.ti.com ([198.47.23.248]:41632 "EHLO lelv0143.ext.ti.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1732098AbfILN0f (ORCPT ); Thu, 12 Sep 2019 09:26:35 -0400 Received: from fllv0035.itg.ti.com ([10.64.41.0]) by lelv0143.ext.ti.com (8.15.2/8.15.2) with ESMTP id x8CDQVNr049544; Thu, 12 Sep 2019 08:26:31 -0500 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=ti.com; s=ti-com-17Q1; t=1568294791; bh=64fqodASKJfeJLGxH1nNhSTYa8joNo1U/kmhF3htzCY=; h=From:To:CC:Subject:Date:In-Reply-To:References; b=btVwRm+W6GNuXn4Cm6khmKzPRo/76ZIDAQMS7ilq8XaK3uMMczfBbATeJdAM72tr3 iey4tVlBN4QG1PCpCsBdnmDWRn6WFJafKquzxIOrHG0/qaXCpu4GpDoH9QRJfWGf1Y cWa818w+bc9oicEQGpIYRb30Ipz8DubNLCa2nioo= Received: from DFLE112.ent.ti.com (dfle112.ent.ti.com [10.64.6.33]) by fllv0035.itg.ti.com (8.15.2/8.15.2) with ESMTP id x8CDQVxw071201; Thu, 12 Sep 2019 08:26:31 -0500 Received: from DFLE108.ent.ti.com (10.64.6.29) by DFLE112.ent.ti.com (10.64.6.33) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.1713.5; Thu, 12 Sep 2019 08:26:31 -0500 Received: from lelv0326.itg.ti.com (10.180.67.84) by DFLE108.ent.ti.com (10.64.6.29) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.1713.5 via Frontend Transport; Thu, 12 Sep 2019 08:26:31 -0500 Received: from sokoban.bb.dnainternet.fi (ileax41-snat.itg.ti.com [10.172.224.153]) by lelv0326.itg.ti.com (8.15.2/8.15.2) with ESMTP id x8CDQFvW130575; Thu, 12 Sep 2019 08:26:29 -0500 From: Tero Kristo To: , , , CC: , Subject: [PATCHv3 07/10] clk: ti: omap4: Drop idlest polling from IPU & DSP clkctrl clocks Date: Thu, 12 Sep 2019 16:26:10 +0300 Message-ID: <20190912132613.28093-8-t-kristo@ti.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20190912132613.28093-1-t-kristo@ti.com> References: <20190912132613.28093-1-t-kristo@ti.com> MIME-Version: 1.0 X-EXCLAIMER-MD-CONFIG: e1e8a2fd-e40a-4ac6-ac9b-f7e9cc9ee180 Sender: linux-clk-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-clk@vger.kernel.org From: Suman Anna The IPU and DSP remote processor cores and their corresponding MMUs on OMAP4 SoCs have hardreset lines associated with them and are controlled by a PRCM reset line each. Any clkctrl enable/disable operations cannot be checked for module enabled/disabled status independent of the reset operation, and this causes some unwanted timeouts in the kernel and unbalanced states for these clocks. These details should be handled by the driver integration code itself. Add the CLKF_NO_IDLEST flag to both the IPU and DSP clkctrl clocks so that these module status checks are skipped. Signed-off-by: Suman Anna --- drivers/clk/ti/clk-44xx.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/drivers/clk/ti/clk-44xx.c b/drivers/clk/ti/clk-44xx.c index b10ed0429091..2b4dab632318 100644 --- a/drivers/clk/ti/clk-44xx.c +++ b/drivers/clk/ti/clk-44xx.c @@ -37,7 +37,7 @@ static const struct omap_clkctrl_reg_data omap4_mpuss_clkctrl_regs[] __initconst }; static const struct omap_clkctrl_reg_data omap4_tesla_clkctrl_regs[] __initconst = { - { OMAP4_DSP_CLKCTRL, NULL, CLKF_HW_SUP, "dpll_iva_m4x2_ck" }, + { OMAP4_DSP_CLKCTRL, NULL, CLKF_HW_SUP | CLKF_NO_IDLEST, "dpll_iva_m4x2_ck" }, { 0 }, }; @@ -219,7 +219,7 @@ static const struct omap_clkctrl_reg_data omap4_l3_2_clkctrl_regs[] __initconst }; static const struct omap_clkctrl_reg_data omap4_ducati_clkctrl_regs[] __initconst = { - { OMAP4_IPU_CLKCTRL, NULL, CLKF_HW_SUP, "ducati_clk_mux_ck" }, + { OMAP4_IPU_CLKCTRL, NULL, CLKF_HW_SUP | CLKF_NO_IDLEST, "ducati_clk_mux_ck" }, { 0 }, }; From patchwork Thu Sep 12 13:26:11 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Tero Kristo X-Patchwork-Id: 11143057 Return-Path: Received: from mail.kernel.org (pdx-korg-mail-1.web.codeaurora.org [172.30.200.123]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id 1D68816B1 for ; Thu, 12 Sep 2019 13:26:37 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.kernel.org (Postfix) with ESMTP id F041820856 for ; Thu, 12 Sep 2019 13:26:36 +0000 (UTC) Authentication-Results: mail.kernel.org; dkim=pass (1024-bit key) header.d=ti.com header.i=@ti.com header.b="V2hJTOnd" Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1732110AbfILN0g (ORCPT ); Thu, 12 Sep 2019 09:26:36 -0400 Received: from lelv0143.ext.ti.com ([198.47.23.248]:41644 "EHLO lelv0143.ext.ti.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1732098AbfILN0g (ORCPT ); Thu, 12 Sep 2019 09:26:36 -0400 Received: from lelv0265.itg.ti.com ([10.180.67.224]) by lelv0143.ext.ti.com (8.15.2/8.15.2) with ESMTP id x8CDQX32049558; Thu, 12 Sep 2019 08:26:33 -0500 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=ti.com; s=ti-com-17Q1; t=1568294793; bh=fW+u/vGNd3Os0mTVhUYzxkOa/BShSQwBQHEQNFyKdFs=; h=From:To:CC:Subject:Date:In-Reply-To:References; b=V2hJTOndcru4A2B+/0dj6uIigedP6zT8br+44ERD4Hul/owl+qMxuj/4pzkqOR2W/ ohXWxEva4Aj5SQ789rN1iQulJk5BonMZp6tzvGU8/50c4wWnR/nt9Y5HxYaudMpl2L 9nyJEGzo1CUdFj7MTynFe5qCTAPbPCQyHMQN9jqc= Received: from DLEE108.ent.ti.com (dlee108.ent.ti.com [157.170.170.38]) by lelv0265.itg.ti.com (8.15.2/8.15.2) with ESMTPS id x8CDQXdA053259 (version=TLSv1.2 cipher=AES256-GCM-SHA384 bits=256 verify=FAIL); Thu, 12 Sep 2019 08:26:33 -0500 Received: from DLEE105.ent.ti.com (157.170.170.35) by DLEE108.ent.ti.com (157.170.170.38) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.1713.5; Thu, 12 Sep 2019 08:26:33 -0500 Received: from lelv0326.itg.ti.com (10.180.67.84) by DLEE105.ent.ti.com (157.170.170.35) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.1713.5 via Frontend Transport; Thu, 12 Sep 2019 08:26:33 -0500 Received: from sokoban.bb.dnainternet.fi (ileax41-snat.itg.ti.com [10.172.224.153]) by lelv0326.itg.ti.com (8.15.2/8.15.2) with ESMTP id x8CDQFvX130575; Thu, 12 Sep 2019 08:26:31 -0500 From: Tero Kristo To: , , , CC: , Subject: [PATCHv3 08/10] clk: ti: omap5: Drop idlest polling from IPU & DSP clkctrl clocks Date: Thu, 12 Sep 2019 16:26:11 +0300 Message-ID: <20190912132613.28093-9-t-kristo@ti.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20190912132613.28093-1-t-kristo@ti.com> References: <20190912132613.28093-1-t-kristo@ti.com> MIME-Version: 1.0 X-EXCLAIMER-MD-CONFIG: e1e8a2fd-e40a-4ac6-ac9b-f7e9cc9ee180 Sender: linux-clk-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-clk@vger.kernel.org From: Suman Anna The IPU and DSP remote processor cores and their corresponding MMUs on OMAP5 SoCs have hardreset lines associated with them and are controlled by a PRCM reset line each. Any clkctrl enable/disable operations cannot be checked for module enabled/disabled status independent of the reset operation, and this causes some unwanted timeouts in the kernel and unbalanced states for these clocks. These details should be handled by the driver integration code itself. Add the CLKF_NO_IDLEST flag to both the IPU and DSP clkctrl clocks so that these module status checks are skipped. Signed-off-by: Suman Anna --- drivers/clk/ti/clk-54xx.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/drivers/clk/ti/clk-54xx.c b/drivers/clk/ti/clk-54xx.c index f63871dac600..b5e5658f614f 100644 --- a/drivers/clk/ti/clk-54xx.c +++ b/drivers/clk/ti/clk-54xx.c @@ -31,7 +31,7 @@ static const struct omap_clkctrl_reg_data omap5_mpu_clkctrl_regs[] __initconst = }; static const struct omap_clkctrl_reg_data omap5_dsp_clkctrl_regs[] __initconst = { - { OMAP5_MMU_DSP_CLKCTRL, NULL, CLKF_HW_SUP, "dpll_iva_h11x2_ck" }, + { OMAP5_MMU_DSP_CLKCTRL, NULL, CLKF_HW_SUP | CLKF_NO_IDLEST, "dpll_iva_h11x2_ck" }, { 0 }, }; @@ -145,7 +145,7 @@ static const struct omap_clkctrl_reg_data omap5_l3main2_clkctrl_regs[] __initcon }; static const struct omap_clkctrl_reg_data omap5_ipu_clkctrl_regs[] __initconst = { - { OMAP5_MMU_IPU_CLKCTRL, NULL, CLKF_HW_SUP, "dpll_core_h22x2_ck" }, + { OMAP5_MMU_IPU_CLKCTRL, NULL, CLKF_HW_SUP | CLKF_NO_IDLEST, "dpll_core_h22x2_ck" }, { 0 }, }; From patchwork Thu Sep 12 13:26:12 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Tero Kristo X-Patchwork-Id: 11143061 Return-Path: Received: from mail.kernel.org (pdx-korg-mail-1.web.codeaurora.org [172.30.200.123]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id 4CB681599 for ; Thu, 12 Sep 2019 13:26:38 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.kernel.org (Postfix) with ESMTP id 296D520830 for ; Thu, 12 Sep 2019 13:26:38 +0000 (UTC) Authentication-Results: mail.kernel.org; dkim=pass (1024-bit key) header.d=ti.com header.i=@ti.com header.b="SWXhSgj1" Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1732113AbfILN0h (ORCPT ); Thu, 12 Sep 2019 09:26:37 -0400 Received: from lelv0142.ext.ti.com ([198.47.23.249]:38390 "EHLO lelv0142.ext.ti.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1732098AbfILN0h (ORCPT ); Thu, 12 Sep 2019 09:26:37 -0400 Received: from fllv0034.itg.ti.com ([10.64.40.246]) by lelv0142.ext.ti.com (8.15.2/8.15.2) with ESMTP id x8CDQZHU021229; Thu, 12 Sep 2019 08:26:35 -0500 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=ti.com; s=ti-com-17Q1; t=1568294795; bh=V1b0FMEeevL3urjdJBuTCnTQb6LW6rgCELNI7FyhZeE=; h=From:To:CC:Subject:Date:In-Reply-To:References; b=SWXhSgj1ds7YXWFx1umEHZxcRWRw/uZMwVBvjO9WU/Jg6BWBTnbaPmj9/XXo7SXcr V8fY7hEVYy7QecLtoCy5rBreQDh8DscRMChz8IgpY42+kZfR1Uu55I7LddG1iLHzQY iRpHJWaUIlempeFzYYXuSgr04W2F9WWbL/Ht+plQ= Received: from DFLE112.ent.ti.com (dfle112.ent.ti.com [10.64.6.33]) by fllv0034.itg.ti.com (8.15.2/8.15.2) with ESMTPS id x8CDQZx0011793 (version=TLSv1.2 cipher=AES256-GCM-SHA384 bits=256 verify=FAIL); Thu, 12 Sep 2019 08:26:35 -0500 Received: from DFLE108.ent.ti.com (10.64.6.29) by DFLE112.ent.ti.com (10.64.6.33) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.1713.5; Thu, 12 Sep 2019 08:26:35 -0500 Received: from lelv0326.itg.ti.com (10.180.67.84) by DFLE108.ent.ti.com (10.64.6.29) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.1713.5 via Frontend Transport; Thu, 12 Sep 2019 08:26:35 -0500 Received: from sokoban.bb.dnainternet.fi (ileax41-snat.itg.ti.com [10.172.224.153]) by lelv0326.itg.ti.com (8.15.2/8.15.2) with ESMTP id x8CDQFvY130575; Thu, 12 Sep 2019 08:26:33 -0500 From: Tero Kristo To: , , , CC: , Subject: [PATCHv3 09/10] clk: ti: am43xx: drop idlest polling from pruss clkctrl clock Date: Thu, 12 Sep 2019 16:26:12 +0300 Message-ID: <20190912132613.28093-10-t-kristo@ti.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20190912132613.28093-1-t-kristo@ti.com> References: <20190912132613.28093-1-t-kristo@ti.com> MIME-Version: 1.0 X-EXCLAIMER-MD-CONFIG: e1e8a2fd-e40a-4ac6-ac9b-f7e9cc9ee180 Sender: linux-clk-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-clk@vger.kernel.org The PRUSS modules on AM43xx SoCs have a hardreset line and are controlled by a PRCM reset line. Any clkctrl enable/disable operations cannot be checked for module enabled/disabled status independent of the reset operation, and this causes some unwanted timeouts in the kernel and unbalanced states for the PRUSS clocks. These details should be handled by the driver integration code itself. Add the CLKF_NO_IDLEST flag to the PRUSS clkctrl clock so that these module status checks are skipped. Signed-off-by: Tero Kristo --- drivers/clk/ti/clk-43xx.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/clk/ti/clk-43xx.c b/drivers/clk/ti/clk-43xx.c index 2782d91838ac..7ec8fe6aa7c1 100644 --- a/drivers/clk/ti/clk-43xx.c +++ b/drivers/clk/ti/clk-43xx.c @@ -126,7 +126,7 @@ static const struct omap_clkctrl_reg_data am4_l3s_clkctrl_regs[] __initconst = { }; static const struct omap_clkctrl_reg_data am4_pruss_ocp_clkctrl_regs[] __initconst = { - { AM4_PRUSS_OCP_PRUSS_CLKCTRL, NULL, CLKF_SW_SUP, "pruss_ocp_gclk" }, + { AM4_PRUSS_OCP_PRUSS_CLKCTRL, NULL, CLKF_SW_SUP | CLKF_NO_IDLEST, "pruss_ocp_gclk" }, { 0 }, }; From patchwork Thu Sep 12 13:26:13 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Tero Kristo X-Patchwork-Id: 11143065 Return-Path: Received: from mail.kernel.org (pdx-korg-mail-1.web.codeaurora.org [172.30.200.123]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id D942816B1 for ; Thu, 12 Sep 2019 13:26:40 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.kernel.org (Postfix) with ESMTP id B777C20856 for ; Thu, 12 Sep 2019 13:26:40 +0000 (UTC) Authentication-Results: mail.kernel.org; dkim=pass (1024-bit key) header.d=ti.com header.i=@ti.com header.b="R5Sx57oF" Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1732114AbfILN0k (ORCPT ); Thu, 12 Sep 2019 09:26:40 -0400 Received: from lelv0143.ext.ti.com ([198.47.23.248]:41666 "EHLO lelv0143.ext.ti.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1732098AbfILN0k (ORCPT ); Thu, 12 Sep 2019 09:26:40 -0400 Received: from fllv0035.itg.ti.com ([10.64.41.0]) by lelv0143.ext.ti.com (8.15.2/8.15.2) with ESMTP id x8CDQbaQ049583; Thu, 12 Sep 2019 08:26:37 -0500 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=ti.com; s=ti-com-17Q1; t=1568294797; bh=K2Q92adlyOlFE+55nlrsCH8twyZ1qvVGlSQOn8cJ0jo=; h=From:To:CC:Subject:Date:In-Reply-To:References; b=R5Sx57oFPzATZ7B13TRpt+LVvRAA0YJuP5aYxx+jWwNQS8vfMX2aRi0AnKQvVctj6 rd3Gyqgm0kY4w4SV8D22PnJimdgujRGc8b6mV/24mjp7YJFQ9zha7YqPb9IcnowqyP SLlcNO9g8efjY/UQmGU1UXuIXex4Rfpf5mIkFftk= Received: from DLEE115.ent.ti.com (dlee115.ent.ti.com [157.170.170.26]) by fllv0035.itg.ti.com (8.15.2/8.15.2) with ESMTP id x8CDQbGA071418; Thu, 12 Sep 2019 08:26:37 -0500 Received: from DLEE101.ent.ti.com (157.170.170.31) by DLEE115.ent.ti.com (157.170.170.26) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.1713.5; Thu, 12 Sep 2019 08:26:37 -0500 Received: from lelv0326.itg.ti.com (10.180.67.84) by DLEE101.ent.ti.com (157.170.170.31) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.1713.5 via Frontend Transport; Thu, 12 Sep 2019 08:26:37 -0500 Received: from sokoban.bb.dnainternet.fi (ileax41-snat.itg.ti.com [10.172.224.153]) by lelv0326.itg.ti.com (8.15.2/8.15.2) with ESMTP id x8CDQFvZ130575; Thu, 12 Sep 2019 08:26:35 -0500 From: Tero Kristo To: , , , CC: , Subject: [PATCHv3 10/10] clk: ti: am33xx: drop idlest polling from pruss clkctrl clock Date: Thu, 12 Sep 2019 16:26:13 +0300 Message-ID: <20190912132613.28093-11-t-kristo@ti.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20190912132613.28093-1-t-kristo@ti.com> References: <20190912132613.28093-1-t-kristo@ti.com> MIME-Version: 1.0 X-EXCLAIMER-MD-CONFIG: e1e8a2fd-e40a-4ac6-ac9b-f7e9cc9ee180 Sender: linux-clk-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-clk@vger.kernel.org The PRUSS module on AM33xx SoCs has a hardreset line and is controlled by a PRCM reset line. Any clkctrl enable/disable operations cannot be checked for module enabled/disabled status independent of the reset operation, and this causes some unwanted timeouts in the kernel and unbalanced states for the PRUSS clocks. These details should be handled by the driver integration code itself. Add the CLKF_NO_IDLEST flag to the PRUSS clkctrl clock so that these module status checks are skipped. Signed-off-by: Tero Kristo --- drivers/clk/ti/clk-33xx.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/clk/ti/clk-33xx.c b/drivers/clk/ti/clk-33xx.c index a360d3109555..935efb66b389 100644 --- a/drivers/clk/ti/clk-33xx.c +++ b/drivers/clk/ti/clk-33xx.c @@ -107,7 +107,7 @@ static const struct omap_clkctrl_reg_data am3_l4hs_clkctrl_regs[] __initconst = }; static const struct omap_clkctrl_reg_data am3_pruss_ocp_clkctrl_regs[] __initconst = { - { AM3_PRUSS_OCP_PRUSS_CLKCTRL, NULL, CLKF_SW_SUP, "pruss_ocp_gclk" }, + { AM3_PRUSS_OCP_PRUSS_CLKCTRL, NULL, CLKF_SW_SUP | CLKF_NO_IDLEST, "pruss_ocp_gclk" }, { 0 }, };