From patchwork Fri Sep 13 21:59:09 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Lina Iyer X-Patchwork-Id: 11145365 Return-Path: Received: from mail.kernel.org (pdx-korg-mail-1.web.codeaurora.org [172.30.200.123]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id 80832184E for ; Fri, 13 Sep 2019 22:00:38 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.kernel.org (Postfix) with ESMTP id 60901214DA for ; Fri, 13 Sep 2019 22:00:38 +0000 (UTC) Authentication-Results: mail.kernel.org; dkim=fail reason="key not found in DNS" (0-bit key) header.d=codeaurora.org header.i=@codeaurora.org header.b="Qm+YCF3O"; dkim=fail reason="key not found in DNS" (0-bit key) header.d=codeaurora.org header.i=@codeaurora.org header.b="GFIEJjp8" Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S2389992AbfIMV7p (ORCPT ); Fri, 13 Sep 2019 17:59:45 -0400 Received: from smtp.codeaurora.org ([198.145.29.96]:59412 "EHLO smtp.codeaurora.org" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1725747AbfIMV7o (ORCPT ); Fri, 13 Sep 2019 17:59:44 -0400 Received: by smtp.codeaurora.org (Postfix, from userid 1000) id CE3616044E; Fri, 13 Sep 2019 21:59:43 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=codeaurora.org; s=default; t=1568411983; bh=r9VU5NwhhErW5lihrBpuQhz4eshG9uEvbjR5J9Nhdt8=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=Qm+YCF3O1Adn77QKMX8qd0IODgk1ZQDBXznpdHZ0x2htiOfXvFzUXbpwgJhBAFq3I 8EJ2XmypNXXYfvqfaxeBYCHQCM4ECjl1+NFYpL78zCU8OZGNQknY/uUoRchILtH3wX XDD8IwOFexv9i7To4T7fp8mIxg6OqEsShtRIYmhk= X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on pdx-caf-mail.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-2.7 required=2.0 tests=ALL_TRUSTED,BAYES_00, DKIM_INVALID,DKIM_SIGNED,SPF_NONE autolearn=no autolearn_force=no version=3.4.0 Received: from codeaurora.org (i-global254.qualcomm.com [199.106.103.254]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-SHA256 (128/128 bits)) (No client certificate requested) (Authenticated sender: ilina@smtp.codeaurora.org) by smtp.codeaurora.org (Postfix) with ESMTPSA id 6129A602C3; Fri, 13 Sep 2019 21:59:41 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=codeaurora.org; s=default; t=1568411982; bh=r9VU5NwhhErW5lihrBpuQhz4eshG9uEvbjR5J9Nhdt8=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=GFIEJjp8j+bneKliC31btEKLSZwnGe3eXjbJG3hIXNXMpuVLMcFCMlsBejou94j7z SC6QgsqyH1PKyrV/OIXoj/5jsyvz1skcQTfpnFrdZgylFwAQv5iKvdpgnS6P6pvoNf ERVF9zxlbeUcIPxhfNP+5qRB+Hk5tVfr3UB5DZk0= DMARC-Filter: OpenDMARC Filter v1.3.2 smtp.codeaurora.org 6129A602C3 Authentication-Results: pdx-caf-mail.web.codeaurora.org; dmarc=none (p=none dis=none) header.from=codeaurora.org Authentication-Results: pdx-caf-mail.web.codeaurora.org; spf=none smtp.mailfrom=ilina@codeaurora.org From: Lina Iyer To: swboyd@chromium.org, evgreen@chromium.org, maz@kernel.org, linus.walleij@linaro.org Cc: linux-kernel@vger.kernel.org, linux-arm-msm@vger.kernel.org, bjorn.andersson@linaro.org, mkshah@codeaurora.org, linux-gpio@vger.kernel.org, Lina Iyer Subject: [PATCH RFC v2 01/14] irqdomain: add bus token DOMAIN_BUS_WAKEUP Date: Fri, 13 Sep 2019 15:59:09 -0600 Message-Id: <1568411962-1022-2-git-send-email-ilina@codeaurora.org> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1568411962-1022-1-git-send-email-ilina@codeaurora.org> References: <1568411962-1022-1-git-send-email-ilina@codeaurora.org> Sender: linux-arm-msm-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-arm-msm@vger.kernel.org A single controller can handle normal interrupts and wake-up interrupts independently, with a different numbering space. It is thus crucial to allow the driver for such a controller discriminate between the two. A simple way to do so is to tag the wake-up irqdomain with a "bus token" that indicates the wake-up domain. This slightly abuses the notion of bus, but also radically simplifies the design of such a driver. Between two evils, we choose the least damaging. Suggested-by: Stephen Boyd Signed-off-by: Lina Iyer --- include/linux/irqdomain.h | 1 + 1 file changed, 1 insertion(+) diff --git a/include/linux/irqdomain.h b/include/linux/irqdomain.h index 07ec8b3..cc846ab 100644 --- a/include/linux/irqdomain.h +++ b/include/linux/irqdomain.h @@ -83,6 +83,7 @@ enum irq_domain_bus_token { DOMAIN_BUS_IPI, DOMAIN_BUS_FSL_MC_MSI, DOMAIN_BUS_TI_SCI_INTA_MSI, + DOMAIN_BUS_WAKEUP, }; /** From patchwork Fri Sep 13 21:59:10 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Lina Iyer X-Patchwork-Id: 11145363 Return-Path: Received: from mail.kernel.org (pdx-korg-mail-1.web.codeaurora.org [172.30.200.123]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id 563801395 for ; Fri, 13 Sep 2019 22:00:38 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.kernel.org (Postfix) with ESMTP id 36E5B214D8 for ; Fri, 13 Sep 2019 22:00:38 +0000 (UTC) Authentication-Results: mail.kernel.org; dkim=fail reason="key not found in DNS" (0-bit key) header.d=codeaurora.org header.i=@codeaurora.org header.b="CvmO9oXI"; dkim=fail reason="key not found in DNS" (0-bit key) header.d=codeaurora.org header.i=@codeaurora.org header.b="XVcCRMi9" Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S2403932AbfIMWAe (ORCPT ); Fri, 13 Sep 2019 18:00:34 -0400 Received: from smtp.codeaurora.org ([198.145.29.96]:59510 "EHLO smtp.codeaurora.org" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1731449AbfIMV7p (ORCPT ); Fri, 13 Sep 2019 17:59:45 -0400 Received: by smtp.codeaurora.org (Postfix, from userid 1000) id 6192160A00; Fri, 13 Sep 2019 21:59:43 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=codeaurora.org; s=default; t=1568411984; bh=6f0lTQnrx5z1wDAiPKuaRnk5KF6fWCBKtD1ja6XdbS8=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=CvmO9oXIZENnRUtpeIiLieiwnQ315SnlUgJmIltt6U61JE7hYnijToNkl2TBRYyUp zo41uofQCRaf9CvAR96iFDrmMpfPFHNVEUACuERB99hpvN2Gl4P6mSYUqMeaRsFlMe 0G7NFtrGSiOFi1Z8RoNGqlov5b54PrQkKMw3E7TU= X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on pdx-caf-mail.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-2.7 required=2.0 tests=ALL_TRUSTED,BAYES_00, DKIM_INVALID,DKIM_SIGNED,SPF_NONE autolearn=no autolearn_force=no version=3.4.0 Received: from codeaurora.org (i-global254.qualcomm.com [199.106.103.254]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-SHA256 (128/128 bits)) (No client certificate requested) (Authenticated sender: ilina@smtp.codeaurora.org) by smtp.codeaurora.org (Postfix) with ESMTPSA id 5C42460790; Fri, 13 Sep 2019 21:59:42 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=codeaurora.org; s=default; t=1568411983; bh=6f0lTQnrx5z1wDAiPKuaRnk5KF6fWCBKtD1ja6XdbS8=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=XVcCRMi9TpjLkyFd0vQLOh2Wa4zb8VngMPImuZAdAZx8RArDt3VQ9R9PWAP19EdNK TA4gK2k54cC19j0K96nx/pEOWjgFHcpB8JlHJWeick1td5KqwKtgWDjA9Afk5QG+1Q /pt1YHixaRh9e4d1JcTA8foTnXZ38GHtA9MAk8N0= DMARC-Filter: OpenDMARC Filter v1.3.2 smtp.codeaurora.org 5C42460790 Authentication-Results: pdx-caf-mail.web.codeaurora.org; dmarc=none (p=none dis=none) header.from=codeaurora.org Authentication-Results: pdx-caf-mail.web.codeaurora.org; spf=none smtp.mailfrom=ilina@codeaurora.org From: Lina Iyer To: swboyd@chromium.org, evgreen@chromium.org, maz@kernel.org, linus.walleij@linaro.org Cc: linux-kernel@vger.kernel.org, linux-arm-msm@vger.kernel.org, bjorn.andersson@linaro.org, mkshah@codeaurora.org, linux-gpio@vger.kernel.org, Lina Iyer Subject: [PATCH RFC v2 02/14] drivers: irqchip: qcom-pdc: update max PDC interrupts Date: Fri, 13 Sep 2019 15:59:10 -0600 Message-Id: <1568411962-1022-3-git-send-email-ilina@codeaurora.org> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1568411962-1022-1-git-send-email-ilina@codeaurora.org> References: <1568411962-1022-1-git-send-email-ilina@codeaurora.org> Sender: linux-arm-msm-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-arm-msm@vger.kernel.org Newer SoCs have increased the number of interrupts routed to the PDC interrupt controller. Update the definition of max PDC interrupts. Signed-off-by: Lina Iyer --- drivers/irqchip/qcom-pdc.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/drivers/irqchip/qcom-pdc.c b/drivers/irqchip/qcom-pdc.c index faa7d61..b230794 100644 --- a/drivers/irqchip/qcom-pdc.c +++ b/drivers/irqchip/qcom-pdc.c @@ -1,6 +1,6 @@ // SPDX-License-Identifier: GPL-2.0 /* - * Copyright (c) 2017-2018, The Linux Foundation. All rights reserved. + * Copyright (c) 2017-2019, The Linux Foundation. All rights reserved. */ #include @@ -18,7 +18,7 @@ #include #include -#define PDC_MAX_IRQS 126 +#define PDC_MAX_IRQS 168 #define CLEAR_INTR(reg, intr) (reg & ~(1 << intr)) #define ENABLE_INTR(reg, intr) (reg | (1 << intr)) From patchwork Fri Sep 13 21:59:11 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Lina Iyer X-Patchwork-Id: 11145361 Return-Path: Received: from mail.kernel.org (pdx-korg-mail-1.web.codeaurora.org [172.30.200.123]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id 1C9691395 for ; Fri, 13 Sep 2019 22:00:31 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.kernel.org (Postfix) with ESMTP id F226D21479 for ; Fri, 13 Sep 2019 22:00:30 +0000 (UTC) Authentication-Results: mail.kernel.org; dkim=fail reason="key not found in DNS" (0-bit key) header.d=codeaurora.org header.i=@codeaurora.org header.b="d6lpwxSY"; dkim=fail reason="key not found in DNS" (0-bit key) header.d=codeaurora.org header.i=@codeaurora.org header.b="II/NOksb" Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S2390253AbfIMV7q (ORCPT ); Fri, 13 Sep 2019 17:59:46 -0400 Received: from smtp.codeaurora.org ([198.145.29.96]:59584 "EHLO smtp.codeaurora.org" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S2390018AbfIMV7q (ORCPT ); Fri, 13 Sep 2019 17:59:46 -0400 Received: by smtp.codeaurora.org (Postfix, from userid 1000) id 01543607C6; Fri, 13 Sep 2019 21:59:44 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=codeaurora.org; s=default; t=1568411985; bh=mJ6ERleIUVuaUxsJYCNgiuvwDk4I+BHBd01lZAWccGo=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=d6lpwxSYc+zd5X0IcJDdYCozHY4WhBW/Tx/zkIZz/rddzXOY0Xqhy4tR88hnN3T42 utY4T9CXiXBVsh9v6ZjKUH6skna3erY1mbtOGTrGRMbXPnv358SsWM3QuIiky8KBdU dk4SCxceuz+aol45an39SMkUzdG5MtmOzjOERe+c= X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on pdx-caf-mail.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-2.7 required=2.0 tests=ALL_TRUSTED,BAYES_00, DKIM_INVALID,DKIM_SIGNED,SPF_NONE autolearn=no autolearn_force=no version=3.4.0 Received: from codeaurora.org (i-global254.qualcomm.com [199.106.103.254]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-SHA256 (128/128 bits)) (No client certificate requested) (Authenticated sender: ilina@smtp.codeaurora.org) by smtp.codeaurora.org (Postfix) with ESMTPSA id 66F3E607C6; Fri, 13 Sep 2019 21:59:43 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=codeaurora.org; s=default; t=1568411984; bh=mJ6ERleIUVuaUxsJYCNgiuvwDk4I+BHBd01lZAWccGo=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=II/NOksbYtlYfHVAXo4v22YeoSLlO1vjfyL5pBMTAH2FFZ4O1nI8UHl6Yl6vtIa/1 O1FmWfkjsrGVldlxZ5aKi0pBUcdkbOzHZdnBMYdPc0pLp00i48bkgn6zB/Ziha8QfV o0O0qG10yoU8DwtuL+VFVBawXwo99vbs9rBxTC08= DMARC-Filter: OpenDMARC Filter v1.3.2 smtp.codeaurora.org 66F3E607C6 Authentication-Results: pdx-caf-mail.web.codeaurora.org; dmarc=none (p=none dis=none) header.from=codeaurora.org Authentication-Results: pdx-caf-mail.web.codeaurora.org; spf=none smtp.mailfrom=ilina@codeaurora.org From: Lina Iyer To: swboyd@chromium.org, evgreen@chromium.org, maz@kernel.org, linus.walleij@linaro.org Cc: linux-kernel@vger.kernel.org, linux-arm-msm@vger.kernel.org, bjorn.andersson@linaro.org, mkshah@codeaurora.org, linux-gpio@vger.kernel.org, Lina Iyer Subject: [PATCH RFC v2 03/14] drivers: irqchip: pdc: Do not toggle IRQ_ENABLE during mask/unmask Date: Fri, 13 Sep 2019 15:59:11 -0600 Message-Id: <1568411962-1022-4-git-send-email-ilina@codeaurora.org> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1568411962-1022-1-git-send-email-ilina@codeaurora.org> References: <1568411962-1022-1-git-send-email-ilina@codeaurora.org> Sender: linux-arm-msm-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-arm-msm@vger.kernel.org When an interrupt is to be serviced, the convention is to mask the interrupt at the chip and unmask after servicing the interrupt. Enabling and disabling the interrupt at the PDC irqchip causes an interrupt storm due to the way dual edge interrupts are handled in hardware. Skip configuring the PDC when the IRQ is masked and unmasked, instead use the irq_enable/irq_disable callbacks to toggle the IRQ_ENABLE register at the PDC. The PDC's IRQ_ENABLE register is only used during the monitoring mode when the system is asleep and is not needed for active mode detection. Signed-off-by: Lina Iyer --- drivers/irqchip/qcom-pdc.c | 16 ++++++++++++++-- 1 file changed, 14 insertions(+), 2 deletions(-) diff --git a/drivers/irqchip/qcom-pdc.c b/drivers/irqchip/qcom-pdc.c index b230794..5eef5ea 100644 --- a/drivers/irqchip/qcom-pdc.c +++ b/drivers/irqchip/qcom-pdc.c @@ -63,15 +63,25 @@ static void pdc_enable_intr(struct irq_data *d, bool on) raw_spin_unlock(&pdc_lock); } -static void qcom_pdc_gic_mask(struct irq_data *d) +static void qcom_pdc_gic_disable(struct irq_data *d) { pdc_enable_intr(d, false); + irq_chip_disable_parent(d); +} + +static void qcom_pdc_gic_enable(struct irq_data *d) +{ + pdc_enable_intr(d, true); + irq_chip_enable_parent(d); +} + +static void qcom_pdc_gic_mask(struct irq_data *d) +{ irq_chip_mask_parent(d); } static void qcom_pdc_gic_unmask(struct irq_data *d) { - pdc_enable_intr(d, true); irq_chip_unmask_parent(d); } @@ -148,6 +158,8 @@ static struct irq_chip qcom_pdc_gic_chip = { .irq_eoi = irq_chip_eoi_parent, .irq_mask = qcom_pdc_gic_mask, .irq_unmask = qcom_pdc_gic_unmask, + .irq_disable = qcom_pdc_gic_disable, + .irq_enable = qcom_pdc_gic_enable, .irq_retrigger = irq_chip_retrigger_hierarchy, .irq_set_type = qcom_pdc_gic_set_type, .flags = IRQCHIP_MASK_ON_SUSPEND | From patchwork Fri Sep 13 21:59:12 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Lina Iyer X-Patchwork-Id: 11145357 Return-Path: Received: from mail.kernel.org (pdx-korg-mail-1.web.codeaurora.org [172.30.200.123]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id 040F117E6 for ; Fri, 13 Sep 2019 22:00:26 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.kernel.org (Postfix) with ESMTP id CFC1D2084F for ; Fri, 13 Sep 2019 22:00:25 +0000 (UTC) Authentication-Results: mail.kernel.org; dkim=fail reason="key not found in DNS" (0-bit key) header.d=codeaurora.org header.i=@codeaurora.org header.b="QZE1yn5W"; dkim=fail reason="key not found in DNS" (0-bit key) header.d=codeaurora.org header.i=@codeaurora.org header.b="XXHxsbeS" Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S2390389AbfIMV7s (ORCPT ); Fri, 13 Sep 2019 17:59:48 -0400 Received: from smtp.codeaurora.org ([198.145.29.96]:59684 "EHLO smtp.codeaurora.org" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S2390255AbfIMV7s (ORCPT ); Fri, 13 Sep 2019 17:59:48 -0400 Received: by smtp.codeaurora.org (Postfix, from userid 1000) id 85A206115D; Fri, 13 Sep 2019 21:59:46 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=codeaurora.org; s=default; t=1568411986; bh=2I3OznB05KCeXf3W88tVhcT1RGf58DfhNJ3raIc5OVQ=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=QZE1yn5WrZNPqCI3g5T4/hluS/bnpsp3wK5e+Awa37kjJplQPPom07Gk7o10fHxdd 0BFbCcbnBHPZd711rzMOJjW0RNXWNxXjGWTBW8D0nxDamfSF6GTWGrl4vFXA7efWiu v1y0qO5VODS9Aje50X3V2ApB2mCQLVCp0HtzCv5o= X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on pdx-caf-mail.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-2.7 required=2.0 tests=ALL_TRUSTED,BAYES_00, DKIM_INVALID,DKIM_SIGNED,SPF_NONE autolearn=no autolearn_force=no version=3.4.0 Received: from codeaurora.org (i-global254.qualcomm.com [199.106.103.254]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-SHA256 (128/128 bits)) (No client certificate requested) (Authenticated sender: ilina@smtp.codeaurora.org) by smtp.codeaurora.org (Postfix) with ESMTPSA id 71AB560A60; Fri, 13 Sep 2019 21:59:44 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=codeaurora.org; s=default; t=1568411985; bh=2I3OznB05KCeXf3W88tVhcT1RGf58DfhNJ3raIc5OVQ=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=XXHxsbeSTAPsRdfTOzEyYcNUeHQTgvEqC/hOUmrv9Yy2Dv5eUhdI2de+Frz2Vfsl8 qsqe9SWX1H0lNX7PgbXbeWZqNHwh34ScVM+L1OKAUPX/ERQKC5ncxiPR+KmsLEPMpe l5CWYWIuECaCNWQxiVkYLIC0snqGU5+2vN2LorHA= DMARC-Filter: OpenDMARC Filter v1.3.2 smtp.codeaurora.org 71AB560A60 Authentication-Results: pdx-caf-mail.web.codeaurora.org; dmarc=none (p=none dis=none) header.from=codeaurora.org Authentication-Results: pdx-caf-mail.web.codeaurora.org; spf=none smtp.mailfrom=ilina@codeaurora.org From: Lina Iyer To: swboyd@chromium.org, evgreen@chromium.org, maz@kernel.org, linus.walleij@linaro.org Cc: linux-kernel@vger.kernel.org, linux-arm-msm@vger.kernel.org, bjorn.andersson@linaro.org, mkshah@codeaurora.org, linux-gpio@vger.kernel.org, Lina Iyer Subject: [PATCH RFC v2 04/14] drivers: irqchip: add PDC irqdomain for wakeup capable GPIOs Date: Fri, 13 Sep 2019 15:59:12 -0600 Message-Id: <1568411962-1022-5-git-send-email-ilina@codeaurora.org> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1568411962-1022-1-git-send-email-ilina@codeaurora.org> References: <1568411962-1022-1-git-send-email-ilina@codeaurora.org> Sender: linux-arm-msm-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-arm-msm@vger.kernel.org Introduce a new domain for wakeup capable GPIOs. The domain can be requested using the bus token DOMAIN_BUS_WAKEUP. In the following patches, we will specify PDC as the wakeup-parent for the TLMM GPIO irqchip. Requesting a wakeup GPIO will setup the GPIO and the corresponding PDC interrupt as its parent. Co-developed-by: Stephen Boyd Signed-off-by: Stephen Boyd Signed-off-by: Lina Iyer --- Changes in RFC v2: - Move irq_domain_qcom_handle_wakeup to the patch where it is used - Replace #define definitons - Add Signed-off-by and other minor changes --- drivers/irqchip/qcom-pdc.c | 104 +++++++++++++++++++++++++++++++++++++++---- include/linux/soc/qcom/irq.h | 19 ++++++++ 2 files changed, 114 insertions(+), 9 deletions(-) create mode 100644 include/linux/soc/qcom/irq.h diff --git a/drivers/irqchip/qcom-pdc.c b/drivers/irqchip/qcom-pdc.c index 5eef5ea..4abd775 100644 --- a/drivers/irqchip/qcom-pdc.c +++ b/drivers/irqchip/qcom-pdc.c @@ -13,12 +13,13 @@ #include #include #include +#include #include -#include #include #include #define PDC_MAX_IRQS 168 +#define PDC_MAX_GPIO_IRQS 256 #define CLEAR_INTR(reg, intr) (reg & ~(1 << intr)) #define ENABLE_INTR(reg, intr) (reg | (1 << intr)) @@ -26,6 +27,8 @@ #define IRQ_ENABLE_BANK 0x10 #define IRQ_i_CFG 0x110 +#define PDC_NO_PARENT_IRQ ~0UL + struct pdc_pin_region { u32 pin_base; u32 parent_base; @@ -65,23 +68,35 @@ static void pdc_enable_intr(struct irq_data *d, bool on) static void qcom_pdc_gic_disable(struct irq_data *d) { + if (d->hwirq == GPIO_NO_WAKE_IRQ) + return; + pdc_enable_intr(d, false); irq_chip_disable_parent(d); } static void qcom_pdc_gic_enable(struct irq_data *d) { + if (d->hwirq == GPIO_NO_WAKE_IRQ) + return; + pdc_enable_intr(d, true); irq_chip_enable_parent(d); } static void qcom_pdc_gic_mask(struct irq_data *d) { + if (d->hwirq == GPIO_NO_WAKE_IRQ) + return; + irq_chip_mask_parent(d); } static void qcom_pdc_gic_unmask(struct irq_data *d) { + if (d->hwirq == GPIO_NO_WAKE_IRQ) + return; + irq_chip_unmask_parent(d); } @@ -124,6 +139,9 @@ static int qcom_pdc_gic_set_type(struct irq_data *d, unsigned int type) int pin_out = d->hwirq; enum pdc_irq_config_bits pdc_type; + if (pin_out == GPIO_NO_WAKE_IRQ) + return 0; + switch (type) { case IRQ_TYPE_EDGE_RISING: pdc_type = PDC_EDGE_RISING; @@ -181,8 +199,7 @@ static irq_hw_number_t get_parent_hwirq(int pin) return (region->parent_base + pin - region->pin_base); } - WARN_ON(1); - return ~0UL; + return PDC_NO_PARENT_IRQ; } static int qcom_pdc_translate(struct irq_domain *d, struct irq_fwspec *fwspec, @@ -211,17 +228,17 @@ static int qcom_pdc_alloc(struct irq_domain *domain, unsigned int virq, ret = qcom_pdc_translate(domain, fwspec, &hwirq, &type); if (ret) - return -EINVAL; - - parent_hwirq = get_parent_hwirq(hwirq); - if (parent_hwirq == ~0UL) - return -EINVAL; + return ret; ret = irq_domain_set_hwirq_and_chip(domain, virq, hwirq, &qcom_pdc_gic_chip, NULL); if (ret) return ret; + parent_hwirq = get_parent_hwirq(hwirq); + if (parent_hwirq == PDC_NO_PARENT_IRQ) + return 0; + if (type & IRQ_TYPE_EDGE_BOTH) type = IRQ_TYPE_EDGE_RISING; @@ -244,6 +261,60 @@ static const struct irq_domain_ops qcom_pdc_ops = { .free = irq_domain_free_irqs_common, }; +static int qcom_pdc_gpio_alloc(struct irq_domain *domain, unsigned int virq, + unsigned int nr_irqs, void *data) +{ + struct irq_fwspec *fwspec = data; + struct irq_fwspec parent_fwspec; + irq_hw_number_t hwirq, parent_hwirq; + unsigned int type; + int ret; + + ret = qcom_pdc_translate(domain, fwspec, &hwirq, &type); + if (ret) + return ret; + + ret = irq_domain_set_hwirq_and_chip(domain, virq, hwirq, + &qcom_pdc_gic_chip, NULL); + if (ret) + return ret; + + if (hwirq == GPIO_NO_WAKE_IRQ) + return 0; + + parent_hwirq = get_parent_hwirq(hwirq); + if (parent_hwirq == PDC_NO_PARENT_IRQ) + return 0; + + if (type & IRQ_TYPE_EDGE_BOTH) + type = IRQ_TYPE_EDGE_RISING; + + if (type & IRQ_TYPE_LEVEL_MASK) + type = IRQ_TYPE_LEVEL_HIGH; + + parent_fwspec.fwnode = domain->parent->fwnode; + parent_fwspec.param_count = 3; + parent_fwspec.param[0] = 0; + parent_fwspec.param[1] = parent_hwirq; + parent_fwspec.param[2] = type; + + return irq_domain_alloc_irqs_parent(domain, virq, nr_irqs, + &parent_fwspec); +} + +static int qcom_pdc_gpio_domain_select(struct irq_domain *d, + struct irq_fwspec *fwspec, + enum irq_domain_bus_token bus_token) +{ + return bus_token == DOMAIN_BUS_WAKEUP; +} + +static const struct irq_domain_ops qcom_pdc_gpio_ops = { + .select = qcom_pdc_gpio_domain_select, + .alloc = qcom_pdc_gpio_alloc, + .free = irq_domain_free_irqs_common, +}; + static int pdc_setup_pin_mapping(struct device_node *np) { int ret, n; @@ -282,7 +353,7 @@ static int pdc_setup_pin_mapping(struct device_node *np) static int qcom_pdc_init(struct device_node *node, struct device_node *parent) { - struct irq_domain *parent_domain, *pdc_domain; + struct irq_domain *parent_domain, *pdc_domain, *pdc_gpio_domain; int ret; pdc_base = of_iomap(node, 0); @@ -313,8 +384,23 @@ static int qcom_pdc_init(struct device_node *node, struct device_node *parent) goto fail; } + pdc_gpio_domain = irq_domain_create_hierarchy(parent_domain, + IRQ_DOMAIN_FLAG_QCOM_PDC_WAKEUP, + PDC_MAX_GPIO_IRQS, + of_fwnode_handle(node), + &qcom_pdc_gpio_ops, NULL); + if (!pdc_gpio_domain) { + pr_err("%pOF: PDC domain add failed for GPIO domain\n", node); + ret = -ENOMEM; + goto remove; + } + + irq_domain_update_bus_token(pdc_gpio_domain, DOMAIN_BUS_WAKEUP); + return 0; +remove: + irq_domain_remove(pdc_domain); fail: kfree(pdc_region); iounmap(pdc_base); diff --git a/include/linux/soc/qcom/irq.h b/include/linux/soc/qcom/irq.h new file mode 100644 index 0000000..85ac4b6 --- /dev/null +++ b/include/linux/soc/qcom/irq.h @@ -0,0 +1,19 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#ifndef __QCOM_IRQ_H +#define __QCOM_IRQ_H + +#define GPIO_NO_WAKE_IRQ ~0U + +/** + * QCOM specific IRQ domain flags that distinguishes the handling of wakeup + * capable interrupts by different interrupt controllers. + * + * IRQ_DOMAIN_FLAG_QCOM_PDC_WAKEUP: Line must be masked at TLMM and the + * interrupt configuration is done at PDC + * IRQ_DOMAIN_FLAG_QCOM_MPM_WAKEUP: Interrupt configuration is handled at TLMM + */ +#define IRQ_DOMAIN_FLAG_QCOM_PDC_WAKEUP (IRQ_DOMAIN_FLAG_NONCORE << 0) +#define IRQ_DOMAIN_FLAG_QCOM_MPM_WAKEUP (IRQ_DOMAIN_FLAG_NONCORE << 1) + +#endif From patchwork Fri Sep 13 21:59:13 2019 Content-Type: text/plain; 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Fri, 13 Sep 2019 21:59:45 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=codeaurora.org; s=default; t=1568411986; bh=Nma9mWXyYVp2E0wi8Zqshh5FM0cWL4gvjEG+g+1UyeA=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=cxphENNdwsUDWvQuIOiqIc4JWPFSWkaGsuRImOb9XIuVtKg/Fs7xzokdrGyS74xnV MXJr57gCG6whBnAjGq5pvgiVejWJXwqvT9iRk7hLQzPjML3JtneFCtSjeb1IWxQTob D3G/VePO0vz3G6VZi1BTrHhqn1wsNe3JdTORylxA= DMARC-Filter: OpenDMARC Filter v1.3.2 smtp.codeaurora.org 6DF0560C72 Authentication-Results: pdx-caf-mail.web.codeaurora.org; dmarc=none (p=none dis=none) header.from=codeaurora.org Authentication-Results: pdx-caf-mail.web.codeaurora.org; spf=none smtp.mailfrom=ilina@codeaurora.org From: Lina Iyer To: swboyd@chromium.org, evgreen@chromium.org, maz@kernel.org, linus.walleij@linaro.org Cc: linux-kernel@vger.kernel.org, linux-arm-msm@vger.kernel.org, bjorn.andersson@linaro.org, mkshah@codeaurora.org, linux-gpio@vger.kernel.org, Lina Iyer , devicetree@vger.kernel.org Subject: [PATCH RFC v2 05/14] of: irq: document properties for wakeup interrupt parent Date: Fri, 13 Sep 2019 15:59:13 -0600 Message-Id: <1568411962-1022-6-git-send-email-ilina@codeaurora.org> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1568411962-1022-1-git-send-email-ilina@codeaurora.org> References: <1568411962-1022-1-git-send-email-ilina@codeaurora.org> Sender: linux-arm-msm-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-arm-msm@vger.kernel.org Some interrupt controllers in a SoC, are always powered on and have a select interrupts routed to them, so that they can wakeup the SoC from suspend. Add wakeup-parent DT property to refer to these interrupt controllers. Cc: devicetree@vger.kernel.org Signed-off-by: Lina Iyer Reviewed-by: Rob Herring Reviewed-by: Linus Walleij --- .../devicetree/bindings/interrupt-controller/interrupts.txt | 13 +++++++++++++ 1 file changed, 13 insertions(+) diff --git a/Documentation/devicetree/bindings/interrupt-controller/interrupts.txt b/Documentation/devicetree/bindings/interrupt-controller/interrupts.txt index 8a3c408..c10e310 100644 --- a/Documentation/devicetree/bindings/interrupt-controller/interrupts.txt +++ b/Documentation/devicetree/bindings/interrupt-controller/interrupts.txt @@ -108,3 +108,16 @@ commonly used: sensitivity = <7>; }; }; + +3) Interrupt wakeup parent +-------------------------- + +Some interrupt controllers in a SoC, are always powered on and have a select +interrupts routed to them, so that they can wakeup the SoC from suspend. These +interrupt controllers do not fall into the category of a parent interrupt +controller and can be specified by the "wakeup-parent" property and contain a +single phandle referring to the wakeup capable interrupt controller. + + Example: + wakeup-parent = <&pdc_intc>; + From patchwork Fri Sep 13 21:59:14 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Lina Iyer X-Patchwork-Id: 11145355 Return-Path: Received: from mail.kernel.org (pdx-korg-mail-1.web.codeaurora.org [172.30.200.123]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id 80DD71395 for ; Fri, 13 Sep 2019 22:00:22 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.kernel.org (Postfix) with ESMTP id 60F3D20CC7 for ; Fri, 13 Sep 2019 22:00:22 +0000 (UTC) Authentication-Results: mail.kernel.org; dkim=fail reason="key not found in DNS" (0-bit key) header.d=codeaurora.org header.i=@codeaurora.org header.b="Imn5MV4F"; dkim=fail reason="key not found in DNS" (0-bit key) header.d=codeaurora.org header.i=@codeaurora.org header.b="WdDYeuyc" Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S2390255AbfIMV7t (ORCPT ); Fri, 13 Sep 2019 17:59:49 -0400 Received: from smtp.codeaurora.org ([198.145.29.96]:59796 "EHLO smtp.codeaurora.org" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S2390350AbfIMV7t (ORCPT ); Fri, 13 Sep 2019 17:59:49 -0400 Received: by smtp.codeaurora.org (Postfix, from userid 1000) id 13FEA61213; Fri, 13 Sep 2019 21:59:48 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=codeaurora.org; s=default; t=1568411988; bh=DGRUcZkX4E9MP9Et/d3SKghyE5Vp0MuEkL3EhOi3LeA=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=Imn5MV4F/B/4jek4DtGuiAOwq9WprEWOogJfWQ6hbbMfoMTGRuz8/UeAKIavy2kBM Xg38QsptXuOi1xAMPXwOjEBq4zxDkY/QjmH6HoZmD16/YDqOSVNA8phAQdGHG5cR1A 6YWMOT6zPxkCO/Ond3eSERxOLLsNRjU2bOLDO9IA= X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on pdx-caf-mail.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-2.7 required=2.0 tests=ALL_TRUSTED,BAYES_00, DKIM_INVALID,DKIM_SIGNED,SPF_NONE autolearn=no autolearn_force=no version=3.4.0 Received: from codeaurora.org (i-global254.qualcomm.com [199.106.103.254]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-SHA256 (128/128 bits)) (No client certificate requested) (Authenticated sender: ilina@smtp.codeaurora.org) by smtp.codeaurora.org (Postfix) with ESMTPSA id 82031611C5; Fri, 13 Sep 2019 21:59:46 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=codeaurora.org; s=default; t=1568411987; bh=DGRUcZkX4E9MP9Et/d3SKghyE5Vp0MuEkL3EhOi3LeA=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=WdDYeuyc+ms22wHWnXHHwjHmZGuIFJNkoSaXiQTsX5hBFF6Xz2RXoRdLCi4jago4x XBK1S1lcto54FMBwApzioCMjfRQL8Flx3/VXqPqYJ+H0wlyd8qmD0EZISF4dgSsR+c Jm6qmB2gwLQRWRSfOjjkKmEnr7OHsJLHYYXgqRGg= DMARC-Filter: OpenDMARC Filter v1.3.2 smtp.codeaurora.org 82031611C5 Authentication-Results: pdx-caf-mail.web.codeaurora.org; dmarc=none (p=none dis=none) header.from=codeaurora.org Authentication-Results: pdx-caf-mail.web.codeaurora.org; spf=none smtp.mailfrom=ilina@codeaurora.org From: Lina Iyer To: swboyd@chromium.org, evgreen@chromium.org, maz@kernel.org, linus.walleij@linaro.org Cc: linux-kernel@vger.kernel.org, linux-arm-msm@vger.kernel.org, bjorn.andersson@linaro.org, mkshah@codeaurora.org, linux-gpio@vger.kernel.org, Lina Iyer , devicetree@vger.kernel.org Subject: [PATCH RFC v2 06/14] dt-bindings/interrupt-controller: pdc: add SPI config register Date: Fri, 13 Sep 2019 15:59:14 -0600 Message-Id: <1568411962-1022-7-git-send-email-ilina@codeaurora.org> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1568411962-1022-1-git-send-email-ilina@codeaurora.org> References: <1568411962-1022-1-git-send-email-ilina@codeaurora.org> Sender: linux-arm-msm-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-arm-msm@vger.kernel.org In addition to configuring the PDC, additional registers that interface the GIC have to be configured to match the GPIO type. The registers on some QCOM SoCs are access restricted, while on other SoCs are not. They SoCs with access restriction to these SPI registers need to be written from the firmware using the SCM interface. Add a flag to indicate if the register is to be written using SCM interface. Cc: devicetree@vger.kernel.org Signed-off-by: Lina Iyer Reviewed-by: Rob Herring --- .../devicetree/bindings/interrupt-controller/qcom,pdc.txt | 13 ++++++++++++- 1 file changed, 12 insertions(+), 1 deletion(-) diff --git a/Documentation/devicetree/bindings/interrupt-controller/qcom,pdc.txt b/Documentation/devicetree/bindings/interrupt-controller/qcom,pdc.txt index 8e0797c..e329f8d 100644 --- a/Documentation/devicetree/bindings/interrupt-controller/qcom,pdc.txt +++ b/Documentation/devicetree/bindings/interrupt-controller/qcom,pdc.txt @@ -24,6 +24,9 @@ Properties: Usage: required Value type: Definition: Specifies the base physical address for PDC hardware. + Optionally, specify the PDC's GIC interface registers that + need to be configured for wakeup capable GPIOs routed to + the PDC. - interrupt-cells: Usage: required @@ -50,15 +53,23 @@ Properties: The second element is the GIC hwirq number for the PDC port. The third element is the number of interrupts in sequence. +- qcom,scm-spi-cfg: + Usage: optional + Value type: + Definition: Specifies if the SPI configuration registers have to be + written from the firmware. Sometimes the PDC interface + register to the GIC can only be written from the firmware. + Example: pdc: interrupt-controller@b220000 { compatible = "qcom,sdm845-pdc"; - reg = <0xb220000 0x30000>; + reg = <0 0x0b220000 0 0x30000>, <0 0x179900f0 0 0x60>; qcom,pdc-ranges = <0 512 94>, <94 641 15>, <115 662 7>; #interrupt-cells = <2>; interrupt-parent = <&intc>; interrupt-controller; + qcom,scm-spi-cfg; }; DT binding of a device that wants to use the GIC SPI 514 as a wakeup From patchwork Fri Sep 13 21:59:15 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Lina Iyer X-Patchwork-Id: 11145353 Return-Path: Received: from mail.kernel.org (pdx-korg-mail-1.web.codeaurora.org [172.30.200.123]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id 0D48D1395 for ; Fri, 13 Sep 2019 22:00:21 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.kernel.org (Postfix) with ESMTP id D952620CC7 for ; Fri, 13 Sep 2019 22:00:20 +0000 (UTC) Authentication-Results: mail.kernel.org; dkim=fail reason="key not found in DNS" (0-bit key) header.d=codeaurora.org header.i=@codeaurora.org header.b="GeBi1Gyp"; dkim=fail reason="key not found in DNS" (0-bit key) header.d=codeaurora.org header.i=@codeaurora.org header.b="GeBi1Gyp" Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S2390537AbfIMV7v (ORCPT ); Fri, 13 Sep 2019 17:59:51 -0400 Received: from smtp.codeaurora.org ([198.145.29.96]:59838 "EHLO smtp.codeaurora.org" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S2390431AbfIMV7u (ORCPT ); Fri, 13 Sep 2019 17:59:50 -0400 Received: by smtp.codeaurora.org (Postfix, from userid 1000) id CE44A61231; Fri, 13 Sep 2019 21:59:48 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=codeaurora.org; s=default; t=1568411988; bh=D72EJTD2RGe2SPhGafah7f7DzgpjP9aQgjraD4RHoiM=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=GeBi1GypDzFndf2zoqBXNKaYStly77TVzNgQX2yG8rQl8Hq3AkghbpDUjCT1pupKQ ss4Q67M9/XHuwLUBCg7+J7e0sZ4lQ9X9eRUXAcikcZLEKegx1fctUH9ss7W2dgorfE ZyGvEZqG9W8dXXiRN5/sj7Dxgwz1SyTZeVSY/Tig= X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on pdx-caf-mail.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-2.7 required=2.0 tests=ALL_TRUSTED,BAYES_00, DKIM_INVALID,DKIM_SIGNED,SPF_NONE autolearn=no autolearn_force=no version=3.4.0 Received: from codeaurora.org (i-global254.qualcomm.com [199.106.103.254]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-SHA256 (128/128 bits)) (No client certificate requested) (Authenticated sender: ilina@smtp.codeaurora.org) by smtp.codeaurora.org (Postfix) with ESMTPSA id 8DD59611CE; Fri, 13 Sep 2019 21:59:47 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=codeaurora.org; s=default; t=1568411988; bh=D72EJTD2RGe2SPhGafah7f7DzgpjP9aQgjraD4RHoiM=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=GeBi1GypDzFndf2zoqBXNKaYStly77TVzNgQX2yG8rQl8Hq3AkghbpDUjCT1pupKQ ss4Q67M9/XHuwLUBCg7+J7e0sZ4lQ9X9eRUXAcikcZLEKegx1fctUH9ss7W2dgorfE ZyGvEZqG9W8dXXiRN5/sj7Dxgwz1SyTZeVSY/Tig= DMARC-Filter: OpenDMARC Filter v1.3.2 smtp.codeaurora.org 8DD59611CE Authentication-Results: pdx-caf-mail.web.codeaurora.org; dmarc=none (p=none dis=none) header.from=codeaurora.org Authentication-Results: pdx-caf-mail.web.codeaurora.org; spf=none smtp.mailfrom=ilina@codeaurora.org From: Lina Iyer To: swboyd@chromium.org, evgreen@chromium.org, maz@kernel.org, linus.walleij@linaro.org Cc: linux-kernel@vger.kernel.org, linux-arm-msm@vger.kernel.org, bjorn.andersson@linaro.org, mkshah@codeaurora.org, linux-gpio@vger.kernel.org, Lina Iyer Subject: [PATCH RFC v2 07/14] drivers: irqchip: pdc: additionally set type in SPI config registers Date: Fri, 13 Sep 2019 15:59:15 -0600 Message-Id: <1568411962-1022-8-git-send-email-ilina@codeaurora.org> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1568411962-1022-1-git-send-email-ilina@codeaurora.org> References: <1568411962-1022-1-git-send-email-ilina@codeaurora.org> Sender: linux-arm-msm-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-arm-msm@vger.kernel.org GPIOs that can be configured as wakeup are routed to the PDC wakeup interrupt controller and from there to the GIC interrupt controller. On some QCOM SoCs, the interface to the GIC for wakeup capable GPIOs have additional hardware registers that need to be configured as well to match the trigger type of the GPIO. This register interfaces the PDC to the GIC and therefore updated from the PDC driver. Typically, the firmware intializes the interface registers for the wakeup capable GPIOs with commonly used GPIO trigger type, but it is possible that a platform may want to use the GPIO differently. So, in addition to configuring the PDC, configure the interface registers as well. Signed-off-by: Lina Iyer --- drivers/irqchip/qcom-pdc.c | 93 ++++++++++++++++++++++++++++++++++++++++++++++ 1 file changed, 93 insertions(+) diff --git a/drivers/irqchip/qcom-pdc.c b/drivers/irqchip/qcom-pdc.c index 4abd775..affb0bfa 100644 --- a/drivers/irqchip/qcom-pdc.c +++ b/drivers/irqchip/qcom-pdc.c @@ -18,6 +18,8 @@ #include #include +#include + #define PDC_MAX_IRQS 168 #define PDC_MAX_GPIO_IRQS 256 @@ -35,10 +37,20 @@ struct pdc_pin_region { u32 cnt; }; +struct spi_cfg_regs { + union { + u64 start; + void __iomem *base; + }; + resource_size_t size; + bool scm_io; +}; + static DEFINE_RAW_SPINLOCK(pdc_lock); static void __iomem *pdc_base; static struct pdc_pin_region *pdc_region; static int pdc_region_cnt; +static struct spi_cfg_regs *spi_cfg; static void pdc_reg_write(int reg, u32 i, u32 val) { @@ -100,6 +112,57 @@ static void qcom_pdc_gic_unmask(struct irq_data *d) irq_chip_unmask_parent(d); } +static u32 __spi_pin_read(unsigned int pin) +{ + void __iomem *cfg_reg = spi_cfg->base + pin * 4; + u64 scm_cfg_reg = spi_cfg->start + pin * 4; + + if (spi_cfg->scm_io) { + unsigned int val; + + qcom_scm_io_readl(scm_cfg_reg, &val); + return val; + } else { + return readl(cfg_reg); + } +} + +static void __spi_pin_write(unsigned int pin, unsigned int val) +{ + void __iomem *cfg_reg = spi_cfg->base + pin * 4; + u64 scm_cfg_reg = spi_cfg->start + pin * 4; + + if (spi_cfg->scm_io) + qcom_scm_io_writel(scm_cfg_reg, val); + else + writel(val, cfg_reg); +} + +static int spi_configure_type(irq_hw_number_t hwirq, unsigned int type) +{ + int spi = hwirq - 32; + u32 pin = spi / 32; + u32 mask = BIT(spi % 32); + u32 val; + unsigned long flags; + + if (!spi_cfg) + return 0; + + if (pin * 4 > spi_cfg->size) + return -EFAULT; + + raw_spin_lock_irqsave(&pdc_lock, flags); + val = __spi_pin_read(pin); + val &= ~mask; + if (type & IRQ_TYPE_LEVEL_MASK) + val |= mask; + __spi_pin_write(pin, val); + raw_spin_unlock_irqrestore(&pdc_lock, flags); + + return 0; +} + /* * GIC does not handle falling edge or active low. To allow falling edge and * active low interrupts to be handled at GIC, PDC has an inverter that inverts @@ -137,7 +200,9 @@ enum pdc_irq_config_bits { static int qcom_pdc_gic_set_type(struct irq_data *d, unsigned int type) { int pin_out = d->hwirq; + int parent_hwirq = d->parent_data->hwirq; enum pdc_irq_config_bits pdc_type; + int ret; if (pin_out == GPIO_NO_WAKE_IRQ) return 0; @@ -168,6 +233,11 @@ static int qcom_pdc_gic_set_type(struct irq_data *d, unsigned int type) pdc_reg_write(IRQ_i_CFG, pin_out, pdc_type); + /* Additionally, configure (only) the GPIO in the f/w */ + ret = spi_configure_type(parent_hwirq, type); + if (ret) + return ret; + return irq_chip_set_type_parent(d, type); } @@ -354,6 +424,7 @@ static int pdc_setup_pin_mapping(struct device_node *np) static int qcom_pdc_init(struct device_node *node, struct device_node *parent) { struct irq_domain *parent_domain, *pdc_domain, *pdc_gpio_domain; + struct resource res; int ret; pdc_base = of_iomap(node, 0); @@ -384,6 +455,27 @@ static int qcom_pdc_init(struct device_node *node, struct device_node *parent) goto fail; } + ret = of_address_to_resource(node, 1, &res); + if (!ret) { + spi_cfg = kcalloc(1, sizeof(*spi_cfg), GFP_KERNEL); + if (!spi_cfg) { + ret = -ENOMEM; + goto remove; + } + spi_cfg->scm_io = of_find_property(node, + "qcom,scm-spi-cfg", NULL); + spi_cfg->size = resource_size(&res); + if (spi_cfg->scm_io) { + spi_cfg->start = res.start; + } else { + spi_cfg->base = ioremap(res.start, spi_cfg->size); + if (!spi_cfg->base) { + ret = -ENOMEM; + goto remove; + } + } + } + pdc_gpio_domain = irq_domain_create_hierarchy(parent_domain, IRQ_DOMAIN_FLAG_QCOM_PDC_WAKEUP, PDC_MAX_GPIO_IRQS, @@ -401,6 +493,7 @@ static int qcom_pdc_init(struct device_node *node, struct device_node *parent) remove: irq_domain_remove(pdc_domain); + kfree(spi_cfg); fail: kfree(pdc_region); iounmap(pdc_base); From patchwork Fri Sep 13 21:59:16 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Lina Iyer X-Patchwork-Id: 11145351 Return-Path: Received: from mail.kernel.org (pdx-korg-mail-1.web.codeaurora.org [172.30.200.123]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id 861F417E6 for ; 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h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=ChBh9U/6oOwqK3wMOxW3DwvFOifAU48UTZT4uloj3FeTugaToJ7G9QNFRHp6CgZ/J 809XILEYeGw61mX7Vfr6eRZkLINIgQAmLXjcg6FczH2Jol0hde86akq/L1TDjSFw0n ouRD8qDah9+FuvrGEuGJQj5i87fzvn2VbWedPVbc= DMARC-Filter: OpenDMARC Filter v1.3.2 smtp.codeaurora.org 8CCB061215 Authentication-Results: pdx-caf-mail.web.codeaurora.org; dmarc=none (p=none dis=none) header.from=codeaurora.org Authentication-Results: pdx-caf-mail.web.codeaurora.org; spf=none smtp.mailfrom=ilina@codeaurora.org From: Lina Iyer To: swboyd@chromium.org, evgreen@chromium.org, maz@kernel.org, linus.walleij@linaro.org Cc: linux-kernel@vger.kernel.org, linux-arm-msm@vger.kernel.org, bjorn.andersson@linaro.org, mkshah@codeaurora.org, linux-gpio@vger.kernel.org, Lina Iyer Subject: [PATCH RFC v2 08/14] genirq: Introduce irq_chip_get/set_parent_state calls Date: Fri, 13 Sep 2019 15:59:16 -0600 Message-Id: <1568411962-1022-9-git-send-email-ilina@codeaurora.org> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1568411962-1022-1-git-send-email-ilina@codeaurora.org> References: <1568411962-1022-1-git-send-email-ilina@codeaurora.org> Sender: linux-arm-msm-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-arm-msm@vger.kernel.org From: Maulik Shah On certain QTI chipsets some GPIOs are direct-connect interrupts to the GIC to be used as regular interrupt lines. When the GPIOs are not used for interrupt generation the interrupt line is disabled. But disabling the interrupt at GIC does not prevent the interrupt to be reported as pending at GIC_ISPEND. Later, when drivers call enable_irq() on the interrupt, an unwanted interrupt occurs. Introduce get and set methods for irqchip's parent to clear it's pending irq state. This then can be invoked by the GPIO interrupt controller on the parents in it hierarchy to clear the interrupt before enabling the interrupt. Signed-off-by: Maulik Shah [updated commit text and minor code fixes] Signed-off-by: Lina Iyer --- Changes in RFC v2 - - Rephrase commit text - Address code review comments --- include/linux/irq.h | 6 ++++++ kernel/irq/chip.c | 44 ++++++++++++++++++++++++++++++++++++++++++++ 2 files changed, 50 insertions(+) diff --git a/include/linux/irq.h b/include/linux/irq.h index fb301cf..7853eb9 100644 --- a/include/linux/irq.h +++ b/include/linux/irq.h @@ -610,6 +610,12 @@ extern int irq_chip_pm_put(struct irq_data *data); #ifdef CONFIG_IRQ_DOMAIN_HIERARCHY extern void handle_fasteoi_ack_irq(struct irq_desc *desc); extern void handle_fasteoi_mask_irq(struct irq_desc *desc); +extern int irq_chip_set_parent_state(struct irq_data *data, + enum irqchip_irq_state which, + bool val); +extern int irq_chip_get_parent_state(struct irq_data *data, + enum irqchip_irq_state which, + bool *state); extern void irq_chip_enable_parent(struct irq_data *data); extern void irq_chip_disable_parent(struct irq_data *data); extern void irq_chip_ack_parent(struct irq_data *data); diff --git a/kernel/irq/chip.c b/kernel/irq/chip.c index b76703b..b3fa2d8 100644 --- a/kernel/irq/chip.c +++ b/kernel/irq/chip.c @@ -1298,6 +1298,50 @@ EXPORT_SYMBOL_GPL(handle_fasteoi_mask_irq); #endif /* CONFIG_IRQ_FASTEOI_HIERARCHY_HANDLERS */ /** + * irq_chip_set_parent_state - set the state of a parent interrupt. + * + * @data: Pointer to interrupt specific data + * @which: State to be restored (one of IRQCHIP_STATE_*) + * @val: Value corresponding to @which + * + * Conditional success, if the underlying irqchip does not implement it. + */ +int irq_chip_set_parent_state(struct irq_data *data, + enum irqchip_irq_state which, + bool val) +{ + data = data->parent_data; + + if (!data || !data->chip->irq_set_irqchip_state) + return 0; + + return data->chip->irq_set_irqchip_state(data, which, val); +} +EXPORT_SYMBOL_GPL(irq_chip_set_parent_state); + +/** + * irq_chip_get_parent_state - get the state of a parent interrupt. + * + * @data: Pointer to interrupt specific data + * @which: one of IRQCHIP_STATE_* the caller wants to know + * @state: a pointer to a boolean where the state is to be stored + * + * Conditional success, if the underlying irqchip does not implement it. + */ +int irq_chip_get_parent_state(struct irq_data *data, + enum irqchip_irq_state which, + bool *state) +{ + data = data->parent_data; + + if (!data || !data->chip->irq_get_irqchip_state) + return 0; + + return data->chip->irq_get_irqchip_state(data, which, state); +} +EXPORT_SYMBOL_GPL(irq_chip_get_parent_state); + +/** * irq_chip_enable_parent - Enable the parent interrupt (defaults to unmask if * NULL) * @data: Pointer to interrupt specific data From patchwork Fri Sep 13 21:59:17 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Lina Iyer X-Patchwork-Id: 11145349 Return-Path: Received: from mail.kernel.org (pdx-korg-mail-1.web.codeaurora.org [172.30.200.123]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id D2A411395 for ; Fri, 13 Sep 2019 22:00:19 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.kernel.org (Postfix) with ESMTP id B30E7214D9 for ; Fri, 13 Sep 2019 22:00:19 +0000 (UTC) Authentication-Results: mail.kernel.org; dkim=fail reason="key not found in DNS" (0-bit key) header.d=codeaurora.org header.i=@codeaurora.org header.b="KsllB6Em"; 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Fri, 13 Sep 2019 21:59:49 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=codeaurora.org; s=default; t=1568411990; bh=PdwMJsA9h89YRbDUO1YMlOlH2+m9AQqQkm7xDJFf0jQ=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=KsllB6EmSPRPeZKRIyykgAO0eUava43hncoPY7JCxMPWRh1fGinfiQc28YDpQmCGl IQv1/oEZHRK2dJK2XpsZLsQkJtIQnuYwD55zFjH+oq9UF9DIM2yxOCw4z+FMBqMm1N 8NG+2/UZhCkOmXubu5dicruAO8gOwSKDJXxL45Ag= DMARC-Filter: OpenDMARC Filter v1.3.2 smtp.codeaurora.org 9132A611CE Authentication-Results: pdx-caf-mail.web.codeaurora.org; dmarc=none (p=none dis=none) header.from=codeaurora.org Authentication-Results: pdx-caf-mail.web.codeaurora.org; spf=none smtp.mailfrom=ilina@codeaurora.org From: Lina Iyer To: swboyd@chromium.org, evgreen@chromium.org, maz@kernel.org, linus.walleij@linaro.org Cc: linux-kernel@vger.kernel.org, linux-arm-msm@vger.kernel.org, bjorn.andersson@linaro.org, mkshah@codeaurora.org, linux-gpio@vger.kernel.org, Lina Iyer Subject: [PATCH RFC v2 09/14] drivers: irqchip: pdc: Add irqchip set/get state calls Date: Fri, 13 Sep 2019 15:59:17 -0600 Message-Id: <1568411962-1022-10-git-send-email-ilina@codeaurora.org> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1568411962-1022-1-git-send-email-ilina@codeaurora.org> References: <1568411962-1022-1-git-send-email-ilina@codeaurora.org> Sender: linux-arm-msm-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-arm-msm@vger.kernel.org From: Maulik Shah Add irqchip calls to set/get interrupt state from the parent interrupt controller. When GPIOs are renabled as interrupt lines, it is desirable to clear the interrupt state at the GIC. This avoids any unwanted interrupt as a result of stale pending state recorded when the line was used as a GPIO. Signed-off-by: Maulik Shah [updated commit text] Signed-off-by: Lina Iyer --- drivers/irqchip/qcom-pdc.c | 21 +++++++++++++++++++++ 1 file changed, 21 insertions(+) diff --git a/drivers/irqchip/qcom-pdc.c b/drivers/irqchip/qcom-pdc.c index affb0bfa..2b49e70 100644 --- a/drivers/irqchip/qcom-pdc.c +++ b/drivers/irqchip/qcom-pdc.c @@ -5,6 +5,7 @@ #include #include +#include #include #include #include @@ -87,6 +88,24 @@ static void qcom_pdc_gic_disable(struct irq_data *d) irq_chip_disable_parent(d); } +static int qcom_pdc_gic_get_irqchip_state(struct irq_data *d, + enum irqchip_irq_state which, bool *state) +{ + if (d->hwirq == GPIO_NO_WAKE_IRQ) + return 0; + + return irq_chip_get_parent_state(d, which, state); +} + +static int qcom_pdc_gic_set_irqchip_state(struct irq_data *d, + enum irqchip_irq_state which, bool value) +{ + if (d->hwirq == GPIO_NO_WAKE_IRQ) + return 0; + + return irq_chip_set_parent_state(d, which, value); +} + static void qcom_pdc_gic_enable(struct irq_data *d) { if (d->hwirq == GPIO_NO_WAKE_IRQ) @@ -248,6 +267,8 @@ static struct irq_chip qcom_pdc_gic_chip = { .irq_unmask = qcom_pdc_gic_unmask, .irq_disable = qcom_pdc_gic_disable, .irq_enable = qcom_pdc_gic_enable, + .irq_get_irqchip_state = qcom_pdc_gic_get_irqchip_state, + .irq_set_irqchip_state = qcom_pdc_gic_set_irqchip_state, .irq_retrigger = irq_chip_retrigger_hierarchy, .irq_set_type = qcom_pdc_gic_set_type, .flags = IRQCHIP_MASK_ON_SUSPEND | From patchwork Fri Sep 13 21:59:18 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Lina Iyer X-Patchwork-Id: 11145345 Return-Path: Received: from mail.kernel.org (pdx-korg-mail-1.web.codeaurora.org [172.30.200.123]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id 961D617E6 for ; Fri, 13 Sep 2019 22:00:10 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.kernel.org (Postfix) with ESMTP id 6625D21897 for ; Fri, 13 Sep 2019 22:00:10 +0000 (UTC) Authentication-Results: mail.kernel.org; dkim=fail reason="key not found in DNS" (0-bit key) header.d=codeaurora.org header.i=@codeaurora.org header.b="Eeh2x1jf"; dkim=fail reason="key not found in DNS" (0-bit key) header.d=codeaurora.org header.i=@codeaurora.org header.b="VAnW58aa" Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S2403789AbfIMV7y (ORCPT ); Fri, 13 Sep 2019 17:59:54 -0400 Received: from smtp.codeaurora.org ([198.145.29.96]:60134 "EHLO smtp.codeaurora.org" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S2390564AbfIMV7y (ORCPT ); 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Fri, 13 Sep 2019 21:59:50 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=codeaurora.org; s=default; t=1568411991; bh=xTGRNviMhGXnSFoKJKqthHSateNRWbIby0VAJSXYSRY=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=VAnW58aa0lZHjucSNWnbGnQ2sLy5FWNY6z4EqlKiF7z360h9HxJSaaezU5cP78Rkz 1NYzIKOuZGkcShTw4PJEnIHXlrr8rfCrP3TIc6QZPYcdlNQmXwaVBx8aO6w5vzGGcW GtvYfjnS/YbhhzeFe8GU61YruixrhcHALQPRbgoM= DMARC-Filter: OpenDMARC Filter v1.3.2 smtp.codeaurora.org 907976132B Authentication-Results: pdx-caf-mail.web.codeaurora.org; dmarc=none (p=none dis=none) header.from=codeaurora.org Authentication-Results: pdx-caf-mail.web.codeaurora.org; spf=none smtp.mailfrom=ilina@codeaurora.org From: Lina Iyer To: swboyd@chromium.org, evgreen@chromium.org, maz@kernel.org, linus.walleij@linaro.org Cc: linux-kernel@vger.kernel.org, linux-arm-msm@vger.kernel.org, bjorn.andersson@linaro.org, mkshah@codeaurora.org, linux-gpio@vger.kernel.org, Lina Iyer Subject: [PATCH RFC v2 10/14] drivers: pinctrl: msm: setup GPIO chip in hierarchy Date: Fri, 13 Sep 2019 15:59:18 -0600 Message-Id: <1568411962-1022-11-git-send-email-ilina@codeaurora.org> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1568411962-1022-1-git-send-email-ilina@codeaurora.org> References: <1568411962-1022-1-git-send-email-ilina@codeaurora.org> Sender: linux-arm-msm-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-arm-msm@vger.kernel.org Some GPIOs are marked as wakeup capable and are routed to another interrupt controller that is an always-domain and can detect interrupts even most of the SoC is powered off. The wakeup interrupt controller wakes up the GIC and replays the interrupt at the GIC. Setup the TLMM irqchip in hierarchy with the wakeup interrupt controller and ensure the wakeup GPIOs are handled correctly. Signed-off-by: Maulik Shah Signed-off-by: Lina Iyer ---- Changes in RFC v2: - Define irq_domain_qcom_handle_wakeup() - Rebase on top of GPIO hierarchy support in linux-next - Set the chained irq handler for summary line --- drivers/pinctrl/qcom/pinctrl-msm.c | 119 +++++++++++++++++++++++++++++++++++++ drivers/pinctrl/qcom/pinctrl-msm.h | 16 +++++ include/linux/soc/qcom/irq.h | 13 ++++ 3 files changed, 148 insertions(+) diff --git a/drivers/pinctrl/qcom/pinctrl-msm.c b/drivers/pinctrl/qcom/pinctrl-msm.c index f355ddd..c5ba389 100644 --- a/drivers/pinctrl/qcom/pinctrl-msm.c +++ b/drivers/pinctrl/qcom/pinctrl-msm.c @@ -23,6 +23,8 @@ #include #include +#include + #include "../core.h" #include "../pinconf.h" #include "pinctrl-msm.h" @@ -44,6 +46,7 @@ * @enabled_irqs: Bitmap of currently enabled irqs. * @dual_edge_irqs: Bitmap of irqs that need sw emulated dual edge * detection. + * @skip_wake_irqs: Skip IRQs that are handled by wakeup interrupt contrroller * @soc; Reference to soc_data of platform specific data. * @regs: Base addresses for the TLMM tiles. */ @@ -61,6 +64,7 @@ struct msm_pinctrl { DECLARE_BITMAP(dual_edge_irqs, MAX_NR_GPIO); DECLARE_BITMAP(enabled_irqs, MAX_NR_GPIO); + DECLARE_BITMAP(skip_wake_irqs, MAX_NR_GPIO); const struct msm_pinctrl_soc_data *soc; void __iomem *regs[MAX_NR_TILES]; @@ -709,6 +713,12 @@ static void msm_gpio_irq_mask(struct irq_data *d) unsigned long flags; u32 val; + if (d->parent_data) + irq_chip_mask_parent(d); + + if (test_bit(d->hwirq, pctrl->skip_wake_irqs)) + return; + g = &pctrl->soc->groups[d->hwirq]; raw_spin_lock_irqsave(&pctrl->lock, flags); @@ -753,6 +763,12 @@ static void msm_gpio_irq_clear_unmask(struct irq_data *d, bool status_clear) unsigned long flags; u32 val; + if (d->parent_data) + irq_chip_unmask_parent(d); + + if (test_bit(d->hwirq, pctrl->skip_wake_irqs)) + return; + g = &pctrl->soc->groups[d->hwirq]; raw_spin_lock_irqsave(&pctrl->lock, flags); @@ -780,10 +796,37 @@ static void msm_gpio_irq_clear_unmask(struct irq_data *d, bool status_clear) static void msm_gpio_irq_enable(struct irq_data *d) { + /* + * Clear the interrupt that may be pending before we enable + * the line. + * This is especially a problem with the GPIOs routed to the + * PDC. These GPIOs are direct-connect interrupts to the GIC. + * Disabling the interrupt line at the PDC does not prevent + * the interrupt from being latched at the GIC. The state at + * GIC needs to be cleared before enabling. + */ + if (d->parent_data) { + irq_chip_set_parent_state(d, IRQCHIP_STATE_PENDING, 0); + irq_chip_enable_parent(d); + } msm_gpio_irq_clear_unmask(d, true); } +static void msm_gpio_irq_disable(struct irq_data *d) +{ + struct gpio_chip *gc = irq_data_get_irq_chip_data(d); + struct msm_pinctrl *pctrl = gpiochip_get_data(gc); + + if (d->parent_data) + irq_chip_disable_parent(d); + + if (test_bit(d->hwirq, pctrl->skip_wake_irqs)) + return; + + msm_gpio_irq_mask(d); +} + static void msm_gpio_irq_unmask(struct irq_data *d) { msm_gpio_irq_clear_unmask(d, false); @@ -797,6 +840,9 @@ static void msm_gpio_irq_ack(struct irq_data *d) unsigned long flags; u32 val; + if (test_bit(d->hwirq, pctrl->skip_wake_irqs)) + return; + g = &pctrl->soc->groups[d->hwirq]; raw_spin_lock_irqsave(&pctrl->lock, flags); @@ -822,6 +868,12 @@ static int msm_gpio_irq_set_type(struct irq_data *d, unsigned int type) unsigned long flags; u32 val; + if (d->parent_data) + irq_chip_set_type_parent(d, type); + + if (test_bit(d->hwirq, pctrl->skip_wake_irqs)) + return 0; + g = &pctrl->soc->groups[d->hwirq]; raw_spin_lock_irqsave(&pctrl->lock, flags); @@ -914,6 +966,15 @@ static int msm_gpio_irq_set_wake(struct irq_data *d, unsigned int on) struct msm_pinctrl *pctrl = gpiochip_get_data(gc); unsigned long flags; + if (d->parent_data) + irq_chip_set_wake_parent(d, on); + + /* + * While they may not wake up when the TLMM is powered off, + * some GPIOs would like to wakeup the system from suspend + * when TLMM is powered on. To allow that, enable the GPIO + * summary line to be wakeup capable at GIC. + */ raw_spin_lock_irqsave(&pctrl->lock, flags); irq_set_irq_wake(pctrl->irq, on); @@ -992,6 +1053,30 @@ static void msm_gpio_irq_handler(struct irq_desc *desc) chained_irq_exit(chip, desc); } +static int msm_gpio_wakeirq(struct gpio_chip *gc, + unsigned int child, + unsigned int child_type, + unsigned int *parent, + unsigned int *parent_type) +{ + struct msm_pinctrl *pctrl = gpiochip_get_data(gc); + const struct msm_gpio_wakeirq_map *map; + int i; + + *parent = GPIO_NO_WAKE_IRQ; + *parent_type = IRQ_TYPE_EDGE_RISING; + + for (i = 0; i < pctrl->soc->nwakeirq_map; i++) { + map = &pctrl->soc->wakeirq_map[i]; + if (map->gpio == child) { + *parent = map->wakeirq; + break; + } + } + + return 0; +} + static bool msm_gpio_needs_valid_mask(struct msm_pinctrl *pctrl) { if (pctrl->soc->reserved_gpios) @@ -1006,6 +1091,7 @@ static int msm_gpio_init(struct msm_pinctrl *pctrl) struct gpio_irq_chip *girq; int ret; unsigned ngpio = pctrl->soc->ngpios; + struct device_node *dn; if (WARN_ON(ngpio > MAX_NR_GPIO)) return -EINVAL; @@ -1021,17 +1107,40 @@ static int msm_gpio_init(struct msm_pinctrl *pctrl) pctrl->irq_chip.name = "msmgpio"; pctrl->irq_chip.irq_enable = msm_gpio_irq_enable; + pctrl->irq_chip.irq_disable = msm_gpio_irq_disable; pctrl->irq_chip.irq_mask = msm_gpio_irq_mask; pctrl->irq_chip.irq_unmask = msm_gpio_irq_unmask; pctrl->irq_chip.irq_ack = msm_gpio_irq_ack; + pctrl->irq_chip.irq_eoi = irq_chip_eoi_parent; pctrl->irq_chip.irq_set_type = msm_gpio_irq_set_type; pctrl->irq_chip.irq_set_wake = msm_gpio_irq_set_wake; pctrl->irq_chip.irq_request_resources = msm_gpio_irq_reqres; pctrl->irq_chip.irq_release_resources = msm_gpio_irq_relres; + dn = of_parse_phandle(pctrl->dev->of_node, "wakeup-parent", 0); + if (dn) { + int i; + bool skip; + unsigned int gpio; + + chip->irq.parent_domain = irq_find_matching_host(dn, + DOMAIN_BUS_WAKEUP); + of_node_put(dn); + if (!chip->irq.parent_domain) + return -EPROBE_DEFER; + chip->irq.child_to_parent_hwirq = msm_gpio_wakeirq; + + skip = irq_domain_qcom_handle_wakeup(chip->irq.parent_domain); + for (i = 0; skip && i < pctrl->soc->nwakeirq_map; i++) { + gpio = pctrl->soc->wakeirq_map[i].gpio; + set_bit(gpio, pctrl->skip_wake_irqs); + } + } + girq = &chip->irq; girq->chip = &pctrl->irq_chip; girq->parent_handler = msm_gpio_irq_handler; + girq->fwnode = pctrl->dev->fwnode; girq->num_parents = 1; girq->parents = devm_kcalloc(pctrl->dev, 1, sizeof(*girq->parents), GFP_KERNEL); @@ -1067,6 +1176,16 @@ static int msm_gpio_init(struct msm_pinctrl *pctrl) } } + /* + * Since we are chained to the GIC using the TLMM summary line + * and in hierarchy with the wakeup parent interrupt controller, + * explicitly set the chained summary line. We need to do this because + * the summary line is not routed to the wakeup parent but directly + * to the GIC. + */ + gpiochip_set_chained_irqchip(chip, &pctrl->irq_chip, pctrl->irq, + msm_gpio_irq_handler); + return 0; } diff --git a/drivers/pinctrl/qcom/pinctrl-msm.h b/drivers/pinctrl/qcom/pinctrl-msm.h index 48569cda8..1547020 100644 --- a/drivers/pinctrl/qcom/pinctrl-msm.h +++ b/drivers/pinctrl/qcom/pinctrl-msm.h @@ -5,6 +5,8 @@ #ifndef __PINCTRL_MSM_H__ #define __PINCTRL_MSM_H__ +#include + struct pinctrl_pin_desc; /** @@ -92,6 +94,16 @@ struct msm_pingroup { }; /** + * struct msm_gpio_wakeirq_map - Map of GPIOs and their wakeup pins + * @gpio: The GPIOs that are wakeup capable + * @wakeirq: The interrupt at the always-on interrupt controller + */ +struct msm_gpio_wakeirq_map { + unsigned int gpio; + unsigned int wakeirq; +}; + +/** * struct msm_pinctrl_soc_data - Qualcomm pin controller driver configuration * @pins: An array describing all pins the pin controller affects. * @npins: The number of entries in @pins. @@ -101,6 +113,8 @@ struct msm_pingroup { * @ngroups: The numbmer of entries in @groups. * @ngpio: The number of pingroups the driver should expose as GPIOs. * @pull_no_keeper: The SoC does not support keeper bias. + * @wakeirq_map: The map of wakeup capable GPIOs and the pin at PDC/MPM + * @nwakeirq_map: The number of entries in @hierarchy_map */ struct msm_pinctrl_soc_data { const struct pinctrl_pin_desc *pins; @@ -114,6 +128,8 @@ struct msm_pinctrl_soc_data { const char *const *tiles; unsigned int ntiles; const int *reserved_gpios; + const struct msm_gpio_wakeirq_map *wakeirq_map; + unsigned int nwakeirq_map; }; extern const struct dev_pm_ops msm_pinctrl_dev_pm_ops; diff --git a/include/linux/soc/qcom/irq.h b/include/linux/soc/qcom/irq.h index 85ac4b6..098d57c 100644 --- a/include/linux/soc/qcom/irq.h +++ b/include/linux/soc/qcom/irq.h @@ -16,4 +16,17 @@ #define IRQ_DOMAIN_FLAG_QCOM_PDC_WAKEUP (IRQ_DOMAIN_FLAG_NONCORE << 0) #define IRQ_DOMAIN_FLAG_QCOM_MPM_WAKEUP (IRQ_DOMAIN_FLAG_NONCORE << 1) +/** + * irq_domain_qcom_handle_wakeup: Return if the domain handles interrupt + * configuration + * @parent: irq domain + * + * This QCOM specific irq domain call returns if the interrupt controller + * requires the interrupt be masked at the child interrupt controller. + */ +static inline bool irq_domain_qcom_handle_wakeup(struct irq_domain *parent) +{ + return (parent->flags & IRQ_DOMAIN_FLAG_QCOM_PDC_WAKEUP); +} + #endif From patchwork Fri Sep 13 21:59:19 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Lina Iyer X-Patchwork-Id: 11145347 Return-Path: Received: from mail.kernel.org (pdx-korg-mail-1.web.codeaurora.org [172.30.200.123]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id F16FB17E6 for ; Fri, 13 Sep 2019 22:00:11 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.kernel.org (Postfix) with ESMTP id D183620CC7 for ; Fri, 13 Sep 2019 22:00:11 +0000 (UTC) Authentication-Results: mail.kernel.org; dkim=fail reason="key not found in DNS" (0-bit key) header.d=codeaurora.org header.i=@codeaurora.org header.b="fCguyrRZ"; dkim=fail reason="key not found in DNS" (0-bit key) header.d=codeaurora.org header.i=@codeaurora.org header.b="fCguyrRZ" Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S2403756AbfIMV7y (ORCPT ); Fri, 13 Sep 2019 17:59:54 -0400 Received: from smtp.codeaurora.org ([198.145.29.96]:60104 "EHLO smtp.codeaurora.org" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S2390559AbfIMV7x (ORCPT ); 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Fri, 13 Sep 2019 21:59:51 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=codeaurora.org; s=default; t=1568411992; bh=rmhnZDa5DvGyEFcw8DBTGLtXibcXJptqhTVYshv2Dc0=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=fCguyrRZhptn9hkMLD8LhOUGm47YnF8a7XCBbsO6hZUFaK3ofylISPbLs7uCs4Pph y+xnttDVufQBS1k4zw8wi71oIVzVs1DqD/PI5+GFPH1+oPhiyoIoVBL99xmcrrDyNU CkztHJyM1zfcLwLspk6mwEf1h9X03177Iy+w4++k= DMARC-Filter: OpenDMARC Filter v1.3.2 smtp.codeaurora.org 9D25161418 Authentication-Results: pdx-caf-mail.web.codeaurora.org; dmarc=none (p=none dis=none) header.from=codeaurora.org Authentication-Results: pdx-caf-mail.web.codeaurora.org; spf=none smtp.mailfrom=ilina@codeaurora.org From: Lina Iyer To: swboyd@chromium.org, evgreen@chromium.org, maz@kernel.org, linus.walleij@linaro.org Cc: linux-kernel@vger.kernel.org, linux-arm-msm@vger.kernel.org, bjorn.andersson@linaro.org, mkshah@codeaurora.org, linux-gpio@vger.kernel.org, Lina Iyer Subject: [PATCH RFC v2 11/14] drivers: pinctrl: sdm845: add PDC wakeup interrupt map for GPIOs Date: Fri, 13 Sep 2019 15:59:19 -0600 Message-Id: <1568411962-1022-12-git-send-email-ilina@codeaurora.org> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1568411962-1022-1-git-send-email-ilina@codeaurora.org> References: <1568411962-1022-1-git-send-email-ilina@codeaurora.org> Sender: linux-arm-msm-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-arm-msm@vger.kernel.org Add interrupt parents for wakeup capable GPIOs for Qualcomm SDM845 SoC. Signed-off-by: Lina Iyer Reviewed-by: Linus Walleij --- Changes in RFC v2: - Rearranged GPIO wakeup parent map --- drivers/pinctrl/qcom/pinctrl-sdm845.c | 23 ++++++++++++++++++++++- 1 file changed, 22 insertions(+), 1 deletion(-) diff --git a/drivers/pinctrl/qcom/pinctrl-sdm845.c b/drivers/pinctrl/qcom/pinctrl-sdm845.c index 39f498c..9cff3a4 100644 --- a/drivers/pinctrl/qcom/pinctrl-sdm845.c +++ b/drivers/pinctrl/qcom/pinctrl-sdm845.c @@ -1,6 +1,6 @@ // SPDX-License-Identifier: GPL-2.0 /* - * Copyright (c) 2016-2018, The Linux Foundation. All rights reserved. + * Copyright (c) 2016-2019, The Linux Foundation. All rights reserved. */ #include @@ -1282,6 +1282,24 @@ static const int sdm845_acpi_reserved_gpios[] = { 0, 1, 2, 3, 81, 82, 83, 84, -1 }; +static const struct msm_gpio_wakeirq_map sdm845_pdc_map[] = { + { 1, 30 }, { 3, 31 }, { 5, 32 }, { 10, 33 }, { 11, 34 }, + { 20, 35 }, { 22, 36 }, { 24, 37 }, { 26, 38 }, { 30, 39 }, + { 31, 117 }, { 32, 41 }, { 34, 42 }, { 36, 43 }, { 37, 44 }, + { 38, 45 }, { 39, 46 }, { 40, 47 }, { 41, 115 }, { 43, 49 }, + { 44, 50 }, { 46, 51 }, { 48, 52 }, { 49, 118 }, { 52, 54 }, + { 53, 55 }, { 54, 56 }, { 56, 57 }, { 57, 58 }, { 58, 59 }, + { 59, 60 }, { 60, 61 }, { 61, 62 }, { 62, 63 }, { 63, 64 }, + { 64, 65 }, { 66, 66 }, { 68, 67 }, { 71, 68 }, { 73, 69 }, + { 77, 70 }, { 78, 71 }, { 79, 72 }, { 80, 73 }, { 84, 74 }, + { 85, 75 }, { 86, 76 }, { 88, 77 }, { 89, 116 }, { 91, 79 }, + { 92, 80 }, { 95, 81 }, { 96, 82 }, { 97, 83 }, { 101, 84 }, + { 103, 85 }, { 104, 86 }, { 115, 90 }, { 116, 91 }, { 117, 92 }, + { 118, 93 }, { 119, 94 }, { 120, 95 }, { 121, 96 }, { 122, 97 }, + { 123, 98 }, { 124, 99 }, { 125, 100 }, { 127, 102 }, { 128, 103 }, + { 129, 104 }, { 130, 105 }, { 132, 106 }, { 133, 107 }, { 145, 108 }, +}; + static const struct msm_pinctrl_soc_data sdm845_pinctrl = { .pins = sdm845_pins, .npins = ARRAY_SIZE(sdm845_pins), @@ -1290,6 +1308,9 @@ static const struct msm_pinctrl_soc_data sdm845_pinctrl = { .groups = sdm845_groups, .ngroups = ARRAY_SIZE(sdm845_groups), .ngpios = 151, + .wakeirq_map = sdm845_pdc_map, + .nwakeirq_map = ARRAY_SIZE(sdm845_pdc_map), + }; static const struct msm_pinctrl_soc_data sdm845_acpi_pinctrl = { From patchwork Fri Sep 13 21:59:20 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Lina Iyer X-Patchwork-Id: 11145339 Return-Path: Received: from mail.kernel.org (pdx-korg-mail-1.web.codeaurora.org [172.30.200.123]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id 0BC4E14DB for ; Fri, 13 Sep 2019 21:59:57 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.kernel.org (Postfix) with ESMTP id E06FB20830 for ; Fri, 13 Sep 2019 21:59:56 +0000 (UTC) Authentication-Results: mail.kernel.org; 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Fri, 13 Sep 2019 21:59:52 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=codeaurora.org; s=default; t=1568411993; bh=zA+ZCKY0R8V8qszkGMazGbgmIX907KgflfYIX6eF6No=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=pJkD41+qC1/AhMM9SHWs7zPFKlDOsf3SHWUWPwnAIKF+qp8Vx/EtR1Npy7RjsdIsJ HaJXV8Aoxbb/bvgoq0uBzNYK2YTp1ATuZVFdA4pjn///U24xeFKzI42GGTwNARlYsJ 5KwfWlc81M8nWrXjxEVJknrjiiwm3buYWza/J0Vo= DMARC-Filter: OpenDMARC Filter v1.3.2 smtp.codeaurora.org 9872761424 Authentication-Results: pdx-caf-mail.web.codeaurora.org; dmarc=none (p=none dis=none) header.from=codeaurora.org Authentication-Results: pdx-caf-mail.web.codeaurora.org; spf=none smtp.mailfrom=ilina@codeaurora.org From: Lina Iyer To: swboyd@chromium.org, evgreen@chromium.org, maz@kernel.org, linus.walleij@linaro.org Cc: linux-kernel@vger.kernel.org, linux-arm-msm@vger.kernel.org, bjorn.andersson@linaro.org, mkshah@codeaurora.org, linux-gpio@vger.kernel.org, Lina Iyer Subject: [PATCH RFC v2 12/14] arm64: dts: qcom: add PDC interrupt controller for SDM845 Date: Fri, 13 Sep 2019 15:59:20 -0600 Message-Id: <1568411962-1022-13-git-send-email-ilina@codeaurora.org> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1568411962-1022-1-git-send-email-ilina@codeaurora.org> References: <1568411962-1022-1-git-send-email-ilina@codeaurora.org> Sender: linux-arm-msm-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-arm-msm@vger.kernel.org Add PDC interrupt controller device bindings for SDM845. Signed-off-by: Lina Iyer --- arch/arm64/boot/dts/qcom/sdm845.dtsi | 10 ++++++++++ 1 file changed, 10 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/sdm845.dtsi b/arch/arm64/boot/dts/qcom/sdm845.dtsi index be0022e..41455b8 100644 --- a/arch/arm64/boot/dts/qcom/sdm845.dtsi +++ b/arch/arm64/boot/dts/qcom/sdm845.dtsi @@ -2375,6 +2375,16 @@ #power-domain-cells = <1>; }; + pdc_intc: interrupt-controller@b220000 { + compatible = "qcom,sdm845-pdc"; + reg = <0 0x0b220000 0 0x30000>, <0 0x179900f0 0 0x60>; + qcom,pdc-ranges = <0 480 94>, <94 609 15>, <115 630 7>; + #interrupt-cells = <2>; + interrupt-parent = <&intc>; + interrupt-controller; + qcom,scm-spi-cfg; + }; + pdc_reset: reset-controller@b2e0000 { compatible = "qcom,sdm845-pdc-global"; reg = <0 0x0b2e0000 0 0x20000>; From patchwork Fri Sep 13 21:59:21 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Lina Iyer X-Patchwork-Id: 11145343 Return-Path: Received: from mail.kernel.org (pdx-korg-mail-1.web.codeaurora.org [172.30.200.123]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id 3B07F1395 for ; Fri, 13 Sep 2019 22:00:09 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.kernel.org (Postfix) with ESMTP id 1B2EB2084F for ; Fri, 13 Sep 2019 22:00:09 +0000 (UTC) Authentication-Results: mail.kernel.org; dkim=fail reason="key not found in DNS" (0-bit key) header.d=codeaurora.org header.i=@codeaurora.org header.b="GS5zUpR3"; dkim=fail reason="key not found in DNS" (0-bit key) header.d=codeaurora.org header.i=@codeaurora.org header.b="GINagmKJ" Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S2403822AbfIMV74 (ORCPT ); Fri, 13 Sep 2019 17:59:56 -0400 Received: from smtp.codeaurora.org ([198.145.29.96]:60310 "EHLO smtp.codeaurora.org" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S2403798AbfIMV74 (ORCPT ); Fri, 13 Sep 2019 17:59:56 -0400 Received: by smtp.codeaurora.org (Postfix, from userid 1000) id 06A5861572; Fri, 13 Sep 2019 21:59:54 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=codeaurora.org; s=default; t=1568411995; bh=RkPTz7sLNcUVhcpu56ji8HogFM/HLe7mwUPyf10X7Tk=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=GS5zUpR3SXyCi13ukFTaNuPG59oOL4I1FBuS+XxQkt5Q2gpoLVxVFAzZqbjD4sI6x HQ+zTu1HqvaxOQ9Fem0iGU0ZXgdmzjEpqEupO+fbwFPOvRNwxWydAQ4PHH9clP5kIP kLSp7qBIlJz+XMLUzIFS1ZVA9IUJtEZGjAWrWO1E= X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on pdx-caf-mail.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-2.7 required=2.0 tests=ALL_TRUSTED,BAYES_00, DKIM_INVALID,DKIM_SIGNED,SPF_NONE autolearn=no autolearn_force=no version=3.4.0 Received: from codeaurora.org (i-global254.qualcomm.com [199.106.103.254]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-SHA256 (128/128 bits)) (No client certificate requested) (Authenticated sender: ilina@smtp.codeaurora.org) by smtp.codeaurora.org (Postfix) with ESMTPSA id 95AD5614DB; Fri, 13 Sep 2019 21:59:53 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=codeaurora.org; s=default; t=1568411994; bh=RkPTz7sLNcUVhcpu56ji8HogFM/HLe7mwUPyf10X7Tk=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=GINagmKJjVjx8TAOPGwCvZNKMjxn73Kwp/m2koBQ7dwD1lLrpUw2jX9ly/teJmLsV TzSnDic+lXCH92/DGDivjilAviAusS9xhuCZ5AEdyvAh/lam6WMJ42V2gLyfw1knIb qGgmrF7nSQnyL2fa+xfHGtroMXu1pD/WkunuX8XY= DMARC-Filter: OpenDMARC Filter v1.3.2 smtp.codeaurora.org 95AD5614DB Authentication-Results: pdx-caf-mail.web.codeaurora.org; dmarc=none (p=none dis=none) header.from=codeaurora.org Authentication-Results: pdx-caf-mail.web.codeaurora.org; spf=none smtp.mailfrom=ilina@codeaurora.org From: Lina Iyer To: swboyd@chromium.org, evgreen@chromium.org, maz@kernel.org, linus.walleij@linaro.org Cc: linux-kernel@vger.kernel.org, linux-arm-msm@vger.kernel.org, bjorn.andersson@linaro.org, mkshah@codeaurora.org, linux-gpio@vger.kernel.org, Lina Iyer Subject: [PATCH RFC v2 13/14] arm64: dts: qcom: setup PDC as the wakeup parent for TLMM on SDM845 Date: Fri, 13 Sep 2019 15:59:21 -0600 Message-Id: <1568411962-1022-14-git-send-email-ilina@codeaurora.org> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1568411962-1022-1-git-send-email-ilina@codeaurora.org> References: <1568411962-1022-1-git-send-email-ilina@codeaurora.org> Sender: linux-arm-msm-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-arm-msm@vger.kernel.org PDC always-on interrupt controller can detect certain GPIOs even when the TLMM interrupt controller is powered off. Link the PDC as TLMM's wakeup parent. Signed-off-by: Lina Iyer --- arch/arm64/boot/dts/qcom/sdm845.dtsi | 1 + 1 file changed, 1 insertion(+) diff --git a/arch/arm64/boot/dts/qcom/sdm845.dtsi b/arch/arm64/boot/dts/qcom/sdm845.dtsi index 41455b8..1b70254 100644 --- a/arch/arm64/boot/dts/qcom/sdm845.dtsi +++ b/arch/arm64/boot/dts/qcom/sdm845.dtsi @@ -1358,6 +1358,7 @@ interrupt-controller; #interrupt-cells = <2>; gpio-ranges = <&tlmm 0 0 150>; + wakeup-parent = <&pdc_intc>; qspi_clk: qspi-clk { pinmux { From patchwork Fri Sep 13 21:59:22 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Lina Iyer X-Patchwork-Id: 11145341 Return-Path: Received: from mail.kernel.org (pdx-korg-mail-1.web.codeaurora.org [172.30.200.123]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id 0675F17E6 for ; Fri, 13 Sep 2019 22:00:08 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.kernel.org (Postfix) with ESMTP id DAC9B21925 for ; Fri, 13 Sep 2019 22:00:07 +0000 (UTC) Authentication-Results: mail.kernel.org; dkim=fail reason="key not found in DNS" (0-bit key) header.d=codeaurora.org header.i=@codeaurora.org header.b="UccG/WMB"; dkim=fail reason="key not found in DNS" (0-bit key) header.d=codeaurora.org header.i=@codeaurora.org header.b="UccG/WMB" Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S2403838AbfIMV74 (ORCPT ); Fri, 13 Sep 2019 17:59:56 -0400 Received: from smtp.codeaurora.org ([198.145.29.96]:60224 "EHLO smtp.codeaurora.org" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S2403810AbfIMV74 (ORCPT ); Fri, 13 Sep 2019 17:59:56 -0400 Received: by smtp.codeaurora.org (Postfix, from userid 1000) id BE9CA6155F; Fri, 13 Sep 2019 21:59:55 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=codeaurora.org; s=default; t=1568411995; bh=tOdi53r950iLkmXvUmN+jY4TQ4fKdBRyPIEbVWZA66g=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=UccG/WMB14CHYrEFDl2xKWb/M5Kt2jvEGig9LOlLDM8Wgz0+OAC9YwiVkBpPAIdu4 KGIwohSERVyQZ8ZVLVRMRnkPEbDnU1Zi0T2mjf+cVRuC2MnlV8AL3jnXIRrW69fkeE /4srxSznk1lr9z9BbR1EX4vtZTLu+ecbT0XO4sQI= X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on pdx-caf-mail.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-2.7 required=2.0 tests=ALL_TRUSTED,BAYES_00, DKIM_INVALID,DKIM_SIGNED,SPF_NONE autolearn=no autolearn_force=no version=3.4.0 Received: from codeaurora.org (i-global254.qualcomm.com [199.106.103.254]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-SHA256 (128/128 bits)) (No client certificate requested) (Authenticated sender: ilina@smtp.codeaurora.org) by smtp.codeaurora.org (Postfix) with ESMTPSA id 91A586155F; Fri, 13 Sep 2019 21:59:54 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=codeaurora.org; s=default; t=1568411995; bh=tOdi53r950iLkmXvUmN+jY4TQ4fKdBRyPIEbVWZA66g=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=UccG/WMB14CHYrEFDl2xKWb/M5Kt2jvEGig9LOlLDM8Wgz0+OAC9YwiVkBpPAIdu4 KGIwohSERVyQZ8ZVLVRMRnkPEbDnU1Zi0T2mjf+cVRuC2MnlV8AL3jnXIRrW69fkeE /4srxSznk1lr9z9BbR1EX4vtZTLu+ecbT0XO4sQI= DMARC-Filter: OpenDMARC Filter v1.3.2 smtp.codeaurora.org 91A586155F Authentication-Results: pdx-caf-mail.web.codeaurora.org; dmarc=none (p=none dis=none) header.from=codeaurora.org Authentication-Results: pdx-caf-mail.web.codeaurora.org; spf=none smtp.mailfrom=ilina@codeaurora.org From: Lina Iyer To: swboyd@chromium.org, evgreen@chromium.org, maz@kernel.org, linus.walleij@linaro.org Cc: linux-kernel@vger.kernel.org, linux-arm-msm@vger.kernel.org, bjorn.andersson@linaro.org, mkshah@codeaurora.org, linux-gpio@vger.kernel.org, Lina Iyer Subject: [PATCH RFC v2 14/14] arm64: defconfig: enable PDC interrupt controller for Qualcomm SDM845 Date: Fri, 13 Sep 2019 15:59:22 -0600 Message-Id: <1568411962-1022-15-git-send-email-ilina@codeaurora.org> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1568411962-1022-1-git-send-email-ilina@codeaurora.org> References: <1568411962-1022-1-git-send-email-ilina@codeaurora.org> Sender: linux-arm-msm-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-arm-msm@vger.kernel.org Enable PDC interrupt controller for SDM845 devices. The interrupt controller can detect wakeup capable interrupts when the SoC is in a low power state. Signed-off-by: Lina Iyer --- arch/arm64/configs/defconfig | 1 + 1 file changed, 1 insertion(+) diff --git a/arch/arm64/configs/defconfig b/arch/arm64/configs/defconfig index 0e58ef0..310b604 100644 --- a/arch/arm64/configs/defconfig +++ b/arch/arm64/configs/defconfig @@ -729,6 +729,7 @@ CONFIG_ARCH_R8A77970=y CONFIG_ARCH_R8A77980=y CONFIG_ARCH_R8A77990=y CONFIG_ARCH_R8A77995=y +CONFIG_QCOM_PDC=y CONFIG_ROCKCHIP_PM_DOMAINS=y CONFIG_ARCH_TEGRA_132_SOC=y CONFIG_ARCH_TEGRA_210_SOC=y