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Wed, 18 Sep 2019 22:03:27 +0000 From: Paul Burton To: "linux-mips@vger.kernel.org" CC: Paul Burton , Dmitry Korotin Subject: [PATCH 1/3] MIPS: Disable pte_special() for MIPS32 with 4KiB pages & RiXi Thread-Topic: [PATCH 1/3] MIPS: Disable pte_special() for MIPS32 with 4KiB pages & RiXi Thread-Index: AQHVbmzmqHjqG429vkSh9effcziumA== Date: Wed, 18 Sep 2019 22:03:27 +0000 Message-ID: <20190918220258.29428-1-paul.burton@mips.com> Accept-Language: en-US Content-Language: en-US X-MS-Has-Attach: X-MS-TNEF-Correlator: x-clientproxiedby: MN2PR04CA0030.namprd04.prod.outlook.com (2603:10b6:208:d4::43) To MWHPR2201MB1277.namprd22.prod.outlook.com (2603:10b6:301:18::12) authentication-results: spf=none (sender IP is ) smtp.mailfrom=pburton@wavecomp.com; x-ms-exchange-messagesentrepresentingtype: 1 x-mailer: git-send-email 2.23.0 x-originating-ip: [12.246.51.142] x-ms-publictraffictype: Email x-ms-office365-filtering-correlation-id: 69021238-503e-4b53-9599-08d73c840892 x-microsoft-antispam: BCL:0;PCL:0;RULEID:(2390118)(7020095)(4652040)(8989299)(5600167)(711020)(4605104)(1401327)(4534185)(4627221)(201703031133081)(201702281549075)(8990200)(2017052603328)(7193020);SRVR:MWHPR2201MB1375; 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Unfortunately for MIPS32 configurations with RiXi support this pushed the number of pgprot bits to 13 (ie. _PFN_SHIFT = 13). When using 4KB pages (ie. PAGE_SHIFT = 12) this results in us shifting the most significant bit of the physical address beyond the end of the PTE, leading any mapped access to a physical address above 2GB to incorrectly access an address 2GB lower than intended. For now, disable the pte_special() support for MIPS32 configurations that use 4KB pages & support RiXi. Fixes: 61cbfff4b1a7 ("MIPS: pte_special()/pte_mkspecial() support") Signed-off-by: Paul Burton Cc: Dmitry Korotin --- arch/mips/Kconfig | 2 +- arch/mips/include/asm/pgtable-bits.h | 14 +++++++++++++- 2 files changed, 14 insertions(+), 2 deletions(-) diff --git a/arch/mips/Kconfig b/arch/mips/Kconfig index 3f18aa018a0c..18163c138676 100644 --- a/arch/mips/Kconfig +++ b/arch/mips/Kconfig @@ -84,7 +84,7 @@ config MIPS select RTC_LIB select SYSCTL_EXCEPTION_TRACE select VIRT_TO_BUS - select ARCH_HAS_PTE_SPECIAL + select ARCH_HAS_PTE_SPECIAL if !(32BIT && PAGE_SIZE_4KB && CPU_HAS_RIXI) menu "Machine selection" diff --git a/arch/mips/include/asm/pgtable-bits.h b/arch/mips/include/asm/pgtable-bits.h index 409ae01ed7be..4da79b85c179 100644 --- a/arch/mips/include/asm/pgtable-bits.h +++ b/arch/mips/include/asm/pgtable-bits.h @@ -52,7 +52,9 @@ enum pgtable_bits { _PAGE_WRITE_SHIFT, _PAGE_ACCESSED_SHIFT, _PAGE_MODIFIED_SHIFT, +#if defined(CONFIG_ARCH_HAS_PTE_SPECIAL) _PAGE_SPECIAL_SHIFT, +#endif }; /* @@ -79,7 +81,9 @@ enum pgtable_bits { _PAGE_WRITE_SHIFT, _PAGE_ACCESSED_SHIFT, _PAGE_MODIFIED_SHIFT, +#if defined(CONFIG_ARCH_HAS_PTE_SPECIAL) _PAGE_SPECIAL_SHIFT, +#endif }; #elif defined(CONFIG_CPU_R3K_TLB) @@ -92,7 +96,9 @@ enum pgtable_bits { _PAGE_WRITE_SHIFT, _PAGE_ACCESSED_SHIFT, _PAGE_MODIFIED_SHIFT, +#if defined(CONFIG_ARCH_HAS_PTE_SPECIAL) _PAGE_SPECIAL_SHIFT, +#endif /* Used by TLB hardware (placed in EntryLo) */ _PAGE_GLOBAL_SHIFT = 8, @@ -116,7 +122,9 @@ enum pgtable_bits { #if defined(CONFIG_MIPS_HUGE_TLB_SUPPORT) _PAGE_HUGE_SHIFT, #endif +#if defined(CONFIG_ARCH_HAS_PTE_SPECIAL) _PAGE_SPECIAL_SHIFT, +#endif /* Used by TLB hardware (placed in EntryLo*) */ #if defined(CONFIG_CPU_HAS_RIXI) @@ -139,7 +147,11 @@ enum pgtable_bits { #if defined(CONFIG_MIPS_HUGE_TLB_SUPPORT) # define _PAGE_HUGE (1 << _PAGE_HUGE_SHIFT) #endif -#define _PAGE_SPECIAL (1 << _PAGE_SPECIAL_SHIFT) +#if defined(CONFIG_ARCH_HAS_PTE_SPECIAL) +# define _PAGE_SPECIAL (1 << _PAGE_SPECIAL_SHIFT) +#else +# define _PAGE_SPECIAL 0 +#endif /* Used by TLB hardware (placed in EntryLo*) */ #if defined(CONFIG_XPA) From patchwork Wed Sep 18 22:03:29 2019 Content-Type: text/plain; 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Wed, 18 Sep 2019 22:03:29 +0000 From: Paul Burton To: "linux-mips@vger.kernel.org" CC: Paul Burton , Daniel Silsby , Dmitry Korotin , Paul Cercueil Subject: [PATCH 2/3] MIPS: Disable hugepages for MIPS32 with 4KB pages Thread-Topic: [PATCH 2/3] MIPS: Disable hugepages for MIPS32 with 4KB pages Thread-Index: AQHVbmznrzP4VEr5N0evITtuDogpAw== Date: Wed, 18 Sep 2019 22:03:29 +0000 Message-ID: <20190918220258.29428-2-paul.burton@mips.com> References: <20190918220258.29428-1-paul.burton@mips.com> In-Reply-To: <20190918220258.29428-1-paul.burton@mips.com> Accept-Language: en-US Content-Language: en-US X-MS-Has-Attach: X-MS-TNEF-Correlator: x-clientproxiedby: MN2PR04CA0030.namprd04.prod.outlook.com (2603:10b6:208:d4::43) To MWHPR2201MB1277.namprd22.prod.outlook.com (2603:10b6:301:18::12) authentication-results: spf=none (sender IP is ) smtp.mailfrom=pburton@wavecomp.com; x-ms-exchange-messagesentrepresentingtype: 1 x-mailer: git-send-email 2.23.0 x-originating-ip: [12.246.51.142] x-ms-publictraffictype: Email x-ms-office365-filtering-correlation-id: ee0bdc3b-6acf-4b13-905a-08d73c840983 x-microsoft-antispam: BCL:0;PCL:0;RULEID:(2390118)(7020095)(4652040)(8989299)(5600167)(711020)(4605104)(1401327)(4534185)(4627221)(201703031133081)(201702281549075)(8990200)(2017052603328)(7193020);SRVR:MWHPR2201MB1088; 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Unfortunately for configurations that support RiXI this pushed the number of pgprot bits to 13 (ie. _PFN_SHIFT = 13). When using 4KB pages (ie. PAGE_SHIFT = 12) this results in us shifting the most significant bit of the physical address beyond the end of the PTE, leading any mapped access to a physical address above 2GB to incorrectly access an address 2GB lower than intended. Separately, commit 61cbfff4b1a7 ("MIPS: pte_special()/pte_mkspecial() support") added support for pte_special() which involved another new pgprot bit. This leads the lack of an available pgprot bit for _PAGE_HUGE in MIPS32 4KiB page configurations to be extended to non-RiXi configurations too. Disable huge page support for the affected configurations to prevent unexpected misbehaviour. Fixes: 35476311e529 ("MIPS: Add partial 32-bit huge page support") Signed-off-by: Paul Burton Cc: Daniel Silsby Cc: Dmitry Korotin Cc: Paul Cercueil --- arch/mips/Kconfig | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/mips/Kconfig b/arch/mips/Kconfig index 18163c138676..fb75ed5443b8 100644 --- a/arch/mips/Kconfig +++ b/arch/mips/Kconfig @@ -1227,7 +1227,7 @@ config SYS_SUPPORTS_LITTLE_ENDIAN config SYS_SUPPORTS_HUGETLBFS bool - depends on CPU_SUPPORTS_HUGEPAGES + depends on CPU_SUPPORTS_HUGEPAGES && !(32BIT && PAGE_SIZE_4KB) default y config MIPS_HUGE_TLB_SUPPORT From patchwork Wed Sep 18 22:03:30 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Paul Burton X-Patchwork-Id: 11151255 Return-Path: Received: from mail.kernel.org (pdx-korg-mail-1.web.codeaurora.org [172.30.200.123]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id D0C1E14DB for ; Wed, 18 Sep 2019 22:03:34 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.kernel.org (Postfix) with ESMTP id AED7921848 for ; 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received-spf: None (protection.outlook.com: wavecomp.com does not designate permitted sender hosts) x-ms-exchange-senderadcheck: 1 x-microsoft-antispam-message-info: bACovr9j92EHNvLXN7nw4B81w5vSs/FFZ/pPyVkzAiLSdmelXoK7FLBVX+i8ISw5tzFkRYSpyqjzbM4YtdSZ32bcYElAWLJKClbGKuQcS9YxewhKR7Ed1ticW0V5YmVCxXT7DLx5X3H+Fzpn5h/eX4YoPGqWZCBBqQua/XWCjqQgZ0N1ZjvnOmuxb8I5fIl5jVUGabVmJnCSvjb+mE1/ibCjgvCVnIfR9qCvUlZJAWE7lwguRxOfqtVU2I5AytZZq5jyjzCHYJaNarXm9/wRaV4gAM4fIlGMmgj/YG7/WdLWoEf32idYo1hxNhOc28pCdE75CBp3KZDDLwvZ0PH6zPFwMY2wjchPXklvPItDqN/eMaDVxoQttyrWcYq9Pi6EyVhTXmPIywLZJpND389n3NZpOWWQeJSeFcSzCBgsXrw= MIME-Version: 1.0 X-OriginatorOrg: mips.com X-MS-Exchange-CrossTenant-Network-Message-Id: b438b3db-0357-49db-7b37-08d73c840a4f X-MS-Exchange-CrossTenant-originalarrivaltime: 18 Sep 2019 22:03:30.4804 (UTC) X-MS-Exchange-CrossTenant-fromentityheader: Hosted X-MS-Exchange-CrossTenant-id: 463607d3-1db3-40a0-8a29-970c56230104 X-MS-Exchange-CrossTenant-mailboxtype: HOSTED X-MS-Exchange-CrossTenant-userprincipalname: 1pIVG06hy41FQYIuDNpc0cCQHYdC0ydztwrvL/HKRFqi4OJX5S07jBlM/vQWWU1O5PQuoBWgm3lskWxkH/t/jg== X-MS-Exchange-Transport-CrossTenantHeadersStamped: MWHPR2201MB1088 Sender: linux-mips-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-mips@vger.kernel.org 2 recent commits have fixed issues where _PFN_SHIFT grew too large due to the introduction of too many pgprot bits in our PTEs for some MIPS32 kernel configurations. Tracking down such issues can be tricky, so add a BUILD_BUG_ON() to help. Signed-off-by: Paul Burton --- arch/mips/mm/init.c | 6 ++++++ 1 file changed, 6 insertions(+) diff --git a/arch/mips/mm/init.c b/arch/mips/mm/init.c index 6fea3b54c961..090fa653dfa9 100644 --- a/arch/mips/mm/init.c +++ b/arch/mips/mm/init.c @@ -446,6 +446,12 @@ static inline void __init mem_init_free_highmem(void) void __init mem_init(void) { + /* + * When _PFN_SHIFT is greater than PAGE_SHIFT we won't have enough PTE + * bits to hold a full 32b physical address on MIPS32 systems. + */ + BUILD_BUG_ON(IS_ENABLED(CONFIG_32BIT) && (_PFN_SHIFT > PAGE_SHIFT)); + #ifdef CONFIG_HIGHMEM #ifdef CONFIG_DISCONTIGMEM #error "CONFIG_HIGHMEM and CONFIG_DISCONTIGMEM dont work together yet"