From patchwork Thu Sep 19 12:11:02 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Jianxin Pan X-Patchwork-Id: 11152219 Return-Path: Received: from mail.kernel.org (pdx-korg-mail-1.web.codeaurora.org [172.30.200.123]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id 9E7C4112B for ; Thu, 19 Sep 2019 12:11:55 +0000 (UTC) Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id 7CABA21929 for ; Thu, 19 Sep 2019 12:11:55 +0000 (UTC) Authentication-Results: mail.kernel.org; dkim=pass (2048-bit key) header.d=lists.infradead.org header.i=@lists.infradead.org header.b="AlxxbAKR" DMARC-Filter: OpenDMARC Filter v1.3.2 mail.kernel.org 7CABA21929 Authentication-Results: mail.kernel.org; dmarc=none (p=none dis=none) header.from=amlogic.com Authentication-Results: mail.kernel.org; spf=none smtp.mailfrom=linux-amlogic-bounces+patchwork-linux-amlogic=patchwork.kernel.org@lists.infradead.org DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=bombadil.20170209; h=Sender: Content-Transfer-Encoding:Content-Type:Cc:List-Subscribe:List-Help:List-Post: List-Archive:List-Unsubscribe:List-Id:MIME-Version:References:In-Reply-To: Message-ID:Date:Subject:To:From:Reply-To:Content-ID:Content-Description: Resent-Date:Resent-From:Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID: List-Owner; bh=sARu/JZu0YtZk51a2PzeTkpKF1ZtDKkx/kW/hKcOKL0=; b=AlxxbAKR3lFJ9O dHIwk5UVPVFxLrh2XHEe1UG9eJM52mT2cCadVfNA9cELuPLvF9DVUv7xm8fcuwo1wlAgByXhBi2w1 coQVI77zVqpeUmgN98rHAoDHW2GH8bMemsuuqDRKKXTOq/YkMALoLM6sNos9yG6Zak0M1d0b4CGG2 oln17Z8FjasZDwLta6JLfdtH6n4Mix+FHC4dxxZz9LTfigabdIdhylJbEHMi6hvNW5UFOe4Ko33ht Lv+SZN0mpyIVvxoSFWdax5AHP1LwRAT9vgjX0K0z4/T4i3GyYwkgGHDsduL7sq7eKYmrqPE9HgM99 cDXuVlmwyfWbVJts0Wtg==; Received: from localhost ([127.0.0.1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.92.2 #3 (Red Hat Linux)) id 1iAvHt-0003mZ-RG; Thu, 19 Sep 2019 12:11:54 +0000 Received: from mail-sh.amlogic.com ([58.32.228.43]) by bombadil.infradead.org with esmtps (Exim 4.92.2 #3 (Red Hat Linux)) id 1iAvHK-0003TK-J8; Thu, 19 Sep 2019 12:11:20 +0000 Received: from droid13.amlogic.com (116.236.93.172) by mail-sh.amlogic.com (10.18.11.5) with Microsoft SMTP Server id 15.1.1591.10; Thu, 19 Sep 2019 20:12:06 +0800 From: Jianxin Pan To: Kevin Hilman , Subject: [PATCH 1/3] dt-bindings: power: add Amlogic secure power domains bindings Date: Thu, 19 Sep 2019 08:11:02 -0400 Message-ID: <1568895064-4116-2-git-send-email-jianxin.pan@amlogic.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1568895064-4116-1-git-send-email-jianxin.pan@amlogic.com> References: <1568895064-4116-1-git-send-email-jianxin.pan@amlogic.com> MIME-Version: 1.0 X-Originating-IP: [116.236.93.172] X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20190919_051118_642593_15B58B6E X-CRM114-Status: UNSURE ( 9.13 ) X-CRM114-Notice: Please train this message. X-Spam-Score: 0.0 (/) X-Spam-Report: SpamAssassin version 3.4.2 on bombadil.infradead.org summary: Content analysis details: (0.0 points) pts rule name description ---- ---------------------- -------------------------------------------------- 0.0 SPF_HELO_NONE SPF: HELO does not publish an SPF Record -0.0 SPF_PASS SPF: sender matches SPF record X-BeenThere: linux-amlogic@lists.infradead.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: devicetree@vger.kernel.org, Hanjie Lin , Victor Wan , Jianxin Pan , Neil Armstrong , Martin Blumenstingl , linux-pm@vger.kernel.org, linux-kernel@vger.kernel.org, Zhiqiang Liang , Rob Herring , Jian Hu , Xingyu Chen , linux-arm-kernel@lists.infradead.org, Jerome Brunet Sender: "linux-amlogic" Errors-To: linux-amlogic-bounces+patchwork-linux-amlogic=patchwork.kernel.org@lists.infradead.org Add the bindings for the Amlogic Secure power domains, controlling the secure power domains. The bindings targets the Amlogic A1 and C1 compatible SoCs, in which the power domain registers are in secure world. Signed-off-by: Jianxin Pan Signed-off-by: Zhiqiang Liang --- .../bindings/power/amlogic,meson-sec-pwrc.yaml | 32 ++++++++++++++++++++++ include/dt-bindings/power/meson-a1-power.h | 32 ++++++++++++++++++++++ 2 files changed, 64 insertions(+) create mode 100644 Documentation/devicetree/bindings/power/amlogic,meson-sec-pwrc.yaml create mode 100644 include/dt-bindings/power/meson-a1-power.h diff --git a/Documentation/devicetree/bindings/power/amlogic,meson-sec-pwrc.yaml b/Documentation/devicetree/bindings/power/amlogic,meson-sec-pwrc.yaml new file mode 100644 index 00000000..327e0d9 --- /dev/null +++ b/Documentation/devicetree/bindings/power/amlogic,meson-sec-pwrc.yaml @@ -0,0 +1,32 @@ +# SPDX-License-Identifier: (GPL-2.0+ OR MIT) +# Copyright (c) 2019 Amlogic, Inc +# Author: Jianxin Pan +%YAML 1.2 +--- +$id: "http://devicetree.org/schemas/power/amlogic,meson-sec-pwrc.yaml#" +$schema: "http://devicetree.org/meta-schemas/core.yaml#" + +title: Amlogic Meson Secure Power Domains + +maintainers: + - Jianxin Pan + +description: |+ + A1/C1 series The Secure Power Domains node should be the child of a syscon + node with the required property. + +properties: + compatible: + enum: + - amlogic,meson-a1-pwrc + +required: + - compatible + +examples: + - | + pwrc: power-controller { + compatible = "amlogic,meson-a1-pwrc"; + }; + + diff --git a/include/dt-bindings/power/meson-a1-power.h b/include/dt-bindings/power/meson-a1-power.h new file mode 100644 index 00000000..6cf50bf --- /dev/null +++ b/include/dt-bindings/power/meson-a1-power.h @@ -0,0 +1,32 @@ +/* SPDX-License-Identifier: (GPL-2.0+ or MIT) */ +/* + * Copyright (c) 2019 Amlogic, Inc. + * Author: Jianxin Pan + */ + +#ifndef _DT_BINDINGS_MESON_A1_POWER_H +#define _DT_BINDINGS_MESON_A1_POWER_H + +#define PWRC_DSPA_ID 8 +#define PWRC_DSPB_ID 9 +#define PWRC_UART_ID 10 +#define PWRC_DMC_ID 11 +#define PWRC_I2C_ID 12 +#define PWRC_PSRAM_ID 13 +#define PWRC_ACODEC_ID 14 +#define PWRC_AUDIO_ID 15 +#define PWRC_OTP_ID 16 +#define PWRC_DMA_ID 17 +#define PWRC_SD_EMMC_ID 18 +#define PWRC_RAMA_ID 19 +#define PWRC_RAMB_ID 20 +#define PWRC_IR_ID 21 +#define PWRC_SPICC_ID 22 +#define PWRC_SPIFC_ID 23 +#define PWRC_USB_ID 24 +#define PWRC_NIC_ID 25 +#define PWRC_PDMIN_ID 26 +#define PWRC_RSA_ID 27 +#define PWRC_MAX_ID 28 + +#endif From patchwork Thu Sep 19 12:11:03 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Jianxin Pan X-Patchwork-Id: 11152223 Return-Path: Received: from mail.kernel.org (pdx-korg-mail-1.web.codeaurora.org [172.30.200.123]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id 04F2913BD for ; Thu, 19 Sep 2019 12:12:20 +0000 (UTC) Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id D6FDE21929 for ; Thu, 19 Sep 2019 12:12:19 +0000 (UTC) Authentication-Results: mail.kernel.org; dkim=pass (2048-bit key) header.d=lists.infradead.org header.i=@lists.infradead.org header.b="hXEK/Umd" DMARC-Filter: OpenDMARC Filter v1.3.2 mail.kernel.org D6FDE21929 Authentication-Results: mail.kernel.org; dmarc=none (p=none dis=none) header.from=amlogic.com Authentication-Results: mail.kernel.org; spf=none smtp.mailfrom=linux-amlogic-bounces+patchwork-linux-amlogic=patchwork.kernel.org@lists.infradead.org DKIM-Signature: v=1; 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Thu, 19 Sep 2019 12:11:23 +0000 Received: from droid13.amlogic.com (116.236.93.172) by mail-sh.amlogic.com (10.18.11.5) with Microsoft SMTP Server id 15.1.1591.10; Thu, 19 Sep 2019 20:12:06 +0800 From: Jianxin Pan To: Kevin Hilman , Subject: [PATCH 2/3] soc: amlogic: Add support for Secure power domains controller Date: Thu, 19 Sep 2019 08:11:03 -0400 Message-ID: <1568895064-4116-3-git-send-email-jianxin.pan@amlogic.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1568895064-4116-1-git-send-email-jianxin.pan@amlogic.com> References: <1568895064-4116-1-git-send-email-jianxin.pan@amlogic.com> MIME-Version: 1.0 X-Originating-IP: [116.236.93.172] X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20190919_051122_148840_C51F0296 X-CRM114-Status: GOOD ( 12.87 ) X-Spam-Score: 0.0 (/) X-Spam-Report: SpamAssassin version 3.4.2 on bombadil.infradead.org summary: Content analysis details: (0.0 points) pts rule name description ---- ---------------------- -------------------------------------------------- 0.0 SPF_HELO_NONE SPF: HELO does not publish an SPF Record -0.0 SPF_PASS SPF: sender matches SPF record X-BeenThere: linux-amlogic@lists.infradead.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: devicetree@vger.kernel.org, Hanjie Lin , Victor Wan , Jianxin Pan , Neil Armstrong , Martin Blumenstingl , linux-pm@vger.kernel.org, linux-kernel@vger.kernel.org, Zhiqiang Liang , Rob Herring , Jian Hu , Xingyu Chen , linux-arm-kernel@lists.infradead.org, Jerome Brunet Sender: "linux-amlogic" Errors-To: linux-amlogic-bounces+patchwork-linux-amlogic=patchwork.kernel.org@lists.infradead.org Add support for the Amlogic Secure Power controller. In A1/C1 series, power control registers are in secure domain, and should be accessed by smc. Signed-off-by: Jianxin Pan Signed-off-by: Zhiqiang Liang --- drivers/soc/amlogic/Kconfig | 13 +++ drivers/soc/amlogic/Makefile | 1 + drivers/soc/amlogic/meson-secure-pwrc.c | 182 ++++++++++++++++++++++++++++++++ 3 files changed, 196 insertions(+) create mode 100644 drivers/soc/amlogic/meson-secure-pwrc.c diff --git a/drivers/soc/amlogic/Kconfig b/drivers/soc/amlogic/Kconfig index bc2c912..6cb06e7 100644 --- a/drivers/soc/amlogic/Kconfig +++ b/drivers/soc/amlogic/Kconfig @@ -48,6 +48,19 @@ config MESON_EE_PM_DOMAINS Say yes to expose Amlogic Meson Everything-Else Power Domains as Generic Power Domains. +config MESON_SECURE_PM_DOMAINS + bool "Amlogic Meson Secure Power Domains driver" + depends on ARCH_MESON || COMPILE_TEST + depends on PM && OF + depends on HAVE_ARM_SMCCC + default ARCH_MESON + select PM_GENERIC_DOMAINS + select PM_GENERIC_DOMAINS_OF + help + Support for the power controller on Amlogic A1/C1 series. + Say yes to expose Amlogic Meson Secure Power Domains as Generic + Power Domains. + config MESON_MX_SOCINFO bool "Amlogic Meson MX SoC Information driver" depends on ARCH_MESON || COMPILE_TEST diff --git a/drivers/soc/amlogic/Makefile b/drivers/soc/amlogic/Makefile index de79d044..7b8c5d3 100644 --- a/drivers/soc/amlogic/Makefile +++ b/drivers/soc/amlogic/Makefile @@ -5,3 +5,4 @@ obj-$(CONFIG_MESON_GX_SOCINFO) += meson-gx-socinfo.o obj-$(CONFIG_MESON_GX_PM_DOMAINS) += meson-gx-pwrc-vpu.o obj-$(CONFIG_MESON_MX_SOCINFO) += meson-mx-socinfo.o obj-$(CONFIG_MESON_EE_PM_DOMAINS) += meson-ee-pwrc.o +obj-$(CONFIG_MESON_SECURE_PM_DOMAINS) += meson-secure-pwrc.o diff --git a/drivers/soc/amlogic/meson-secure-pwrc.c b/drivers/soc/amlogic/meson-secure-pwrc.c new file mode 100644 index 00000000..00c7232 --- /dev/null +++ b/drivers/soc/amlogic/meson-secure-pwrc.c @@ -0,0 +1,182 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Copyright (c) 2019 Amlogic, Inc. + * Author: Jianxin Pan + */ +#include +#include +#include +#include +#include +#include + +#define PWRC_ON 1 +#define PWRC_OFF 0 +#define SMC_PWRC_SET 0x82000093 +#define SMC_PWRC_GET 0x82000095 + +struct meson_secure_pwrc_domain { + struct generic_pm_domain base; + unsigned int index; +}; + +struct meson_secure_pwrc { + struct meson_secure_pwrc_domain *domains; + struct genpd_onecell_data xlate; +}; + +struct meson_secure_pwrc_domain_desc { + unsigned int index; + unsigned int flags; + char *name; + bool (*get_power)(struct meson_secure_pwrc_domain *pwrc_domain); +}; + +struct meson_secure_pwrc_domain_data { + unsigned int count; + struct meson_secure_pwrc_domain_desc *domains; +}; + +static bool pwrc_secure_get_power(struct meson_secure_pwrc_domain *pwrc_domain) +{ + struct arm_smccc_res res; + + arm_smccc_smc(SMC_PWRC_GET, pwrc_domain->index, 0, + 0, 0, 0, 0, 0, &res); + + return res.a0 & 0x1; +} + +static int meson_secure_pwrc_off(struct generic_pm_domain *domain) +{ + struct arm_smccc_res res; + struct meson_secure_pwrc_domain *pwrc_domain = + container_of(domain, struct meson_secure_pwrc_domain, base); + + arm_smccc_smc(SMC_PWRC_SET, pwrc_domain->index, PWRC_OFF, + 0, 0, 0, 0, 0, &res); + + return 0; +} + +static int meson_secure_pwrc_on(struct generic_pm_domain *domain) +{ + struct arm_smccc_res res; + struct meson_secure_pwrc_domain *pwrc_domain = + container_of(domain, struct meson_secure_pwrc_domain, base); + + arm_smccc_smc(SMC_PWRC_SET, pwrc_domain->index, PWRC_ON, + 0, 0, 0, 0, 0, &res); + + return 0; +} + +#define SEC_PD(__name, __flag) \ +{ \ + .name = #__name, \ + .index = PWRC_##__name##_ID, \ + .get_power = pwrc_secure_get_power, \ + .flags = __flag, \ +} + +static struct meson_secure_pwrc_domain_desc a1_pwrc_domains[] = { + SEC_PD(DSPA, 0), + SEC_PD(DSPB, 0), + SEC_PD(UART, GENPD_FLAG_ALWAYS_ON), + SEC_PD(DMC, GENPD_FLAG_ALWAYS_ON), + SEC_PD(I2C, 0), + SEC_PD(PSRAM, 0), + SEC_PD(ACODEC, 0), + SEC_PD(AUDIO, 0), + SEC_PD(OTP, 0), + SEC_PD(DMA, 0), + SEC_PD(SD_EMMC, 0), + SEC_PD(RAMA, 0), + SEC_PD(RAMB, GENPD_FLAG_ALWAYS_ON), + SEC_PD(IR, 0), + SEC_PD(SPICC, 0), + SEC_PD(SPIFC, 0), + SEC_PD(USB, 0), + SEC_PD(NIC, GENPD_FLAG_ALWAYS_ON), + SEC_PD(PDMIN, 0), + SEC_PD(RSA, 0), +}; + +static int meson_secure_pwrc_probe(struct platform_device *pdev) +{ + const struct meson_secure_pwrc_domain_data *match; + struct meson_secure_pwrc *pwrc; + int i; + + match = of_device_get_match_data(&pdev->dev); + if (!match) { + dev_err(&pdev->dev, "failed to get match data\n"); + return -ENODEV; + } + + pwrc = devm_kzalloc(&pdev->dev, sizeof(*pwrc), GFP_KERNEL); + if (!pwrc) + return -ENOMEM; + + pwrc->xlate.domains = devm_kcalloc(&pdev->dev, match->count, + sizeof(*pwrc->xlate.domains), + GFP_KERNEL); + if (!pwrc->xlate.domains) + return -ENOMEM; + + pwrc->domains = devm_kcalloc(&pdev->dev, match->count, + sizeof(*pwrc->domains), GFP_KERNEL); + if (!pwrc->domains) + return -ENOMEM; + + pwrc->xlate.num_domains = match->count; + platform_set_drvdata(pdev, pwrc); + + for (i = 0 ; i < match->count ; ++i) { + struct meson_secure_pwrc_domain *dom = &pwrc->domains[i]; + + if (!match->domains[i].index) + continue; + + dom->index = match->domains[i].index; + dom->base.name = match->domains[i].name; + dom->base.flags = match->domains[i].flags; + dom->base.power_on = meson_secure_pwrc_on; + dom->base.power_off = meson_secure_pwrc_off; + + pm_genpd_init(&dom->base, NULL, + (match->domains[i].get_power ? + match->domains[i].get_power(dom) : true)); + + pwrc->xlate.domains[i] = &dom->base; + } + + return of_genpd_add_provider_onecell(pdev->dev.of_node, &pwrc->xlate); +} + +static struct meson_secure_pwrc_domain_data meson_secure_a1_pwrc_data = { + .domains = a1_pwrc_domains, + .count = ARRAY_SIZE(a1_pwrc_domains), +}; + +static const struct of_device_id meson_secure_pwrc_match_table[] = { + { + .compatible = "amlogic,meson-a1-pwrc", + .data = &meson_secure_a1_pwrc_data, + }, + { } +}; + +static struct platform_driver meson_secure_pwrc_driver = { + .probe = meson_secure_pwrc_probe, + .driver = { + .name = "meson_secure_pwrc", + .of_match_table = meson_secure_pwrc_match_table, + }, +}; + +static int meson_secure_pwrc_init(void) +{ + return platform_driver_register(&meson_secure_pwrc_driver); +} +arch_initcall_sync(meson_secure_pwrc_init); From patchwork Thu Sep 19 12:11:04 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Jianxin Pan X-Patchwork-Id: 11152227 Return-Path: Received: from mail.kernel.org (pdx-korg-mail-1.web.codeaurora.org [172.30.200.123]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id CEDA3112B for ; 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bh=SAL4OnmSQ6DVRCA4akaArGzIAuQ8oM3NadXLq1770Ys=; b=k8dcOd+lYETkLT Hz9C2wpk2q5VZnSyPGHr7RXYMS0fDfMqwE0SEObNDp5zWns8eJ9v3s9SQLS1YTuRW0Wh0wR1o7fJV G1R2zl2rUgzTZjG0z7K7SDJRAT4zzQRpTBbsojw5gq/8DOGpDscva3jS5hwAcubHoZqC9G3OoF7bV zy7MI2xZxHK1oMHYRb3UHyGOE3QFSKVHyH8PU0CIPL6BP4UVWaY2jOZ7Vgje/AoBCGLWMPEXSSI1G NuVZjSE1ulFEmfXMefZeumLIE+PQA2SYAPMpwht9w6rEd2LtIVPvqAceTjE14QWD8AWFsdTAPsR9Y uReQGcxS2nKYpJrA7frQ==; Received: from localhost ([127.0.0.1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.92.2 #3 (Red Hat Linux)) id 1iAvId-0004N0-3X; Thu, 19 Sep 2019 12:12:39 +0000 Received: from mail-sh.amlogic.com ([58.32.228.43]) by bombadil.infradead.org with esmtps (Exim 4.92.2 #3 (Red Hat Linux)) id 1iAvHQ-0003TK-As; Thu, 19 Sep 2019 12:11:26 +0000 Received: from droid13.amlogic.com (116.236.93.172) by mail-sh.amlogic.com (10.18.11.5) with Microsoft SMTP Server id 15.1.1591.10; Thu, 19 Sep 2019 20:12:06 +0800 From: Jianxin Pan To: Kevin Hilman , Subject: [PATCH 3/3] arm64: dts: meson: a1: add secure power domain controller Date: Thu, 19 Sep 2019 08:11:04 -0400 Message-ID: <1568895064-4116-4-git-send-email-jianxin.pan@amlogic.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1568895064-4116-1-git-send-email-jianxin.pan@amlogic.com> References: <1568895064-4116-1-git-send-email-jianxin.pan@amlogic.com> MIME-Version: 1.0 X-Originating-IP: [116.236.93.172] X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20190919_051125_110126_4219D529 X-CRM114-Status: UNSURE ( 6.43 ) X-CRM114-Notice: Please train this message. X-Spam-Score: 0.0 (/) X-Spam-Report: SpamAssassin version 3.4.2 on bombadil.infradead.org summary: Content analysis details: (0.0 points) pts rule name description ---- ---------------------- -------------------------------------------------- 0.0 SPF_HELO_NONE SPF: HELO does not publish an SPF Record -0.0 SPF_PASS SPF: sender matches SPF record X-BeenThere: linux-amlogic@lists.infradead.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: devicetree@vger.kernel.org, Hanjie Lin , Victor Wan , Jianxin Pan , Neil Armstrong , Martin Blumenstingl , linux-pm@vger.kernel.org, linux-kernel@vger.kernel.org, Zhiqiang Liang , Rob Herring , Jian Hu , Xingyu Chen , linux-arm-kernel@lists.infradead.org, Jerome Brunet Sender: "linux-amlogic" Errors-To: linux-amlogic-bounces+patchwork-linux-amlogic=patchwork.kernel.org@lists.infradead.org Enable power domain controller for Meson A1 SoC. Signed-off-by: Jianxin Pan Signed-off-by: Zhiqiang Liang --- arch/arm64/boot/dts/amlogic/meson-a1.dtsi | 6 ++++++ 1 file changed, 6 insertions(+) diff --git a/arch/arm64/boot/dts/amlogic/meson-a1.dtsi b/arch/arm64/boot/dts/amlogic/meson-a1.dtsi index 7210ad0..d689e5c 100644 --- a/arch/arm64/boot/dts/amlogic/meson-a1.dtsi +++ b/arch/arm64/boot/dts/amlogic/meson-a1.dtsi @@ -93,6 +93,12 @@ clock-names = "xtal", "pclk", "baud"; status = "disabled"; }; + + pwrc: power-controller { + compatible = "amlogic,meson-a1-pwrc"; + #power-domain-cells = <1>; + status = "okay"; + }; }; gic: interrupt-controller@ff901000 {