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Wed, 25 Sep 2019 02:09:08 +0000 Received: from AM0PR04MB4481.eurprd04.prod.outlook.com ([fe80::6ca2:ec08:2b37:8ab8]) by AM0PR04MB4481.eurprd04.prod.outlook.com ([fe80::6ca2:ec08:2b37:8ab8%6]) with mapi id 15.20.2284.023; Wed, 25 Sep 2019 02:09:08 +0000 From: Peng Fan To: "robh+dt@kernel.org" , "mark.rutland@arm.com" , "jassisinghbrar@gmail.com" , "sudeep.holla@arm.com" , "andre.przywara@arm.com" , "f.fainelli@gmail.com" Subject: [PATCH V9 1/2] dt-bindings: mailbox: add binding doc for the ARM SMC/HVC mailbox Thread-Topic: [PATCH V9 1/2] dt-bindings: mailbox: add binding doc for the ARM SMC/HVC mailbox Thread-Index: AQHVc0Y291KPBxEKYUuzX6RMzv1TyQ== Date: Wed, 25 Sep 2019 02:09:08 +0000 Message-ID: <1569377224-5755-2-git-send-email-peng.fan@nxp.com> References: <1569377224-5755-1-git-send-email-peng.fan@nxp.com> In-Reply-To: <1569377224-5755-1-git-send-email-peng.fan@nxp.com> Accept-Language: en-US Content-Language: en-US X-MS-Has-Attach: X-MS-TNEF-Correlator: x-mailer: git-send-email 2.7.4 x-clientproxiedby: HK0PR03CA0041.apcprd03.prod.outlook.com (2603:1096:203:2f::29) To AM0PR04MB4481.eurprd04.prod.outlook.com (2603:10a6:208:70::15) authentication-results: spf=none (sender IP is ) smtp.mailfrom=peng.fan@nxp.com; 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DIR:OUT; SFP:1101; SCL:1; SRVR:AM0PR04MB4451; H:AM0PR04MB4481.eurprd04.prod.outlook.com; FPR:; SPF:None; LANG:en; PTR:InfoNoRecords; MX:1; A:1; received-spf: None (protection.outlook.com: nxp.com does not designate permitted sender hosts) x-ms-exchange-senderadcheck: 1 x-microsoft-antispam-message-info: f8C/G9ZETagMY0slCkSc90dCO59JOWpvtx3kLUIz5FzHWG5cYOWaUpWug3ElmVykm8LPu/XjRoezfngkrZ3ISuGS2yEWMLgM6zKZ6rJy36r9wCMQFDphlYZyC5e6fL4OXvN7qWk85gjH7fk1JLirSxkObkzwYFfNGQt4cHvQmPI9FRiesowyzKF5NUvgQXsTQkxs9cIT4VjpFYIvw0pmLlOCLDqR5Go2BwKOvQ/YqhptOisakDJL08KRSc3VAXABo+MdSr1hZDoktorE+OaPcmW3Xr2NbVZKvkEJkDfXG3bxiYPACdljcjbB3MIGL7JSh2xwxHAEr4GnqDgwjApXW+KX4p5CqXtcSX51l/ExHE7K2i+EDwHngAL9ln/KVTXJqenfTg7B8rFPPIiE9B+yDkD+cWvh6ICNzceiW9S2RCEMsclrXWbpXLnULfZxSptA MIME-Version: 1.0 X-OriginatorOrg: nxp.com X-MS-Exchange-CrossTenant-Network-Message-Id: c2c68e1a-3066-4696-63e2-08d7415d591f X-MS-Exchange-CrossTenant-originalarrivaltime: 25 Sep 2019 02:09:08.0587 (UTC) X-MS-Exchange-CrossTenant-fromentityheader: Hosted X-MS-Exchange-CrossTenant-id: 686ea1d3-bc2b-4c6f-a92c-d99c5c301635 X-MS-Exchange-CrossTenant-mailboxtype: HOSTED X-MS-Exchange-CrossTenant-userprincipalname: j0vVMXspMMTDgcgDBaX5SGlMuzLSyL0UeeoOO26TEi4piqDBgeJrb782+r1OJmcWvOJUAsvJoStW0VoWesNPeg== X-MS-Exchange-Transport-CrossTenantHeadersStamped: AM0PR04MB4451 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20190924_190911_630874_F9C4D8A7 X-CRM114-Status: GOOD ( 16.04 ) X-Spam-Score: -0.2 (/) X-Spam-Report: SpamAssassin version 3.4.2 on bombadil.infradead.org summary: Content analysis details: (-0.2 points) pts rule name description ---- ---------------------- -------------------------------------------------- -0.0 RCVD_IN_DNSWL_NONE RBL: Sender listed at https://www.dnswl.org/, no trust [40.107.5.56 listed in list.dnswl.org] -0.0 SPF_PASS SPF: sender matches SPF record -0.0 SPF_HELO_PASS SPF: HELO matches SPF record 0.1 DKIM_SIGNED Message has a DKIM or DK signature, not necessarily valid -0.1 DKIM_VALID_EF Message has a valid DKIM or DK signature from envelope-from domain -0.1 DKIM_VALID_AU Message has a valid DKIM or DK signature from author's domain -0.1 DKIM_VALID Message has at least one valid DKIM or DK signature X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: "devicetree@vger.kernel.org" , Peng Fan , "linux-kernel@vger.kernel.org" , "linux-arm-kernel@lists.infradead.org" , dl-linux-imx Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+patchwork-linux-arm=patchwork.kernel.org@lists.infradead.org From: Peng Fan The ARM SMC/HVC mailbox binding describes a firmware interface to trigger actions in software layers running in the EL2 or EL3 exception levels. The term "ARM" here relates to the SMC instruction as part of the ARM instruction set, not as a standard endorsed by ARM Ltd. Signed-off-by: Peng Fan Reviewed-by: Florian Fainelli Reviewed-by: Andre Przywara Reviewed-by: Rob Herring --- .../devicetree/bindings/mailbox/arm-smc.yaml | 96 ++++++++++++++++++++++ 1 file changed, 96 insertions(+) create mode 100644 Documentation/devicetree/bindings/mailbox/arm-smc.yaml diff --git a/Documentation/devicetree/bindings/mailbox/arm-smc.yaml b/Documentation/devicetree/bindings/mailbox/arm-smc.yaml new file mode 100644 index 000000000000..b061954d1678 --- /dev/null +++ b/Documentation/devicetree/bindings/mailbox/arm-smc.yaml @@ -0,0 +1,96 @@ +# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/mailbox/arm-smc.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: ARM SMC Mailbox Interface + +maintainers: + - Peng Fan + +description: | + This mailbox uses the ARM smc (secure monitor call) or hvc (hypervisor + call) instruction to trigger a mailbox-connected activity in firmware, + executing on the very same core as the caller. The value of r0/w0/x0 + the firmware returns after the smc call is delivered as a received + message to the mailbox framework, so synchronous communication can be + established. The exact meaning of the action the mailbox triggers as + well as the return value is defined by their users and is not subject + to this binding. + + One example use case of this mailbox is the SCMI interface, which uses + shared memory to transfer commands and parameters, and a mailbox to + trigger a function call. This allows SoCs without a separate management + processor (or when such a processor is not available or used) to use + this standardized interface anyway. + + This binding describes no hardware, but establishes a firmware interface. + Upon receiving an SMC using the described SMC function identifier, the + firmware is expected to trigger some mailbox connected functionality. + The communication follows the ARM SMC calling convention. + Firmware expects an SMC function identifier in r0 or w0. The supported + identifier are passed from consumers, or listed in the the arm,func-id + property as described below. The firmware can return one value in + the first SMC result register, it is expected to be an error value, + which shall be propagated to the mailbox client. + + Any core which supports the SMC or HVC instruction can be used, as long + as a firmware component running in EL3 or EL2 is handling these calls. + +properties: + compatible: + oneOf: + - description: + For implementations using ARM SMC instruction. + const: arm,smc-mbox + + - description: + For implementations using ARM HVC instruction. + const: arm,hvc-mbox + + "#mbox-cells": + const: 0 + + arm,func-id: + description: | + An single 32-bit value specifying the function ID used by the mailbox. + The function ID follows the ARM SMC calling convention standard. + $ref: /schemas/types.yaml#/definitions/uint32 + +required: + - compatible + - "#mbox-cells" + - arm,func-id + +examples: + - | + sram@93f000 { + compatible = "mmio-sram"; + reg = <0x0 0x93f000 0x0 0x1000>; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0x0 0x93f000 0x1000>; + + cpu_scp_lpri: scp-shmem@0 { + compatible = "arm,scmi-shmem"; + reg = <0x0 0x200>; + }; + }; + + smc_tx_mbox: tx_mbox { + #mbox-cells = <0>; + compatible = "arm,smc-mbox"; + arm,func-id = <0xc20000fe>; + }; + + firmware { + scmi { + compatible = "arm,scmi"; + mboxes = <&smc_tx_mbox>; + mbox-names = "tx"; + shmem = <&cpu_scp_lpri>; + }; + }; + +... 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Wed, 25 Sep 2019 02:09:11 +0000 Received: from AM0PR04MB4481.eurprd04.prod.outlook.com ([fe80::6ca2:ec08:2b37:8ab8]) by AM0PR04MB4481.eurprd04.prod.outlook.com ([fe80::6ca2:ec08:2b37:8ab8%6]) with mapi id 15.20.2284.023; Wed, 25 Sep 2019 02:09:11 +0000 From: Peng Fan To: "robh+dt@kernel.org" , "mark.rutland@arm.com" , "jassisinghbrar@gmail.com" , "sudeep.holla@arm.com" , "andre.przywara@arm.com" , "f.fainelli@gmail.com" Subject: [PATCH V9 2/2] mailbox: introduce ARM SMC based mailbox Thread-Topic: [PATCH V9 2/2] mailbox: introduce ARM SMC based mailbox Thread-Index: AQHVc0Y4wdHLx7HssEii123ZZ3l8/w== Date: Wed, 25 Sep 2019 02:09:11 +0000 Message-ID: <1569377224-5755-3-git-send-email-peng.fan@nxp.com> References: <1569377224-5755-1-git-send-email-peng.fan@nxp.com> In-Reply-To: <1569377224-5755-1-git-send-email-peng.fan@nxp.com> Accept-Language: en-US Content-Language: en-US X-MS-Has-Attach: X-MS-TNEF-Correlator: x-mailer: git-send-email 2.7.4 x-clientproxiedby: HK0PR03CA0041.apcprd03.prod.outlook.com (2603:1096:203:2f::29) To AM0PR04MB4481.eurprd04.prod.outlook.com (2603:10a6:208:70::15) authentication-results: spf=none (sender IP is ) smtp.mailfrom=peng.fan@nxp.com; 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The mailbox receiver is implemented in firmware and can synchronously return data when it returns execution to the non-secure world again. An asynchronous receive path is not implemented. This allows the usage of a mailbox to trigger firmware actions on SoCs which either don't have a separate management processor or on which such a core is not available. A user of this mailbox could be the SCP interface. Modified from Andre Przywara's v2 patch https://lore.kernel.org/patchwork/patch/812999/ Cc: Andre Przywara Signed-off-by: Peng Fan Reviewed-by: Andre Przywara Reviewed-by: Florian Fainelli --- drivers/mailbox/Kconfig | 7 ++ drivers/mailbox/Makefile | 2 + drivers/mailbox/arm-smc-mailbox.c | 167 +++++++++++++++++++++++++++++++++ include/linux/mailbox/arm-smccc-mbox.h | 20 ++++ 4 files changed, 196 insertions(+) create mode 100644 drivers/mailbox/arm-smc-mailbox.c create mode 100644 include/linux/mailbox/arm-smccc-mbox.h diff --git a/drivers/mailbox/Kconfig b/drivers/mailbox/Kconfig index ab4eb750bbdd..7707ee26251a 100644 --- a/drivers/mailbox/Kconfig +++ b/drivers/mailbox/Kconfig @@ -16,6 +16,13 @@ config ARM_MHU The controller has 3 mailbox channels, the last of which can be used in Secure mode only. +config ARM_SMC_MBOX + tristate "Generic ARM smc mailbox" + depends on OF && HAVE_ARM_SMCCC + help + Generic mailbox driver which uses ARM smc calls to call into + firmware for triggering mailboxes. + config IMX_MBOX tristate "i.MX Mailbox" depends on ARCH_MXC || COMPILE_TEST diff --git a/drivers/mailbox/Makefile b/drivers/mailbox/Makefile index c22fad6f696b..93918a84c91b 100644 --- a/drivers/mailbox/Makefile +++ b/drivers/mailbox/Makefile @@ -7,6 +7,8 @@ obj-$(CONFIG_MAILBOX_TEST) += mailbox-test.o obj-$(CONFIG_ARM_MHU) += arm_mhu.o +obj-$(CONFIG_ARM_SMC_MBOX) += arm-smc-mailbox.o + obj-$(CONFIG_IMX_MBOX) += imx-mailbox.o obj-$(CONFIG_ARMADA_37XX_RWTM_MBOX) += armada-37xx-rwtm-mailbox.o diff --git a/drivers/mailbox/arm-smc-mailbox.c b/drivers/mailbox/arm-smc-mailbox.c new file mode 100644 index 000000000000..6f0b5fd6ad1b --- /dev/null +++ b/drivers/mailbox/arm-smc-mailbox.c @@ -0,0 +1,167 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Copyright (C) 2016,2017 ARM Ltd. + * Copyright 2019 NXP + */ + +#include +#include +#include +#include +#include +#include +#include +#include + +typedef unsigned long (smc_mbox_fn)(unsigned int, unsigned long, + unsigned long, unsigned long, + unsigned long, unsigned long, + unsigned long); + +struct arm_smc_chan_data { + unsigned int function_id; + smc_mbox_fn *invoke_smc_mbox_fn; +}; + +static int arm_smc_send_data(struct mbox_chan *link, void *data) +{ + struct arm_smc_chan_data *chan_data = link->con_priv; + struct arm_smccc_mbox_cmd *cmd = data; + unsigned long ret; + + if (ARM_SMCCC_IS_64(chan_data->function_id)) { + ret = chan_data->invoke_smc_mbox_fn(chan_data->function_id, + cmd->args_smccc64[0], + cmd->args_smccc64[1], + cmd->args_smccc64[2], + cmd->args_smccc64[3], + cmd->args_smccc64[4], + cmd->args_smccc64[5]); + } else { + ret = chan_data->invoke_smc_mbox_fn(chan_data->function_id, + cmd->args_smccc32[0], + cmd->args_smccc32[1], + cmd->args_smccc32[2], + cmd->args_smccc32[3], + cmd->args_smccc32[4], + cmd->args_smccc32[5]); + } + + mbox_chan_received_data(link, (void *)ret); + + return 0; +} + +static unsigned long __invoke_fn_hvc(unsigned int function_id, + unsigned long arg0, unsigned long arg1, + unsigned long arg2, unsigned long arg3, + unsigned long arg4, unsigned long arg5) +{ + struct arm_smccc_res res; + + arm_smccc_hvc(function_id, arg0, arg1, arg2, arg3, arg4, + arg5, 0, &res); + return res.a0; +} + +static unsigned long __invoke_fn_smc(unsigned int function_id, + unsigned long arg0, unsigned long arg1, + unsigned long arg2, unsigned long arg3, + unsigned long arg4, unsigned long arg5) +{ + struct arm_smccc_res res; + + arm_smccc_smc(function_id, arg0, arg1, arg2, arg3, arg4, + arg5, 0, &res); + return res.a0; +} + +static const struct mbox_chan_ops arm_smc_mbox_chan_ops = { + .send_data = arm_smc_send_data, +}; + +static struct mbox_chan * +arm_smc_mbox_of_xlate(struct mbox_controller *mbox, + const struct of_phandle_args *sp) +{ + return mbox->chans; +} + +static int arm_smc_mbox_probe(struct platform_device *pdev) +{ + struct device *dev = &pdev->dev; + struct mbox_controller *mbox; + struct arm_smc_chan_data *chan_data; + int ret; + + mbox = devm_kzalloc(dev, sizeof(*mbox), GFP_KERNEL); + if (!mbox) + return -ENOMEM; + + mbox->of_xlate = arm_smc_mbox_of_xlate; + mbox->num_chans = 1; + mbox->chans = devm_kzalloc(dev, sizeof(*mbox->chans), GFP_KERNEL); + if (!mbox->chans) + return -ENOMEM; + + chan_data = devm_kzalloc(dev, sizeof(*chan_data), GFP_KERNEL); + if (!chan_data) + return -ENOMEM; + + ret = of_property_read_u32(dev->of_node, "arm,func-id", + &chan_data->function_id); + if (ret) + return ret; + + if (of_device_is_compatible(dev->of_node, "arm,smc-mbox")) + chan_data->invoke_smc_mbox_fn = __invoke_fn_smc; + else + chan_data->invoke_smc_mbox_fn = __invoke_fn_hvc; + + + mbox->chans->con_priv = chan_data; + + mbox->txdone_poll = false; + mbox->txdone_irq = false; + mbox->ops = &arm_smc_mbox_chan_ops; + mbox->dev = dev; + + platform_set_drvdata(pdev, mbox); + + ret = devm_mbox_controller_register(dev, mbox); + if (ret) + return ret; + + dev_info(dev, "ARM SMC mailbox enabled.\n"); + + return ret; +} + +static int arm_smc_mbox_remove(struct platform_device *pdev) +{ + struct mbox_controller *mbox = platform_get_drvdata(pdev); + + mbox_controller_unregister(mbox); + return 0; +} + +static const struct of_device_id arm_smc_mbox_of_match[] = { + { .compatible = "arm,smc-mbox", }, + { .compatible = "arm,hvc-mbox", }, + {}, +}; +MODULE_DEVICE_TABLE(of, arm_smc_mbox_of_match); + +static struct platform_driver arm_smc_mbox_driver = { + .driver = { + .name = "arm-smc-mbox", + .of_match_table = arm_smc_mbox_of_match, + }, + .probe = arm_smc_mbox_probe, + .remove = arm_smc_mbox_remove, +}; +module_platform_driver(arm_smc_mbox_driver); + +MODULE_AUTHOR("Peng Fan "); +MODULE_DESCRIPTION("Generic ARM smc mailbox driver"); +MODULE_LICENSE("GPL v2"); diff --git a/include/linux/mailbox/arm-smccc-mbox.h b/include/linux/mailbox/arm-smccc-mbox.h new file mode 100644 index 000000000000..d35fb89a77f5 --- /dev/null +++ b/include/linux/mailbox/arm-smccc-mbox.h @@ -0,0 +1,20 @@ +/* SPDX-License-Identifier: GPL-2.0 */ + +#ifndef _LINUX_ARM_SMCCC_MBOX_H_ +#define _LINUX_ARM_SMCCC_MBOX_H_ + +#include + +/** + * struct arm_smccc_mbox_cmd - ARM SMCCC message structure + * @args_smccc32/64: actual usage of registers is up to the protocol + * (within the SMCCC limits) + */ +struct arm_smccc_mbox_cmd { + union { + u32 args_smccc32[6]; + u64 args_smccc64[6]; + }; +}; + +#endif /* _LINUX_ARM_SMCCC_MBOX_H_ */