From patchwork Fri Sep 27 09:09:42 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: AngeloGioacchino Del Regno X-Patchwork-Id: 11164129 Return-Path: Received: from mail.kernel.org (pdx-korg-mail-1.web.codeaurora.org [172.30.200.123]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id A855317D4 for ; Fri, 27 Sep 2019 09:09:56 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.kernel.org (Postfix) with ESMTP id 869C2217D7 for ; Fri, 27 Sep 2019 09:09:56 +0000 (UTC) Authentication-Results: mail.kernel.org; dkim=pass (2048-bit key) header.d=gmail.com header.i=@gmail.com header.b="OlGApvIh" Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1726300AbfI0JJ4 (ORCPT ); Fri, 27 Sep 2019 05:09:56 -0400 Received: from mail-wr1-f66.google.com ([209.85.221.66]:41803 "EHLO mail-wr1-f66.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1725946AbfI0JJ4 (ORCPT ); Fri, 27 Sep 2019 05:09:56 -0400 Received: by mail-wr1-f66.google.com with SMTP id h7so1820978wrw.8 for ; Fri, 27 Sep 2019 02:09:54 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=U4Qhxl6tUusm5VMROCgNErvb6ASg1CMb20QnnU7lpLo=; b=OlGApvIhx8pg+BB4lJeB/nyvHrDZMROB7FmdrmKlG9eDwa/wnlZxoTt/Ib05Ryw5uB su5jwOfU2l7CmLk5VtX9SmczQ4ilXrSluKUckOcM6rF+vfCrf/db/sqVOO40kkoNQTer CMpS4kOsGzUfF3x/HL13KKDJUOLocIC+rTa1PZvnWJ0+XKkP+kax15J5GHWSpKUwKmko wFwJlJZmk4KxIpxtZjxFPGAVRLZaF6S0SaL5qF1fqlLWokl20cqXAFxIQu/HZgCDly5o J6au7S+xMsIq3UYuui8/rp1YbCLz57jzsYTVUIPictpj8x1DeAGI2J6nkm/uVlH519h+ ZFug== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=U4Qhxl6tUusm5VMROCgNErvb6ASg1CMb20QnnU7lpLo=; b=uCQSlaDAhzp+3z98MCB4qmT08L6iIuFHojsLmRDI78aIVlq3mpsxE2i81d1bG8+Qox GO5iIhgbcstar4JK2RCOtX+rbFJyau1JCN0xaki15PQ+pdZrh5PrpIC6e1COeY9hG1rT Kzcir7v8DrfDQcfqULRrXh1+/TK8E1G1WVjzSdzOvwyLbgXK1M6DTF1QQg9yHVZ1sCxx znrgTMoHJTSabRx30NXGveCZMB6Q7hWQbWFKAt1NBKngnbAqFPIMEVAUX2wsMkBmwHS2 wzmMNga7t9BypdIJpJZC9h56AMcSaIvLkvJWm6CeV6qwUM4bfvQ3wxzxd0/Kf2fsC6JU B9/Q== X-Gm-Message-State: APjAAAWoco56q9ZNzfXng9Z77AuuzZdIxkiyGOWaWqWNVnxZv17oTiS6 is2dYFpYO7Xx7EdRreZVqYSz5Hlas3s= X-Google-Smtp-Source: APXvYqygkF8IXkzwVcVZLI/fdmqqOpfqtHD2O+5idO7MjQVLp62UD6tqFkKGgkp3Odfkhh8Lkoebfg== X-Received: by 2002:a5d:4b46:: with SMTP id w6mr2234896wrs.223.1569575392935; Fri, 27 Sep 2019 02:09:52 -0700 (PDT) Received: from IcarusMOD.eternityproject.eu ([93.51.16.173]) by smtp.gmail.com with ESMTPSA id b62sm6037791wmc.13.2019.09.27.02.09.51 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Fri, 27 Sep 2019 02:09:52 -0700 (PDT) From: kholk11@gmail.com To: linux-arm-msm@vger.kernel.org Cc: iommu@lists.linux-foundation.org, marijns95@gmail.com, agross@kernel.org, robdclark@gmail.com, joro@8bytes.org, AngeloGioacchino Del Regno Subject: [PATCH v2 1/6] iommu/qcom: Use the asid read from device-tree if specified Date: Fri, 27 Sep 2019 11:09:42 +0200 Message-Id: <20190927090947.11175-2-kholk11@gmail.com> X-Mailer: git-send-email 2.21.0 In-Reply-To: <20190927090947.11175-1-kholk11@gmail.com> References: <20190927090947.11175-1-kholk11@gmail.com> MIME-Version: 1.0 Sender: linux-arm-msm-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-arm-msm@vger.kernel.org From: AngeloGioacchino Del Regno As specified in this driver, the context banks are 0x1000 apart. Problem is that sometimes the context number (our asid) does not match this logic and we end up using the wrong one: this starts being a problem in the case that we need to send TZ commands to do anything on a specific context. For this reason, read the ASID from the DT if the property "qcom,ctx-num" is present on the IOMMU context node. Signed-off-by: AngeloGioacchino Del Regno --- .../devicetree/bindings/iommu/qcom,iommu.txt | 1 + drivers/iommu/qcom_iommu.c | 17 ++++++++++++++--- 2 files changed, 15 insertions(+), 3 deletions(-) diff --git a/Documentation/devicetree/bindings/iommu/qcom,iommu.txt b/Documentation/devicetree/bindings/iommu/qcom,iommu.txt index 059139abce35..ba0b77889f02 100644 --- a/Documentation/devicetree/bindings/iommu/qcom,iommu.txt +++ b/Documentation/devicetree/bindings/iommu/qcom,iommu.txt @@ -46,6 +46,7 @@ to non-secure vs secure interrupt line. for routing of context bank irq's to secure vs non- secure lines. (Ie. if the iommu contains secure context banks) +- qcom,ctx-num : The number associated to the context bank ** Examples: diff --git a/drivers/iommu/qcom_iommu.c b/drivers/iommu/qcom_iommu.c index dadc707573a2..5837556af147 100644 --- a/drivers/iommu/qcom_iommu.c +++ b/drivers/iommu/qcom_iommu.c @@ -557,7 +557,8 @@ static int qcom_iommu_of_xlate(struct device *dev, struct of_phandle_args *args) * index into qcom_iommu->ctxs: */ if (WARN_ON(asid < 1) || - WARN_ON(asid > qcom_iommu->num_ctxs)) + WARN_ON(asid > qcom_iommu->num_ctxs) || + WARN_ON(qcom_iommu->ctxs[asid - 1] == NULL)) return -EINVAL; if (!fwspec->iommu_priv) { @@ -665,7 +666,8 @@ static int qcom_iommu_sec_ptbl_init(struct device *dev) static int get_asid(const struct device_node *np) { - u32 reg; + u32 reg, val; + int asid; /* read the "reg" property directly to get the relative address * of the context bank, and calculate the asid from that: @@ -673,7 +675,16 @@ static int get_asid(const struct device_node *np) if (of_property_read_u32_index(np, "reg", 0, ®)) return -ENODEV; - return reg / 0x1000; /* context banks are 0x1000 apart */ + /* Context banks are 0x1000 apart but, in some cases, the ASID + * number doesn't match to this logic and needs to be passed + * from the DT configuration explicitly. + */ + if (of_property_read_u32(np, "qcom,ctx-num", &val)) + asid = reg / 0x1000; + else + asid = val; + + return asid; } static int qcom_iommu_ctx_probe(struct platform_device *pdev) From patchwork Fri Sep 27 09:09:43 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: AngeloGioacchino Del Regno X-Patchwork-Id: 11164131 Return-Path: Received: from mail.kernel.org (pdx-korg-mail-1.web.codeaurora.org [172.30.200.123]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id 2CF8A14DB for ; Fri, 27 Sep 2019 09:09:57 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.kernel.org (Postfix) with ESMTP id 0A2FD217D7 for ; Fri, 27 Sep 2019 09:09:57 +0000 (UTC) Authentication-Results: mail.kernel.org; dkim=pass (2048-bit key) header.d=gmail.com header.i=@gmail.com header.b="eEv4Fwdh" Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1725946AbfI0JJ4 (ORCPT ); Fri, 27 Sep 2019 05:09:56 -0400 Received: from mail-wr1-f68.google.com ([209.85.221.68]:37893 "EHLO mail-wr1-f68.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1725882AbfI0JJ4 (ORCPT ); Fri, 27 Sep 2019 05:09:56 -0400 Received: by mail-wr1-f68.google.com with SMTP id w12so1831227wro.5 for ; Fri, 27 Sep 2019 02:09:54 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=gVA/w0d2QWMzk0mJERhCeM6+8qnZiMPqI0NO/jhQ/j0=; b=eEv4Fwdh0pKiRgTd7B+EjixtmSqNuJRkv5XvtTVqWqDQGeLn3vI6OnLxqfMGfKl++v SlE30ctasb7M/IB2m4PlKU3EF0gXP4nBSORk/elCm4vvpU0U8AD2rB+bdRz8ClkbIO0G L8WpVctLB5e42o/qE9i5gslMYR81fSV89eOzC9PRBRJJoDOoIXeb0CkkOogjbMVNkuf3 GTUNhDzE1AKmRldtFH+AtoNAodsEmaSrCOoCCwkF9wlmAjR2kPkRXcy9Z8FGaDEjt69C pdXnm2lmaYT38JEmQ+UWg7takuMVaCbpVWMDoMy2b8ix81+GXOfVo+yBO4sm8NEoYizc T0tw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=gVA/w0d2QWMzk0mJERhCeM6+8qnZiMPqI0NO/jhQ/j0=; b=dK9Ut5GdC2fLfYa1h6U+dy+CtsnMZy8RLezgOWxnoDT8eYq5knwD8I4InKNyxxiT89 negfO7YykZoPn3HtSfk0YETOUM95ibChlqL61domcmnVia40vOQir+zJOyRmmsWpz+Dr 3+tKsJ32ebPoVfn56BpKb+jw3nNLvpu7kabZOIxyQ6zYwzIuUGoLLTYXPRe2jdci10rg QtRCAyAayD9AJH+1C58eHEAcWTbvNLR+Jj2SrWhhJB7Z3uRMtIX96Ym0KZEKS8Pq+g/6 +Z/tK7pD0bLgyRXwRbo2amuWp1l7C70Wg4rPQH4/4WzBRLUiNS9IndqVkCK8+uk6EYNz P+Lw== X-Gm-Message-State: APjAAAWG3DO+7U+h18pLLh0TDEpxX3PNYurQDLJQmiy8ksKtKNXW6UB/ d1AnzBNwIlZWISi1ueGidVxb4CXxJZM= X-Google-Smtp-Source: APXvYqxVKsiXL1Z2wTAdpcGgdahPsNpSu6ApZ18dtwjjc5bXfkSvKuV99jMnkb11JfefA9bA7MQWPw== X-Received: by 2002:a5d:4ed0:: with SMTP id s16mr2139684wrv.248.1569575393628; Fri, 27 Sep 2019 02:09:53 -0700 (PDT) Received: from IcarusMOD.eternityproject.eu ([93.51.16.173]) by smtp.gmail.com with ESMTPSA id b62sm6037791wmc.13.2019.09.27.02.09.52 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Fri, 27 Sep 2019 02:09:53 -0700 (PDT) From: kholk11@gmail.com To: linux-arm-msm@vger.kernel.org Cc: iommu@lists.linux-foundation.org, marijns95@gmail.com, agross@kernel.org, robdclark@gmail.com, joro@8bytes.org, AngeloGioacchino Del Regno Subject: [PATCH v2 2/6] iommu/qcom: Write TCR before TTBRs to fix ASID access behavior Date: Fri, 27 Sep 2019 11:09:43 +0200 Message-Id: <20190927090947.11175-3-kholk11@gmail.com> X-Mailer: git-send-email 2.21.0 In-Reply-To: <20190927090947.11175-1-kholk11@gmail.com> References: <20190927090947.11175-1-kholk11@gmail.com> MIME-Version: 1.0 Sender: linux-arm-msm-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-arm-msm@vger.kernel.org From: AngeloGioacchino Del Regno As also stated in the arm-smmu driver, we must write the TCR before writing the TTBRs, since the TCR determines the access behavior of some fields. Signed-off-by: AngeloGioacchino Del Regno --- drivers/iommu/qcom_iommu.c | 14 +++++++------- 1 file changed, 7 insertions(+), 7 deletions(-) diff --git a/drivers/iommu/qcom_iommu.c b/drivers/iommu/qcom_iommu.c index 5837556af147..8431fb97a50f 100644 --- a/drivers/iommu/qcom_iommu.c +++ b/drivers/iommu/qcom_iommu.c @@ -245,6 +245,13 @@ static int qcom_iommu_init_domain(struct iommu_domain *domain, ctx->secure_init = true; } + /* TCR */ + iommu_writel(ctx, ARM_SMMU_CB_TCR2, + (pgtbl_cfg.arm_lpae_s1_cfg.tcr >> 32) | + FIELD_PREP(TCR2_SEP, TCR2_SEP_UPSTREAM)); + iommu_writel(ctx, ARM_SMMU_CB_TCR, + pgtbl_cfg.arm_lpae_s1_cfg.tcr); + /* TTBRs */ iommu_writeq(ctx, ARM_SMMU_CB_TTBR0, pgtbl_cfg.arm_lpae_s1_cfg.ttbr[0] | @@ -253,13 +260,6 @@ static int qcom_iommu_init_domain(struct iommu_domain *domain, pgtbl_cfg.arm_lpae_s1_cfg.ttbr[1] | FIELD_PREP(TTBRn_ASID, ctx->asid)); - /* TCR */ - iommu_writel(ctx, ARM_SMMU_CB_TCR2, - (pgtbl_cfg.arm_lpae_s1_cfg.tcr >> 32) | - FIELD_PREP(TCR2_SEP, TCR2_SEP_UPSTREAM)); - iommu_writel(ctx, ARM_SMMU_CB_TCR, - pgtbl_cfg.arm_lpae_s1_cfg.tcr); - /* MAIRs (stage-1 only) */ iommu_writel(ctx, ARM_SMMU_CB_S1_MAIR0, pgtbl_cfg.arm_lpae_s1_cfg.mair[0]); From patchwork Fri Sep 27 09:09:44 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: AngeloGioacchino Del Regno X-Patchwork-Id: 11164133 Return-Path: Received: from mail.kernel.org (pdx-korg-mail-1.web.codeaurora.org [172.30.200.123]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id 11F0E14DB for ; Fri, 27 Sep 2019 09:09:58 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.kernel.org (Postfix) with ESMTP id E19EE21848 for ; Fri, 27 Sep 2019 09:09:57 +0000 (UTC) Authentication-Results: mail.kernel.org; dkim=pass (2048-bit key) header.d=gmail.com header.i=@gmail.com header.b="hxcwnRY5" Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1726294AbfI0JJ5 (ORCPT ); Fri, 27 Sep 2019 05:09:57 -0400 Received: from mail-wr1-f67.google.com ([209.85.221.67]:46145 "EHLO mail-wr1-f67.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1726284AbfI0JJ5 (ORCPT ); Fri, 27 Sep 2019 05:09:57 -0400 Received: by mail-wr1-f67.google.com with SMTP id o18so1791805wrv.13 for ; Fri, 27 Sep 2019 02:09:55 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=sOvGRsd/SK03y6L73WlYgpmOS4qwC0AiL1VcwW/j4sA=; b=hxcwnRY5g2OErPiFxaUbfpFJ9ctrTXDnVSdUZMnMZvpc8R8xWk4a6yuR39Opn2wQSe Rdlzb8HPdc3gRHtaj+NqJs9bZk7WBwaP5kKacF96siA2aUlxGCuP9r56DBAJ2jrtGfnq uMWLNMWhB9oiZ25tBNsb1hHy9N50w+aROulTz2StTEQvQf6ggFVqPDYBfaoGW+sUXkwo a9JbjuwTjG9MOGK0aY0zKqc94aTWRf3YmlUjkJTj8M+R+fOQFTZRQ2a8ROcvv3KAElDB 8e+goYRjmYZ8F3BjxfwDz7te5jw5nLahiFImgHPchtnkRJ/gpYCmqHQi7IT5zZqBk4xE AdFA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=sOvGRsd/SK03y6L73WlYgpmOS4qwC0AiL1VcwW/j4sA=; b=PhwzRbXdROg4nl2TeVzyDgkkoR0QsP2ZgzHzPbv4SJzrSjuLlOSZWc/mcnwjyccWPe n8hDppxpsXBC5xv+pGgvtqI5pKiA+cOejELPKHg0a2zU+LREJBzID+L+20PUWPfYwRxk UsUvVlKyBtcpXSQ9OOYZ0YAjFgrzzqNa3ROXWX5brk49EL8trdRVZnv6+ZAOwfD8K5Oq UqxZtY5V2r2GcoMyHsRv3oIRm4SSwBgoKifDZOGoRpgh3/pc/qjZcmlXvvCk3hMIfi8v +EjsRRYUERkgl39L76bkykwkqt0OOMQ6yTv26XS8xFnVdMrboqjibyZM/eEHL47jKBul FQZg== X-Gm-Message-State: APjAAAX8rUAeIOHesPtfhGdxDQvWgPbR9bV6Te7htzai0c+BkDZu+DEN IpbJYz1SlQFcWcvH5ePE3HWELZppVi0= X-Google-Smtp-Source: APXvYqwB//2FykcH09Wh56p9ftThgdopQyr4u9pGWP1pbEIfcWkZ3VzhVpLpY4C7MADtO6X9CgEkBQ== X-Received: by 2002:adf:ed8f:: with SMTP id c15mr2071587wro.83.1569575394957; Fri, 27 Sep 2019 02:09:54 -0700 (PDT) Received: from IcarusMOD.eternityproject.eu ([93.51.16.173]) by smtp.gmail.com with ESMTPSA id b62sm6037791wmc.13.2019.09.27.02.09.53 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Fri, 27 Sep 2019 02:09:53 -0700 (PDT) From: kholk11@gmail.com To: linux-arm-msm@vger.kernel.org Cc: iommu@lists.linux-foundation.org, marijns95@gmail.com, agross@kernel.org, robdclark@gmail.com, joro@8bytes.org, AngeloGioacchino Del Regno Subject: [PATCH v2 3/6] iommu/qcom: Properly reset the IOMMU context Date: Fri, 27 Sep 2019 11:09:44 +0200 Message-Id: <20190927090947.11175-4-kholk11@gmail.com> X-Mailer: git-send-email 2.21.0 In-Reply-To: <20190927090947.11175-1-kholk11@gmail.com> References: <20190927090947.11175-1-kholk11@gmail.com> MIME-Version: 1.0 Sender: linux-arm-msm-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-arm-msm@vger.kernel.org From: AngeloGioacchino Del Regno To avoid context faults reset the context entirely on detach and to ensure a fresh clean start also do a complete reset before programming the context for domain initialization. Signed-off-by: AngeloGioacchino Del Regno --- drivers/iommu/qcom_iommu.c | 23 +++++++++++++++++++++-- 1 file changed, 21 insertions(+), 2 deletions(-) diff --git a/drivers/iommu/qcom_iommu.c b/drivers/iommu/qcom_iommu.c index 8431fb97a50f..2f31da2e7add 100644 --- a/drivers/iommu/qcom_iommu.c +++ b/drivers/iommu/qcom_iommu.c @@ -198,6 +198,23 @@ static irqreturn_t qcom_iommu_fault(int irq, void *dev) return IRQ_HANDLED; } +static void qcom_iommu_reset_ctx(struct qcom_iommu_ctx *ctx) +{ + iommu_writel(ctx, ARM_SMMU_CB_FAR, 0); + iommu_writel(ctx, ARM_SMMU_CB_FSR, 0); + iommu_writel(ctx, ARM_SMMU_CB_S1_MAIR1, 0); + iommu_writel(ctx, ARM_SMMU_CB_PAR, 0); + iommu_writel(ctx, ARM_SMMU_CB_S1_MAIR0, 0); + iommu_writel(ctx, ARM_SMMU_CB_SCTLR, 0); + iommu_writel(ctx, ARM_SMMU_CB_TCR2, 0); + iommu_writel(ctx, ARM_SMMU_CB_TCR, 0); + iommu_writeq(ctx, ARM_SMMU_CB_TTBR0, 0); + iommu_writeq(ctx, ARM_SMMU_CB_TTBR1, 0); + + /* Should we issue a TLBSYNC there instead? */ + mb(); +} + static int qcom_iommu_init_domain(struct iommu_domain *domain, struct qcom_iommu_dev *qcom_iommu, struct iommu_fwspec *fwspec) @@ -245,6 +262,8 @@ static int qcom_iommu_init_domain(struct iommu_domain *domain, ctx->secure_init = true; } + qcom_iommu_reset_ctx(ctx); + /* TCR */ iommu_writel(ctx, ARM_SMMU_CB_TCR2, (pgtbl_cfg.arm_lpae_s1_cfg.tcr >> 32) | @@ -390,8 +409,8 @@ static void qcom_iommu_detach_dev(struct iommu_domain *domain, struct device *de for (i = 0; i < fwspec->num_ids; i++) { struct qcom_iommu_ctx *ctx = to_ctx(fwspec, fwspec->ids[i]); - /* Disable the context bank: */ - iommu_writel(ctx, ARM_SMMU_CB_SCTLR, 0); + /* Disable and reset the context bank */ + qcom_iommu_reset_ctx(ctx); ctx->domain = NULL; } From patchwork Fri Sep 27 09:09:45 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: AngeloGioacchino Del Regno X-Patchwork-Id: 11164137 Return-Path: Received: from mail.kernel.org (pdx-korg-mail-1.web.codeaurora.org [172.30.200.123]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id 4468E14DB for ; Fri, 27 Sep 2019 09:10:01 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.kernel.org (Postfix) with ESMTP id 17E8C217D7 for ; Fri, 27 Sep 2019 09:10:01 +0000 (UTC) Authentication-Results: mail.kernel.org; dkim=pass (2048-bit key) header.d=gmail.com header.i=@gmail.com header.b="D1A8whOx" Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1726284AbfI0JKA (ORCPT ); Fri, 27 Sep 2019 05:10:00 -0400 Received: from mail-wr1-f68.google.com ([209.85.221.68]:43540 "EHLO mail-wr1-f68.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1726295AbfI0JKA (ORCPT ); Fri, 27 Sep 2019 05:10:00 -0400 Received: by mail-wr1-f68.google.com with SMTP id q17so1810363wrx.10 for ; Fri, 27 Sep 2019 02:09:56 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=OGNly6Vphv4Itb2RkdK4y5BItxcdcc9y36+Z8tgTcg0=; b=D1A8whOxqTnPyfllVyOo5GUyHH22JDWdvQC5wS14rOykrm6oXxi/V5GFZltXKFdMHb VZnIkAioDjmgJftBRWcCnWqUdKMNSh4H4t+unuF5/f50AjwON9p0X0lKEt8RfMnZlfdK ZdgQfAvpsBuBMWGc/ynfvxSjY4RnCFi7S0TdYCa3IWeUpvYnepmdALTIVAI01eiib1Rv ofE/IMxfDpbg0+DmXNQR42QeoWONfkMrCtua6SHLyhhgD6CNBNX260oGlbKOYOACVR4w FyLNYYVhHiIBRHb1osjLLiigFbuXSmnaS4cnye84eeloC3uOkOhAgxvplY/XS9zi9pLo 8p9w== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=OGNly6Vphv4Itb2RkdK4y5BItxcdcc9y36+Z8tgTcg0=; b=rVlQiV8XhCLWO8wT+uoaDNddjUREfhzKsEkAma5VHE4o9DF16pXwmktOl5UKu0h5ax M74aFZHUapMhwBByVQSQvJow+DZDaUPCxj3XxGTfotaN9el7QSlKiV1vTipTsRSjkOsO 0eceewHogoWbE0Qvknf+w04P6g19NIKb9qZo4R+fMP9D1yXxsF44zuteDbwNOPTaOv6l SPR81BZm7q4auYECx/zddeVPyVM3mI3Ca5Fd6TdAOzvG3lcvJXYtDquFqKY0b1Hgxs4D s9KIkRzXKyXIV9cPGSHnUjLs9f/tXNLNHI3NGDf/NQxbT3G5emqmLCN2ZyPJB10N7isU 1CYQ== X-Gm-Message-State: APjAAAXQ80iZBqvsuZWbC2CxpGdjizMcwxBfeUZDh7/ZtAwWCrlbeT2d gikksq1qJvGchSLRblQZAwD+LLVrWeI= X-Google-Smtp-Source: APXvYqyLUk60co2pvzNJ6RPKFw6KfagzRfLG0nZmbQ9wr6rfa33FqxbfqApVgK8/rwVUtrB+sBRw1w== X-Received: by 2002:a5d:5048:: with SMTP id h8mr2053286wrt.280.1569575395940; Fri, 27 Sep 2019 02:09:55 -0700 (PDT) Received: from IcarusMOD.eternityproject.eu ([93.51.16.173]) by smtp.gmail.com with ESMTPSA id b62sm6037791wmc.13.2019.09.27.02.09.54 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Fri, 27 Sep 2019 02:09:55 -0700 (PDT) From: kholk11@gmail.com To: linux-arm-msm@vger.kernel.org Cc: iommu@lists.linux-foundation.org, marijns95@gmail.com, agross@kernel.org, robdclark@gmail.com, joro@8bytes.org, AngeloGioacchino Del Regno Subject: [PATCH v2 4/6] iommu/qcom: Add support for AArch64 IOMMU pagetables Date: Fri, 27 Sep 2019 11:09:45 +0200 Message-Id: <20190927090947.11175-5-kholk11@gmail.com> X-Mailer: git-send-email 2.21.0 In-Reply-To: <20190927090947.11175-1-kholk11@gmail.com> References: <20190927090947.11175-1-kholk11@gmail.com> MIME-Version: 1.0 Sender: linux-arm-msm-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-arm-msm@vger.kernel.org From: AngeloGioacchino Del Regno Some IOMMUs associated with some TZ firmwares may support switching to the AArch64 pagetable format by sending a "set pagetable format" scm command indicating the IOMMU secure ID and the context number to switch. Add a DT property "qcom,use-aarch64-pagetables" for this driver to send this command to the secure world and to switch the pagetable format to benefit of the ARM64 IOMMU pagetables, where possible. Note that, even though the command should be valid to switch each context, the property is made global because: 1. It doesn't make too much sense to switch only one or two context(s) to AA64 instead of just the entire thing 2. Some IOMMUs will go crazy and produce spectacular results when trying to mix up the pagetables on a per-context basis. Signed-off-by: AngeloGioacchino Del Regno --- .../devicetree/bindings/iommu/qcom,iommu.txt | 2 + drivers/iommu/qcom_iommu.c | 55 +++++++++++++++---- 2 files changed, 47 insertions(+), 10 deletions(-) diff --git a/Documentation/devicetree/bindings/iommu/qcom,iommu.txt b/Documentation/devicetree/bindings/iommu/qcom,iommu.txt index ba0b77889f02..72ae0595efff 100644 --- a/Documentation/devicetree/bindings/iommu/qcom,iommu.txt +++ b/Documentation/devicetree/bindings/iommu/qcom,iommu.txt @@ -47,6 +47,8 @@ to non-secure vs secure interrupt line. secure lines. (Ie. if the iommu contains secure context banks) - qcom,ctx-num : The number associated to the context bank +- qcom,use-aarch64-pagetables : Switch to AArch64 pagetable format on all + contexts declared in this IOMMU ** Examples: diff --git a/drivers/iommu/qcom_iommu.c b/drivers/iommu/qcom_iommu.c index 2f31da2e7add..233ef496af27 100644 --- a/drivers/iommu/qcom_iommu.c +++ b/drivers/iommu/qcom_iommu.c @@ -48,6 +48,7 @@ struct qcom_iommu_dev { void __iomem *local_base; u32 sec_id; u8 num_ctxs; + bool use_aarch64_pt; struct qcom_iommu_ctx *ctxs[0]; /* indexed by asid-1 */ }; @@ -153,11 +154,17 @@ static void qcom_iommu_tlb_inv_range_nosync(unsigned long iova, size_t size, reg = leaf ? ARM_SMMU_CB_S1_TLBIVAL : ARM_SMMU_CB_S1_TLBIVA; for (i = 0; i < fwspec->num_ids; i++) { + struct qcom_iommu_dev *qcom_iommu = to_iommu(fwspec); struct qcom_iommu_ctx *ctx = to_ctx(fwspec, fwspec->ids[i]); size_t s = size; - iova &= ~12UL; - iova |= ctx->asid; + if (qcom_iommu->use_aarch64_pt) { + iova >>= 12; + iova |= (u64)ctx->asid << 48; + } else { + iova &= ~12UL; + iova |= ctx->asid; + } do { iommu_writel(ctx, reg, iova); iova += granule; @@ -222,6 +229,8 @@ static int qcom_iommu_init_domain(struct iommu_domain *domain, struct qcom_iommu_domain *qcom_domain = to_qcom_iommu_domain(domain); struct io_pgtable_ops *pgtbl_ops; struct io_pgtable_cfg pgtbl_cfg; + enum io_pgtable_fmt pgtbl_fmt; + unsigned long ias, oas; int i, ret = 0; u32 reg; @@ -229,16 +238,25 @@ static int qcom_iommu_init_domain(struct iommu_domain *domain, if (qcom_domain->iommu) goto out_unlock; + if (qcom_iommu->use_aarch64_pt) { + pgtbl_fmt = ARM_64_LPAE_S1; + ias = oas = 48; + } else { + pgtbl_fmt = ARM_32_LPAE_S1; + ias = 32; + oas = 40; + } + pgtbl_cfg = (struct io_pgtable_cfg) { .pgsize_bitmap = qcom_iommu_ops.pgsize_bitmap, - .ias = 32, - .oas = 40, + .ias = ias, + .oas = oas, .tlb = &qcom_gather_ops, .iommu_dev = qcom_iommu->dev, }; qcom_domain->iommu = qcom_iommu; - pgtbl_ops = alloc_io_pgtable_ops(ARM_32_LPAE_S1, &pgtbl_cfg, fwspec); + pgtbl_ops = alloc_io_pgtable_ops(pgtbl_fmt, &pgtbl_cfg, fwspec); if (!pgtbl_ops) { dev_err(qcom_iommu->dev, "failed to allocate pagetable ops\n"); ret = -ENOMEM; @@ -252,6 +270,7 @@ static int qcom_iommu_init_domain(struct iommu_domain *domain, for (i = 0; i < fwspec->num_ids; i++) { struct qcom_iommu_ctx *ctx = to_ctx(fwspec, fwspec->ids[i]); + u32 tcr[2]; if (!ctx->secure_init) { ret = qcom_scm_restore_sec_cfg(qcom_iommu->sec_id, ctx->asid); @@ -264,12 +283,25 @@ static int qcom_iommu_init_domain(struct iommu_domain *domain, qcom_iommu_reset_ctx(ctx); + tcr[0] = pgtbl_cfg.arm_lpae_s1_cfg.tcr; + tcr[1] = pgtbl_cfg.arm_lpae_s1_cfg.tcr >> 32; + tcr[1] |= FIELD_PREP(TCR2_SEP, TCR2_SEP_UPSTREAM); + + if (qcom_iommu->use_aarch64_pt) { + /* This shall not fail, or spectacular things happen */ + if (qcom_scm_iommu_set_pt_format(qcom_iommu->sec_id, + ctx->asid, 1)) { + dev_warn(qcom_iommu->dev, + "Cannot set AArch64 pt format\n"); + goto out_clear_iommu; + } + + tcr[1] |= TCR2_AS; + } + /* TCR */ - iommu_writel(ctx, ARM_SMMU_CB_TCR2, - (pgtbl_cfg.arm_lpae_s1_cfg.tcr >> 32) | - FIELD_PREP(TCR2_SEP, TCR2_SEP_UPSTREAM)); - iommu_writel(ctx, ARM_SMMU_CB_TCR, - pgtbl_cfg.arm_lpae_s1_cfg.tcr); + iommu_writel(ctx, ARM_SMMU_CB_TCR2, tcr[1]); + iommu_writel(ctx, ARM_SMMU_CB_TCR, tcr[0]); /* TTBRs */ iommu_writeq(ctx, ARM_SMMU_CB_TTBR0, @@ -844,6 +876,9 @@ static int qcom_iommu_device_probe(struct platform_device *pdev) return -ENODEV; } + if (of_property_read_bool(dev->of_node, "qcom,use-aarch64-pagetables")) + qcom_iommu->use_aarch64_pt = true; + if (qcom_iommu_has_secure_context(qcom_iommu)) { ret = qcom_iommu_sec_ptbl_init(dev); if (ret) { From patchwork Fri Sep 27 09:09:46 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: AngeloGioacchino Del Regno X-Patchwork-Id: 11164135 Return-Path: Received: from mail.kernel.org (pdx-korg-mail-1.web.codeaurora.org [172.30.200.123]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id 6F10814DB for ; Fri, 27 Sep 2019 09:10:00 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.kernel.org (Postfix) with ESMTP id 4C7412146E for ; Fri, 27 Sep 2019 09:10:00 +0000 (UTC) Authentication-Results: mail.kernel.org; dkim=pass (2048-bit key) header.d=gmail.com header.i=@gmail.com header.b="CrzA0dAf" Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1725882AbfI0JKA (ORCPT ); Fri, 27 Sep 2019 05:10:00 -0400 Received: from mail-wr1-f68.google.com ([209.85.221.68]:33811 "EHLO mail-wr1-f68.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1726284AbfI0JJ7 (ORCPT ); Fri, 27 Sep 2019 05:09:59 -0400 Received: by mail-wr1-f68.google.com with SMTP id a11so1857124wrx.1 for ; Fri, 27 Sep 2019 02:09:57 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=hM8YfKOj/veQZGpRjHkC1Z8EKmrCYB/PVErpOmpXBBM=; b=CrzA0dAfHvZNmbLRvm4lFR17eWd8Ghg2Klbm9BaaXYu1POcOkS1OHFsrjrHsBrnVWX yIWdxL8VdDKercQrGymD4aV/jShY/crNRlpatpYEL+IjKsq79dBlJdTLSOAjd3fi11Fi xX/BPI7UGr0U1EgqSSXr/dr9h/74QYj2jrlzmMGLh8KRTHP6W6WzzgbPw7cV6KGe2jrb 1lmPAkoV58ENLjpDQsdCj4s//IYVsaHLXchfilnocklqSEDUu8adyFPigDCQSo4D8s/6 LuPeoNREXq/jkAZ2jeNJno3F6XdR1d4mARXCKVO8+ldY/YnUMLnfNFXrn8qTXv193Ofz cJ3g== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=hM8YfKOj/veQZGpRjHkC1Z8EKmrCYB/PVErpOmpXBBM=; b=jPYy2ZaoUf9DLS/+bS7DK3PyG64l2f9br33zkDMkgsIh/ebzs/0NMqLJNglJMLWi+m xs51gOn0cUnpVQKNcSqlOwGkwzs8791b/oU5s7EWJR+pQivbXxArWkNF+KVour5rDPnA +BNkEExBcrufXbVJmTElo/kQRZmJEak7hpl78dleiZWOCBUprYaPPH2ru6F/oTkfbtsu 9hKhKYjkRxcnd7bFeI8CheXfsJt6HxmyaXXz/xyJaO+zmW7zLl8iDZVMxp5Gp6djHSF/ mfscMZisG8pXBmLZRvDtO2rpdl4Bef90jlSrbLnLeBIGgeXPVlxNp8yZef9wMFMi7sRH C3HQ== X-Gm-Message-State: APjAAAWoBZyArTbxsCtMBzDQX+nzAsvAmuqFw97TORq5XHRFhhOqaliL Qh2FLVuFe7yIWfjV61EkX7X8SjDPXyM= X-Google-Smtp-Source: APXvYqxCPVPtme/YWFWgASY/x3e6HTbdBDsmgmYFg3JZUApCu1I6Fv1JhMVs2di/I7KdPoLmWNxjpA== X-Received: by 2002:a5d:4491:: with SMTP id j17mr1982358wrq.257.1569575396956; Fri, 27 Sep 2019 02:09:56 -0700 (PDT) Received: from IcarusMOD.eternityproject.eu ([93.51.16.173]) by smtp.gmail.com with ESMTPSA id b62sm6037791wmc.13.2019.09.27.02.09.55 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Fri, 27 Sep 2019 02:09:56 -0700 (PDT) From: kholk11@gmail.com To: linux-arm-msm@vger.kernel.org Cc: iommu@lists.linux-foundation.org, marijns95@gmail.com, agross@kernel.org, robdclark@gmail.com, joro@8bytes.org, AngeloGioacchino Del Regno Subject: [PATCH v2 5/6] iommu/qcom: Index contexts by asid number to allow asid 0 Date: Fri, 27 Sep 2019 11:09:46 +0200 Message-Id: <20190927090947.11175-6-kholk11@gmail.com> X-Mailer: git-send-email 2.21.0 In-Reply-To: <20190927090947.11175-1-kholk11@gmail.com> References: <20190927090947.11175-1-kholk11@gmail.com> MIME-Version: 1.0 Sender: linux-arm-msm-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-arm-msm@vger.kernel.org From: AngeloGioacchino Del Regno This driver was indexing the contexts by asid-1, which is probably done under the assumption that the first ASID is always 1. Unfortunately this is not entirely true: at least in the MSM8956 and MSM8976 GPU IOMMU, the gpu_user context's ASID number is zero. To allow using an asid number of zero, stop indexing the contexts by asid-1 and rather index them by asid. Signed-off-by: AngeloGioacchino Del Regno --- drivers/iommu/qcom_iommu.c | 19 +++++++++---------- 1 file changed, 9 insertions(+), 10 deletions(-) diff --git a/drivers/iommu/qcom_iommu.c b/drivers/iommu/qcom_iommu.c index 233ef496af27..03c68fe9439b 100644 --- a/drivers/iommu/qcom_iommu.c +++ b/drivers/iommu/qcom_iommu.c @@ -49,7 +49,7 @@ struct qcom_iommu_dev { u32 sec_id; u8 num_ctxs; bool use_aarch64_pt; - struct qcom_iommu_ctx *ctxs[0]; /* indexed by asid-1 */ + struct qcom_iommu_ctx *ctxs[0]; /* indexed by asid */ }; struct qcom_iommu_ctx { @@ -87,7 +87,7 @@ static struct qcom_iommu_ctx * to_ctx(struct iommu_fwspec *fwspec, unsigned asid struct qcom_iommu_dev *qcom_iommu = to_iommu(fwspec); if (!qcom_iommu) return NULL; - return qcom_iommu->ctxs[asid - 1]; + return qcom_iommu->ctxs[asid]; } static inline void @@ -604,12 +604,10 @@ static int qcom_iommu_of_xlate(struct device *dev, struct of_phandle_args *args) qcom_iommu = platform_get_drvdata(iommu_pdev); /* make sure the asid specified in dt is valid, so we don't have - * to sanity check this elsewhere, since 'asid - 1' is used to - * index into qcom_iommu->ctxs: + * to sanity check this elsewhere: */ - if (WARN_ON(asid < 1) || - WARN_ON(asid > qcom_iommu->num_ctxs) || - WARN_ON(qcom_iommu->ctxs[asid - 1] == NULL)) + if (WARN_ON(asid > qcom_iommu->num_ctxs) || + WARN_ON(qcom_iommu->ctxs[asid] == NULL)) return -EINVAL; if (!fwspec->iommu_priv) { @@ -789,7 +787,7 @@ static int qcom_iommu_ctx_probe(struct platform_device *pdev) dev_dbg(dev, "found asid %u\n", ctx->asid); - qcom_iommu->ctxs[ctx->asid - 1] = ctx; + qcom_iommu->ctxs[ctx->asid] = ctx; return 0; } @@ -801,7 +799,7 @@ static int qcom_iommu_ctx_remove(struct platform_device *pdev) platform_set_drvdata(pdev, NULL); - qcom_iommu->ctxs[ctx->asid - 1] = NULL; + qcom_iommu->ctxs[ctx->asid] = NULL; return 0; } @@ -846,7 +844,8 @@ static int qcom_iommu_device_probe(struct platform_device *pdev) for_each_child_of_node(dev->of_node, child) max_asid = max(max_asid, get_asid(child)); - sz = sizeof(*qcom_iommu) + (max_asid * sizeof(qcom_iommu->ctxs[0])); + sz = sizeof(*qcom_iommu); + sz += (max_asid + 1) * sizeof(qcom_iommu->ctxs[0]); qcom_iommu = devm_kzalloc(dev, sz, GFP_KERNEL); if (!qcom_iommu) From patchwork Fri Sep 27 09:09:47 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: AngeloGioacchino Del Regno X-Patchwork-Id: 11164139 Return-Path: Received: from mail.kernel.org (pdx-korg-mail-1.web.codeaurora.org [172.30.200.123]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id A6F1514DB for ; Fri, 27 Sep 2019 09:10:03 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.kernel.org (Postfix) with ESMTP id 8352E217D9 for ; Fri, 27 Sep 2019 09:10:03 +0000 (UTC) Authentication-Results: mail.kernel.org; dkim=pass (2048-bit key) header.d=gmail.com header.i=@gmail.com header.b="Y8bNJbVl" Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1726323AbfI0JKD (ORCPT ); Fri, 27 Sep 2019 05:10:03 -0400 Received: from mail-wr1-f66.google.com ([209.85.221.66]:37309 "EHLO mail-wr1-f66.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1726087AbfI0JKD (ORCPT ); Fri, 27 Sep 2019 05:10:03 -0400 Received: by mail-wr1-f66.google.com with SMTP id i1so1839516wro.4 for ; Fri, 27 Sep 2019 02:09:59 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=gDR8RfHxA3WQexjQRU+FhsBkTYfjsmwuWajLt1uR8GA=; b=Y8bNJbVlQbl39tIfZcW3jVk+/9O+6GSwLntgWOMqPj/9NwDa3ChW5rWFqV9BwCOFae 3WZD7xngvggoksBv+cKxhuZPb0k8dC+qpDs7BaLpVdQl+mVCDT4an0IrxdtT0goBVZpz +dHoh7zLr98EuEgBymBuuJTtZCj2aRBrwm19BErfXhTZP1H5Hhil6KivdGUsAVi32Kt0 PeOvUoajW61hX8taMI7nLvRaiGK62PbP3gZ2SBwfwj+n5Ge/096P5k+vlkDDOIb9SnpV orSLRAbmJCBX7Tq4JlwjoIGInBs3Ckjq+RWV83hYl2TkqAZQsqkzlQQMyMaulRwb33dk +TLw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=gDR8RfHxA3WQexjQRU+FhsBkTYfjsmwuWajLt1uR8GA=; b=onDd1pRe/I7HKKCmzUyccGktn4NtnFCVD6RwBhBMq62d+HXKMavZwnyNvo4XM9WCLp +PVzD75JLevgciHTGVoExOuM3Y+epUPydpr/FjGgXfmOZzeo+WNx1h7vqebg7i7J1/XO yGIbLUw33VbDg41yRrqjrsny2HGButuGDARdgG6ho/aqeUpYShEVBC7epojrsSUQpcr2 FnV15cwe5Kq+T207NaNsCgwcwzJ+FA4oHqCc1SN+4FleoJQOzWG/V6325wVHSUm7V39a 5DEZzmNYbDEDwOdRQ3tbyu4hh6quPiJV9BZvgFhqwFp3UEcn7N5l+XTddRpVl6w542Qm lwaw== X-Gm-Message-State: APjAAAUaAy+zXOPz/FQnyJJGUixibrQzQxz9Yx+cRX1b2UM8OPP4H2mh 9JLyGlRvV6HjVntB1EJEqlpfMLjY9+k= X-Google-Smtp-Source: APXvYqyJa9541jCs1yD3MOTwafEeGgPAfsDWIGMlNcZan6hy5JpLKKLAlfV6HEIY87+9qcoG9buz3A== X-Received: by 2002:adf:ef8f:: with SMTP id d15mr2057383wro.67.1569575398102; Fri, 27 Sep 2019 02:09:58 -0700 (PDT) Received: from IcarusMOD.eternityproject.eu ([93.51.16.173]) by smtp.gmail.com with ESMTPSA id b62sm6037791wmc.13.2019.09.27.02.09.56 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Fri, 27 Sep 2019 02:09:57 -0700 (PDT) From: kholk11@gmail.com To: linux-arm-msm@vger.kernel.org Cc: iommu@lists.linux-foundation.org, marijns95@gmail.com, agross@kernel.org, robdclark@gmail.com, joro@8bytes.org, AngeloGioacchino Del Regno Subject: [PATCH v2 6/6] iommu/qcom: Add support for QCIOMMUv2 and QCIOMMU-500 secured contexts Date: Fri, 27 Sep 2019 11:09:47 +0200 Message-Id: <20190927090947.11175-7-kholk11@gmail.com> X-Mailer: git-send-email 2.21.0 In-Reply-To: <20190927090947.11175-1-kholk11@gmail.com> References: <20190927090947.11175-1-kholk11@gmail.com> MIME-Version: 1.0 Sender: linux-arm-msm-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-arm-msm@vger.kernel.org From: AngeloGioacchino Del Regno This IOMMU is yet another Qualcomm variant of known IOMMUs, found in Family-B SoCs, such as MSM8956, MSM8976, MSM8953, MSM8917 and others, and that firmware perfectly adheres to this driver logic. This time, though, the catch is that the secure contexts are also secured, meaning that these are programmed by the bootloader or TZ and their "interesting" registers are locked out, so the hypervisor disallows touching them from the non-secure world: in this case the OS is supposed to blindly trust the secure configuration of these contexts and just use them "as they are". For this reason, it is necessary to distinguish between the v1 and 500/v2 secure contexts in this driver in order to adhere to this specification. To do this, add a new DT compatible, named "qcom,msm-iommu-v2-sec" that will trigger the new behavior. For the sake of completeness, also add a "qcom,msm-iommu-v2-ns" so that the human eye gets pleased with it when reading the contexts in the final SoC DT. Of course, the latter is just cosmetic. Signed-off-by: AngeloGioacchino Del Regno --- .../devicetree/bindings/iommu/qcom,iommu.txt | 2 ++ drivers/iommu/qcom_iommu.c | 19 +++++++++++++++++-- 2 files changed, 19 insertions(+), 2 deletions(-) diff --git a/Documentation/devicetree/bindings/iommu/qcom,iommu.txt b/Documentation/devicetree/bindings/iommu/qcom,iommu.txt index 72ae0595efff..861c0cd9c512 100644 --- a/Documentation/devicetree/bindings/iommu/qcom,iommu.txt +++ b/Documentation/devicetree/bindings/iommu/qcom,iommu.txt @@ -36,6 +36,8 @@ to non-secure vs secure interrupt line. - compatible : Should be one of: - "qcom,msm-iommu-v1-ns" : non-secure context bank - "qcom,msm-iommu-v1-sec" : secure context bank + - "qcom,msm-iommu-v2-ns" : non-secure QSMMUv2/QSMMU500 context bank + - "qcom,msm-iommu-v2-sec" : secure QSMMUv2/QSMMU500 context bank - reg : Base address and size of context bank within the iommu - interrupts : The context fault irq. diff --git a/drivers/iommu/qcom_iommu.c b/drivers/iommu/qcom_iommu.c index 03c68fe9439b..2f65a4cdca78 100644 --- a/drivers/iommu/qcom_iommu.c +++ b/drivers/iommu/qcom_iommu.c @@ -56,6 +56,7 @@ struct qcom_iommu_ctx { struct device *dev; void __iomem *base; bool secure_init; + bool secured_ctx; u8 asid; /* asid and ctx bank # are 1:1 */ struct iommu_domain *domain; }; @@ -281,6 +282,12 @@ static int qcom_iommu_init_domain(struct iommu_domain *domain, ctx->secure_init = true; } + /* Secured QSMMU-500/QSMMU-v2 contexts cannot be programmed */ + if (ctx->secured_ctx) { + ctx->domain = domain; + break; + } + qcom_iommu_reset_ctx(ctx); tcr[0] = pgtbl_cfg.arm_lpae_s1_cfg.tcr; @@ -762,10 +769,15 @@ static int qcom_iommu_ctx_probe(struct platform_device *pdev) return -ENODEV; } + if (of_device_is_compatible(dev->of_node, "qcom,msm-iommu-v2-sec")) + ctx->secured_ctx = true; + /* clear IRQs before registering fault handler, just in case the * boot-loader left us a surprise: */ - iommu_writel(ctx, ARM_SMMU_CB_FSR, iommu_readl(ctx, ARM_SMMU_CB_FSR)); + if (!ctx->secured_ctx) + iommu_writel(ctx, ARM_SMMU_CB_FSR, + iommu_readl(ctx, ARM_SMMU_CB_FSR)); ret = devm_request_irq(dev, irq, qcom_iommu_fault, @@ -807,6 +819,8 @@ static int qcom_iommu_ctx_remove(struct platform_device *pdev) static const struct of_device_id ctx_of_match[] = { { .compatible = "qcom,msm-iommu-v1-ns" }, { .compatible = "qcom,msm-iommu-v1-sec" }, + { .compatible = "qcom,msm-iommu-v2-ns" }, + { .compatible = "qcom,msm-iommu-v2-sec" }, { /* sentinel */ } }; @@ -824,7 +838,8 @@ static bool qcom_iommu_has_secure_context(struct qcom_iommu_dev *qcom_iommu) struct device_node *child; for_each_child_of_node(qcom_iommu->dev->of_node, child) - if (of_device_is_compatible(child, "qcom,msm-iommu-v1-sec")) + if (of_device_is_compatible(child, "qcom,msm-iommu-v1-sec") || + of_device_is_compatible(child, "qcom,msm-iommu-v2-sec")) return true; return false;