From patchwork Fri Sep 27 09:26:54 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: =?utf-8?b?SmlheGluIFl1ICjkv57lrrbpkasp?= X-Patchwork-Id: 11164195 Return-Path: Received: from mail.kernel.org (pdx-korg-mail-1.web.codeaurora.org [172.30.200.123]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id 59FEE112B for ; Fri, 27 Sep 2019 09:29:06 +0000 (UTC) Received: from alsa0.perex.cz (alsa0.perex.cz [77.48.224.243]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id E2E8F217D9 for ; Fri, 27 Sep 2019 09:29:05 +0000 (UTC) Authentication-Results: mail.kernel.org; dkim=pass (1024-bit key) header.d=alsa-project.org header.i=@alsa-project.org header.b="Srl2hb3G" DMARC-Filter: OpenDMARC Filter v1.3.2 mail.kernel.org E2E8F217D9 Authentication-Results: mail.kernel.org; dmarc=fail (p=none dis=none) header.from=mediatek.com Authentication-Results: mail.kernel.org; spf=pass smtp.mailfrom=alsa-devel-bounces@alsa-project.org Received: from alsa1.perex.cz (alsa1.perex.cz [207.180.221.201]) (using TLSv1.2 with cipher AECDH-AES256-SHA (256/256 bits)) (No client certificate requested) by alsa0.perex.cz (Postfix) with ESMTPS id 16D5F1674; Fri, 27 Sep 2019 11:28:14 +0200 (CEST) DKIM-Filter: OpenDKIM Filter v2.11.0 alsa0.perex.cz 16D5F1674 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=alsa-project.org; s=default; t=1569576544; bh=j285CrNIXQQ78yAvFSmrKfNgdy3p2IQ6K2jrHiS2Myk=; h=From:To:Date:In-Reply-To:References:Cc:Subject:List-Id: List-Unsubscribe:List-Archive:List-Post:List-Help:List-Subscribe: From; b=Srl2hb3GaE9LV0aFfIFLZ24dJVc1qERi4Diz+eNp9jerYhYv9uCzZgHgSlGPv/jtg 9S16+X3taAiH68+s7wYnWiWBOcxR3IF2yLfn2EASHGJ5g0hcql6G43qFdP6Fi3HZV3 mipxNyd1Wb4j1N/9nFb3y9I7I4uMqC9HtiY9mOtc= Received: from alsa1.perex.cz (localhost.localdomain [127.0.0.1]) by alsa1.perex.cz (Postfix) with ESMTP id 2EF2BF805A8; Fri, 27 Sep 2019 11:27:19 +0200 (CEST) X-Original-To: alsa-devel@alsa-project.org Delivered-To: alsa-devel@alsa-project.org Received: by alsa1.perex.cz (Postfix, from userid 50401) id 651C5F805A8; Fri, 27 Sep 2019 11:27:17 +0200 (CEST) X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on alsa1.perex.cz X-Spam-Level: * X-Spam-Status: No, score=1.0 required=5.0 tests=RDNS_NONE,SPF_HELO_NONE, SPF_PASS,UNPARSEABLE_RELAY,URIBL_BLOCKED autolearn=disabled version=3.4.0 Received: from mailgw01.mediatek.com (unknown [210.61.82.183]) by alsa1.perex.cz (Postfix) with ESMTP id D3427F800B3 for ; Fri, 27 Sep 2019 11:27:12 +0200 (CEST) DKIM-Filter: OpenDKIM Filter v2.11.0 alsa1.perex.cz D3427F800B3 X-UUID: d35aa753a4b34ede95ad268a835d7ebb-20190927 X-UUID: d35aa753a4b34ede95ad268a835d7ebb-20190927 Received: from mtkexhb01.mediatek.inc [(172.21.101.102)] by mailgw01.mediatek.com (envelope-from ) (Cellopoint E-mail Firewall v4.1.10 Build 0809 with TLS) with ESMTP id 1733209468; Fri, 27 Sep 2019 17:27:10 +0800 Received: from mtkcas09.mediatek.inc (172.21.101.178) by mtkmbs01n1.mediatek.inc (172.21.101.68) with Microsoft SMTP Server (TLS) id 15.0.1395.4; Fri, 27 Sep 2019 17:27:01 +0800 Received: from localhost.localdomain (10.17.3.153) by mtkcas09.mediatek.inc (172.21.101.73) with Microsoft SMTP Server id 15.0.1395.4 via Frontend Transport; Fri, 27 Sep 2019 17:27:00 +0800 From: Jiaxin Yu To: , , , , Date: Fri, 27 Sep 2019 17:26:54 +0800 Message-ID: <1569576417-20663-2-git-send-email-jiaxin.yu@mediatek.com> X-Mailer: git-send-email 1.8.1.1.dirty In-Reply-To: <1569576417-20663-1-git-send-email-jiaxin.yu@mediatek.com> References: <1569576417-20663-1-git-send-email-jiaxin.yu@mediatek.com> MIME-Version: 1.0 X-MTK: N Cc: alsa-devel@alsa-project.org, yong.liang@mediatek.com, "yong.liang" , lgirdwood@gmail.com, jiaxin.yu@mediatek.com, tzungbi@google.com, linux-mediatek@lists.infradead.org, eason.yen@mediatek.com, linux-arm-kernel@lists.infradead.org Subject: [alsa-devel] [PATCH 1/4] WIP: dt-bindings: mediatek: mt8183: Add #reset-cells X-BeenThere: alsa-devel@alsa-project.org X-Mailman-Version: 2.1.15 Precedence: list List-Id: "Alsa-devel mailing list for ALSA developers - http://www.alsa-project.org" List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: alsa-devel-bounces@alsa-project.org Sender: "Alsa-devel" From: "yong.liang" Add #reset-cells property and update example. Signed-off-by: yong.liang --- .../devicetree/bindings/watchdog/mtk-wdt.txt | 9 ++++++--- .../dt-bindings/reset-controller/mt8183-resets.h | 13 +++++++++++++ 2 files changed, 19 insertions(+), 3 deletions(-) diff --git a/Documentation/devicetree/bindings/watchdog/mtk-wdt.txt b/Documentation/devicetree/bindings/watchdog/mtk-wdt.txt index 3ee625d0812f..ecb9ff784832 100644 --- a/Documentation/devicetree/bindings/watchdog/mtk-wdt.txt +++ b/Documentation/devicetree/bindings/watchdog/mtk-wdt.txt @@ -16,11 +16,14 @@ Required properties: Optional properties: - timeout-sec: contains the watchdog timeout in seconds. +- #reset-cells: Should be 1. Example: -wdt: watchdog@10000000 { - compatible = "mediatek,mt6589-wdt"; - reg = <0x10000000 0x18>; +watchdog: watchdog@10007000 { + compatible = "mediatek,mt8183-wdt", + "mediatek,mt6589-wdt"; + reg = <0 0x10007000 0 0x100>; timeout-sec = <10>; + #reset-cells = <1>; }; diff --git a/include/dt-bindings/reset-controller/mt8183-resets.h b/include/dt-bindings/reset-controller/mt8183-resets.h index 8804e34ebdd4..47dadcf3fd24 100644 --- a/include/dt-bindings/reset-controller/mt8183-resets.h +++ b/include/dt-bindings/reset-controller/mt8183-resets.h @@ -78,4 +78,17 @@ #define MT8183_INFRACFG_AO_I2C7_SW_RST 126 #define MT8183_INFRACFG_AO_I2C8_SW_RST 127 +#define MT8183_TOPRGU_MM_SW_RST 1 +#define MT8183_TOPRGU_MFG_SW_RST 2 +#define MT8183_TOPRGU_VENC_SW_RST 3 +#define MT8183_TOPRGU_VDEC_SW_RST 4 +#define MT8183_TOPRGU_IMG_SW_RST 5 +#define MT8183_TOPRGU_MD_SW_RST 7 +#define MT8183_TOPRGU_CONN_SW_RST 9 +#define MT8183_TOPRGU_CONN_MCU_SW_RST 12 +#define MT8183_TOPRGU_IPU0_SW_RST 14 +#define MT8183_TOPRGU_IPU1_SW_RST 15 +#define MT8183_TOPRGU_AUDIO_SW_RST 17 +#define MT8183_TOPRGU_CAMSYS_SW_RST 18 + #endif /* _DT_BINDINGS_RESET_CONTROLLER_MT8183 */ From patchwork Fri Sep 27 09:26:55 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: =?utf-8?b?SmlheGluIFl1ICjkv57lrrbpkasp?= X-Patchwork-Id: 11164201 Return-Path: Received: from mail.kernel.org (pdx-korg-mail-1.web.codeaurora.org [172.30.200.123]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id 271A813B1 for ; Fri, 27 Sep 2019 09:30:57 +0000 (UTC) Received: from alsa0.perex.cz (alsa0.perex.cz [77.48.224.243]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id AF8E6217D7 for ; Fri, 27 Sep 2019 09:30:56 +0000 (UTC) Authentication-Results: mail.kernel.org; dkim=pass (1024-bit key) header.d=alsa-project.org header.i=@alsa-project.org header.b="Gj5j5frU" DMARC-Filter: OpenDMARC Filter v1.3.2 mail.kernel.org AF8E6217D7 Authentication-Results: mail.kernel.org; dmarc=fail (p=none dis=none) header.from=mediatek.com Authentication-Results: mail.kernel.org; spf=pass smtp.mailfrom=alsa-devel-bounces@alsa-project.org Received: from alsa1.perex.cz (alsa1.perex.cz [207.180.221.201]) (using TLSv1.2 with cipher AECDH-AES256-SHA (256/256 bits)) (No client certificate requested) by alsa0.perex.cz (Postfix) with ESMTPS id 0239D1663; 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Fri, 27 Sep 2019 11:27:14 +0200 (CEST) DKIM-Filter: OpenDKIM Filter v2.11.0 alsa1.perex.cz 10DC3F80138 X-UUID: b8be764cc7eb4a07aee7da7218eac653-20190927 X-UUID: b8be764cc7eb4a07aee7da7218eac653-20190927 Received: from mtkexhb01.mediatek.inc [(172.21.101.102)] by mailgw01.mediatek.com (envelope-from ) (Cellopoint E-mail Firewall v4.1.10 Build 0809 with TLS) with ESMTP id 617532656; Fri, 27 Sep 2019 17:27:10 +0800 Received: from mtkcas09.mediatek.inc (172.21.101.178) by mtkmbs01n1.mediatek.inc (172.21.101.68) with Microsoft SMTP Server (TLS) id 15.0.1395.4; Fri, 27 Sep 2019 17:27:02 +0800 Received: from localhost.localdomain (10.17.3.153) by mtkcas09.mediatek.inc (172.21.101.73) with Microsoft SMTP Server id 15.0.1395.4 via Frontend Transport; Fri, 27 Sep 2019 17:27:01 +0800 From: Jiaxin Yu To: , , , , Date: Fri, 27 Sep 2019 17:26:55 +0800 Message-ID: <1569576417-20663-3-git-send-email-jiaxin.yu@mediatek.com> X-Mailer: git-send-email 1.8.1.1.dirty In-Reply-To: <1569576417-20663-1-git-send-email-jiaxin.yu@mediatek.com> References: <1569576417-20663-1-git-send-email-jiaxin.yu@mediatek.com> MIME-Version: 1.0 X-MTK: N Cc: alsa-devel@alsa-project.org, yong.liang@mediatek.com, lgirdwood@gmail.com, jiaxin.yu@mediatek.com, tzungbi@google.com, linux-mediatek@lists.infradead.org, eason.yen@mediatek.com, linux-arm-kernel@lists.infradead.org Subject: [alsa-devel] [PATCH 2/4] WIP: watchdog: mtk_wdt: mt8183: Add reset controller X-BeenThere: alsa-devel@alsa-project.org X-Mailman-Version: 2.1.15 Precedence: list List-Id: "Alsa-devel mailing list for ALSA developers - http://www.alsa-project.org" List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: alsa-devel-bounces@alsa-project.org Sender: "Alsa-devel" From: "yong.liang" Provide assert/deassert/reset API in watchdog driver. Register reset controller for toprgu device in watchdog probe. Signed-off-by: yong.liang --- drivers/watchdog/Kconfig | 1 + drivers/watchdog/mtk_wdt.c | 110 ++++++++++++++++++++++++++++++++++++- 2 files changed, 110 insertions(+), 1 deletion(-) diff --git a/drivers/watchdog/Kconfig b/drivers/watchdog/Kconfig index 2e07caab9db2..629249fe5305 100644 --- a/drivers/watchdog/Kconfig +++ b/drivers/watchdog/Kconfig @@ -717,6 +717,7 @@ config MEDIATEK_WATCHDOG tristate "Mediatek SoCs watchdog support" depends on ARCH_MEDIATEK || COMPILE_TEST select WATCHDOG_CORE + select RESET_CONTROLLER help Say Y here to include support for the watchdog timer in Mediatek SoCs. diff --git a/drivers/watchdog/mtk_wdt.c b/drivers/watchdog/mtk_wdt.c index 9c3d0033260d..660fb0e48d8e 100644 --- a/drivers/watchdog/mtk_wdt.c +++ b/drivers/watchdog/mtk_wdt.c @@ -20,6 +20,10 @@ #include #include #include +#include +#include +#include +#include #define WDT_MAX_TIMEOUT 31 #define WDT_MIN_TIMEOUT 1 @@ -44,17 +48,113 @@ #define WDT_SWRST 0x14 #define WDT_SWRST_KEY 0x1209 +#define WDT_SWSYSRST 0x18U +#define WDT_SWSYS_RST_KEY 0x88000000 + #define DRV_NAME "mtk-wdt" #define DRV_VERSION "1.0" static bool nowayout = WATCHDOG_NOWAYOUT; static unsigned int timeout; +struct toprgu_reset { + spinlock_t lock; /* Protects reset_controller access */ + void __iomem *toprgu_swrst_base; + int regofs; + struct reset_controller_dev rcdev; +}; + struct mtk_wdt_dev { struct watchdog_device wdt_dev; void __iomem *wdt_base; + struct toprgu_reset reset_controller; + const struct mtk_wdt_compatible *dev_comp; +}; + +struct mtk_wdt_compatible { + int sw_rst_num; +}; + +static int toprgu_reset_assert(struct reset_controller_dev *rcdev, + unsigned long id) +{ + unsigned int tmp; + unsigned long flags; + struct toprgu_reset *data = container_of(rcdev, + struct toprgu_reset, rcdev); + + spin_lock_irqsave(&data->lock, flags); + + tmp = __raw_readl(data->toprgu_swrst_base + data->regofs); + tmp |= BIT(id); + tmp |= WDT_SWSYS_RST_KEY; + writel(tmp, data->toprgu_swrst_base + data->regofs); + + spin_unlock_irqrestore(&data->lock, flags); + + return 0; +} + +static int toprgu_reset_deassert(struct reset_controller_dev *rcdev, + unsigned long id) +{ + unsigned int tmp; + unsigned long flags; + struct toprgu_reset *data = container_of(rcdev, + struct toprgu_reset, rcdev); + + spin_lock_irqsave(&data->lock, flags); + + tmp = __raw_readl(data->toprgu_swrst_base + data->regofs); + tmp &= ~BIT(id); + tmp |= WDT_SWSYS_RST_KEY; + writel(tmp, data->toprgu_swrst_base + data->regofs); + + spin_unlock_irqrestore(&data->lock, flags); + + return 0; +} + +static int toprgu_reset(struct reset_controller_dev *rcdev, + unsigned long id) +{ + int ret; + + ret = toprgu_reset_assert(rcdev, id); + if (ret) + return ret; + + return toprgu_reset_deassert(rcdev, id); +} + +static struct reset_control_ops toprgu_reset_ops = { + .assert = toprgu_reset_assert, + .deassert = toprgu_reset_deassert, + .reset = toprgu_reset, }; +static void toprgu_register_reset_controller(struct platform_device *pdev, + int regofs) +{ + int ret; + struct mtk_wdt_dev *mtk_wdt = platform_get_drvdata(pdev); + + spin_lock_init(&mtk_wdt->reset_controller.lock); + + mtk_wdt->dev_comp = of_device_get_match_data(&pdev->dev); + mtk_wdt->reset_controller.toprgu_swrst_base = mtk_wdt->wdt_base; + mtk_wdt->reset_controller.regofs = regofs; + mtk_wdt->reset_controller.rcdev.owner = THIS_MODULE; + mtk_wdt->reset_controller.rcdev.nr_resets = + mtk_wdt->dev_comp->sw_rst_num; + mtk_wdt->reset_controller.rcdev.ops = &toprgu_reset_ops; + mtk_wdt->reset_controller.rcdev.of_node = pdev->dev.of_node; + ret = reset_controller_register(&mtk_wdt->reset_controller.rcdev); + if (ret != 0) + dev_err(&pdev->dev, + "couldn't register wdt reset controller: %d\n", ret); +} + static int mtk_wdt_restart(struct watchdog_device *wdt_dev, unsigned long action, void *data) { @@ -187,9 +287,12 @@ static int mtk_wdt_probe(struct platform_device *pdev) if (unlikely(err)) return err; - dev_info(dev, "Watchdog enabled (timeout=%d sec, nowayout=%d)\n", + dev_info(&pdev->dev, "Watchdog enabled (timeout=%d sec, nowayout=%d)\n", mtk_wdt->wdt_dev.timeout, nowayout); + mtk_wdt->dev_comp = of_device_get_match_data(&pdev->dev); + if (mtk_wdt->dev_comp) + toprgu_register_reset_controller(pdev, WDT_SWSYSRST); return 0; } @@ -217,7 +320,12 @@ static int mtk_wdt_resume(struct device *dev) } #endif +static const struct mtk_wdt_compatible mt8183_compat = { + .sw_rst_num = 18, +}; + static const struct of_device_id mtk_wdt_dt_ids[] = { + { .compatible = "mediatek,mt8183-wdt", .data = &mt8183_compat }, { .compatible = "mediatek,mt6589-wdt" }, { /* sentinel */ } }; From patchwork Fri Sep 27 09:26:56 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: =?utf-8?b?SmlheGluIFl1ICjkv57lrrbpkasp?= X-Patchwork-Id: 11164199 Return-Path: Received: from mail.kernel.org (pdx-korg-mail-1.web.codeaurora.org [172.30.200.123]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id 8364714DB for ; Fri, 27 Sep 2019 09:30:18 +0000 (UTC) Received: from alsa0.perex.cz (alsa0.perex.cz [77.48.224.243]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id 15EC9217F4 for ; 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b=I8RgkiTGiBTKbtalx+d0lQZXt6nmzANoIDMJt6Hv+iPb/TrywOwkMYP3sKtYLyogW oPedypKz6kCGD5Sg81uf1V31IbPqP0vvyxvQ3vYIt9GHixAgpjnIIcrXmHMd6i4yol KA1ZqRoxWTKL07M4sSu4wbyYIdp3T4eVyotoxNLM= Received: from alsa1.perex.cz (localhost.localdomain [127.0.0.1]) by alsa1.perex.cz (Postfix) with ESMTP id 66464F805FD; Fri, 27 Sep 2019 11:27:22 +0200 (CEST) X-Original-To: alsa-devel@alsa-project.org Delivered-To: alsa-devel@alsa-project.org Received: by alsa1.perex.cz (Postfix, from userid 50401) id 7D6B2F805A8; Fri, 27 Sep 2019 11:27:18 +0200 (CEST) X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on alsa1.perex.cz X-Spam-Level: * X-Spam-Status: No, score=1.0 required=5.0 tests=RDNS_NONE,SPF_HELO_NONE, SPF_PASS,UNPARSEABLE_RELAY,URIBL_BLOCKED autolearn=disabled version=3.4.0 Received: from mailgw01.mediatek.com (unknown [210.61.82.183]) by alsa1.perex.cz (Postfix) with ESMTP id 3D730F8049C for ; Fri, 27 Sep 2019 11:27:13 +0200 (CEST) DKIM-Filter: OpenDKIM Filter v2.11.0 alsa1.perex.cz 3D730F8049C X-UUID: ee981bd0a8fb408e833e0882503ded89-20190927 X-UUID: ee981bd0a8fb408e833e0882503ded89-20190927 Received: from mtkexhb01.mediatek.inc [(172.21.101.102)] by mailgw01.mediatek.com (envelope-from ) (Cellopoint E-mail Firewall v4.1.10 Build 0809 with TLS) with ESMTP id 514659822; Fri, 27 Sep 2019 17:27:10 +0800 Received: from mtkcas09.mediatek.inc (172.21.101.178) by mtkmbs01n1.mediatek.inc (172.21.101.68) with Microsoft SMTP Server (TLS) id 15.0.1395.4; Fri, 27 Sep 2019 17:27:03 +0800 Received: from localhost.localdomain (10.17.3.153) by mtkcas09.mediatek.inc (172.21.101.73) with Microsoft SMTP Server id 15.0.1395.4 via Frontend Transport; Fri, 27 Sep 2019 17:27:02 +0800 From: Jiaxin Yu To: , , , , Date: Fri, 27 Sep 2019 17:26:56 +0800 Message-ID: <1569576417-20663-4-git-send-email-jiaxin.yu@mediatek.com> X-Mailer: git-send-email 1.8.1.1.dirty In-Reply-To: <1569576417-20663-1-git-send-email-jiaxin.yu@mediatek.com> References: <1569576417-20663-1-git-send-email-jiaxin.yu@mediatek.com> MIME-Version: 1.0 X-MTK: N Cc: alsa-devel@alsa-project.org, yong.liang@mediatek.com, lgirdwood@gmail.com, jiaxin.yu@mediatek.com, tzungbi@google.com, linux-mediatek@lists.infradead.org, eason.yen@mediatek.com, linux-arm-kernel@lists.infradead.org Subject: [alsa-devel] [PATCH 3/4] WIP: dt-bindings: medaitek: mt8183: add property "resets" && "reset-names" X-BeenThere: alsa-devel@alsa-project.org X-Mailman-Version: 2.1.15 Precedence: list List-Id: "Alsa-devel mailing list for ALSA developers - http://www.alsa-project.org" List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: alsa-devel-bounces@alsa-project.org Sender: "Alsa-devel" This patch add property "resets" && "reset-names" in examples so that we can use reset controller to reset audio domain regs. Signed-off-by: Jiaxin Yu --- Documentation/devicetree/bindings/sound/mt8183-afe-pcm.txt | 6 ++++++ 1 file changed, 6 insertions(+) diff --git a/Documentation/devicetree/bindings/sound/mt8183-afe-pcm.txt b/Documentation/devicetree/bindings/sound/mt8183-afe-pcm.txt index 396ba38619f6..1f1cba4152ce 100644 --- a/Documentation/devicetree/bindings/sound/mt8183-afe-pcm.txt +++ b/Documentation/devicetree/bindings/sound/mt8183-afe-pcm.txt @@ -4,6 +4,10 @@ Required properties: - compatible = "mediatek,mt68183-audio"; - reg: register location and size - interrupts: should contain AFE interrupt +- resets: Must contain an entry for each entry in reset-names + See ../reset/reset.txt for details. +- reset-names: should have these reset names: + "audiosys"; - power-domains: should define the power domain - clocks: Must contain an entry for each entry in clock-names - clock-names: should have these clock names: @@ -20,6 +24,8 @@ Example: compatible = "mediatek,mt8183-audio"; reg = <0 0x11220000 0 0x1000>; interrupts = ; + resets = <&watchdog MT8183_TOPRGU_AUDIO_SW_RST>; + reset-names = "audiosys"; power-domains = <&scpsys MT8183_POWER_DOMAIN_AUDIO>; clocks = <&infrasys CLK_INFRA_AUDIO>, <&infrasys CLK_INFRA_AUDIO_26M_BCLK>, From patchwork Fri Sep 27 09:26:57 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: =?utf-8?b?SmlheGluIFl1ICjkv57lrrbpkasp?= X-Patchwork-Id: 11164197 Return-Path: Received: from mail.kernel.org (pdx-korg-mail-1.web.codeaurora.org [172.30.200.123]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id BE1E013B1 for ; Fri, 27 Sep 2019 09:29:52 +0000 (UTC) Received: from alsa0.perex.cz (alsa0.perex.cz [77.48.224.243]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id 520E5207E0 for ; Fri, 27 Sep 2019 09:29:52 +0000 (UTC) Authentication-Results: mail.kernel.org; dkim=pass (1024-bit key) header.d=alsa-project.org header.i=@alsa-project.org header.b="dOxB8rRS" DMARC-Filter: OpenDMARC Filter v1.3.2 mail.kernel.org 520E5207E0 Authentication-Results: mail.kernel.org; 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Fri, 27 Sep 2019 17:27:04 +0800 Received: from localhost.localdomain (10.17.3.153) by mtkcas09.mediatek.inc (172.21.101.73) with Microsoft SMTP Server id 15.0.1395.4 via Frontend Transport; Fri, 27 Sep 2019 17:27:03 +0800 From: Jiaxin Yu To: , , , , Date: Fri, 27 Sep 2019 17:26:57 +0800 Message-ID: <1569576417-20663-5-git-send-email-jiaxin.yu@mediatek.com> X-Mailer: git-send-email 1.8.1.1.dirty In-Reply-To: <1569576417-20663-1-git-send-email-jiaxin.yu@mediatek.com> References: <1569576417-20663-1-git-send-email-jiaxin.yu@mediatek.com> MIME-Version: 1.0 X-TM-SNTS-SMTP: 0E7DD3929E57BA9D199786983E2A5AA297FE759E5F051ADD3EC10F5F87E8286A2000:8 X-MTK: N Cc: alsa-devel@alsa-project.org, yong.liang@mediatek.com, lgirdwood@gmail.com, jiaxin.yu@mediatek.com, tzungbi@google.com, linux-mediatek@lists.infradead.org, eason.yen@mediatek.com, linux-arm-kernel@lists.infradead.org Subject: [alsa-devel] [PATCH 4/4] WIP: ASoC: mt8183: fix audio playback slowly after playback during bootup X-BeenThere: alsa-devel@alsa-project.org X-Mailman-Version: 2.1.15 Precedence: list List-Id: "Alsa-devel mailing list for ALSA developers - http://www.alsa-project.org" List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: alsa-devel-bounces@alsa-project.org Sender: "Alsa-devel" Before regmap_reinit_cache we must reset audio regs as default values. So we use reset controller unit(toprgu) to reset audio hw. Signed-off-by: Jiaxin Yu --- sound/soc/mediatek/mt8183/mt8183-afe-pcm.c | 15 +++++++++++++++ 1 file changed, 15 insertions(+) diff --git a/sound/soc/mediatek/mt8183/mt8183-afe-pcm.c b/sound/soc/mediatek/mt8183/mt8183-afe-pcm.c index 4a31106d3471..721632386a50 100644 --- a/sound/soc/mediatek/mt8183/mt8183-afe-pcm.c +++ b/sound/soc/mediatek/mt8183/mt8183-afe-pcm.c @@ -11,6 +11,7 @@ #include #include #include +#include #include "mt8183-afe-common.h" #include "mt8183-afe-clk.h" @@ -1089,6 +1090,7 @@ static int mt8183_afe_pcm_dev_probe(struct platform_device *pdev) struct mtk_base_afe *afe; struct mt8183_afe_private *afe_priv; struct device *dev; + struct reset_control *rstc; int i, irq_id, ret; afe = devm_kzalloc(&pdev->dev, sizeof(*afe), GFP_KERNEL); @@ -1126,6 +1128,19 @@ static int mt8183_afe_pcm_dev_probe(struct platform_device *pdev) return ret; } + rstc = devm_reset_control_get(dev, "audiosys"); + if (IS_ERR(rstc)) { + ret = PTR_ERR(rstc); + dev_err(dev, "could not get audiosys reset:%d\n", ret); + return ret; + } + + ret = reset_control_reset(rstc); + if (ret) { + dev_err(dev, "failed to trigger audio reset:%d\n", ret); + return ret; + } + /* enable clock for regcache get default value from hw */ afe_priv->pm_runtime_bypass_reg_ctl = true; pm_runtime_get_sync(&pdev->dev);