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[94.29.32.67]) by smtp.gmail.com with ESMTPSA id y3sm2355511lfh.97.2019.09.29.11.00.08 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sun, 29 Sep 2019 11:00:08 -0700 (PDT) From: Dmitry Osipenko To: Thierry Reding , Jonathan Hunter , Peter De Schrijver , "Rafael J. Wysocki" , Daniel Lezcano Cc: linux-pm@vger.kernel.org, linux-tegra@vger.kernel.org, linux-kernel@vger.kernel.org Subject: [PATCH v5 01/14] ARM: tegra: Remove cpuidle drivers to replace them with a new driver Date: Sun, 29 Sep 2019 20:59:39 +0300 Message-Id: <20190929175952.22690-2-digetx@gmail.com> X-Mailer: git-send-email 2.23.0 In-Reply-To: <20190929175952.22690-1-digetx@gmail.com> References: <20190929175952.22690-1-digetx@gmail.com> MIME-Version: 1.0 Sender: linux-pm-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-pm@vger.kernel.org Remove the old drivers to replace them cleanly with a new one later on. Please note that old Tegra20 CPUIDLE driver used pen-locking in order to block secondary CPU waking-up if IRQ happened to raise during of the entering into CC6 and primary CPU already crossed point of no return, but that is unnecessary in practice because CPUIDLE simply won't enter the coupled CC6 state if there is some CPU activity going on. The new driver will ensure that all secondary CPUs parked successfully at first and thus primary CPU won't be racing with the secondaries, hence the pen-locking functionality isn't needed anymore at all. This is the most notable thing of this patch. Signed-off-by: Dmitry Osipenko --- arch/arm/mach-tegra/Makefile | 13 -- arch/arm/mach-tegra/cpuidle-tegra114.c | 89 ----------- arch/arm/mach-tegra/cpuidle-tegra20.c | 212 ------------------------- arch/arm/mach-tegra/cpuidle-tegra30.c | 132 --------------- arch/arm/mach-tegra/cpuidle.c | 50 ------ arch/arm/mach-tegra/cpuidle.h | 21 --- arch/arm/mach-tegra/irq.c | 1 - arch/arm/mach-tegra/irq.h | 11 -- arch/arm/mach-tegra/pm.c | 7 - arch/arm/mach-tegra/pm.h | 1 - arch/arm/mach-tegra/reset-handler.S | 11 -- arch/arm/mach-tegra/reset.h | 9 +- arch/arm/mach-tegra/sleep-tegra20.S | 170 -------------------- arch/arm/mach-tegra/sleep.h | 12 -- arch/arm/mach-tegra/tegra.c | 3 - drivers/soc/tegra/Kconfig | 1 - include/soc/tegra/cpuidle.h | 4 - 17 files changed, 2 insertions(+), 745 deletions(-) delete mode 100644 arch/arm/mach-tegra/cpuidle-tegra114.c delete mode 100644 arch/arm/mach-tegra/cpuidle-tegra20.c delete mode 100644 arch/arm/mach-tegra/cpuidle-tegra30.c delete mode 100644 arch/arm/mach-tegra/cpuidle.c delete mode 100644 arch/arm/mach-tegra/cpuidle.h delete mode 100644 arch/arm/mach-tegra/irq.h diff --git a/arch/arm/mach-tegra/Makefile b/arch/arm/mach-tegra/Makefile index 6c1dff2eccc2..5d93a0b36866 100644 --- a/arch/arm/mach-tegra/Makefile +++ b/arch/arm/mach-tegra/Makefile @@ -8,29 +8,16 @@ obj-y += reset.o obj-y += reset-handler.o obj-y += sleep.o obj-y += tegra.o -obj-$(CONFIG_CPU_IDLE) += cpuidle.o obj-$(CONFIG_ARCH_TEGRA_2x_SOC) += sleep-tegra20.o obj-$(CONFIG_ARCH_TEGRA_2x_SOC) += pm-tegra20.o -ifeq ($(CONFIG_CPU_IDLE),y) -obj-$(CONFIG_ARCH_TEGRA_2x_SOC) += cpuidle-tegra20.o -endif obj-$(CONFIG_ARCH_TEGRA_3x_SOC) += sleep-tegra30.o obj-$(CONFIG_ARCH_TEGRA_3x_SOC) += pm-tegra30.o -ifeq ($(CONFIG_CPU_IDLE),y) -obj-$(CONFIG_ARCH_TEGRA_3x_SOC) += cpuidle-tegra30.o -endif obj-$(CONFIG_SMP) += platsmp.o obj-$(CONFIG_HOTPLUG_CPU) += hotplug.o obj-$(CONFIG_ARCH_TEGRA_114_SOC) += sleep-tegra30.o obj-$(CONFIG_ARCH_TEGRA_114_SOC) += pm-tegra30.o -ifeq ($(CONFIG_CPU_IDLE),y) -obj-$(CONFIG_ARCH_TEGRA_114_SOC) += cpuidle-tegra114.o -endif obj-$(CONFIG_ARCH_TEGRA_124_SOC) += sleep-tegra30.o obj-$(CONFIG_ARCH_TEGRA_124_SOC) += pm-tegra30.o -ifeq ($(CONFIG_CPU_IDLE),y) -obj-$(CONFIG_ARCH_TEGRA_124_SOC) += cpuidle-tegra114.o -endif obj-$(CONFIG_ARCH_TEGRA_2x_SOC) += board-paz00.o diff --git a/arch/arm/mach-tegra/cpuidle-tegra114.c b/arch/arm/mach-tegra/cpuidle-tegra114.c deleted file mode 100644 index 5118f777fd66..000000000000 --- a/arch/arm/mach-tegra/cpuidle-tegra114.c +++ /dev/null @@ -1,89 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0-only -/* - * Copyright (c) 2013, NVIDIA Corporation. All rights reserved. - */ - -#include -#include -#include -#include -#include -#include - -#include - -#include -#include -#include -#include - -#include "cpuidle.h" -#include "pm.h" -#include "sleep.h" - -#ifdef CONFIG_PM_SLEEP -#define TEGRA114_MAX_STATES 2 -#else -#define TEGRA114_MAX_STATES 1 -#endif - -#ifdef CONFIG_PM_SLEEP -static int tegra114_idle_power_down(struct cpuidle_device *dev, - struct cpuidle_driver *drv, - int index) -{ - local_fiq_disable(); - - tegra_set_cpu_in_lp2(); - cpu_pm_enter(); - - call_firmware_op(prepare_idle, TF_PM_MODE_LP2_NOFLUSH_L2); - - /* Do suspend by ourselves if the firmware does not implement it */ - if (call_firmware_op(do_idle, 0) == -ENOSYS) - cpu_suspend(0, tegra30_sleep_cpu_secondary_finish); - - cpu_pm_exit(); - tegra_clear_cpu_in_lp2(); - - local_fiq_enable(); - - return index; -} - -static void tegra114_idle_enter_s2idle(struct cpuidle_device *dev, - struct cpuidle_driver *drv, - int index) -{ - tegra114_idle_power_down(dev, drv, index); -} -#endif - -static struct cpuidle_driver tegra_idle_driver = { - .name = "tegra_idle", - .owner = THIS_MODULE, - .state_count = TEGRA114_MAX_STATES, - .states = { - [0] = ARM_CPUIDLE_WFI_STATE_PWR(600), -#ifdef CONFIG_PM_SLEEP - [1] = { - .enter = tegra114_idle_power_down, - .enter_s2idle = tegra114_idle_enter_s2idle, - .exit_latency = 500, - .target_residency = 1000, - .flags = CPUIDLE_FLAG_TIMER_STOP, - .power_usage = 0, - .name = "powered-down", - .desc = "CPU power gated", - }, -#endif - }, -}; - -int __init tegra114_cpuidle_init(void) -{ - if (!psci_smp_available()) - return cpuidle_register(&tegra_idle_driver, NULL); - - return 0; -} diff --git a/arch/arm/mach-tegra/cpuidle-tegra20.c b/arch/arm/mach-tegra/cpuidle-tegra20.c deleted file mode 100644 index 2447427cb4a8..000000000000 --- a/arch/arm/mach-tegra/cpuidle-tegra20.c +++ /dev/null @@ -1,212 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0-or-later -/* - * CPU idle driver for Tegra CPUs - * - * Copyright (c) 2010-2012, NVIDIA Corporation. - * Copyright (c) 2011 Google, Inc. - * Author: Colin Cross - * Gary King - * - * Rework for 3.3 by Peter De Schrijver - */ - -#include -#include -#include -#include -#include -#include - -#include - -#include -#include -#include - -#include "cpuidle.h" -#include "iomap.h" -#include "irq.h" -#include "pm.h" -#include "reset.h" -#include "sleep.h" - -#ifdef CONFIG_PM_SLEEP -static bool abort_flag; -static atomic_t abort_barrier; -static int tegra20_idle_lp2_coupled(struct cpuidle_device *dev, - struct cpuidle_driver *drv, - int index); -#define TEGRA20_MAX_STATES 2 -#else -#define TEGRA20_MAX_STATES 1 -#endif - -static struct cpuidle_driver tegra_idle_driver = { - .name = "tegra_idle", - .owner = THIS_MODULE, - .states = { - ARM_CPUIDLE_WFI_STATE_PWR(600), -#ifdef CONFIG_PM_SLEEP - { - .enter = tegra20_idle_lp2_coupled, - .exit_latency = 5000, - .target_residency = 10000, - .power_usage = 0, - .flags = CPUIDLE_FLAG_COUPLED | - CPUIDLE_FLAG_TIMER_STOP, - .name = "powered-down", - .desc = "CPU power gated", - }, -#endif - }, - .state_count = TEGRA20_MAX_STATES, - .safe_state_index = 0, -}; - -#ifdef CONFIG_PM_SLEEP -#ifdef CONFIG_SMP -static int tegra20_reset_sleeping_cpu_1(void) -{ - int ret = 0; - - tegra_pen_lock(); - - if (readb(tegra20_cpu1_resettable_status) == CPU_RESETTABLE) - tegra20_cpu_shutdown(1); - else - ret = -EINVAL; - - tegra_pen_unlock(); - - return ret; -} - -static void tegra20_wake_cpu1_from_reset(void) -{ - tegra_pen_lock(); - - tegra20_cpu_clear_resettable(); - - /* enable cpu clock on cpu */ - tegra_enable_cpu_clock(1); - - /* take the CPU out of reset */ - tegra_cpu_out_of_reset(1); - - /* unhalt the cpu */ - flowctrl_write_cpu_halt(1, 0); - - tegra_pen_unlock(); -} - -static int tegra20_reset_cpu_1(void) -{ - if (!cpu_online(1) || !tegra20_reset_sleeping_cpu_1()) - return 0; - - tegra20_wake_cpu1_from_reset(); - return -EBUSY; -} -#else -static inline void tegra20_wake_cpu1_from_reset(void) -{ -} - -static inline int tegra20_reset_cpu_1(void) -{ - return 0; -} -#endif - -static bool tegra20_cpu_cluster_power_down(struct cpuidle_device *dev, - struct cpuidle_driver *drv, - int index) -{ - while (tegra20_cpu_is_resettable_soon()) - cpu_relax(); - - if (tegra20_reset_cpu_1() || !tegra_cpu_rail_off_ready()) - return false; - - tegra_idle_lp2_last(); - - if (cpu_online(1)) - tegra20_wake_cpu1_from_reset(); - - return true; -} - -#ifdef CONFIG_SMP -static bool tegra20_idle_enter_lp2_cpu_1(struct cpuidle_device *dev, - struct cpuidle_driver *drv, - int index) -{ - cpu_suspend(0, tegra20_sleep_cpu_secondary_finish); - - tegra20_cpu_clear_resettable(); - - return true; -} -#else -static inline bool tegra20_idle_enter_lp2_cpu_1(struct cpuidle_device *dev, - struct cpuidle_driver *drv, - int index) -{ - return true; -} -#endif - -static int tegra20_idle_lp2_coupled(struct cpuidle_device *dev, - struct cpuidle_driver *drv, - int index) -{ - bool entered_lp2 = false; - - if (tegra_pending_sgi()) - WRITE_ONCE(abort_flag, true); - - cpuidle_coupled_parallel_barrier(dev, &abort_barrier); - - if (abort_flag) { - cpuidle_coupled_parallel_barrier(dev, &abort_barrier); - abort_flag = false; /* clean flag for next coming */ - return -EINTR; - } - - local_fiq_disable(); - - tegra_set_cpu_in_lp2(); - cpu_pm_enter(); - - if (dev->cpu == 0) - entered_lp2 = tegra20_cpu_cluster_power_down(dev, drv, index); - else - entered_lp2 = tegra20_idle_enter_lp2_cpu_1(dev, drv, index); - - cpu_pm_exit(); - tegra_clear_cpu_in_lp2(); - - local_fiq_enable(); - - smp_rmb(); - - return entered_lp2 ? index : 0; -} -#endif - -/* - * Tegra20 HW appears to have a bug such that PCIe device interrupts, whether - * they are legacy IRQs or MSI, are lost when LP2 is enabled. To work around - * this, simply disable LP2 if the PCI driver and DT node are both enabled. - */ -void tegra20_cpuidle_pcie_irqs_in_use(void) -{ - pr_info_once( - "Disabling cpuidle LP2 state, since PCIe IRQs are in use\n"); - tegra_idle_driver.states[1].disabled = true; -} - -int __init tegra20_cpuidle_init(void) -{ - return cpuidle_register(&tegra_idle_driver, cpu_possible_mask); -} diff --git a/arch/arm/mach-tegra/cpuidle-tegra30.c b/arch/arm/mach-tegra/cpuidle-tegra30.c deleted file mode 100644 index c6128526877d..000000000000 --- a/arch/arm/mach-tegra/cpuidle-tegra30.c +++ /dev/null @@ -1,132 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0-or-later -/* - * CPU idle driver for Tegra CPUs - * - * Copyright (c) 2010-2012, NVIDIA Corporation. - * Copyright (c) 2011 Google, Inc. - * Author: Colin Cross - * Gary King - * - * Rework for 3.3 by Peter De Schrijver - */ - -#include -#include -#include -#include -#include -#include - -#include -#include -#include - -#include "cpuidle.h" -#include "pm.h" -#include "sleep.h" - -#ifdef CONFIG_PM_SLEEP -static int tegra30_idle_lp2(struct cpuidle_device *dev, - struct cpuidle_driver *drv, - int index); -#endif - -static struct cpuidle_driver tegra_idle_driver = { - .name = "tegra_idle", - .owner = THIS_MODULE, -#ifdef CONFIG_PM_SLEEP - .state_count = 2, -#else - .state_count = 1, -#endif - .states = { - [0] = ARM_CPUIDLE_WFI_STATE_PWR(600), -#ifdef CONFIG_PM_SLEEP - [1] = { - .enter = tegra30_idle_lp2, - .exit_latency = 2000, - .target_residency = 2200, - .power_usage = 0, - .flags = CPUIDLE_FLAG_TIMER_STOP, - .name = "powered-down", - .desc = "CPU power gated", - }, -#endif - }, -}; - -#ifdef CONFIG_PM_SLEEP -static bool tegra30_cpu_cluster_power_down(struct cpuidle_device *dev, - struct cpuidle_driver *drv, - int index) -{ - /* All CPUs entering LP2 is not working. - * Don't let CPU0 enter LP2 when any secondary CPU is online. - */ - if (num_online_cpus() > 1 || !tegra_cpu_rail_off_ready()) { - cpu_do_idle(); - return false; - } - - tegra_idle_lp2_last(); - - return true; -} - -#ifdef CONFIG_SMP -static bool tegra30_cpu_core_power_down(struct cpuidle_device *dev, - struct cpuidle_driver *drv, - int index) -{ - smp_wmb(); - - cpu_suspend(0, tegra30_sleep_cpu_secondary_finish); - - return true; -} -#else -static inline bool tegra30_cpu_core_power_down(struct cpuidle_device *dev, - struct cpuidle_driver *drv, - int index) -{ - return true; -} -#endif - -static int tegra30_idle_lp2(struct cpuidle_device *dev, - struct cpuidle_driver *drv, - int index) -{ - bool entered_lp2 = false; - bool last_cpu; - - local_fiq_disable(); - - last_cpu = tegra_set_cpu_in_lp2(); - cpu_pm_enter(); - - if (dev->cpu == 0) { - if (last_cpu) - entered_lp2 = tegra30_cpu_cluster_power_down(dev, drv, - index); - else - cpu_do_idle(); - } else { - entered_lp2 = tegra30_cpu_core_power_down(dev, drv, index); - } - - cpu_pm_exit(); - tegra_clear_cpu_in_lp2(); - - local_fiq_enable(); - - smp_rmb(); - - return (entered_lp2) ? index : 0; -} -#endif - -int __init tegra30_cpuidle_init(void) -{ - return cpuidle_register(&tegra_idle_driver, NULL); -} diff --git a/arch/arm/mach-tegra/cpuidle.c b/arch/arm/mach-tegra/cpuidle.c deleted file mode 100644 index d565c44cfc93..000000000000 --- a/arch/arm/mach-tegra/cpuidle.c +++ /dev/null @@ -1,50 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0-or-later -/* - * arch/arm/mach-tegra/cpuidle.c - * - * CPU idle driver for Tegra CPUs - * - * Copyright (c) 2010-2012, NVIDIA Corporation. - * Copyright (c) 2011 Google, Inc. - * Author: Colin Cross - * Gary King - * - * Rework for 3.3 by Peter De Schrijver - */ - -#include -#include - -#include - -#include "cpuidle.h" - -void __init tegra_cpuidle_init(void) -{ - switch (tegra_get_chip_id()) { - case TEGRA20: - if (IS_ENABLED(CONFIG_ARCH_TEGRA_2x_SOC)) - tegra20_cpuidle_init(); - break; - case TEGRA30: - if (IS_ENABLED(CONFIG_ARCH_TEGRA_3x_SOC)) - tegra30_cpuidle_init(); - break; - case TEGRA114: - case TEGRA124: - if (IS_ENABLED(CONFIG_ARCH_TEGRA_114_SOC) || - IS_ENABLED(CONFIG_ARCH_TEGRA_124_SOC)) - tegra114_cpuidle_init(); - break; - } -} - -void tegra_cpuidle_pcie_irqs_in_use(void) -{ - switch (tegra_get_chip_id()) { - case TEGRA20: - if (IS_ENABLED(CONFIG_ARCH_TEGRA_2x_SOC)) - tegra20_cpuidle_pcie_irqs_in_use(); - break; - } -} diff --git a/arch/arm/mach-tegra/cpuidle.h b/arch/arm/mach-tegra/cpuidle.h deleted file mode 100644 index 4e1f459f5bd8..000000000000 --- a/arch/arm/mach-tegra/cpuidle.h +++ /dev/null @@ -1,21 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0-only */ -/* - * Copyright (c) 2012, NVIDIA Corporation. All rights reserved. - */ - -#ifndef __MACH_TEGRA_CPUIDLE_H -#define __MACH_TEGRA_CPUIDLE_H - -#ifdef CONFIG_CPU_IDLE -int tegra20_cpuidle_init(void); -void tegra20_cpuidle_pcie_irqs_in_use(void); -int tegra30_cpuidle_init(void); -int tegra114_cpuidle_init(void); -void tegra_cpuidle_init(void); -void tegra_cpuidle_pcie_irqs_in_use(void); -#else -static inline void tegra_cpuidle_init(void) {} -static inline void tegra_cpuidle_pcie_irqs_in_use(void) {} -#endif - -#endif diff --git a/arch/arm/mach-tegra/irq.c b/arch/arm/mach-tegra/irq.c index ace7a390b5fe..4c065b54cbe7 100644 --- a/arch/arm/mach-tegra/irq.c +++ b/arch/arm/mach-tegra/irq.c @@ -20,7 +20,6 @@ #include "board.h" #include "iomap.h" -#include "irq.h" #define SGI_MASK 0xFFFF diff --git a/arch/arm/mach-tegra/irq.h b/arch/arm/mach-tegra/irq.h deleted file mode 100644 index 7a94cf121448..000000000000 --- a/arch/arm/mach-tegra/irq.h +++ /dev/null @@ -1,11 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0-only */ -/* - * Copyright (c) 2012, NVIDIA Corporation. All rights reserved. - */ - -#ifndef __TEGRA_IRQ_H -#define __TEGRA_IRQ_H - -bool tegra_pending_sgi(void); - -#endif diff --git a/arch/arm/mach-tegra/pm.c b/arch/arm/mach-tegra/pm.c index 3cab81b82866..6aaacb5757e1 100644 --- a/arch/arm/mach-tegra/pm.c +++ b/arch/arm/mach-tegra/pm.c @@ -137,18 +137,11 @@ bool tegra_set_cpu_in_lp2(void) if ((phy_cpu_id == 0) && cpumask_equal(cpu_lp2_mask, cpu_online_mask)) last_cpu = true; - else if (tegra_get_chip_id() == TEGRA20 && phy_cpu_id == 1) - tegra20_cpu_set_resettable_soon(); spin_unlock(&tegra_lp2_lock); return last_cpu; } -int tegra_cpu_do_idle(void) -{ - return cpu_do_idle(); -} - static int tegra_sleep_cpu(unsigned long v2p) { /* diff --git a/arch/arm/mach-tegra/pm.h b/arch/arm/mach-tegra/pm.h index 569151b3edc0..1e51a9b636eb 100644 --- a/arch/arm/mach-tegra/pm.h +++ b/arch/arm/mach-tegra/pm.h @@ -25,7 +25,6 @@ void tegra30_sleep_core_init(void); void tegra_clear_cpu_in_lp2(void); bool tegra_set_cpu_in_lp2(void); -int tegra_cpu_do_idle(void); void tegra_idle_lp2_last(void); extern void (*tegra_tear_down_cpu)(void); diff --git a/arch/arm/mach-tegra/reset-handler.S b/arch/arm/mach-tegra/reset-handler.S index 67b763fea005..df44828a34d3 100644 --- a/arch/arm/mach-tegra/reset-handler.S +++ b/arch/arm/mach-tegra/reset-handler.S @@ -183,17 +183,6 @@ after_errata: bleq __die @ CPU not present (to OS) #endif -#ifdef CONFIG_ARCH_TEGRA_2x_SOC - /* Are we on Tegra20? */ - cmp r6, #TEGRA20 - bne 1f - /* If not CPU0, don't let CPU0 reset CPU1 now that CPU1 is coming up. */ - mov r0, #CPU_NOT_RESETTABLE - cmp r10, #0 - strbne r0, [r12, #RESET_DATA(RESETTABLE_STATUS)] -1: -#endif - /* Waking up from LP1? */ ldr r8, [r12, #RESET_DATA(MASK_LP1)] tst r8, r11 @ if in_lp1 diff --git a/arch/arm/mach-tegra/reset.h b/arch/arm/mach-tegra/reset.h index a4cfc08159f6..51265592cb1a 100644 --- a/arch/arm/mach-tegra/reset.h +++ b/arch/arm/mach-tegra/reset.h @@ -16,9 +16,8 @@ #define TEGRA_RESET_STARTUP_SECONDARY 3 #define TEGRA_RESET_STARTUP_LP2 4 #define TEGRA_RESET_STARTUP_LP1 5 -#define TEGRA_RESET_RESETTABLE_STATUS 6 -#define TEGRA_RESET_TF_PRESENT 7 -#define TEGRA_RESET_DATA_SIZE 8 +#define TEGRA_RESET_TF_PRESENT 6 +#define TEGRA_RESET_DATA_SIZE 7 #define RESET_DATA(x) ((TEGRA_RESET_##x)*4) @@ -42,10 +41,6 @@ void __tegra_cpu_reset_handler_end(void); (IO_ADDRESS(TEGRA_IRAM_BASE + TEGRA_IRAM_RESET_HANDLER_OFFSET + \ ((u32)&__tegra_cpu_reset_handler_data[TEGRA_RESET_MASK_LP2] - \ (u32)__tegra_cpu_reset_handler_start))) -#define tegra20_cpu1_resettable_status \ - (IO_ADDRESS(TEGRA_IRAM_BASE + TEGRA_IRAM_RESET_HANDLER_OFFSET + \ - ((u32)&__tegra_cpu_reset_handler_data[TEGRA_RESET_RESETTABLE_STATUS] - \ - (u32)__tegra_cpu_reset_handler_start))) #endif #define tegra_cpu_reset_handler_offset \ diff --git a/arch/arm/mach-tegra/sleep-tegra20.S b/arch/arm/mach-tegra/sleep-tegra20.S index 9a89f30d53ca..0e00ba8cf646 100644 --- a/arch/arm/mach-tegra/sleep-tegra20.S +++ b/arch/arm/mach-tegra/sleep-tegra20.S @@ -43,9 +43,6 @@ #define APB_MISC_XM2CFGCPADCTRL2 0x8e4 #define APB_MISC_XM2CFGDPADCTRL2 0x8e8 -#define __tegra20_cpu1_resettable_status_offset \ - (__tegra_cpu_reset_handler_data_offset + RESET_DATA(RESETTABLE_STATUS)) - .macro pll_enable, rd, r_car_base, pll_base ldr \rd, [\r_car_base, #\pll_base] tst \rd, #(1 << 30) @@ -90,10 +87,6 @@ ENDPROC(tegra20_hotplug_shutdown) ENTRY(tegra20_cpu_shutdown) cmp r0, #0 reteq lr @ must not be called for CPU 0 - mov32 r1, TEGRA_IRAM_RESET_BASE_VIRT - ldr r2, =__tegra20_cpu1_resettable_status_offset - mov r12, #CPU_RESETTABLE - strb r12, [r1, r2] cpu_to_halt_reg r1, r0 ldr r3, =TEGRA_FLOW_CTRL_VIRT @@ -116,107 +109,6 @@ ENDPROC(tegra20_cpu_shutdown) #endif #ifdef CONFIG_PM_SLEEP -/* - * tegra_pen_lock - * - * spinlock implementation with no atomic test-and-set and no coherence - * using Peterson's algorithm on strongly-ordered registers - * used to synchronize a cpu waking up from wfi with entering lp2 on idle - * - * The reference link of Peterson's algorithm: - * http://en.wikipedia.org/wiki/Peterson's_algorithm - * - * SCRATCH37 = r1 = !turn (inverted from Peterson's algorithm) - * on cpu 0: - * r2 = flag[0] (in SCRATCH38) - * r3 = flag[1] (in SCRATCH39) - * on cpu1: - * r2 = flag[1] (in SCRATCH39) - * r3 = flag[0] (in SCRATCH38) - * - * must be called with MMU on - * corrupts r0-r3, r12 - */ -ENTRY(tegra_pen_lock) - mov32 r3, TEGRA_PMC_VIRT - cpu_id r0 - add r1, r3, #PMC_SCRATCH37 - cmp r0, #0 - addeq r2, r3, #PMC_SCRATCH38 - addeq r3, r3, #PMC_SCRATCH39 - addne r2, r3, #PMC_SCRATCH39 - addne r3, r3, #PMC_SCRATCH38 - - mov r12, #1 - str r12, [r2] @ flag[cpu] = 1 - dsb - str r12, [r1] @ !turn = cpu -1: dsb - ldr r12, [r3] - cmp r12, #1 @ flag[!cpu] == 1? - ldreq r12, [r1] - cmpeq r12, r0 @ !turn == cpu? - beq 1b @ while !turn == cpu && flag[!cpu] == 1 - - ret lr @ locked -ENDPROC(tegra_pen_lock) - -ENTRY(tegra_pen_unlock) - dsb - mov32 r3, TEGRA_PMC_VIRT - cpu_id r0 - cmp r0, #0 - addeq r2, r3, #PMC_SCRATCH38 - addne r2, r3, #PMC_SCRATCH39 - mov r12, #0 - str r12, [r2] - ret lr -ENDPROC(tegra_pen_unlock) - -/* - * tegra20_cpu_clear_resettable(void) - * - * Called to clear the "resettable soon" flag in IRAM variable when - * it is expected that the secondary CPU will be idle soon. - */ -ENTRY(tegra20_cpu_clear_resettable) - mov32 r1, TEGRA_IRAM_RESET_BASE_VIRT - ldr r2, =__tegra20_cpu1_resettable_status_offset - mov r12, #CPU_NOT_RESETTABLE - strb r12, [r1, r2] - ret lr -ENDPROC(tegra20_cpu_clear_resettable) - -/* - * tegra20_cpu_set_resettable_soon(void) - * - * Called to set the "resettable soon" flag in IRAM variable when - * it is expected that the secondary CPU will be idle soon. - */ -ENTRY(tegra20_cpu_set_resettable_soon) - mov32 r1, TEGRA_IRAM_RESET_BASE_VIRT - ldr r2, =__tegra20_cpu1_resettable_status_offset - mov r12, #CPU_RESETTABLE_SOON - strb r12, [r1, r2] - ret lr -ENDPROC(tegra20_cpu_set_resettable_soon) - -/* - * tegra20_cpu_is_resettable_soon(void) - * - * Returns true if the "resettable soon" flag in IRAM variable has been - * set because it is expected that the secondary CPU will be idle soon. - */ -ENTRY(tegra20_cpu_is_resettable_soon) - mov32 r1, TEGRA_IRAM_RESET_BASE_VIRT - ldr r2, =__tegra20_cpu1_resettable_status_offset - ldrb r12, [r1, r2] - cmp r12, #CPU_RESETTABLE_SOON - moveq r0, #1 - movne r0, #0 - ret lr -ENDPROC(tegra20_cpu_is_resettable_soon) - /* * tegra20_sleep_core_finish(unsigned long v2p) * @@ -242,68 +134,6 @@ ENTRY(tegra20_sleep_core_finish) ret r3 ENDPROC(tegra20_sleep_core_finish) -/* - * tegra20_sleep_cpu_secondary_finish(unsigned long v2p) - * - * Enters WFI on secondary CPU by exiting coherency. - */ -ENTRY(tegra20_sleep_cpu_secondary_finish) - stmfd sp!, {r4-r11, lr} - - mrc p15, 0, r11, c1, c0, 1 @ save actlr before exiting coherency - - /* Flush and disable the L1 data cache */ - mov r0, #TEGRA_FLUSH_CACHE_LOUIS - bl tegra_disable_clean_inv_dcache - - mov32 r0, TEGRA_IRAM_RESET_BASE_VIRT - ldr r4, =__tegra20_cpu1_resettable_status_offset - mov r3, #CPU_RESETTABLE - strb r3, [r0, r4] - - bl tegra_cpu_do_idle - - /* - * cpu may be reset while in wfi, which will return through - * tegra_resume to cpu_resume - * or interrupt may wake wfi, which will return here - * cpu state is unchanged - MMU is on, cache is on, coherency - * is off, and the data cache is off - * - * r11 contains the original actlr - */ - - bl tegra_pen_lock - - mov32 r0, TEGRA_IRAM_RESET_BASE_VIRT - ldr r4, =__tegra20_cpu1_resettable_status_offset - mov r3, #CPU_NOT_RESETTABLE - strb r3, [r0, r4] - - bl tegra_pen_unlock - - /* Re-enable the data cache */ - mrc p15, 0, r10, c1, c0, 0 - orr r10, r10, #CR_C - mcr p15, 0, r10, c1, c0, 0 - isb - - mcr p15, 0, r11, c1, c0, 1 @ reenable coherency - - /* Invalidate the TLBs & BTAC */ - mov r1, #0 - mcr p15, 0, r1, c8, c3, 0 @ invalidate shared TLBs - mcr p15, 0, r1, c7, c1, 6 @ invalidate shared BTAC - dsb - isb - - /* the cpu was running with coherency disabled, - * caches may be out of date */ - bl v7_flush_kern_cache_louis - - ldmfd sp!, {r4 - r11, pc} -ENDPROC(tegra20_sleep_cpu_secondary_finish) - /* * tegra20_tear_down_cpu * diff --git a/arch/arm/mach-tegra/sleep.h b/arch/arm/mach-tegra/sleep.h index 78ef32a907c8..d219872b7546 100644 --- a/arch/arm/mach-tegra/sleep.h +++ b/arch/arm/mach-tegra/sleep.h @@ -114,8 +114,6 @@ .endm #else -void tegra_pen_lock(void); -void tegra_pen_unlock(void); void tegra_resume(void); int tegra_sleep_cpu_finish(unsigned long); void tegra_disable_clean_inv_dcache(u32 flag); @@ -125,16 +123,6 @@ void tegra20_hotplug_shutdown(void); void tegra30_hotplug_shutdown(void); #endif -void tegra20_cpu_shutdown(int cpu); -int tegra20_cpu_is_resettable_soon(void); -void tegra20_cpu_clear_resettable(void); -#ifdef CONFIG_ARCH_TEGRA_2x_SOC -void tegra20_cpu_set_resettable_soon(void); -#else -static inline void tegra20_cpu_set_resettable_soon(void) {} -#endif - -int tegra20_sleep_cpu_secondary_finish(unsigned long); void tegra20_tear_down_cpu(void); int tegra30_sleep_cpu_secondary_finish(unsigned long); void tegra30_tear_down_cpu(void); diff --git a/arch/arm/mach-tegra/tegra.c b/arch/arm/mach-tegra/tegra.c index e512e606eabd..d9237769a37c 100644 --- a/arch/arm/mach-tegra/tegra.c +++ b/arch/arm/mach-tegra/tegra.c @@ -40,9 +40,7 @@ #include "board.h" #include "common.h" -#include "cpuidle.h" #include "iomap.h" -#include "irq.h" #include "pm.h" #include "reset.h" #include "sleep.h" @@ -86,7 +84,6 @@ static void __init tegra_dt_init(void) static void __init tegra_dt_init_late(void) { tegra_init_suspend(); - tegra_cpuidle_init(); if (IS_ENABLED(CONFIG_ARCH_TEGRA_2x_SOC) && of_machine_is_compatible("compal,paz00")) diff --git a/drivers/soc/tegra/Kconfig b/drivers/soc/tegra/Kconfig index c8ef05d6b8c7..d98c69efb7e0 100644 --- a/drivers/soc/tegra/Kconfig +++ b/drivers/soc/tegra/Kconfig @@ -6,7 +6,6 @@ if ARM config ARCH_TEGRA_2x_SOC bool "Enable support for Tegra20 family" - select ARCH_NEEDS_CPU_IDLE_COUPLED if SMP select ARM_ERRATA_720789 select ARM_ERRATA_754327 if SMP select ARM_ERRATA_764369 if SMP diff --git a/include/soc/tegra/cpuidle.h b/include/soc/tegra/cpuidle.h index 029ba1f4b2cc..f758808342b6 100644 --- a/include/soc/tegra/cpuidle.h +++ b/include/soc/tegra/cpuidle.h @@ -6,12 +6,8 @@ #ifndef __SOC_TEGRA_CPUIDLE_H__ #define __SOC_TEGRA_CPUIDLE_H__ -#if defined(CONFIG_ARM) && defined(CONFIG_ARCH_TEGRA) && defined(CONFIG_CPU_IDLE) -void tegra_cpuidle_pcie_irqs_in_use(void); -#else static inline void tegra_cpuidle_pcie_irqs_in_use(void) { } -#endif #endif /* __SOC_TEGRA_CPUIDLE_H__ */ From patchwork Sun Sep 29 17:59:40 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Dmitry Osipenko X-Patchwork-Id: 11165843 Return-Path: Received: from mail.kernel.org (pdx-korg-mail-1.web.codeaurora.org [172.30.200.123]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id C253E14DB for ; Sun, 29 Sep 2019 18:00:57 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.kernel.org (Postfix) with ESMTP id 9EBE9217F5 for ; Sun, 29 Sep 2019 18:00:57 +0000 (UTC) Authentication-Results: mail.kernel.org; dkim=pass (2048-bit key) header.d=gmail.com header.i=@gmail.com header.b="fc9pCJf1" Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1729022AbfI2SAO (ORCPT ); Sun, 29 Sep 2019 14:00:14 -0400 Received: from mail-lf1-f66.google.com ([209.85.167.66]:33197 "EHLO mail-lf1-f66.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1728853AbfI2SAN (ORCPT ); Sun, 29 Sep 2019 14:00:13 -0400 Received: by mail-lf1-f66.google.com with SMTP id y127so5341755lfc.0; Sun, 29 Sep 2019 11:00:10 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=CVJwFVXBEAamYflB/lqjMOTdbTS2JG3wi6554M0zQk0=; b=fc9pCJf1wEZb2IiwTfJqDvGJslAM/3KX+YORlFOJ4RoPfg8lnCQQhQncL+yxB93Nk3 A4b050AcFCnFO3NPGKG3lAossJ7rubPJ8xXkiKETTwuHxlm/K8B3j/FrqXf9/y/rkd3S ob+QPb7TiKxdUW5rbmz0ZDeptar8Ui9sCjWX8N+0CFaxL7GKNcXPFY2pL+cjwTbG8LPP TJivu5uxIA9N6rJX11GaIALCGfvWWag7mKy03NYEUvk0iqbBkr+kEGmK6JuruiGAXpyd UL3zAqyvsmp8/jjvw7t7j8Sx/j78p7pLUIC39TiinbTo+k+BPSVPd0kRXTF8iwHZonym lniw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=CVJwFVXBEAamYflB/lqjMOTdbTS2JG3wi6554M0zQk0=; b=hfWWVt5vdDByU0+ziZmg5MmdhS61KTTX85Mx2ET3Me0JG8+x22cbvfpxLBvpVaxSaX CckkWYlUtzV+GaxGPpch8+ZZyUE5rQY2F/TWM12B1sJ/GzhgfOS51gwpmFBpmcTufEK6 n1AwtbNaiQlU2/TmN+INLaHyVM8csqnkFpYijyMSALZ2AwrdsNZGAuhtSCRTVMXpiVde oyn6E31anvx9fvI77wCteyu1oEj2J1wJ+G0BSh7TxSwnPXFbRtiOWMDCk/DuXP0vkEMN HYzUjFWSTmGIUyABDlsWork116PH0wmHBNuksAnhv+ij3NCmHUW3lCJN0PjmOqlUTc+q V3Ow== X-Gm-Message-State: APjAAAXXQwojfxXISVAloZAovLk3MXy5VgkQkt4/u41SoHFy2Yf/nA/d XnpNbBeaWW4pC/SNDygWUpA= X-Google-Smtp-Source: APXvYqxnwOm5TCNZ89b8v1Ub0XR4vpc7n9sIBi/JAh8ggLML2WhYRhB8OXhaweZ96nXX9fAkD9kTxg== X-Received: by 2002:a19:98e:: with SMTP id 136mr9147200lfj.156.1569780010172; Sun, 29 Sep 2019 11:00:10 -0700 (PDT) Received: from localhost.localdomain (ppp94-29-32-67.pppoe.spdop.ru. [94.29.32.67]) by smtp.gmail.com with ESMTPSA id y3sm2355511lfh.97.2019.09.29.11.00.09 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sun, 29 Sep 2019 11:00:09 -0700 (PDT) From: Dmitry Osipenko To: Thierry Reding , Jonathan Hunter , Peter De Schrijver , "Rafael J. Wysocki" , Daniel Lezcano Cc: linux-pm@vger.kernel.org, linux-tegra@vger.kernel.org, linux-kernel@vger.kernel.org Subject: [PATCH v5 02/14] ARM: tegra: Change tegra_set_cpu_in_lp2() type to void Date: Sun, 29 Sep 2019 20:59:40 +0300 Message-Id: <20190929175952.22690-3-digetx@gmail.com> X-Mailer: git-send-email 2.23.0 In-Reply-To: <20190929175952.22690-1-digetx@gmail.com> References: <20190929175952.22690-1-digetx@gmail.com> MIME-Version: 1.0 Sender: linux-pm-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-pm@vger.kernel.org The old Tegra30 CPUIDLE driver had intention to check whether primary CPU was the last CPU that entered LP2 (CC6) idle-state, but that functionality never got utilized by the old-removed driver because it never supported the CC6 while secondary CPUs were online. The new driver will properly support CC6 on Tegra30, including the case where secondary CPUs are online, and that knowledge about what CPUs entered CC6 won't be needed at all because new driver will use different approach by making use of the coupled idle-state and explicitly parking secondary CPUs before entering into CC6. Signed-off-by: Dmitry Osipenko --- arch/arm/mach-tegra/pm.c | 8 +------- arch/arm/mach-tegra/pm.h | 2 +- 2 files changed, 2 insertions(+), 8 deletions(-) diff --git a/arch/arm/mach-tegra/pm.c b/arch/arm/mach-tegra/pm.c index 6aaacb5757e1..2f6fb54be9f8 100644 --- a/arch/arm/mach-tegra/pm.c +++ b/arch/arm/mach-tegra/pm.c @@ -123,11 +123,9 @@ void tegra_clear_cpu_in_lp2(void) spin_unlock(&tegra_lp2_lock); } -bool tegra_set_cpu_in_lp2(void) +void tegra_set_cpu_in_lp2(void) { int phy_cpu_id = cpu_logical_map(smp_processor_id()); - bool last_cpu = false; - cpumask_t *cpu_lp2_mask = tegra_cpu_lp2_mask; u32 *cpu_in_lp2 = tegra_cpu_lp2_mask; spin_lock(&tegra_lp2_lock); @@ -135,11 +133,7 @@ bool tegra_set_cpu_in_lp2(void) BUG_ON((*cpu_in_lp2 & BIT(phy_cpu_id))); *cpu_in_lp2 |= BIT(phy_cpu_id); - if ((phy_cpu_id == 0) && cpumask_equal(cpu_lp2_mask, cpu_online_mask)) - last_cpu = true; - spin_unlock(&tegra_lp2_lock); - return last_cpu; } static int tegra_sleep_cpu(unsigned long v2p) diff --git a/arch/arm/mach-tegra/pm.h b/arch/arm/mach-tegra/pm.h index 1e51a9b636eb..3f3164ad04b7 100644 --- a/arch/arm/mach-tegra/pm.h +++ b/arch/arm/mach-tegra/pm.h @@ -24,7 +24,7 @@ void tegra30_lp1_iram_hook(void); void tegra30_sleep_core_init(void); void tegra_clear_cpu_in_lp2(void); -bool tegra_set_cpu_in_lp2(void); +void tegra_set_cpu_in_lp2(void); void tegra_idle_lp2_last(void); extern void (*tegra_tear_down_cpu)(void); From patchwork Sun Sep 29 17:59:41 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Dmitry Osipenko X-Patchwork-Id: 11165849 Return-Path: Received: from mail.kernel.org (pdx-korg-mail-1.web.codeaurora.org [172.30.200.123]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id 98CA3112B for ; Sun, 29 Sep 2019 18:01:13 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.kernel.org (Postfix) with ESMTP id 7787421A4C for ; Sun, 29 Sep 2019 18:01:13 +0000 (UTC) Authentication-Results: mail.kernel.org; dkim=pass (2048-bit key) header.d=gmail.com header.i=@gmail.com header.b="jEkRti53" Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1729213AbfI2SAN (ORCPT ); Sun, 29 Sep 2019 14:00:13 -0400 Received: from mail-lj1-f193.google.com ([209.85.208.193]:33794 "EHLO mail-lj1-f193.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1729022AbfI2SAN (ORCPT ); Sun, 29 Sep 2019 14:00:13 -0400 Received: by mail-lj1-f193.google.com with SMTP id j19so7125096lja.1; Sun, 29 Sep 2019 11:00:11 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=hb10u+5FTmJk4Ov2bvkx+DvcjkejWf8nRCYDqHfhxFs=; b=jEkRti53uzQ/wwAgHw3isn/r1DUVfAcnhnVf+caN1qoNtV8C2z0dc07uMUxWpc3qXQ LV87UD9YX/htWOt6ZnjjuNYxKsvlybnvbkcZcteDQ2iBbe8oi9ySqn24IxT+MiUxOAyj d9s7o9O+Mt/Pz/2gTgihD16xYGMFFvJyno8MJ6+srEiY7OyxVrF2SIy5QA9HPzOTMUgZ 7JFJ/8EclvgokkLb2wmDkNKVI+RfSsnYBXoCDwv/q6k7I9cqPMbHne5XVKpjs1AD8uz2 myZ+I+rCV8Sxnev1sQErd3MGEjDnvlUjpLgsTDV967JVmeTuobCkUugo/TS+Eo6cjwgo zDvg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=hb10u+5FTmJk4Ov2bvkx+DvcjkejWf8nRCYDqHfhxFs=; b=J+SolWxgZzJN3e7JQTsduWXWWLO/FPJPhectAT1mCRiYAGphACrQH0RT20XeLGYw4v rfZzfENXh7mfAK/gLwyX+19f9uMfPk4ZUcHbZ+ZsSMJIHON0aL/1z5sjXrbBadpnUlVH QqGug6IJS+wfBybX2k3ZlLhYeIJyNRTVpeP/6RmGylf5eSNv40tiDRS4p1c6P0YLXWkx oVOR0M5tHcLt2UP8AEbePitlPs4oDEzlyyh2/T3jyjmWCjtbcbyxsIsbufopWoNbqgJQ L6uBc1bsD/MIOzYkJdXaRS80kPcuzkKUuYVKGkwL0TDsLhPhC+z7Yci9axdHzAKZDb2b APqg== X-Gm-Message-State: APjAAAUSFxQFopyhZRf3VCEaMfyay6ShEzGKVWIJPIN7DXAKcsl87dOW TwRFyac+m73CtxIq81Fd4UPfPTYn X-Google-Smtp-Source: APXvYqymnfaHb1KTiEwwOGyKrX3EBgNSg9249nqO2pYjwowQ5RKJ4/YQ1pghOnwwn9JKfAheibJdpA== X-Received: by 2002:a2e:9a83:: with SMTP id p3mr9684509lji.136.1569780011032; Sun, 29 Sep 2019 11:00:11 -0700 (PDT) Received: from localhost.localdomain (ppp94-29-32-67.pppoe.spdop.ru. [94.29.32.67]) by smtp.gmail.com with ESMTPSA id y3sm2355511lfh.97.2019.09.29.11.00.10 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sun, 29 Sep 2019 11:00:10 -0700 (PDT) From: Dmitry Osipenko To: Thierry Reding , Jonathan Hunter , Peter De Schrijver , "Rafael J. Wysocki" , Daniel Lezcano Cc: linux-pm@vger.kernel.org, linux-tegra@vger.kernel.org, linux-kernel@vger.kernel.org Subject: [PATCH v5 03/14] ARM: tegra: Propagate error from tegra_idle_lp2_last() Date: Sun, 29 Sep 2019 20:59:41 +0300 Message-Id: <20190929175952.22690-4-digetx@gmail.com> X-Mailer: git-send-email 2.23.0 In-Reply-To: <20190929175952.22690-1-digetx@gmail.com> References: <20190929175952.22690-1-digetx@gmail.com> MIME-Version: 1.0 Sender: linux-pm-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-pm@vger.kernel.org The cpu_suspend() may fail, it's never good to lose information about failure because it may become very useful for the caller. The new CPUIDLE driver will handle all of possible error cases, including the case of tegra_idle_lp2_last() failure. Signed-off-by: Dmitry Osipenko --- arch/arm/mach-tegra/pm.c | 8 ++++++-- arch/arm/mach-tegra/pm.h | 2 +- 2 files changed, 7 insertions(+), 3 deletions(-) diff --git a/arch/arm/mach-tegra/pm.c b/arch/arm/mach-tegra/pm.c index 2f6fb54be9f8..f9c9bce9e15d 100644 --- a/arch/arm/mach-tegra/pm.c +++ b/arch/arm/mach-tegra/pm.c @@ -189,14 +189,16 @@ static void tegra_pm_set(enum tegra_suspend_mode mode) tegra_pmc_enter_suspend_mode(mode); } -void tegra_idle_lp2_last(void) +int tegra_idle_lp2_last(void) { + int err; + tegra_pm_set(TEGRA_SUSPEND_LP2); cpu_cluster_pm_enter(); suspend_cpu_complex(); - cpu_suspend(PHYS_OFFSET - PAGE_OFFSET, &tegra_sleep_cpu); + err = cpu_suspend(PHYS_OFFSET - PAGE_OFFSET, &tegra_sleep_cpu); /* * Resume L2 cache if it wasn't re-enabled early during resume, @@ -208,6 +210,8 @@ void tegra_idle_lp2_last(void) restore_cpu_complex(); cpu_cluster_pm_exit(); + + return err; } enum tegra_suspend_mode tegra_pm_validate_suspend_mode( diff --git a/arch/arm/mach-tegra/pm.h b/arch/arm/mach-tegra/pm.h index 3f3164ad04b7..ae68fc7db576 100644 --- a/arch/arm/mach-tegra/pm.h +++ b/arch/arm/mach-tegra/pm.h @@ -25,7 +25,7 @@ void tegra30_sleep_core_init(void); void tegra_clear_cpu_in_lp2(void); void tegra_set_cpu_in_lp2(void); -void tegra_idle_lp2_last(void); +int tegra_idle_lp2_last(void); extern void (*tegra_tear_down_cpu)(void); #ifdef CONFIG_PM_SLEEP From patchwork Sun Sep 29 17:59:42 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Dmitry Osipenko X-Patchwork-Id: 11165847 Return-Path: Received: from mail.kernel.org (pdx-korg-mail-1.web.codeaurora.org [172.30.200.123]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id 27C91112B for ; Sun, 29 Sep 2019 18:01:11 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.kernel.org (Postfix) with ESMTP id 06C1321920 for ; Sun, 29 Sep 2019 18:01:11 +0000 (UTC) Authentication-Results: mail.kernel.org; dkim=pass (2048-bit key) header.d=gmail.com header.i=@gmail.com header.b="rVkS1bYq" Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1728995AbfI2SBB (ORCPT ); Sun, 29 Sep 2019 14:01:01 -0400 Received: from mail-lj1-f194.google.com ([209.85.208.194]:37757 "EHLO mail-lj1-f194.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1729204AbfI2SAO (ORCPT ); Sun, 29 Sep 2019 14:00:14 -0400 Received: by mail-lj1-f194.google.com with SMTP id l21so7104523lje.4; Sun, 29 Sep 2019 11:00:12 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=QTe520CmQimwT2xQ5E8nuav6QtZ6H2RpuHeGJzEXlUU=; b=rVkS1bYq7yTo5Wid5Q7+gJrdUik9pzwimLaTHB5lcZlF+eUDw7FRwmbJiGLZHcENO/ bDewtVS21qX7a346iZHlce2bdxQy3XxSo1XgHlKBHJfZpytRG5aAx6Z62NVtgW6pJHFX gmQR5bDn4FOkupXzZ41EyPOJHhynsqhxsCPi/Pu9R7K527TLe7cnYycmMXju9TrW82O1 ev7GFPqNC2VmO3mwjCH4Vv1sBFRQl1feJ6tZQR1+nJU2w32+A6JT/HR4AyRk1NFHBfH+ IJDp4LmO7uaZrXtAjVnKChCGRqKcIUpEzsixCOHy+yKi0ebRwyKXi+pO12tegUwc7Kaj qcxg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=QTe520CmQimwT2xQ5E8nuav6QtZ6H2RpuHeGJzEXlUU=; b=PB0diX8YHbAvTyhQlSBRfth237mcn5+/Vf3y5P0l2PYgqxJ10bR7Ep9bWiQCk/o51k TPb9cbu7yVRkTeoU8Obqz5xftIXjS6wQlWfYxLnaW/2UfsjniLnCdzN21cjLi8zz9H6P zu8/L4kKW/LQrPnvpwJ2vkCdg+qdzbDjtBgmYUiQH4EtdMndL0x9w2z2mbtGJQLX1uBA A0yzMuu1WMjUmWPbXN2mqU/VCi3NVMimLI2fce/wkBuX2yNhW1f9C9ksPdfnUNMhwaX8 SvhmJS3seZrkCVd/YYqFralH93gT/oAAB/cN6ycqGUw7uLnlU63rbvtaMWMqsDkZ/sGv Vu3A== X-Gm-Message-State: APjAAAVbFKXtUChV0lvymJaOzf8pX1AmGUAB12jutxELg3URbE6f5jDo +45ZeneM8nGj1bLNcWXPNSE= X-Google-Smtp-Source: APXvYqywmKThcID9Y4bQDnpwwINY5zGv1U0D25LkbKaYwBszzmAuZ2kNcnAhInBPPy+nRhLXFMYnRw== X-Received: by 2002:a2e:85d2:: with SMTP id h18mr8911567ljj.18.1569780011874; Sun, 29 Sep 2019 11:00:11 -0700 (PDT) Received: from localhost.localdomain (ppp94-29-32-67.pppoe.spdop.ru. [94.29.32.67]) by smtp.gmail.com with ESMTPSA id y3sm2355511lfh.97.2019.09.29.11.00.11 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sun, 29 Sep 2019 11:00:11 -0700 (PDT) From: Dmitry Osipenko To: Thierry Reding , Jonathan Hunter , Peter De Schrijver , "Rafael J. Wysocki" , Daniel Lezcano Cc: linux-pm@vger.kernel.org, linux-tegra@vger.kernel.org, linux-kernel@vger.kernel.org Subject: [PATCH v5 04/14] ARM: tegra: Compile sleep-tegra20/30.S unconditionally Date: Sun, 29 Sep 2019 20:59:42 +0300 Message-Id: <20190929175952.22690-5-digetx@gmail.com> X-Mailer: git-send-email 2.23.0 In-Reply-To: <20190929175952.22690-1-digetx@gmail.com> References: <20190929175952.22690-1-digetx@gmail.com> MIME-Version: 1.0 Sender: linux-pm-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-pm@vger.kernel.org The sleep-tegra*.S provides functionality required for suspend/resume and CPU hotplugging. The new unified CPUIDLE driver will support multiple hardware generations starting from Terga20 and ending with Tegra124, the driver will utilize functions that are provided by the assembly and thus it is cleaner to compile that code without any build-dependencies in order to avoid churning with #ifdef's. Signed-off-by: Dmitry Osipenko --- arch/arm/mach-tegra/Makefile | 10 ++++------ arch/arm/mach-tegra/sleep.h | 2 -- 2 files changed, 4 insertions(+), 8 deletions(-) diff --git a/arch/arm/mach-tegra/Makefile b/arch/arm/mach-tegra/Makefile index 5d93a0b36866..3bb44246d928 100644 --- a/arch/arm/mach-tegra/Makefile +++ b/arch/arm/mach-tegra/Makefile @@ -8,16 +8,14 @@ obj-y += reset.o obj-y += reset-handler.o obj-y += sleep.o obj-y += tegra.o -obj-$(CONFIG_ARCH_TEGRA_2x_SOC) += sleep-tegra20.o -obj-$(CONFIG_ARCH_TEGRA_2x_SOC) += pm-tegra20.o -obj-$(CONFIG_ARCH_TEGRA_3x_SOC) += sleep-tegra30.o -obj-$(CONFIG_ARCH_TEGRA_3x_SOC) += pm-tegra30.o +obj-y += sleep-tegra20.o +obj-y += sleep-tegra30.o obj-$(CONFIG_SMP) += platsmp.o obj-$(CONFIG_HOTPLUG_CPU) += hotplug.o -obj-$(CONFIG_ARCH_TEGRA_114_SOC) += sleep-tegra30.o +obj-$(CONFIG_ARCH_TEGRA_2x_SOC) += pm-tegra20.o +obj-$(CONFIG_ARCH_TEGRA_3x_SOC) += pm-tegra30.o obj-$(CONFIG_ARCH_TEGRA_114_SOC) += pm-tegra30.o -obj-$(CONFIG_ARCH_TEGRA_124_SOC) += sleep-tegra30.o obj-$(CONFIG_ARCH_TEGRA_124_SOC) += pm-tegra30.o obj-$(CONFIG_ARCH_TEGRA_2x_SOC) += board-paz00.o diff --git a/arch/arm/mach-tegra/sleep.h b/arch/arm/mach-tegra/sleep.h index d219872b7546..4978def9db46 100644 --- a/arch/arm/mach-tegra/sleep.h +++ b/arch/arm/mach-tegra/sleep.h @@ -118,10 +118,8 @@ void tegra_resume(void); int tegra_sleep_cpu_finish(unsigned long); void tegra_disable_clean_inv_dcache(u32 flag); -#ifdef CONFIG_HOTPLUG_CPU void tegra20_hotplug_shutdown(void); void tegra30_hotplug_shutdown(void); -#endif void tegra20_tear_down_cpu(void); int tegra30_sleep_cpu_secondary_finish(unsigned long); From patchwork Sun Sep 29 17:59:43 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Dmitry Osipenko X-Patchwork-Id: 11165841 Return-Path: Received: from mail.kernel.org (pdx-korg-mail-1.web.codeaurora.org [172.30.200.123]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id 489DF1747 for ; Sun, 29 Sep 2019 18:00:56 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.kernel.org (Postfix) with ESMTP id 2707E21882 for ; Sun, 29 Sep 2019 18:00:56 +0000 (UTC) Authentication-Results: mail.kernel.org; dkim=pass (2048-bit key) header.d=gmail.com header.i=@gmail.com header.b="R69svrcL" Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1729326AbfI2SAP (ORCPT ); Sun, 29 Sep 2019 14:00:15 -0400 Received: from mail-lf1-f65.google.com ([209.85.167.65]:45800 "EHLO mail-lf1-f65.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1729215AbfI2SAP (ORCPT ); Sun, 29 Sep 2019 14:00:15 -0400 Received: by mail-lf1-f65.google.com with SMTP id r134so5292364lff.12; Sun, 29 Sep 2019 11:00:13 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=0Q6wr4WReeFVr9Ayx3FZ180PdrRVbbg27IxEID5VY5o=; b=R69svrcL8OcnC7HCe1mXe9tPuoE5f+s1zMshvd/MLHHNeYSrJm/b3ih06bK0WUWxwk dlO/d7ZIcAO0RE6+//ccfnNiDAtR8Thqdoo/ReCuIvh2aaFXlkM+ubj7fSmysn06a16t 8XWflB0c3S6iER6TUEJhVDqtZ2oJwDlvpHh/VYwbXaZgALi7dD6MltpQ3H2KtaaaMG+i Iqkjin014i5lE3UknTbVip/nJdKexUgm31RMdaEABjZhKHkbII3l70HI/StD/Z2zrcJg j5TGcC+IlzGOfCFj4dISinNwYUrVH4IIhbV2tUFQQu6XIKG3aebz9nqoBG5WETP6OQBG H6Mw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=0Q6wr4WReeFVr9Ayx3FZ180PdrRVbbg27IxEID5VY5o=; b=jdoHWwDgjUJlEdzb8MOX02rcICzoGDicHt92j7OFTQQ8w2MrxkWjQUqMVtLpCLVcU0 /L0br0M5k8Rmz0CFVhIqU4HTkukXyS8EfeuvurPLrZRFa76MSy0BowYZzO3oEMz4htSo MAFuiAQzVkgoMmKCD+SI+TZIzxKSTuU9qZUXNCql03I+K72ZbdsMpBG9VwNsbtSk+qLP JcZ7iDRbxWQHXoiCk9ywcN0tn/okkAXTe2P/lLYOoHt3A8YZts/KxZwJJXKezimvZLc/ YnL40rg2takZBok1+nSxHX/tQE565xrtVFATGvNo6FN2/bcvpMdavw+cVln2fZcUB43l KcxA== X-Gm-Message-State: APjAAAUKDptmWyiXpRk4niFhvjrEoF2176gChIgJNSs//l4D+gnbxmIM KvltpWMf+9D0AZPpFbOocu8= X-Google-Smtp-Source: APXvYqxofJm5iaQF2h75ZmR7yjAWd7kTND1JOBhPh8xLDxMqccsjxuvek7OyFVuaqRpsTNxxxqqE4A== X-Received: by 2002:ac2:5463:: with SMTP id e3mr8739109lfn.117.1569780012837; Sun, 29 Sep 2019 11:00:12 -0700 (PDT) Received: from localhost.localdomain (ppp94-29-32-67.pppoe.spdop.ru. [94.29.32.67]) by smtp.gmail.com with ESMTPSA id y3sm2355511lfh.97.2019.09.29.11.00.11 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sun, 29 Sep 2019 11:00:12 -0700 (PDT) From: Dmitry Osipenko To: Thierry Reding , Jonathan Hunter , Peter De Schrijver , "Rafael J. Wysocki" , Daniel Lezcano Cc: linux-pm@vger.kernel.org, linux-tegra@vger.kernel.org, linux-kernel@vger.kernel.org Subject: [PATCH v5 05/14] ARM: tegra: Expose PM functions required for new cpuidle driver Date: Sun, 29 Sep 2019 20:59:43 +0300 Message-Id: <20190929175952.22690-6-digetx@gmail.com> X-Mailer: git-send-email 2.23.0 In-Reply-To: <20190929175952.22690-1-digetx@gmail.com> References: <20190929175952.22690-1-digetx@gmail.com> MIME-Version: 1.0 Sender: linux-pm-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-pm@vger.kernel.org The upcoming unified CPUIDLE driver will be added to the drivers/cpuidle/ directory and it will require all these exposed Tegra PM-core functions. Signed-off-by: Dmitry Osipenko --- arch/arm/mach-tegra/irq.c | 2 ++ arch/arm/mach-tegra/pm.h | 3 --- arch/arm/mach-tegra/sleep.h | 1 - include/soc/tegra/irq.h | 13 +++++++++++++ include/soc/tegra/pm.h | 25 +++++++++++++++++++++++++ 5 files changed, 40 insertions(+), 4 deletions(-) create mode 100644 include/soc/tegra/irq.h diff --git a/arch/arm/mach-tegra/irq.c b/arch/arm/mach-tegra/irq.c index 4c065b54cbe7..4e1ee70b2a3f 100644 --- a/arch/arm/mach-tegra/irq.c +++ b/arch/arm/mach-tegra/irq.c @@ -18,6 +18,8 @@ #include #include +#include + #include "board.h" #include "iomap.h" diff --git a/arch/arm/mach-tegra/pm.h b/arch/arm/mach-tegra/pm.h index ae68fc7db576..81525f5f4a44 100644 --- a/arch/arm/mach-tegra/pm.h +++ b/arch/arm/mach-tegra/pm.h @@ -23,9 +23,6 @@ void tegra20_sleep_core_init(void); void tegra30_lp1_iram_hook(void); void tegra30_sleep_core_init(void); -void tegra_clear_cpu_in_lp2(void); -void tegra_set_cpu_in_lp2(void); -int tegra_idle_lp2_last(void); extern void (*tegra_tear_down_cpu)(void); #ifdef CONFIG_PM_SLEEP diff --git a/arch/arm/mach-tegra/sleep.h b/arch/arm/mach-tegra/sleep.h index 4978def9db46..4718a3cb45a1 100644 --- a/arch/arm/mach-tegra/sleep.h +++ b/arch/arm/mach-tegra/sleep.h @@ -122,7 +122,6 @@ void tegra20_hotplug_shutdown(void); void tegra30_hotplug_shutdown(void); void tegra20_tear_down_cpu(void); -int tegra30_sleep_cpu_secondary_finish(unsigned long); void tegra30_tear_down_cpu(void); #endif diff --git a/include/soc/tegra/irq.h b/include/soc/tegra/irq.h new file mode 100644 index 000000000000..8eb11a7109e4 --- /dev/null +++ b/include/soc/tegra/irq.h @@ -0,0 +1,13 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* + * Copyright (c) 2012, NVIDIA Corporation. All rights reserved. + */ + +#ifndef __SOC_TEGRA_IRQ_H +#define __SOC_TEGRA_IRQ_H + +#if defined(CONFIG_ARM) +bool tegra_pending_sgi(void); +#endif + +#endif /* __SOC_TEGRA_IRQ_H */ diff --git a/include/soc/tegra/pm.h b/include/soc/tegra/pm.h index 951fcd738d55..bc1abdf41d61 100644 --- a/include/soc/tegra/pm.h +++ b/include/soc/tegra/pm.h @@ -6,6 +6,8 @@ #ifndef __SOC_TEGRA_PM_H__ #define __SOC_TEGRA_PM_H__ +#include + enum tegra_suspend_mode { TEGRA_SUSPEND_NONE = 0, TEGRA_SUSPEND_LP2, /* CPU voltage off */ @@ -20,6 +22,11 @@ tegra_pm_validate_suspend_mode(enum tegra_suspend_mode mode); /* low-level resume entry point */ void tegra_resume(void); + +int tegra30_sleep_cpu_secondary_finish(unsigned long arg); +void tegra_clear_cpu_in_lp2(void); +void tegra_set_cpu_in_lp2(void); +int tegra_idle_lp2_last(void); #else static inline enum tegra_suspend_mode tegra_pm_validate_suspend_mode(enum tegra_suspend_mode mode) @@ -30,6 +37,24 @@ tegra_pm_validate_suspend_mode(enum tegra_suspend_mode mode) static inline void tegra_resume(void) { } + +static inline int tegra30_sleep_cpu_secondary_finish(unsigned long arg) +{ + return -ENOTSUPP; +} + +static inline void tegra_clear_cpu_in_lp2(void) +{ +} + +static inline void tegra_set_cpu_in_lp2(void) +{ +} + +static inline int tegra_idle_lp2_last(void) +{ + return -ENOTSUPP; +} #endif /* CONFIG_PM_SLEEP */ #endif /* __SOC_TEGRA_PM_H__ */ From patchwork Sun Sep 29 17:59:44 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Dmitry Osipenko X-Patchwork-Id: 11165839 Return-Path: Received: from mail.kernel.org (pdx-korg-mail-1.web.codeaurora.org [172.30.200.123]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id 8D0211747 for ; Sun, 29 Sep 2019 18:00:54 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.kernel.org (Postfix) with ESMTP id 6BE522190F for ; Sun, 29 Sep 2019 18:00:54 +0000 (UTC) Authentication-Results: mail.kernel.org; dkim=pass (2048-bit key) header.d=gmail.com header.i=@gmail.com header.b="f6ZjKJnY" Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1729362AbfI2SAR (ORCPT ); Sun, 29 Sep 2019 14:00:17 -0400 Received: from mail-lf1-f68.google.com ([209.85.167.68]:46947 "EHLO mail-lf1-f68.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1729279AbfI2SAQ (ORCPT ); Sun, 29 Sep 2019 14:00:16 -0400 Received: by mail-lf1-f68.google.com with SMTP id t8so5283239lfc.13; Sun, 29 Sep 2019 11:00:14 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=5RptpaDUxXrw3BpU/T4vq1rijHUh8vyrzkTNBzahvDA=; b=f6ZjKJnYlGmBBN7gvHgoyC9su7djXyxy/uIxAf08UhnwuXTJmdaZmA18PQUeHgNl+v 61qG6xbA/hOeBdSZUvS96yVkV6qa3fRs5SqSHvP5tvtQH+Di1i9vEDdDr6pauH6ehvrq R3wHK0dQt3sU3IAWozuMM6d098wGfBrNgqJoJ0dlpQ6xnygiDuD95TjuUFcPscwgVVz1 R2hfM7KhOR7WNY1pwKJUXs6UJqCarIpUExu6gyxOK9slcJS2Upv+MTxXXzJFOft9d2vc wwNxhZDYhwquFhyGNfNVeuohwhoekVwYHCln71Qs2Y3Jyug1Xir46o4pzJywtKUSNG3U lEsw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=5RptpaDUxXrw3BpU/T4vq1rijHUh8vyrzkTNBzahvDA=; b=jQsSHE30C17PA/eOLaTwSMf3BwTy23PVSM2OvwmJOBdIrAQHBBGkaqgl5H01qdqRMv iHGI43CEBzs09XhbrjWbE0xXnw/iE+tSCt1zUP1FARN1Fj26U5OoXojCECjzdFjCcx2i BVSh5vJ2+5alR+1Z8gBAxBsQ3lQL35tHQHDiY58m8V/HmY07ozi8duncmYT87qwJLUPV xYLyojMWg1jm2S6QothlN3QDFEPUlDDMA0BM44Af4hFZN0G6Zxx7414Ooh+y5ZkNXwAU dQQEFau8nT/j1u0KIXtffJ5OUwap0lwDU7NRfKTNGYzbpebBU3hF13USvdSHb0Hsfj1v w0Xw== X-Gm-Message-State: APjAAAWXXWgXv7VYIA4fR9T0AjgSpvR2uULOPq7Qm9wD4EOI539dVWL/ 2wWqzezRoST20dHFq0l5gRA= X-Google-Smtp-Source: APXvYqy55L9uI6YBnO6btMW6GZoKn61AZx14mopA7bllS3XRL/f6VEMSzzzd0cbRs+/pfurzBS3y0A== X-Received: by 2002:a19:a408:: with SMTP id q8mr8528427lfc.94.1569780013746; Sun, 29 Sep 2019 11:00:13 -0700 (PDT) Received: from localhost.localdomain (ppp94-29-32-67.pppoe.spdop.ru. [94.29.32.67]) by smtp.gmail.com with ESMTPSA id y3sm2355511lfh.97.2019.09.29.11.00.12 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sun, 29 Sep 2019 11:00:13 -0700 (PDT) From: Dmitry Osipenko To: Thierry Reding , Jonathan Hunter , Peter De Schrijver , "Rafael J. Wysocki" , Daniel Lezcano Cc: linux-pm@vger.kernel.org, linux-tegra@vger.kernel.org, linux-kernel@vger.kernel.org Subject: [PATCH v5 06/14] ARM: tegra: Rename some of the newly exposed PM functions Date: Sun, 29 Sep 2019 20:59:44 +0300 Message-Id: <20190929175952.22690-7-digetx@gmail.com> X-Mailer: git-send-email 2.23.0 In-Reply-To: <20190929175952.22690-1-digetx@gmail.com> References: <20190929175952.22690-1-digetx@gmail.com> MIME-Version: 1.0 Sender: linux-pm-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-pm@vger.kernel.org Rename some of the recently exposed PM functions, prefixing them with "tegra_pm_" and making naming of those functions more meaningful, for consistency. Signed-off-by: Dmitry Osipenko --- arch/arm/mach-tegra/pm.c | 10 +++++----- arch/arm/mach-tegra/sleep-tegra30.S | 6 +++--- include/soc/tegra/pm.h | 16 ++++++++-------- 3 files changed, 16 insertions(+), 16 deletions(-) diff --git a/arch/arm/mach-tegra/pm.c b/arch/arm/mach-tegra/pm.c index f9c9bce9e15d..4cc64a135a3e 100644 --- a/arch/arm/mach-tegra/pm.c +++ b/arch/arm/mach-tegra/pm.c @@ -110,7 +110,7 @@ static void suspend_cpu_complex(void) flowctrl_cpu_suspend_enter(cpu); } -void tegra_clear_cpu_in_lp2(void) +void tegra_pm_clear_cpu_in_lp2(void) { int phy_cpu_id = cpu_logical_map(smp_processor_id()); u32 *cpu_in_lp2 = tegra_cpu_lp2_mask; @@ -123,7 +123,7 @@ void tegra_clear_cpu_in_lp2(void) spin_unlock(&tegra_lp2_lock); } -void tegra_set_cpu_in_lp2(void) +void tegra_pm_set_cpu_in_lp2(void) { int phy_cpu_id = cpu_logical_map(smp_processor_id()); u32 *cpu_in_lp2 = tegra_cpu_lp2_mask; @@ -189,7 +189,7 @@ static void tegra_pm_set(enum tegra_suspend_mode mode) tegra_pmc_enter_suspend_mode(mode); } -int tegra_idle_lp2_last(void) +int tegra_pm_enter_lp2(void) { int err; @@ -356,7 +356,7 @@ static int tegra_suspend_enter(suspend_state_t state) tegra_suspend_enter_lp1(); break; case TEGRA_SUSPEND_LP2: - tegra_set_cpu_in_lp2(); + tegra_pm_set_cpu_in_lp2(); break; default: break; @@ -377,7 +377,7 @@ static int tegra_suspend_enter(suspend_state_t state) tegra_suspend_exit_lp1(); break; case TEGRA_SUSPEND_LP2: - tegra_clear_cpu_in_lp2(); + tegra_pm_clear_cpu_in_lp2(); break; default: break; diff --git a/arch/arm/mach-tegra/sleep-tegra30.S b/arch/arm/mach-tegra/sleep-tegra30.S index b408fa56eb89..386319a3d2d2 100644 --- a/arch/arm/mach-tegra/sleep-tegra30.S +++ b/arch/arm/mach-tegra/sleep-tegra30.S @@ -262,11 +262,11 @@ ENTRY(tegra30_sleep_core_finish) ENDPROC(tegra30_sleep_core_finish) /* - * tegra30_sleep_cpu_secondary_finish(unsigned long v2p) + * tegra30_pm_secondary_cpu_suspend(unsigned long unused_arg) * * Enters LP2 on secondary CPU by exiting coherency and powergating the CPU. */ -ENTRY(tegra30_sleep_cpu_secondary_finish) +ENTRY(tegra30_pm_secondary_cpu_suspend) mov r7, lr /* Flush and disable the L1 data cache */ @@ -278,7 +278,7 @@ ENTRY(tegra30_sleep_cpu_secondary_finish) bl tegra30_cpu_shutdown mov r0, #1 @ never return here ret r7 -ENDPROC(tegra30_sleep_cpu_secondary_finish) +ENDPROC(tegra30_pm_secondary_cpu_suspend) /* * tegra30_tear_down_cpu diff --git a/include/soc/tegra/pm.h b/include/soc/tegra/pm.h index bc1abdf41d61..2fbee9efda21 100644 --- a/include/soc/tegra/pm.h +++ b/include/soc/tegra/pm.h @@ -23,10 +23,10 @@ tegra_pm_validate_suspend_mode(enum tegra_suspend_mode mode); /* low-level resume entry point */ void tegra_resume(void); -int tegra30_sleep_cpu_secondary_finish(unsigned long arg); -void tegra_clear_cpu_in_lp2(void); -void tegra_set_cpu_in_lp2(void); -int tegra_idle_lp2_last(void); +int tegra30_pm_secondary_cpu_suspend(unsigned long arg); +void tegra_pm_clear_cpu_in_lp2(void); +void tegra_pm_set_cpu_in_lp2(void); +int tegra_pm_enter_lp2(void); #else static inline enum tegra_suspend_mode tegra_pm_validate_suspend_mode(enum tegra_suspend_mode mode) @@ -38,20 +38,20 @@ static inline void tegra_resume(void) { } -static inline int tegra30_sleep_cpu_secondary_finish(unsigned long arg) +static inline int tegra30_pm_secondary_cpu_suspend(unsigned long arg) { return -ENOTSUPP; } -static inline void tegra_clear_cpu_in_lp2(void) +static inline void tegra_pm_clear_cpu_in_lp2(void) { } -static inline void tegra_set_cpu_in_lp2(void) +static inline void tegra_pm_set_cpu_in_lp2(void) { } -static inline int tegra_idle_lp2_last(void) +static inline int tegra_pm_enter_lp2(void) { return -ENOTSUPP; } From patchwork Sun Sep 29 17:59:45 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Dmitry Osipenko X-Patchwork-Id: 11165837 Return-Path: Received: from mail.kernel.org (pdx-korg-mail-1.web.codeaurora.org [172.30.200.123]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id 13092112B for ; Sun, 29 Sep 2019 18:00:54 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.kernel.org (Postfix) with ESMTP id E68DF21882 for ; Sun, 29 Sep 2019 18:00:53 +0000 (UTC) Authentication-Results: mail.kernel.org; dkim=pass (2048-bit key) header.d=gmail.com header.i=@gmail.com header.b="jw4ypUVS" Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1729372AbfI2SAR (ORCPT ); Sun, 29 Sep 2019 14:00:17 -0400 Received: from mail-lj1-f194.google.com ([209.85.208.194]:40781 "EHLO mail-lj1-f194.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1729325AbfI2SAQ (ORCPT ); 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[94.29.32.67]) by smtp.gmail.com with ESMTPSA id y3sm2355511lfh.97.2019.09.29.11.00.13 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sun, 29 Sep 2019 11:00:14 -0700 (PDT) From: Dmitry Osipenko To: Thierry Reding , Jonathan Hunter , Peter De Schrijver , "Rafael J. Wysocki" , Daniel Lezcano Cc: linux-pm@vger.kernel.org, linux-tegra@vger.kernel.org, linux-kernel@vger.kernel.org Subject: [PATCH v5 07/14] ARM: tegra: Add tegra_pm_park_secondary_cpu() Date: Sun, 29 Sep 2019 20:59:45 +0300 Message-Id: <20190929175952.22690-8-digetx@gmail.com> X-Mailer: git-send-email 2.23.0 In-Reply-To: <20190929175952.22690-1-digetx@gmail.com> References: <20190929175952.22690-1-digetx@gmail.com> MIME-Version: 1.0 Sender: linux-pm-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-pm@vger.kernel.org This function resembles tegra_cpu_die() of the hotplug code, but this variant is more suitable to be used for CPU PM because it's made specifically to be used by cpu_suspend(). In short this function puts secondary CPU offline, it will be used by the new CPUIDLE driver. Signed-off-by: Dmitry Osipenko --- arch/arm/mach-tegra/pm.c | 14 ++++++++++++++ include/soc/tegra/pm.h | 6 ++++++ 2 files changed, 20 insertions(+) diff --git a/arch/arm/mach-tegra/pm.c b/arch/arm/mach-tegra/pm.c index 4cc64a135a3e..7d9ef26e52a7 100644 --- a/arch/arm/mach-tegra/pm.c +++ b/arch/arm/mach-tegra/pm.c @@ -427,4 +427,18 @@ void __init tegra_init_suspend(void) suspend_set_ops(&tegra_suspend_ops); } + +int tegra_pm_park_secondary_cpu(unsigned long cpu) +{ + if (cpu > 0) { + tegra_disable_clean_inv_dcache(TEGRA_FLUSH_CACHE_LOUIS); + + if (tegra_get_chip_id() == TEGRA20) + tegra20_hotplug_shutdown(); + else + tegra30_hotplug_shutdown(); + } + + return -EINVAL; +} #endif diff --git a/include/soc/tegra/pm.h b/include/soc/tegra/pm.h index 2fbee9efda21..08477d7bfab9 100644 --- a/include/soc/tegra/pm.h +++ b/include/soc/tegra/pm.h @@ -27,6 +27,7 @@ int tegra30_pm_secondary_cpu_suspend(unsigned long arg); void tegra_pm_clear_cpu_in_lp2(void); void tegra_pm_set_cpu_in_lp2(void); int tegra_pm_enter_lp2(void); +int tegra_pm_park_secondary_cpu(unsigned long cpu); #else static inline enum tegra_suspend_mode tegra_pm_validate_suspend_mode(enum tegra_suspend_mode mode) @@ -55,6 +56,11 @@ static inline int tegra_pm_enter_lp2(void) { return -ENOTSUPP; } + +static inline int tegra_pm_park_secondary_cpu(unsigned long cpu) +{ + return -ENOTSUPP; +} #endif /* CONFIG_PM_SLEEP */ #endif /* __SOC_TEGRA_PM_H__ */ From patchwork Sun Sep 29 17:59:46 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Dmitry Osipenko X-Patchwork-Id: 11165833 Return-Path: Received: from mail.kernel.org (pdx-korg-mail-1.web.codeaurora.org [172.30.200.123]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id A4F3C14DB for ; Sun, 29 Sep 2019 18:00:46 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.kernel.org (Postfix) with ESMTP id 8397521882 for ; Sun, 29 Sep 2019 18:00:46 +0000 (UTC) Authentication-Results: mail.kernel.org; dkim=pass (2048-bit key) header.d=gmail.com header.i=@gmail.com header.b="hDKvLK+o" Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1729399AbfI2SAS (ORCPT ); Sun, 29 Sep 2019 14:00:18 -0400 Received: from mail-lj1-f196.google.com ([209.85.208.196]:33344 "EHLO mail-lj1-f196.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1729344AbfI2SAS (ORCPT ); Sun, 29 Sep 2019 14:00:18 -0400 Received: by mail-lj1-f196.google.com with SMTP id a22so7129257ljd.0; Sun, 29 Sep 2019 11:00:16 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=ruFgZjU6gpk8s8XpOqnNEi46GBIDFW073D2rWvcyP3o=; b=hDKvLK+oc73wzZgO6xGdFSHze+dv/bUhThfzSJY4usVgr+HPamFf4bJxwIuwGypYx2 8nlgw9IyFc+n/ZSL+HetAut71WUYMA0I1Nqh3TckdH3nxJJkvRCSSTdbUkmVCVU0HZVR 3TUonqT80nPmu9MbWgMs2yGHIynAOycJ5+8f+cuYXGPVsgQKNuAWquBdQkC2B5Uv4guP X1e/TacoUoCu08nI+Ma7qjRxzRMnlcG1/cmt+G0BvrFdpDtZUdgY4mj3ltwnQ4Y3j2lQ FFQzc1N/bbwUsUk0264Nk55hKu1Ojdmo7vrvXCwVrRybsR7Bp40vYyJd20FhYJHn3QJ5 crKg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=ruFgZjU6gpk8s8XpOqnNEi46GBIDFW073D2rWvcyP3o=; b=qE1HrPnMyXpNdDYQFE4L9CcfATNazbS2J57C25IwE1GcuMHtKSHpAU308b7SpIwNt5 hszfYJFoHHps7/XRtoWjK6EwZvCY2JubgZGrdF5xFMuQzTM1xlJF6UdPhTNOOYpVj2ym eE6sxlPwrlIM1c59pJ06wwHScMe2Ao/z8hry6s9n41T4Y9xBqw0EQrsqpHfRwpAQg2Wi a/7cnzZfmC33k+urBHTQnYx1aWl8TDFNVjg/K35A6RxAXQiaIcsmTWYdTpzeN5Uj0yb8 nefxiUS2vN6ZVGYQCgrL+slZZV4K/iuzYMwRT1H/KISdagXEmUEJIX0MuAMkRhPynVf+ /yPg== X-Gm-Message-State: APjAAAVdqYcLSMhCaN//PSYtFVNUB7ZRex8pQVWTuPDWZG0h5rdFIWSY FAoVTnfj3ppDx699Fs8hWk5EGakA X-Google-Smtp-Source: APXvYqwQjO+zs6wRJRpv8uh0LUlNPiZsbOMHWWiDKQuTC2ClgtgeAWFiHCTXq34/3ZegINTqvjpuGw== X-Received: by 2002:a2e:6a13:: with SMTP id f19mr9534607ljc.17.1569780015486; Sun, 29 Sep 2019 11:00:15 -0700 (PDT) Received: from localhost.localdomain (ppp94-29-32-67.pppoe.spdop.ru. [94.29.32.67]) by smtp.gmail.com with ESMTPSA id y3sm2355511lfh.97.2019.09.29.11.00.14 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sun, 29 Sep 2019 11:00:15 -0700 (PDT) From: Dmitry Osipenko To: Thierry Reding , Jonathan Hunter , Peter De Schrijver , "Rafael J. Wysocki" , Daniel Lezcano Cc: linux-pm@vger.kernel.org, linux-tegra@vger.kernel.org, linux-kernel@vger.kernel.org Subject: [PATCH v5 08/14] ARM: tegra: Make outer_disable() open-coded Date: Sun, 29 Sep 2019 20:59:46 +0300 Message-Id: <20190929175952.22690-9-digetx@gmail.com> X-Mailer: git-send-email 2.23.0 In-Reply-To: <20190929175952.22690-1-digetx@gmail.com> References: <20190929175952.22690-1-digetx@gmail.com> MIME-Version: 1.0 Sender: linux-pm-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-pm@vger.kernel.org The outer_disable() of Tegra's suspend code is open-coded now since that helper produces spurious warning message about secondary CPUs being online. The secondaries are actually halted by the cpuidle driver on entering into LP2 idle-state. This fixes a storm of warnings once LP2 idling state is enabled on Tegra30. Signed-off-by: Dmitry Osipenko --- arch/arm/mach-tegra/pm.c | 7 ++++--- 1 file changed, 4 insertions(+), 3 deletions(-) diff --git a/arch/arm/mach-tegra/pm.c b/arch/arm/mach-tegra/pm.c index 7d9ef26e52a7..16a02937d3da 100644 --- a/arch/arm/mach-tegra/pm.c +++ b/arch/arm/mach-tegra/pm.c @@ -146,9 +146,10 @@ static int tegra_sleep_cpu(unsigned long v2p) * if any of secondary CPU's is online and this is the LP2-idle * code-path only for Tegra20/30. */ - if (trusted_foundations_registered()) - outer_disable(); - +#ifdef CONFIG_OUTER_CACHE + if (trusted_foundations_registered() && outer_cache.disable) + outer_cache.disable(); +#endif /* * Note that besides of setting up CPU reset vector this firmware * call may also do the following, depending on the FW version: From patchwork Sun Sep 29 17:59:47 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Dmitry Osipenko X-Patchwork-Id: 11165835 Return-Path: Received: from mail.kernel.org (pdx-korg-mail-1.web.codeaurora.org [172.30.200.123]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id DE13314DB for ; Sun, 29 Sep 2019 18:00:50 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.kernel.org (Postfix) with ESMTP id BC89C218DE for ; Sun, 29 Sep 2019 18:00:50 +0000 (UTC) Authentication-Results: mail.kernel.org; dkim=pass (2048-bit key) header.d=gmail.com header.i=@gmail.com header.b="MK7dOvVy" Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1729454AbfI2SAq (ORCPT ); Sun, 29 Sep 2019 14:00:46 -0400 Received: from mail-lj1-f193.google.com ([209.85.208.193]:38953 "EHLO mail-lj1-f193.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1729215AbfI2SAS (ORCPT ); Sun, 29 Sep 2019 14:00:18 -0400 Received: by mail-lj1-f193.google.com with SMTP id y3so7102202ljj.6; Sun, 29 Sep 2019 11:00:16 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=6WzGxu5Uzxxq0Lu5as86wPG4OXi9gBVk0Y+PLDjSeQQ=; b=MK7dOvVy/RlvfYVUAuigqskJXwF3thms43oKcDxPRMoiIcrSLcheYkO9kVD6b5nybh M6qr3QFduXpuRQbfdfpzBHmwvrNSfgx6fsQIivCzbQ9q213gJh9VQs3F+H3HhjMhLXYr AOAP8ssMJ30kpPCJ4FPkB3jyjQ94wuct4jZTfciaGF1o2qUhaeYrD+YpTLs2N0le/u0L BUIWDY2RKTo+MnHQM48/CxarGovG3imvYko8CeAnpaP+4BkW9UBgsPjCXTLRp1E2p9n/ LvH+W3PJR3uh2iDp0eBAs5xGpa95glOYJFrv90P1OvSTKXXO1RQruw4A+LILADL8j8Au eEBQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=6WzGxu5Uzxxq0Lu5as86wPG4OXi9gBVk0Y+PLDjSeQQ=; b=bJajjM771wKr1Vhe201JstzEE5r3NZeA9Nq7vwfC4Rf4PWEtoeQdZVvfoLY0BtuPZX /K6qfmmWBucuVoeioJW7aESGc6+Sa2Z7wZUVDGVPGfvFOx9MIMFOmDlttauPlTlkUYUw +qu4ON0+nwzquSdJCyTLSRGa7d87B8aLZGmBXSEjSZJOFElJBpPH5PHp22teKulifMXl lcsqqssPJ6HYe4xMFYONjn+rxR7owZWt+KRWiEKW8YeWXi1kAiBDrvfxDPrkde7mNUrO YUZkd8Hn4M7qtPz9zgSbGhQNvKhhFivYb61Lghg8pHPoS12sTBnEWh3yTUj0bghB2YyQ kpMQ== X-Gm-Message-State: APjAAAX03M7upPEKV6/7c80vss7GPrrYH6vjTw3P5e+z4k7DHQhRRYcd aILMSbe5Q+eViiRhbI7EOW0= X-Google-Smtp-Source: APXvYqzQAEP5QQHzoYeemCDiwSZcrgTee5vhjNxTqbt51XqkdHJId79ol4FZKftaYWVSWwhpa1JlDg== X-Received: by 2002:a05:651c:154:: with SMTP id c20mr9470692ljd.83.1569780016335; Sun, 29 Sep 2019 11:00:16 -0700 (PDT) Received: from localhost.localdomain (ppp94-29-32-67.pppoe.spdop.ru. [94.29.32.67]) by smtp.gmail.com with ESMTPSA id y3sm2355511lfh.97.2019.09.29.11.00.15 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sun, 29 Sep 2019 11:00:15 -0700 (PDT) From: Dmitry Osipenko To: Thierry Reding , Jonathan Hunter , Peter De Schrijver , "Rafael J. Wysocki" , Daniel Lezcano Cc: linux-pm@vger.kernel.org, linux-tegra@vger.kernel.org, linux-kernel@vger.kernel.org Subject: [PATCH v5 09/14] clk: tegra: Add missing stubs for the case of !CONFIG_PM_SLEEP Date: Sun, 29 Sep 2019 20:59:47 +0300 Message-Id: <20190929175952.22690-10-digetx@gmail.com> X-Mailer: git-send-email 2.23.0 In-Reply-To: <20190929175952.22690-1-digetx@gmail.com> References: <20190929175952.22690-1-digetx@gmail.com> MIME-Version: 1.0 Sender: linux-pm-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-pm@vger.kernel.org The new CPUIDLE driver uses the Tegra's CLK API and that driver won't strictly depend on CONFIG_PM_SLEEP, hence add the required stubs in order to allow compiling of the new driver with the CONFIG_PM_SLEEP=n. Signed-off-by: Dmitry Osipenko --- include/linux/clk/tegra.h | 13 +++++++++++++ 1 file changed, 13 insertions(+) diff --git a/include/linux/clk/tegra.h b/include/linux/clk/tegra.h index b8aef62cc3f5..cf0f2cb5e109 100644 --- a/include/linux/clk/tegra.h +++ b/include/linux/clk/tegra.h @@ -108,6 +108,19 @@ static inline void tegra_cpu_clock_resume(void) tegra_cpu_car_ops->resume(); } +#else +static inline bool tegra_cpu_rail_off_ready(void) +{ + return false; +} + +static inline void tegra_cpu_clock_suspend(void) +{ +} + +static inline void tegra_cpu_clock_resume(void) +{ +} #endif extern void tegra210_xusb_pll_hw_control_enable(void); From patchwork Sun Sep 29 17:59:48 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Dmitry Osipenko X-Patchwork-Id: 11165831 Return-Path: Received: from mail.kernel.org (pdx-korg-mail-1.web.codeaurora.org [172.30.200.123]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id 29176112B for ; Sun, 29 Sep 2019 18:00:44 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.kernel.org (Postfix) with ESMTP id E771021D7B for ; Sun, 29 Sep 2019 18:00:43 +0000 (UTC) Authentication-Results: mail.kernel.org; dkim=pass (2048-bit key) header.d=gmail.com header.i=@gmail.com header.b="Qa8SdFx4" Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1729469AbfI2SAW (ORCPT ); Sun, 29 Sep 2019 14:00:22 -0400 Received: from mail-lj1-f194.google.com ([209.85.208.194]:36483 "EHLO mail-lj1-f194.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1729431AbfI2SAV (ORCPT ); Sun, 29 Sep 2019 14:00:21 -0400 Received: by mail-lj1-f194.google.com with SMTP id v24so7113732ljj.3; Sun, 29 Sep 2019 11:00:18 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=zlYXTKVG35ki8/3epZWI72d3i86klm6BpPfeezO24m8=; b=Qa8SdFx4vx4y47Cb5wcpwJHHeMbyJYFWRhkD4Y+Y9+eseZP1Avxt4xia4umnE2D9dg s4W79Xu5YmoxsJ5dIox1b3vkE+uqwghDwSFDm0+xcT4wbXVJOhfn6nJaSr6gKW4zumGp ou5oKSZfyoypZMr8Juxrdj1zB+tIEGquj1Gc/rZ83QHhk9hpAXI9/7i+PCM8B4rXSyt0 r3CDXEpNH9RU9E9y9FE37Wi0IEyzb2SWlGrbwUEtU0ZV/4UoRqjW/PDNLakqN3oWjEaw ORyA1LenpQsMV7cZpUkHzq152ENuL482Y8y6jYEInRnsShnV8YeM7qJYbKmHWrVTYreT I3SQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=zlYXTKVG35ki8/3epZWI72d3i86klm6BpPfeezO24m8=; b=bED+tO7lnbc6dg1QAq2IamGqE7oMQGW+raPCFt4HDlVa3f3dIAIuKcXA03H5BGHfp+ C0qRDq4wrqX7dbSladsY22hY0YINUS8WAlsFFxKrInzDhs9ownQqseNn9MCkFKWwskEG +rKdqZ1FIqwTO4HWyupnzDp7fM0Syarya+Ez1CRUmwIO92kAyb45XrDBcsFr18ixFW4c lsMxhnt00PyGsQcnkXnM/8o/Mvx2R5787G2JIO3r+9EIFMTXZtuEO45VKrla8k+q8MWX m28uMjxIJ8V/wu07Y19NVtZrCuWCn4rCFlsXpT8upx1tSTvWFANAne37lxKb23Jds3kI WRgQ== X-Gm-Message-State: APjAAAUQnprcpRWLhdD2WkbNxuFv+EdoGTDHF64PKSxOoGM8yRQ1F5dm bl0EEY44z0OOZll1g2E3Y68= X-Google-Smtp-Source: APXvYqylpwNIU2CHWOdKhT9J3et86PhTxD7bSZZbviAPQ3Q02E9rIVxwmm4Tq5l55ONXPWkwjly46g== X-Received: by 2002:a2e:b0d1:: with SMTP id g17mr9259733ljl.238.1569780017325; Sun, 29 Sep 2019 11:00:17 -0700 (PDT) Received: from localhost.localdomain (ppp94-29-32-67.pppoe.spdop.ru. [94.29.32.67]) by smtp.gmail.com with ESMTPSA id y3sm2355511lfh.97.2019.09.29.11.00.16 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sun, 29 Sep 2019 11:00:16 -0700 (PDT) From: Dmitry Osipenko To: Thierry Reding , Jonathan Hunter , Peter De Schrijver , "Rafael J. Wysocki" , Daniel Lezcano Cc: linux-pm@vger.kernel.org, linux-tegra@vger.kernel.org, linux-kernel@vger.kernel.org Subject: [PATCH v5 10/14] cpuidle: Introduce unified driver for NVIDIA Tegra SoCs Date: Sun, 29 Sep 2019 20:59:48 +0300 Message-Id: <20190929175952.22690-11-digetx@gmail.com> X-Mailer: git-send-email 2.23.0 In-Reply-To: <20190929175952.22690-1-digetx@gmail.com> References: <20190929175952.22690-1-digetx@gmail.com> MIME-Version: 1.0 Sender: linux-pm-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-pm@vger.kernel.org The new driver is based on the old CPU Idle drivers that are removed now from arm/arch/mach-tegra/ directory. Those removed drivers were reworked and squashed into a single unified driver that covers multiple hardware generations, starting from Tegra20 and ending with Tegra124. The new driver takes slightly different approach in regards to handling of CC6 state by parking secondary CPUs explicitly into offline state, in contrast to CPUs suspend/resume racing that old Tegra20 had. The new driver doesn't ignore any possible errors and provides useful diagnostics information in a case of failure. Signed-off-by: Dmitry Osipenko --- drivers/cpuidle/Kconfig.arm | 8 + drivers/cpuidle/Makefile | 1 + drivers/cpuidle/cpuidle-tegra.c | 350 ++++++++++++++++++++++++++++++++ include/soc/tegra/cpuidle.h | 4 + 4 files changed, 363 insertions(+) create mode 100644 drivers/cpuidle/cpuidle-tegra.c diff --git a/drivers/cpuidle/Kconfig.arm b/drivers/cpuidle/Kconfig.arm index d8530475493c..6952bf7bb260 100644 --- a/drivers/cpuidle/Kconfig.arm +++ b/drivers/cpuidle/Kconfig.arm @@ -86,3 +86,11 @@ config ARM_MVEBU_V7_CPUIDLE depends on ARCH_MVEBU && !ARM64 help Select this to enable cpuidle on Armada 370, 38x and XP processors. + +config ARM_TEGRA_CPUIDLE + bool "CPU Idle Driver for NVIDIA Tegra SoCs" + depends on ARCH_TEGRA && !ARM64 + select ARCH_NEEDS_CPU_IDLE_COUPLED if SMP + select ARM_CPU_SUSPEND + help + Select this to enable cpuidle for NVIDIA Tegra20/30/114/124 SoCs. diff --git a/drivers/cpuidle/Makefile b/drivers/cpuidle/Makefile index ee70d5cc5b99..a15e4808d295 100644 --- a/drivers/cpuidle/Makefile +++ b/drivers/cpuidle/Makefile @@ -22,6 +22,7 @@ obj-$(CONFIG_ARM_AT91_CPUIDLE) += cpuidle-at91.o obj-$(CONFIG_ARM_EXYNOS_CPUIDLE) += cpuidle-exynos.o obj-$(CONFIG_ARM_CPUIDLE) += cpuidle-arm.o obj-$(CONFIG_ARM_PSCI_CPUIDLE) += cpuidle-psci.o +obj-$(CONFIG_ARM_TEGRA_CPUIDLE) += cpuidle-tegra.o ############################################################################### # MIPS drivers diff --git a/drivers/cpuidle/cpuidle-tegra.c b/drivers/cpuidle/cpuidle-tegra.c new file mode 100644 index 000000000000..a926d2781227 --- /dev/null +++ b/drivers/cpuidle/cpuidle-tegra.c @@ -0,0 +1,350 @@ +// SPDX-License-Identifier: GPL-2.0-only +/* + * CPU idle driver for Tegra CPUs + * + * Copyright (c) 2010-2013, NVIDIA Corporation. + * Copyright (c) 2011 Google, Inc. + * Author: Colin Cross + * Gary King + * + * Rework for 3.3 by Peter De Schrijver + * + * Tegra20/124 driver unification by Dmitry Osipenko + */ + +#define pr_fmt(fmt) "tegra-cpuidle: " fmt + +#include +#include +#include +#include +#include +#include +#include +#include + +#include +#include + +#include +#include +#include +#include +#include + +#include +#include +#include +#include + +#define TEGRA_C1 0 +#define TEGRA_C7 1 +#define TEGRA_CC6 2 + +static atomic_t tegra_idle_barrier; +static atomic_t tegra_abort_flag; + +static inline bool tegra_cpuidle_using_firmware(void) +{ + return firmware_ops->prepare_idle && firmware_ops->do_idle; +} + +static void tegra_cpuidle_report_cpus_state(void) +{ + unsigned int cpu, lcpu; + + for_each_cpu(lcpu, cpu_possible_mask) { + cpu = cpu_logical_map(lcpu); + + pr_err("cpu%u: online=%d flowctrl_csr=0x%08x\n", + cpu, cpu_online(lcpu), flowctrl_read_cpu_csr(cpu)); + } +} + +static int tegra_cpuidle_wait_for_secondary_cpus_parking(void) +{ + ktime_t timeout = ktime_add_ms(ktime_get(), 100); + + /* + * The primary CPU0 core shall wait for the secondaries shutdown + * in order to power-off CPU's cluster safely. The timeout value + * depends on the current CPU frequency, it takes about 40-150us + * in average and over 1000us in a worst case scenario. + */ + do { + if (tegra_cpu_rail_off_ready()) + return 0; + + } while (ktime_before(ktime_get(), timeout)); + + /* postmortem */ + tegra_cpuidle_report_cpus_state(); + + return -ETIMEDOUT; +} + +static void tegra_cpuidle_unpark_secondary_cpus(void) +{ + unsigned int cpu, lcpu; + + for_each_cpu(lcpu, cpu_online_mask) { + cpu = cpu_logical_map(lcpu); + + if (cpu > 0) { + tegra_enable_cpu_clock(cpu); + tegra_cpu_out_of_reset(cpu); + flowctrl_write_cpu_halt(cpu, 0); + } + } +} + +static int tegra_cpuidle_cc6_enter(unsigned int cpu) +{ + int ret; + + if (cpu > 0) { + ret = cpu_suspend(cpu, tegra_pm_park_secondary_cpu); + } else { + ret = tegra_cpuidle_wait_for_secondary_cpus_parking(); + if (ret) + return ret; + + ret = tegra_pm_enter_lp2(); + + tegra_cpuidle_unpark_secondary_cpus(); + } + + return ret; +} + +static int tegra_cpuidle_c7_enter(void) +{ + int err; + + if (tegra_cpuidle_using_firmware()) { + err = call_firmware_op(prepare_idle, TF_PM_MODE_LP2_NOFLUSH_L2); + if (err) + return err; + + return call_firmware_op(do_idle, 0); + } + + return cpu_suspend(0, tegra30_pm_secondary_cpu_suspend); +} + +static int tegra_cpuidle_coupled_barrier(struct cpuidle_device *dev) +{ + if (tegra_pending_sgi()) { + /* + * CPU got local interrupt that will be lost after GIC's + * shutdown because GIC driver doesn't save/restore the + * pending SGI state across CPU cluster PM. Abort and retry + * next time. + */ + atomic_set(&tegra_abort_flag, 1); + } + + cpuidle_coupled_parallel_barrier(dev, &tegra_idle_barrier); + + if (atomic_read(&tegra_abort_flag)) { + cpuidle_coupled_parallel_barrier(dev, &tegra_idle_barrier); + atomic_set(&tegra_abort_flag, 0); + return -EINTR; + } + + return 0; +} + +static int tegra_cpuidle_state_enter(struct cpuidle_device *dev, + int index, unsigned int cpu) +{ + int ret; + + /* + * CC6 state is the "CPU cluster power-off" state. In order to + * enter this state, at first the secondary CPU cores need to be + * parked into offline mode, then the last CPU should clean out + * remaining dirty cache lines into DRAM and trigger Flow Controller + * logic that turns off the cluster's power domain (which includes + * CPU cores, GIC and L2 cache). + */ + if (index == TEGRA_CC6) { + ret = tegra_cpuidle_coupled_barrier(dev); + if (ret) + return ret; + } + + local_fiq_disable(); + tegra_pm_set_cpu_in_lp2(); + cpu_pm_enter(); + + switch (index) { + case TEGRA_C7: + ret = tegra_cpuidle_c7_enter(); + break; + case TEGRA_CC6: + ret = tegra_cpuidle_cc6_enter(cpu); + break; + default: + ret = -EINVAL; + break; + } + + cpu_pm_exit(); + tegra_pm_clear_cpu_in_lp2(); + local_fiq_enable(); + + return ret; +} + +static int tegra_cpuidle_adjust_state_index(struct cpuidle_device *dev, + struct cpuidle_driver *drv, + int index, unsigned int cpu) +{ + /* + * On Tegra30 CPU0 can't be power-gated while secondary CPUs + * are active because it gates the whole CPU cluster. + */ + if (cpu != 0 || index != TEGRA_C7 || tegra_get_chip_id() != TEGRA30) + return index; + + if (!IS_ENABLED(CONFIG_PM_SLEEP) || num_online_cpus() > 1) + index = TEGRA_C1; + else + index = TEGRA_CC6; + + if (drv->states[index].disabled || dev->states_usage[index].disable) + index = -1; + + return index; +} + +static int tegra_cpuidle_enter(struct cpuidle_device *dev, + struct cpuidle_driver *drv, + int index) +{ + unsigned int cpu = cpu_logical_map(dev->cpu); + int err; + + index = tegra_cpuidle_adjust_state_index(dev, drv, index, cpu); + if (index < 0) + return index; + + if (index == TEGRA_C1) + err = arm_cpuidle_simple_enter(dev, drv, index); + else + err = tegra_cpuidle_state_enter(dev, index, cpu); + + WARN_ONCE(err && (err != -EINTR || index != TEGRA_CC6), + "cpu%u failed to enter idle state %d err: %d\n", + cpu, index, err); + + return err ? -1 : index; +} + +static void tegra114_enter_s2idle(struct cpuidle_device *dev, + struct cpuidle_driver *drv, + int index) +{ + tegra_cpuidle_enter(dev, drv, index); +} + +static struct cpuidle_driver tegra_idle_driver = { + .name = "tegra_idle", + .states = { + [TEGRA_C1] = ARM_CPUIDLE_WFI_STATE_PWR(600), + [TEGRA_C7] = { + .enter = tegra_cpuidle_enter, + .exit_latency = 2000, + .target_residency = 2200, + .power_usage = 100, + .flags = CPUIDLE_FLAG_TIMER_STOP, + .name = "C7", + .desc = "CPU core powered off", + }, + [TEGRA_CC6] = { + .enter = tegra_cpuidle_enter, + .exit_latency = 5000, + .target_residency = 10000, + .power_usage = 0, + .flags = CPUIDLE_FLAG_TIMER_STOP | + CPUIDLE_FLAG_COUPLED, + .name = "CC6", + .desc = "CPU cluster powered off", + }, + }, + .state_count = 3, + .safe_state_index = TEGRA_C1, +}; + +/* + * Tegra20 HW appears to have a bug such that PCIe device interrupts, whether + * they are legacy IRQs or MSI, are lost when CC6 is enabled. To work around + * this, simply disable CC6 if the PCI driver and DT node are both enabled. + */ +void tegra_cpuidle_pcie_irqs_in_use(void) +{ + if (tegra_idle_driver.states[TEGRA_CC6].disabled || + tegra_get_chip_id() != TEGRA20) + return; + + pr_info("disabling CC6 state, since PCIe IRQs are in use\n"); + tegra_idle_driver.states[TEGRA_CC6].disabled = true; +} + +static void tegra_cpuidle_setup_tegra114_c7_state(void) +{ + struct cpuidle_state *s = &tegra_idle_driver.states[TEGRA_C7]; + + s->enter_s2idle = tegra114_enter_s2idle; + s->target_residency = 1000; + s->exit_latency = 500; +} + +static int tegra_cpuidle_probe(struct platform_device *pdev) +{ + /* + * Required suspend-resume functionality, which is provided by the + * Tegra-arch core and PMC driver, is unavailable if PM-sleep option + * is disabled. + */ + if (!IS_ENABLED(CONFIG_PM_SLEEP)) { + if (!tegra_cpuidle_using_firmware()) + tegra_idle_driver.states[TEGRA_C7].disabled = true; + + tegra_idle_driver.states[TEGRA_CC6].disabled = true; + } + + /* + * Generic WFI state (also known as C1 or LP3) and the coupled CPU + * cluster power-off (CC6 or LP2) states are common for all Tegra SoCs. + */ + switch (tegra_get_chip_id()) { + case TEGRA20: + /* Tegra20 isn't capable to power-off individual CPU cores */ + tegra_idle_driver.states[TEGRA_C7].disabled = true; + break; + case TEGRA30: + tegra_idle_driver.states[TEGRA_CC6].disabled = true; + break; + case TEGRA114: + case TEGRA124: + tegra_cpuidle_setup_tegra114_c7_state(); + + /* coupled CC6 (LP2) state isn't implemented yet */ + tegra_idle_driver.states[TEGRA_CC6].disabled = true; + break; + default: + return -EINVAL; + } + + return cpuidle_register(&tegra_idle_driver, cpu_possible_mask); +} + +static struct platform_driver tegra_cpuidle_driver = { + .probe = tegra_cpuidle_probe, + .driver = { + .name = "tegra-cpuidle", + }, +}; +builtin_platform_driver(tegra_cpuidle_driver); diff --git a/include/soc/tegra/cpuidle.h b/include/soc/tegra/cpuidle.h index f758808342b6..5665975015d8 100644 --- a/include/soc/tegra/cpuidle.h +++ b/include/soc/tegra/cpuidle.h @@ -6,8 +6,12 @@ #ifndef __SOC_TEGRA_CPUIDLE_H__ #define __SOC_TEGRA_CPUIDLE_H__ +#ifdef CONFIG_ARM_TEGRA_CPUIDLE +void tegra_cpuidle_pcie_irqs_in_use(void); +#else static inline void tegra_cpuidle_pcie_irqs_in_use(void) { } +#endif #endif /* __SOC_TEGRA_CPUIDLE_H__ */ From patchwork Sun Sep 29 17:59:49 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Dmitry Osipenko X-Patchwork-Id: 11165823 Return-Path: Received: from mail.kernel.org (pdx-korg-mail-1.web.codeaurora.org [172.30.200.123]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id 649CF14DB for ; Sun, 29 Sep 2019 18:00:23 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.kernel.org (Postfix) with ESMTP id 42EE921882 for ; Sun, 29 Sep 2019 18:00:23 +0000 (UTC) Authentication-Results: mail.kernel.org; dkim=pass (2048-bit key) header.d=gmail.com header.i=@gmail.com header.b="eceYAUFZ" Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1729451AbfI2SAU (ORCPT ); Sun, 29 Sep 2019 14:00:20 -0400 Received: from mail-lj1-f194.google.com ([209.85.208.194]:38957 "EHLO mail-lj1-f194.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1729421AbfI2SAU (ORCPT ); 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[94.29.32.67]) by smtp.gmail.com with ESMTPSA id y3sm2355511lfh.97.2019.09.29.11.00.17 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sun, 29 Sep 2019 11:00:17 -0700 (PDT) From: Dmitry Osipenko To: Thierry Reding , Jonathan Hunter , Peter De Schrijver , "Rafael J. Wysocki" , Daniel Lezcano Cc: linux-pm@vger.kernel.org, linux-tegra@vger.kernel.org, linux-kernel@vger.kernel.org Subject: [PATCH v5 11/14] cpuidle: tegra: Support CPU cluster power-down state on Tegra30 Date: Sun, 29 Sep 2019 20:59:49 +0300 Message-Id: <20190929175952.22690-12-digetx@gmail.com> X-Mailer: git-send-email 2.23.0 In-Reply-To: <20190929175952.22690-1-digetx@gmail.com> References: <20190929175952.22690-1-digetx@gmail.com> MIME-Version: 1.0 Sender: linux-pm-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-pm@vger.kernel.org The new Tegra CPU Idle driver now has a unified code path for the coupled LP2/CC6 state, this allows to enable the deepest idling state on Tegra30 SoC where the whole CPU cluster is power-gated. Signed-off-by: Dmitry Osipenko --- drivers/cpuidle/cpuidle-tegra.c | 1 - 1 file changed, 1 deletion(-) diff --git a/drivers/cpuidle/cpuidle-tegra.c b/drivers/cpuidle/cpuidle-tegra.c index a926d2781227..a30a5e4fc863 100644 --- a/drivers/cpuidle/cpuidle-tegra.c +++ b/drivers/cpuidle/cpuidle-tegra.c @@ -325,7 +325,6 @@ static int tegra_cpuidle_probe(struct platform_device *pdev) tegra_idle_driver.states[TEGRA_C7].disabled = true; break; case TEGRA30: - tegra_idle_driver.states[TEGRA_CC6].disabled = true; break; case TEGRA114: case TEGRA124: From patchwork Sun Sep 29 17:59:50 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Dmitry Osipenko X-Patchwork-Id: 11165825 Return-Path: Received: from mail.kernel.org (pdx-korg-mail-1.web.codeaurora.org [172.30.200.123]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id 9072C112B for ; Sun, 29 Sep 2019 18:00:23 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.kernel.org (Postfix) with ESMTP id 6E856218AC for ; Sun, 29 Sep 2019 18:00:23 +0000 (UTC) Authentication-Results: mail.kernel.org; dkim=pass (2048-bit key) header.d=gmail.com header.i=@gmail.com header.b="U/N9s7GG" Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1729471AbfI2SAW (ORCPT ); Sun, 29 Sep 2019 14:00:22 -0400 Received: from mail-lf1-f67.google.com ([209.85.167.67]:36380 "EHLO mail-lf1-f67.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1729445AbfI2SAV (ORCPT ); Sun, 29 Sep 2019 14:00:21 -0400 Received: by mail-lf1-f67.google.com with SMTP id x80so5337212lff.3; Sun, 29 Sep 2019 11:00:19 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=FUprcdsgQIcCjuXx7+bJHEM4hFxUfD9RPhaB/mNFrSI=; b=U/N9s7GGO+CUwsUEn6edvJBI9YsAHht+y06AVHFaf3/WndLmxtjG+CRm6Y++EK8TXE SJVbQmIyPjnmPayODAii8e7DkZE3Kju5cgZjws4G0Bb83moSMOZqFakxjXkHdWcvgSfS aCTdaglXOazdSqBoi+V67+MJJPrQCEbJl6oq6zKCyFkpCfaovq4QwqQPQ/0OedwmrGXl DkP2snylLwgU+onbpI9Yc/7Piy0Bw+vrdMwi2baFVV3Sgmg+oXQvubYPobXz6jX+IWVA 9O1BG+XmhNNYiv03oqq2UN+MhQmpcoCYoFwPuyKcYxkwVzzNV1izC5VIKB77iBO37Eiu GwmQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=FUprcdsgQIcCjuXx7+bJHEM4hFxUfD9RPhaB/mNFrSI=; b=hopNTyliYmqbRrpt1xzH88WlEO8JS+MeAK/m3jkVSkD2US4s661ZZnT6rgFIdHXLxj mVJvbrtcmkjvO8jRriiuBczOdR1WpHLcXQEOrAlDCRz6tEZzwFTZTraAsoDFX4t+meA6 Y6cWaAYHAZWIwtmGqsZUySIV6ROaMyNQc2D8AxKfqirB9lbVanHB0Cjh6/Dqbe87cCC2 Vd/5FU9osAQKvH5HDYmJrXAJVF+q0h80KOMWjhs977igzI3R7nP4xPqaoyrMKxrlNr1W QQX4RqFkduyQO7FC5WgtEaG4L5LOtT87mF1IkxQ9QWafFadjmue64rkEfhly/r/XUFw/ HMRw== X-Gm-Message-State: APjAAAVR3i37hIJyK96C80mwSqcnjkfdujUjnaBghZp4TDXTnYVm//3C DFh4JgnUk2pZPLxw4gknicY= X-Google-Smtp-Source: APXvYqwg6ETLEflxh8XdeUiL4/CI3v/ukiUSHL3pcduh2+viBq5yErQpxtXpfV5sENpmMsB0CaZSrQ== X-Received: by 2002:a19:7d55:: with SMTP id y82mr8963163lfc.106.1569780019170; Sun, 29 Sep 2019 11:00:19 -0700 (PDT) Received: from localhost.localdomain (ppp94-29-32-67.pppoe.spdop.ru. [94.29.32.67]) by smtp.gmail.com with ESMTPSA id y3sm2355511lfh.97.2019.09.29.11.00.18 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sun, 29 Sep 2019 11:00:18 -0700 (PDT) From: Dmitry Osipenko To: Thierry Reding , Jonathan Hunter , Peter De Schrijver , "Rafael J. Wysocki" , Daniel Lezcano Cc: linux-pm@vger.kernel.org, linux-tegra@vger.kernel.org, linux-kernel@vger.kernel.org Subject: [PATCH v5 12/14] ARM: tegra: Create simple platform device for cpuidle driver Date: Sun, 29 Sep 2019 20:59:50 +0300 Message-Id: <20190929175952.22690-13-digetx@gmail.com> X-Mailer: git-send-email 2.23.0 In-Reply-To: <20190929175952.22690-1-digetx@gmail.com> References: <20190929175952.22690-1-digetx@gmail.com> MIME-Version: 1.0 Sender: linux-pm-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-pm@vger.kernel.org The new CPUIDLE driver now is a proper platform driver, hence it needs a platform device in order to be functional. Register the platform device, like we do that for the CPUFreq driver. Note that on some Tegra114(124) devices PSCI may be used for the CPU hotplugging and CPUIDLE driver doesn't support that case, thus CPUIDLE device won't be registered if PCSI presents. Signed-off-by: Dmitry Osipenko --- arch/arm/mach-tegra/tegra.c | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/arch/arm/mach-tegra/tegra.c b/arch/arm/mach-tegra/tegra.c index d9237769a37c..f1ce2857a251 100644 --- a/arch/arm/mach-tegra/tegra.c +++ b/arch/arm/mach-tegra/tegra.c @@ -36,6 +36,7 @@ #include #include #include +#include #include #include "board.h" @@ -92,6 +93,9 @@ static void __init tegra_dt_init_late(void) if (IS_ENABLED(CONFIG_ARCH_TEGRA_2x_SOC) && of_machine_is_compatible("nvidia,tegra20")) platform_device_register_simple("tegra20-cpufreq", -1, NULL, 0); + + if (IS_ENABLED(CONFIG_ARM_TEGRA_CPUIDLE) && !psci_smp_available()) + platform_device_register_simple("tegra-cpuidle", -1, NULL, 0); } static const char * const tegra_dt_board_compat[] = { From patchwork Sun Sep 29 17:59:51 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Dmitry Osipenko X-Patchwork-Id: 11165827 Return-Path: Received: from mail.kernel.org (pdx-korg-mail-1.web.codeaurora.org [172.30.200.123]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id 55AC014DB for ; Sun, 29 Sep 2019 18:00:43 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.kernel.org (Postfix) with ESMTP id 32B1621882 for ; Sun, 29 Sep 2019 18:00:43 +0000 (UTC) Authentication-Results: mail.kernel.org; dkim=pass (2048-bit key) header.d=gmail.com header.i=@gmail.com header.b="Ww65hc4c" Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1729488AbfI2SAY (ORCPT ); Sun, 29 Sep 2019 14:00:24 -0400 Received: from mail-lj1-f195.google.com ([209.85.208.195]:36487 "EHLO mail-lj1-f195.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1729452AbfI2SAW (ORCPT ); Sun, 29 Sep 2019 14:00:22 -0400 Received: by mail-lj1-f195.google.com with SMTP id v24so7113808ljj.3; Sun, 29 Sep 2019 11:00:20 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=iBiJ0G4nRszlIbKqT979ZgjozfbwgChkkqHAh8XRzzc=; b=Ww65hc4c5+I5AL++3C23SFXEdnmCzAxIk71g267k94M+ovQ/kxXVYCw6N4YuNJ8sUQ MZ1xWOTOEuGAkSLw/5uO2olSYVE9Z7xWRez5ic0BJKENuYKBom41zVzqgumFZHaETKke PDR9V660RO4cVNs7Dt38Xv6rX32FgrP7E4wvvKwiG1+PLFUoGQSOoWl7UxrFMYSfpH+3 lQ8DmmOm7/8iT6ao7nTGDvmy/WPQkRh64MTvK01MHnF96uCMDnUzo9OhHJTWTS18PMMm eMFs434J1MdECZSXD95OkacS1JboF8PX6e13zxxVMl+yUDRve9TnR4KKrGeKKRdMMdKn 5Ibg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=iBiJ0G4nRszlIbKqT979ZgjozfbwgChkkqHAh8XRzzc=; b=bjcLnCnKSCH/dUtDj7fTcTpsV9wibnPNZheoWXay3nGXvwuKgdfvbP690ZefE386Yy ZfKpLgSF0ALqfbWcv294PeM8uEKJE1Ywdx793q/Kvqm0M96WlrBh70HDDMtZRN9diEbx AQlR1c4NiUbxuX3aflrnScW0h4HtHUt8yLScGSTx/icFzaaG48dkoeCrmOUmSgxdS7X0 BosRljuQyxi+eIGrTdX0BDzNx9V2lXaZcnNi6Q1pU2WEYE6KwZbQKPb+LGQCGhYpLmQ/ iU2a/NNEcxtWzJWHHMjl8Vgp7rCz0nVEf4mcPYT7FyFsyxGgV9DBPeRn3z+RXS1Wc9xN GGqA== X-Gm-Message-State: APjAAAULHRhdy8ubgdWss5++0RLnADBxR4rG0Nadbvix09PeBVJLY2ED NeKqxriAFfzahpCP6+1mxkQ= X-Google-Smtp-Source: APXvYqx2ANqJ1sgcatHsXZfvbV1+M89+2YvovJKWBv4cg1bts33OskA18fm/W7rfurwe02I+MzQtJw== X-Received: by 2002:a2e:8052:: with SMTP id p18mr9182479ljg.198.1569780020068; Sun, 29 Sep 2019 11:00:20 -0700 (PDT) Received: from localhost.localdomain (ppp94-29-32-67.pppoe.spdop.ru. [94.29.32.67]) by smtp.gmail.com with ESMTPSA id y3sm2355511lfh.97.2019.09.29.11.00.19 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sun, 29 Sep 2019 11:00:19 -0700 (PDT) From: Dmitry Osipenko To: Thierry Reding , Jonathan Hunter , Peter De Schrijver , "Rafael J. Wysocki" , Daniel Lezcano Cc: linux-pm@vger.kernel.org, linux-tegra@vger.kernel.org, linux-kernel@vger.kernel.org Subject: [PATCH v5 13/14] ARM: multi_v7_defconfig: Enable Tegra cpuidle driver Date: Sun, 29 Sep 2019 20:59:51 +0300 Message-Id: <20190929175952.22690-14-digetx@gmail.com> X-Mailer: git-send-email 2.23.0 In-Reply-To: <20190929175952.22690-1-digetx@gmail.com> References: <20190929175952.22690-1-digetx@gmail.com> MIME-Version: 1.0 Sender: linux-pm-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-pm@vger.kernel.org The Tegra CPU Idle driver was moved out into driver/cpuidle/ directory and it is now a proper platform driver. Signed-off-by: Dmitry Osipenko --- arch/arm/configs/multi_v7_defconfig | 1 + 1 file changed, 1 insertion(+) diff --git a/arch/arm/configs/multi_v7_defconfig b/arch/arm/configs/multi_v7_defconfig index 13ba53286901..539bb60069ee 100644 --- a/arch/arm/configs/multi_v7_defconfig +++ b/arch/arm/configs/multi_v7_defconfig @@ -110,6 +110,7 @@ CONFIG_CPU_IDLE=y CONFIG_ARM_CPUIDLE=y CONFIG_ARM_ZYNQ_CPUIDLE=y CONFIG_ARM_EXYNOS_CPUIDLE=y +CONFIG_ARM_TEGRA_CPUIDLE=y CONFIG_KERNEL_MODE_NEON=y CONFIG_RASPBERRYPI_FIRMWARE=y CONFIG_TRUSTED_FOUNDATIONS=y From patchwork Sun Sep 29 17:59:52 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Dmitry Osipenko X-Patchwork-Id: 11165829 Return-Path: Received: from mail.kernel.org (pdx-korg-mail-1.web.codeaurora.org [172.30.200.123]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id 811D01747 for ; Sun, 29 Sep 2019 18:00:43 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.kernel.org (Postfix) with ESMTP id 5F57620815 for ; Sun, 29 Sep 2019 18:00:43 +0000 (UTC) Authentication-Results: mail.kernel.org; dkim=pass (2048-bit key) header.d=gmail.com header.i=@gmail.com header.b="pns5X4J1" Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1729491AbfI2SAY (ORCPT ); Sun, 29 Sep 2019 14:00:24 -0400 Received: from mail-lf1-f65.google.com ([209.85.167.65]:36380 "EHLO mail-lf1-f65.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1729458AbfI2SAX (ORCPT ); Sun, 29 Sep 2019 14:00:23 -0400 Received: by mail-lf1-f65.google.com with SMTP id x80so5337260lff.3; Sun, 29 Sep 2019 11:00:21 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=0lHQRX/0nej0WuuBggHgivhPJMPJeSRnbCLnwWmZEkg=; b=pns5X4J1b/chVzmWCaJ9roJwzlzzxfud3orlNH6RV0Yn6ucwHyR1wBJ7087vpaXc/+ z4nZv3cVNoByARdqV2wJ2JFl7rlhVVmwFgMbgeP4udRh+GLDETUFDwP4rnG8e3MTthrq zbzmr3ca5K9TgKget+lyUbU+vlHYOc+NCVwjLgn1iJuCgAhGqOlBLOJLo1qnLcxUcDty wWQG2O1mACI2KjcfXQ5+nG0SzPSdn66CuqfK8uYn8F+oYTq4uC6ZFUWBzpsEqqAE4BZJ 1boP7tN02u6Ck/db1qaMRagCKX4IS174XEG5G3wXDWgDYUYMToheIavQpM1sbcDizJ19 hOzw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=0lHQRX/0nej0WuuBggHgivhPJMPJeSRnbCLnwWmZEkg=; b=DK0IfckSmSv3u8yI0Q3pI7VevfvFNIulWsY2q6IaccEIxlxqDtZEuVczXwZBY/Uz18 YlWc1kfudzojO1BS6EECX3sLqRSbeHRQAcrqtmWu4XXe92E5uVDCIvUOiHN8N0WW3wnP 2LWkvswOy5ZjpAzfbUjPsnOdTZDL2+wP5xWT2slKvMA5pYVVxmcIrUmj+/2dVkzmKYMc 4p/OLe7LuGSi/M2nr7l87DK8HMuQebTYv1pev8umaufipP3ByWzDKsBPbxnwtyAtovW8 L79fV+MPshL20CPOmA6rQx4TUmoYSMMvPq3K4552Hg2MOh5ZSVQkPATITb4drhGJRv/H 4t2Q== X-Gm-Message-State: APjAAAXDEEhjaiFfWLWa+MwUMuawPg1Or6E5l/4qrh8zaby6h9X2MaIW 0FCO7kjP5ZZBueFayMXh0Ls= X-Google-Smtp-Source: APXvYqwpIJmswVjes73DIsYbkyF58y9adlF3nmlGhQk2yZfZIFvujd7TeVW0RB4eCRfh2ISuiZR+dQ== X-Received: by 2002:ac2:5091:: with SMTP id f17mr9034870lfm.107.1569780020951; Sun, 29 Sep 2019 11:00:20 -0700 (PDT) Received: from localhost.localdomain (ppp94-29-32-67.pppoe.spdop.ru. [94.29.32.67]) by smtp.gmail.com with ESMTPSA id y3sm2355511lfh.97.2019.09.29.11.00.20 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sun, 29 Sep 2019 11:00:20 -0700 (PDT) From: Dmitry Osipenko To: Thierry Reding , Jonathan Hunter , Peter De Schrijver , "Rafael J. Wysocki" , Daniel Lezcano Cc: linux-pm@vger.kernel.org, linux-tegra@vger.kernel.org, linux-kernel@vger.kernel.org Subject: [PATCH v5 14/14] ARM: tegra: Enable Tegra cpuidle driver in tegra_defconfig Date: Sun, 29 Sep 2019 20:59:52 +0300 Message-Id: <20190929175952.22690-15-digetx@gmail.com> X-Mailer: git-send-email 2.23.0 In-Reply-To: <20190929175952.22690-1-digetx@gmail.com> References: <20190929175952.22690-1-digetx@gmail.com> MIME-Version: 1.0 Sender: linux-pm-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-pm@vger.kernel.org The Tegra CPU Idle driver was moved out into driver/cpuidle/ directory and it is now a proper platform driver. Signed-off-by: Dmitry Osipenko --- arch/arm/configs/tegra_defconfig | 1 + 1 file changed, 1 insertion(+) diff --git a/arch/arm/configs/tegra_defconfig b/arch/arm/configs/tegra_defconfig index 8f5c6a5b444c..9a2f11a780a8 100644 --- a/arch/arm/configs/tegra_defconfig +++ b/arch/arm/configs/tegra_defconfig @@ -25,6 +25,7 @@ CONFIG_CPU_FREQ=y CONFIG_CPU_FREQ_DEFAULT_GOV_ONDEMAND=y CONFIG_CPUFREQ_DT=y CONFIG_CPU_IDLE=y +CONFIG_ARM_TEGRA_CPUIDLE=y CONFIG_VFP=y CONFIG_NEON=y CONFIG_TRUSTED_FOUNDATIONS=y