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Tue, 1 Oct 2019 12:54:44 +0000 (GMT) From: Lukasz Luba To: devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-pm@vger.kernel.org, linux-samsung-soc@vger.kernel.org, linux-arm-kernel@lists.infradead.org Cc: b.zolnierkie@samsung.com, krzk@kernel.org, kgene@kernel.org, mark.rutland@arm.com, cw00.choi@samsung.com, kyungmin.park@samsung.com, m.szyprowski@samsung.com, s.nawrocki@samsung.com, myungjoo.ham@samsung.com, robh+dt@kernel.org, willy.mh.wolff.ml@gmail.com, Lukasz Luba Subject: [PATCH v2 1/4] dt-bindings: memory-controllers: Add Exynos5422 DMC interrupts description Date: Tue, 1 Oct 2019 14:54:33 +0200 Message-Id: <20191001125436.24086-2-l.luba@partner.samsung.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20191001125436.24086-1-l.luba@partner.samsung.com> X-Brightmail-Tracker: H4sIAAAAAAAAA0WSbUhTYRTHe+7d3b0OV7er6KGkaBSVkGb04YlejaB9sJIg6AWpqbclObXd rMygGWWlW5qjMumVNGttueYaalq5TWdGrjKa9oa0MsslyEwKluS8Vt9+53/+538ODw9DcnZq BpOVs5/X5qiyFVKZxNH+q2vRuRRj2mJrP+B7lXUU9o18ofBVdxeFy/yDJPZ6rTR+dixA4ze6 OGzzv6Zwd9MlKQ4a3AhXeh8S2OJ+T+Ma3wsCvy26JcUnWtw0dgVOUni04yNaM11pvmJGysaq 97TSZjotVdZXH1W2DjUTyjN2E1IGbbNS6e2yFZl8dtYBXpu4apdsjzPwksyrjTzkszyidcgm K0ERDLBLoWi0RVKCZAzH3kJQ+62REIsRBMdLfUgsggj09n7p35GL/X5JmDm2FsGn+qn/Jrqs zVQJYhgpmwANpn1hTzR7A8Goa3vYQ7IOAvpMo1S4EcVmwuDwp4lQCTsPPD8tZJjl7Gpor/xN istmwx3r4wmOYNfAzZf3qXAQsJ00BF1jlGhaBz02Ly1yFHzz2Cc5Dp4a9RKRBdAZriORj4C/ 7PKkZzm4PC8mjibZhVDXlCjKyVD1+QMdloGdCj3fp4dlchwrHBdIUZbDqWJOdC8Au/45IXIM 1JrPT4YrYcDglorPY0TgMJeS5Wh21f9l1xAyoVg+X9CoeWFJDn8wQVBphPwcdUJGrsaGxv/S 0zHPSANqCqU7EcsgRaS8/OvZNI5SHRAKNE4EDKmIlq8IVaRx8kxVwWFem7tTm5/NC040k5Eo YuWFU/p2cKxatZ/fy/N5vPZvl2AiZuhQ0mbvL1tZoJW3VHQMro1pI4ZSn1jW9WoK1ZH+B9XI 2HR3Y3q3IY+RpX6J9cX7i8/H/Jjf5Y3ckt2XcXsgVDiknkY0r1f06V65is/pk6O3DW4YWTa8 I3fT4+65AxzOr2kLqVMaStNeR1Afte9Werhpu0ucvTVR5n1brxTM6dzSqpAIe1RJ8aRWUP0B DSxpUUcDAAA= X-Brightmail-Tracker: H4sIAAAAAAAAA+NgFprOIsWRmVeSWpSXmKPExsVy+t/xu7pTfCbHGqw8aGqxccZ6VovrX56z Wsw/co7Vov/xa2aL8+c3sFucbXrDbnGrQcZi0+NrrBaXd81hs/jce4TRYsb5fUwWa4/cZbdY ev0ik8XtxhVsFq17j7BbHH7Tzmrx7cQjRgdBjzXz1jB67Jx1l91j06pONo/NS+o9Dr7bw+TR t2UVo8fnTXIB7FF6NkX5pSWpChn5xSW2StGGFkZ6hpYWekYmlnqGxuaxVkamSvp2NimpOZll qUX6dgl6GYfeXGIuWM5TcX3tfvYGxk1cXYycHBICJhIznz1m6WLk4hASWMoocWT6LnaIhJjE pH3boWxhiT/XuthAbCGBT4wSmx8ANXBwsAnoSexYVQjSKyKwnFHi2Kq3zCAOs8ARJomjq68x gjQICyRJbF2zCcxmEVCVOP5jLTOIzStgL3Fsxl9miAXyEqs3HACzOQUcJJZd2soKscxeYsq+ 14wTGPkWMDKsYhRJLS3OTc8tNtIrTswtLs1L10vOz93ECIyUbcd+btnB2PUu+BCjAAejEg+v xfOJsUKsiWXFlbmHGCU4mJVEeG3+TIoV4k1JrKxKLcqPLyrNSS0+xGgKdNREZinR5HxgFOeV xBuaGppbWBqaG5sbm1koifN2CByMERJITyxJzU5NLUgtgulj4uCUamA0mOL7R6ZqaihP1Xqz vDwu8dJ/DneXe91Nt5EVEZuxJL7L7u9ai23Pi4/YhnAxsGUyXph+ZoME573zyrs/+dfu3XpG zq+iSuVJ1J/pZ1fsnOj1xOf70pcT2+Z0SfrK6eWofDvsvvP2aab4qGvbKuRstsvyHd3Bk2yq k3dLdabqi77/Zc2fmCcosRRnJBpqMRcVJwIAN+QHDqoCAAA= X-CMS-MailID: 20191001125444eucas1p2e4254acf8434e1fadf0e208dbe62b2d7 X-Msg-Generator: CA X-RootMTR: 20191001125444eucas1p2e4254acf8434e1fadf0e208dbe62b2d7 X-EPHeader: CA CMS-TYPE: 201P X-CMS-RootMailID: 20191001125444eucas1p2e4254acf8434e1fadf0e208dbe62b2d7 References: <20191001125436.24086-1-l.luba@partner.samsung.com> Sender: linux-pm-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-pm@vger.kernel.org Add description for optional interrupt lines. It provides a new operation mode, which uses internal performance counters interrupt when overflow. This is more reliable than using default polling mode implemented in devfreq. Signed-off-by: Lukasz Luba --- .../bindings/memory-controllers/exynos5422-dmc.txt | 10 ++++++++++ 1 file changed, 10 insertions(+) diff --git a/Documentation/devicetree/bindings/memory-controllers/exynos5422-dmc.txt b/Documentation/devicetree/bindings/memory-controllers/exynos5422-dmc.txt index 02aeb3b5a820..afc38aea6b1c 100644 --- a/Documentation/devicetree/bindings/memory-controllers/exynos5422-dmc.txt +++ b/Documentation/devicetree/bindings/memory-controllers/exynos5422-dmc.txt @@ -31,6 +31,13 @@ Required properties for DMC device for Exynos5422: The register offsets are in the driver code and specyfic for this SoC type. +Optional properties for DMC device for Exynos5422: +- interrupt-parent : The parent interrupt controller. +- interrupts : Contains the IRQ line numbers for the DMC internal performance + event counters. Align with specification of the interrupt line(s) in the + interrupt-parent controller. +- interrupt-names : List of IRQ names. + Example: ppmu_dmc0_0: ppmu@10d00000 { @@ -70,4 +77,7 @@ Example: device-handle = <&samsung_K3QF2F20DB>; vdd-supply = <&buck1_reg>; samsung,syscon-clk = <&clock>; + interrupt-parent = <&combiner>; + interrupts = <16 0>, <16 1>; + interrupt-names = "drex_0", "drex_1"; }; From patchwork Tue Oct 1 12:54:34 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Lukasz Luba X-Patchwork-Id: 11168703 Return-Path: Received: from mail.kernel.org (pdx-korg-mail-1.web.codeaurora.org [172.30.200.123]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id 2D52E14DB for ; Tue, 1 Oct 2019 12:55:11 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.kernel.org (Postfix) with ESMTP id 00D8E21A4C for ; Tue, 1 Oct 2019 12:55:11 +0000 (UTC) Authentication-Results: mail.kernel.org; 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Tue, 1 Oct 2019 12:54:45 +0000 (GMT) X-AuditID: cbfec7f2-54fff70000001175-9d-5d934c9622ab Received: from eusmtip1.samsung.com ( [203.254.199.221]) by eusmgms2.samsung.com (EUCPMTA) with SMTP id 63.D5.04117.59C439D5; Tue, 1 Oct 2019 13:54:45 +0100 (BST) Received: from AMDC3778.digital.local (unknown [106.120.51.20]) by eusmtip1.samsung.com (KnoxPortal) with ESMTPA id 20191001125444eusmtip13eee4dda350294e71d313d53522657ab~JhxidadUa2359723597eusmtip1M; Tue, 1 Oct 2019 12:54:44 +0000 (GMT) From: Lukasz Luba To: devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-pm@vger.kernel.org, linux-samsung-soc@vger.kernel.org, linux-arm-kernel@lists.infradead.org Cc: b.zolnierkie@samsung.com, krzk@kernel.org, kgene@kernel.org, mark.rutland@arm.com, cw00.choi@samsung.com, kyungmin.park@samsung.com, m.szyprowski@samsung.com, s.nawrocki@samsung.com, myungjoo.ham@samsung.com, robh+dt@kernel.org, willy.mh.wolff.ml@gmail.com, Lukasz Luba Subject: [PATCH v2 2/4] ARM: dts: exynos: Add interrupt to DMC controller in Exynos5422 Date: Tue, 1 Oct 2019 14:54:34 +0200 Message-Id: <20191001125436.24086-3-l.luba@partner.samsung.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20191001125436.24086-1-l.luba@partner.samsung.com> X-Brightmail-Tracker: H4sIAAAAAAAAA+NgFtrMKsWRmVeSWpSXmKPExsWy7djP87rTfCbHGjyYz2yxccZ6VovrX56z Wsw/co7Vov/xa2aL8+c3sFucbXrDbnGrQcZi0+NrrBaXd81hs/jce4TRYsb5fUwWa4/cZbdY ev0ik8XtxhVsFq17j7BbHH7Tzmrx7cQjRgdBjzXz1jB67Jx1l91j06pONo/NS+o9Dr7bw+TR t2UVo8fnTXIB7FFcNimpOZllqUX6dglcGV+/bmIt+MZeMXPGbpYGxpNsXYycHBICJhI9F5qY uxi5OIQEVjBK7L30lAXC+cIocWLdCSYI5zOjxPdvn4BaOMBani0qgYgvZ5TYuvEfI1zHjAlv WUCK2AT0JHasKgRZISKwmFHi2+EokBpmgW1MEg9WfWMFSQgLREp83PmTHcRmEVCVWNmzCewm XgF7ifPXr7NA3CcvsXrDAWYQm1PAQWLZpa2sIIMkBM6xS/y7/JERoshFYs75l8wQtrDEq+Nb 2CFsGYnTk3ugBhVLNPQuhKqvkXjcPxeqxlri8PGLrCBHMwtoSqzfpQ/xpKPEpod8ECafxI23 giDFzEDmpG3TmSHCvBIdbUIQMzQktvRcYIKwxSSWr5kGNdtD4unTPmh4TmaUmHR6DvsERvlZ CLsWMDKuYhRPLS3OTU8tNsxLLdcrTswtLs1L10vOz93ECExKp/8d/7SD8eulpEOMAhyMSjy8 Fs8nxgqxJpYVV+YeYpTgYFYS4bX5MylWiDclsbIqtSg/vqg0J7X4EKM0B4uSOG81w4NoIYH0 xJLU7NTUgtQimCwTB6dUA2PLFJXqz1cW2b5V+yu++PdFjld3Ft3UTaqr0hXQbnM+nJ+oUBsa /WDdi4RU419vFSfFCLnsFlF42Rs61yriYt+b00dv/F2+4XT64aMurwyVJrza9u/g3o1n3+6N kb7v0GC7teKZoeBKJv8tcyO0zB5G+Dgu2bk+3UZ3SWJNGVegZoiehjFH7GQlluKMREMt5qLi RACj95jYRgMAAA== X-Brightmail-Tracker: H4sIAAAAAAAAA+NgFprOIsWRmVeSWpSXmKPExsVy+t/xu7pTfSbHGvSeUbfYOGM9q8X1L89Z LeYfOcdq0f/4NbPF+fMb2C3ONr1ht7jVIGOx6fE1VovLu+awWXzuPcJoMeP8PiaLtUfuslss vX6RyeJ24wo2i9a9R9gtDr9pZ7X4duIRo4Ogx5p5axg9ds66y+6xaVUnm8fmJfUeB9/tYfLo 27KK0ePzJrkA9ig9m6L80pJUhYz84hJbpWhDCyM9Q0sLPSMTSz1DY/NYKyNTJX07m5TUnMyy 1CJ9uwS9jK9fN7EWfGOvmDljN0sD40m2LkYODgkBE4lni0q6GLk4hASWMkosmt/D3sXICRQX k5i0bzuULSzx51oXG0TRJ0aJU9fOMII0swnoSexYVQgSFxFYzihxbNVbZhCHWeAIk8TR1dcY QbqFBcIlftw6wARiswioSqzs2cQGYvMK2Eucv36dBWKDvMTqDQeYQWxOAQeJZZe2soLYQkA1 U/a9ZpzAyLeAkWEVo0hqaXFuem6xkV5xYm5xaV66XnJ+7iZGYKRsO/Zzyw7GrnfBhxgFOBiV eHgtnk+MFWJNLCuuzD3EKMHBrCTCa/NnUqwQb0piZVVqUX58UWlOavEhRlOgoyYyS4km5wOj OK8k3tDU0NzC0tDc2NzYzEJJnLdD4GCMkEB6YklqdmpqQWoRTB8TB6dUA2Nc++L96eUx/zZF 3KxfGlmdfLy6Zdra0Mvh6f96jS9uvpj45p+Ex9Mb7UvjeY+mKopH2N2OfOyXMd1ly8cHAgkK K/a9+6uh69uTfajEZ/qDNYuKHj6QsXyy5tP7xMYupmvrHZeyt0pypsdGNL/jE+DyNP6ZepPR ua3rw6offgZKxXIXHSb2rlZiKc5INNRiLipOBADmPvGqqgIAAA== X-CMS-MailID: 20191001125445eucas1p21ea21a92cec96d660994d8d7f91128e0 X-Msg-Generator: CA X-RootMTR: 20191001125445eucas1p21ea21a92cec96d660994d8d7f91128e0 X-EPHeader: CA CMS-TYPE: 201P X-CMS-RootMailID: 20191001125445eucas1p21ea21a92cec96d660994d8d7f91128e0 References: <20191001125436.24086-1-l.luba@partner.samsung.com> Sender: linux-pm-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-pm@vger.kernel.org Add interrupt to Dynamic Memory Controller in Exynos5422 and Odroid XU3-family boards. It will be used instead of devfreq polling mode governor. The interrupt is connected to performance counters private for DMC, which might track utilisation of the memory channels. Signed-off-by: Lukasz Luba --- arch/arm/boot/dts/exynos5420.dtsi | 3 +++ 1 file changed, 3 insertions(+) diff --git a/arch/arm/boot/dts/exynos5420.dtsi b/arch/arm/boot/dts/exynos5420.dtsi index ac49373baae7..45f63cd82e56 100644 --- a/arch/arm/boot/dts/exynos5420.dtsi +++ b/arch/arm/boot/dts/exynos5420.dtsi @@ -240,6 +240,9 @@ dmc: memory-controller@10c20000 { compatible = "samsung,exynos5422-dmc"; reg = <0x10c20000 0x100>, <0x10c30000 0x100>; + interrupt-parent = <&combiner>; + interrupts = <16 0>, <16 1>; + interrupt-names = "drex_0", "drex_1"; clocks = <&clock CLK_FOUT_SPLL>, <&clock CLK_MOUT_SCLK_SPLL>, <&clock CLK_FF_DOUT_SPLL2>, From patchwork Tue Oct 1 12:54:35 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Lukasz Luba X-Patchwork-Id: 11168701 Return-Path: Received: from mail.kernel.org (pdx-korg-mail-1.web.codeaurora.org [172.30.200.123]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id 22D991709 for ; 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Tue, 1 Oct 2019 12:54:46 +0000 (GMT) X-AuditID: cbfec7f4-ae1ff700000010d5-6e-5d934c966cc2 Received: from eusmtip1.samsung.com ( [203.254.199.221]) by eusmgms1.samsung.com (EUCPMTA) with SMTP id 47.6D.04166.69C439D5; Tue, 1 Oct 2019 13:54:46 +0100 (BST) Received: from AMDC3778.digital.local (unknown [106.120.51.20]) by eusmtip1.samsung.com (KnoxPortal) with ESMTPA id 20191001125445eusmtip13bcde73093ffe8d4bfc91c2e04f40688~JhxjLfqXw2414524145eusmtip1S; Tue, 1 Oct 2019 12:54:45 +0000 (GMT) From: Lukasz Luba To: devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-pm@vger.kernel.org, linux-samsung-soc@vger.kernel.org, linux-arm-kernel@lists.infradead.org Cc: b.zolnierkie@samsung.com, krzk@kernel.org, kgene@kernel.org, mark.rutland@arm.com, cw00.choi@samsung.com, kyungmin.park@samsung.com, m.szyprowski@samsung.com, s.nawrocki@samsung.com, myungjoo.ham@samsung.com, robh+dt@kernel.org, willy.mh.wolff.ml@gmail.com, Lukasz Luba Subject: [PATCH v2 3/4] ARM: dts: exynos: map 0x10000 SFR instead of 0x100 in DMC Exynos5422 Date: Tue, 1 Oct 2019 14:54:35 +0200 Message-Id: <20191001125436.24086-4-l.luba@partner.samsung.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20191001125436.24086-1-l.luba@partner.samsung.com> X-Brightmail-Tracker: H4sIAAAAAAAAA+NgFtrCKsWRmVeSWpSXmKPExsWy7djPc7rTfCbHGtw/p2+xccZ6VovrX56z Wsw/co7Vov/xa2aL8+c3sFucbXrDbnGrQcZi0+NrrBaXd81hs/jce4TRYsb5fUwWa4/cZbdY ev0ik8XtxhVsFq17j7BbHH7Tzmrx7cQjRgdBjzXz1jB67Jx1l91j06pONo/NS+o9Dr7bw+TR t2UVo8fnTXIB7FFcNimpOZllqUX6dglcGcfa/7AXPGKv+NS7mbGBcTdbFyMnh4SAiUTXv+vs XYxcHEICKxglfn9/wQThfAFybj1khHA+M0ocnvuECablQNdfFojEckaJJSsOMMO1/Jm5GqiK g4NNQE9ix6pCkAYRgcWMEt8OR4HUMAtsY5J4sOobK0hCWCBO4s3DXWA2i4CqxJZV28GO4hWw lzj+9SAjxDZ5idUbQBZwcnAKOEgsu7SVFWSQhMApdomjcw4yQxS5SCw+sgaqQVji1fEt7BC2 jMTpyT0sEHaxREPvQqiaGonH/XOhaqwlDh+/yApyNLOApsT6XfoQYUeJL4tWg4UlBPgkbrwV BAkzA5mTtk1nhgjzSnS0CUFUa0hs6bkADR8xieVrprFDlHhItH5yg4TOZEaJn3fmskxglJ+F sGsBI+MqRvHU0uLc9NRio7zUcr3ixNzi0rx0veT83E2MwLR0+t/xLzsYd/1JOsQowMGoxMM7 4eXEWCHWxLLiytxDjBIczEoivDZ/JsUK8aYkVlalFuXHF5XmpBYfYpTmYFES561meBAtJJCe WJKanZpakFoEk2Xi4JRqYFyucmTKIv07Ks0xq5Uendd71bbrdXxoevxHpa7ggJrtAmutPHhV thukL9L4acj6ZMcBuZmsX/prpdymnrz7fw/D5AXd+mbhGq4ZoX3NchbPK455hx4vfZZgyJBd e8a3s4DXgMHE6eecwobJTgVH+b2cc1W2vtm8tT2j737yoxcdi25V5YfKK7EUZyQaajEXFScC AKc7d31HAwAA X-Brightmail-Tracker: H4sIAAAAAAAAA+NgFprOIsWRmVeSWpSXmKPExsVy+t/xu7rTfCbHGty/IGmxccZ6VovrX56z Wsw/co7Vov/xa2aL8+c3sFucbXrDbnGrQcZi0+NrrBaXd81hs/jce4TRYsb5fUwWa4/cZbdY ev0ik8XtxhVsFq17j7BbHH7Tzmrx7cQjRgdBjzXz1jB67Jx1l91j06pONo/NS+o9Dr7bw+TR t2UVo8fnTXIB7FF6NkX5pSWpChn5xSW2StGGFkZ6hpYWekYmlnqGxuaxVkamSvp2NimpOZll qUX6dgl6Gcfa/7AXPGKv+NS7mbGBcTdbFyMnh4SAicSBrr8sXYxcHEICSxklpra9ZYRIiElM 2redHcIWlvhzrYsNougTo8Tl+0+AEhwcbAJ6EjtWFYLERQSWM0ocW/WWGcRhFjjCJHF09TVG kCJhgRiJ7a0+IINYBFQltqzaDraZV8Be4vjXg1DL5CVWbzjADGJzCjhILLu0lRXEFgKqmbLv NeMERr4FjAyrGEVSS4tz03OLDfWKE3OLS/PS9ZLzczcxAiNl27Gfm3cwXtoYfIhRgINRiYd3 wsuJsUKsiWXFlbmHGCU4mJVEeG3+TIoV4k1JrKxKLcqPLyrNSS0+xGgKdNREZinR5HxgFOeV xBuaGppbWBqaG5sbm1koifN2CByMERJITyxJzU5NLUgtgulj4uCUamAMCZl05NWkG6u56w9d 5U6xOVoXfH+BKs9PuwaP2bM/5bY/vhKcMPPSNrnmRYUTm4OOPZupZxndWzb5dvHVpOXcKTf2 pHU/7LWd9rPI5ia72eWwOz+iRHWFWhZf3rTAuSUksm5Ckn7Fwqe9UvvXrZNRmmN2Neb2lBP1 bv++xXfv3Pq7WvdTImePEktxRqKhFnNRcSIA06hgvqoCAAA= X-CMS-MailID: 20191001125446eucas1p1fb2ad4c13feac8dfec8d5eeeeec0a64a X-Msg-Generator: CA X-RootMTR: 20191001125446eucas1p1fb2ad4c13feac8dfec8d5eeeeec0a64a X-EPHeader: CA CMS-TYPE: 201P X-CMS-RootMailID: 20191001125446eucas1p1fb2ad4c13feac8dfec8d5eeeeec0a64a References: <20191001125436.24086-1-l.luba@partner.samsung.com> Sender: linux-pm-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-pm@vger.kernel.org There is a need to access registers at address offset near 0x10000. These registers are private DMC performance counters, which might be used as interrupt trigger when overflow. Potential usage is to skip polling in devfreq framework and switch to interrupt managed bandwidth control. Signed-off-by: Lukasz Luba --- arch/arm/boot/dts/exynos5420.dtsi | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/arm/boot/dts/exynos5420.dtsi b/arch/arm/boot/dts/exynos5420.dtsi index 45f63cd82e56..ac6dc44dbe4d 100644 --- a/arch/arm/boot/dts/exynos5420.dtsi +++ b/arch/arm/boot/dts/exynos5420.dtsi @@ -239,7 +239,7 @@ dmc: memory-controller@10c20000 { compatible = "samsung,exynos5422-dmc"; - reg = <0x10c20000 0x100>, <0x10c30000 0x100>; + reg = <0x10c20000 0x10000>, <0x10c30000 0x10000>; interrupt-parent = <&combiner>; interrupts = <16 0>, <16 1>; interrupt-names = "drex_0", "drex_1"; From patchwork Tue Oct 1 12:54:36 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Lukasz Luba X-Patchwork-Id: 11168695 Return-Path: Received: from mail.kernel.org (pdx-korg-mail-1.web.codeaurora.org [172.30.200.123]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id 2BFE11709 for ; Tue, 1 Oct 2019 12:55:04 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.kernel.org (Postfix) with ESMTP id 0B02C21924 for ; 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Tue, 1 Oct 2019 12:54:47 +0000 (GMT) X-AuditID: cbfec7f4-ae1ff700000010d5-74-5d934c976bc7 Received: from eusmtip1.samsung.com ( [203.254.199.221]) by eusmgms1.samsung.com (EUCPMTA) with SMTP id 88.6D.04166.79C439D5; Tue, 1 Oct 2019 13:54:47 +0100 (BST) Received: from AMDC3778.digital.local (unknown [106.120.51.20]) by eusmtip1.samsung.com (KnoxPortal) with ESMTPA id 20191001125446eusmtip166329e9dd53f414cfb76fa84f768f1d1~Jhxj5eE3K2422124221eusmtip1-; Tue, 1 Oct 2019 12:54:46 +0000 (GMT) From: Lukasz Luba To: devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-pm@vger.kernel.org, linux-samsung-soc@vger.kernel.org, linux-arm-kernel@lists.infradead.org Cc: b.zolnierkie@samsung.com, krzk@kernel.org, kgene@kernel.org, mark.rutland@arm.com, cw00.choi@samsung.com, kyungmin.park@samsung.com, m.szyprowski@samsung.com, s.nawrocki@samsung.com, myungjoo.ham@samsung.com, robh+dt@kernel.org, willy.mh.wolff.ml@gmail.com, Lukasz Luba Subject: [PATCH v2 4/4] memory: samsung: exynos5422-dmc: Add support for interrupt from performance counters Date: Tue, 1 Oct 2019 14:54:36 +0200 Message-Id: <20191001125436.24086-5-l.luba@partner.samsung.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20191001125436.24086-1-l.luba@partner.samsung.com> X-Brightmail-Tracker: H4sIAAAAAAAAA0WSa0hTYRjH9+7s7JyJq+OSfNGRsLKyUivCXlLMIOhAfYgiCENs6UEtN21H LS/gDbVkZql5iUqzizZnrqWjTC0vNVHmSqGlNRINxLykTI3SrI5n1bff83/+z+3lJTFZE+5J xqoTGY1aGacQu4hMr79b/cqPlITvzO/Yjh5XNOLINj+Oo6rufhwVjU1iyGo1EMiSPUWg4Uw5 Mo69w9Fgy00xchR2A1RhbReihm47ge7b3grRh6w6Mcpt6yZQ11Q+jhZ7RkGoG62/rQf0sxt2 gjbqLovpJ/cy6I6ZViF9pUkHaIdxw1EizCU4iomLTWY0ASGnXWI+GxqxhMHEi1rHJMgEVREF QEJCag/MylkQFQAXUkbVAfg8u8sZzAM4OeUQ84EDwGXbJ2EBIFdLLHPBvF4LoN1cSfyraF2Y XjWJKX/4VHeeG+FO3QVwsSuM82CUSQhHdIs4l1hHqaGxt4HgWET5wMnRWsCxlNoPLSXtOL+f N6w3vMQ4llCh8MFAM841glQ/AbN+5RG86SB82PvRyevgF3OTk+Wwr0Qr4pmFmYV3AM/pcKzo ltMTBLvMb3FuaYzyhY0tAbx8ADomygn+4DXw/bQbJ2N/sNhUjvGyFF7Kk/HurbBJ+0bI83pY qy9zNqfhUk+Z80FLAMx5dVl0FXjf+D+sGgAd8GCSWFU0w+5WMxf8WaWKTVJH+0fGq4zgz1/q WzHPPwUty2c6AUUChav06sS1cBmuTGZTVJ0AkpjCXRq8XBwuk0YpU1IZTXyEJimOYTuBFylS eEjTBCOnZFS0MpE5xzAJjOZvVkhKPDNBjT6F7N3UkvvN/XACHdm71rQS6HXMfGJk+UXOj5lm rdX6xprmd+1WoUXyM7VN/3VmqfRlja/32o35s+RxuS1jX4T/6NC97fWzgo7N9h5b9ZbW+UM+ pXGuAkNh+oT8vrZmrkh1PSFQMJz+KCJIOGEK8erM3jtAV44PnXWzn9wRKlCI2Bjlrm2YhlX+ Bv0GH+VHAwAA X-Brightmail-Tracker: H4sIAAAAAAAAA+NgFprOIsWRmVeSWpSXmKPExsVy+t/xu7rTfSbHGqw9w2mxccZ6VovrX56z Wsw/co7Vov/xa2aL8+c3sFucbXrDbnGrQcZi0+NrrBaXd81hs/jce4TRYsb5fUwWa4/cZbdY ev0ik8XtxhVsFq17j7BbHH7Tzmrx7cQjRgdBjzXz1jB67Jx1l91j06pONo/NS+o9Dr7bw+TR t2UVo8fnTXIB7FF6NkX5pSWpChn5xSW2StGGFkZ6hpYWekYmlnqGxuaxVkamSvp2NimpOZll qUX6dgl6GU82rGcuuFxS0fP5NWMD4/z4LkYODgkBE4mzH226GLk4hASWMkqc2LyVrYuREygu JjFp33Z2CFtY4s+1LjaIok+MEg+3PmIEaWYT0JPYsaoQJC4isJxR4tiqt8wgDrPAESaJo6uv MYJ0CwvkSNxZuI0JxGYRUJV4/Wg5WJxXwF7i7OR9rBAb5CVWbzjADGJzCjhILLu0FSwuBFQz Zd9rxgmMfAsYGVYxiqSWFuem5xYb6hUn5haX5qXrJefnbmIERsq2Yz8372C8tDH4EKMAB6MS D++ElxNjhVgTy4orcw8xSnAwK4nw2vyZFCvEm5JYWZValB9fVJqTWnyI0RToqInMUqLJ+cAo ziuJNzQ1NLewNDQ3Njc2s1AS5+0QOBgjJJCeWJKanZpakFoE08fEwSnVwJjwcUWa/5GSNesv 13b6snz4tUz7t17Ut6XhfJumbKx7fHX/nYovS/c9f8FQzWAsMzV20gkTNY5PMTWFSekb/u0X afSewfNNv4/9Ev9V3/2eixdc2qC1freaTPiGLbOO9X/u6tHLyb7E5vEmdEt1C9vlZ9J+v2e9 P5McaHbHRCngJsdhgX3LWJOVWIozEg21mIuKEwFpLyhPqgIAAA== X-CMS-MailID: 20191001125447eucas1p229f15daacca52b3df5bfd04b54914fb8 X-Msg-Generator: CA X-RootMTR: 20191001125447eucas1p229f15daacca52b3df5bfd04b54914fb8 X-EPHeader: CA CMS-TYPE: 201P X-CMS-RootMailID: 20191001125447eucas1p229f15daacca52b3df5bfd04b54914fb8 References: <20191001125436.24086-1-l.luba@partner.samsung.com> Sender: linux-pm-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-pm@vger.kernel.org Introduce a new interrupt driven mechanism for managing speed of the memory controller. The interrupts are generated due to performance counters overflow. The performance counters might track memory reads, writes, transfers, page misses, etc. In the basic algorithm tracking read transfers and calculating memory pressure should be enough to skip polling mode in devfreq. Signed-off-by: Lukasz Luba --- drivers/memory/samsung/exynos5422-dmc.c | 345 ++++++++++++++++++++++-- 1 file changed, 320 insertions(+), 25 deletions(-) diff --git a/drivers/memory/samsung/exynos5422-dmc.c b/drivers/memory/samsung/exynos5422-dmc.c index 0fe5f2186139..47dbf6d1789f 100644 --- a/drivers/memory/samsung/exynos5422-dmc.c +++ b/drivers/memory/samsung/exynos5422-dmc.c @@ -8,6 +8,7 @@ #include #include #include +#include #include #include #include @@ -35,6 +36,61 @@ #define USE_BPLL_TIMINGS (0) #define EXYNOS5_AREF_NORMAL (0x2e) +#define DREX_PPCCLKCON (0x0130) +#define DREX_PEREV2CONFIG (0x013c) +#define DREX_PMNC_PPC (0xE000) +#define DREX_CNTENS_PPC (0xE010) +#define DREX_CNTENC_PPC (0xE020) +#define DREX_INTENS_PPC (0xE030) +#define DREX_INTENC_PPC (0xE040) +#define DREX_FLAG_PPC (0xE050) +#define DREX_PMCNT2_PPC (0xE130) + +/* + * A value for register DREX_PMNC_PPC which should be written to reset + * the cycle counter CCNT (a reference wall clock). It sets zero to the + * CCNT counter. + */ +#define CC_RESET BIT(2) + +/* + * A value for register DREX_PMNC_PPC which does the reset of all performance + * counters to zero. + */ +#define PPC_COUNTER_RESET BIT(1) + +/* + * Enables all configured counters (including cycle counter). The value should + * be written to the register DREX_PMNC_PPC. + */ +#define PPC_ENABLE BIT(0) + +/* A value for register DREX_PPCCLKCON which enables performance events clock. + * Must be written before first access to the performance counters register + * set, otherwise it could crash. + */ +#define PEREV_CLK_EN BIT(0) + +/* + * Values which are used to enable counters, interrupts or configure flags of + * the performance counters. They configure counter 2 and cycle counter. + */ +#define PERF_CNT2 BIT(2) +#define PERF_CCNT BIT(31) + +/* + * Performance event types which are used for setting the preferred event + * to track in the counters. + * There is a set of different types, the values are from range 0 to 0x6f. + * These settings should be written to the configuration register which manages + * the type of the event (register DREX_PEREV2CONFIG). + */ +#define READ_TRANSFER_CH0 (0x6d) +#define READ_TRANSFER_CH1 (0x6f) + +#define PERF_COUNTER_START_VALUE 0xff000000 +#define PERF_EVENT_UP_DOWN_THRESHOLD 900000000ULL + /** * struct dmc_opp_table - Operating level desciption * @@ -85,6 +141,10 @@ struct exynos5_dmc { struct clk *mout_mx_mspll_ccore_phy; struct devfreq_event_dev **counter; int num_counters; + u64 last_overflow_ts[2]; + unsigned long load; + unsigned long total; + bool in_irq_mode; }; #define TIMING_FIELD(t_name, t_bit_beg, t_bit_end) \ @@ -653,6 +713,173 @@ static int exynos5_counters_get(struct exynos5_dmc *dmc, return 0; } +/** + * exynos5_dmc_start_perf_events() - Setup and start performance event counters + * @dmc: device for which the counters are going to be checked + * @beg_value: initial value for the counter + * + * Function which enables needed counters, interrupts and sets initial values + * then starts the counters. + */ +static void exynos5_dmc_start_perf_events(struct exynos5_dmc *dmc, + u32 beg_value) +{ + /* Enable interrupts for counter 2 */ + writel(PERF_CNT2, dmc->base_drexi0 + DREX_INTENS_PPC); + writel(PERF_CNT2, dmc->base_drexi1 + DREX_INTENS_PPC); + + /* Enable counter 2 and CCNT */ + writel(PERF_CNT2 | PERF_CCNT, dmc->base_drexi0 + DREX_CNTENS_PPC); + writel(PERF_CNT2 | PERF_CCNT, dmc->base_drexi1 + DREX_CNTENS_PPC); + + /* Clear overflow flag for all counters */ + writel(PERF_CNT2 | PERF_CCNT, dmc->base_drexi0 + DREX_FLAG_PPC); + writel(PERF_CNT2 | PERF_CCNT, dmc->base_drexi1 + DREX_FLAG_PPC); + + /* Reset all counters */ + writel(CC_RESET | PPC_COUNTER_RESET, dmc->base_drexi0 + DREX_PMNC_PPC); + writel(CC_RESET | PPC_COUNTER_RESET, dmc->base_drexi1 + DREX_PMNC_PPC); + + /* + * Set start value for the counters, the number of samples that + * will be gathered is calculated as: 0xffffffff - beg_value + */ + writel(beg_value, dmc->base_drexi0 + DREX_PMCNT2_PPC); + writel(beg_value, dmc->base_drexi1 + DREX_PMCNT2_PPC); + + /* Start all counters */ + writel(PPC_ENABLE, dmc->base_drexi0 + DREX_PMNC_PPC); + writel(PPC_ENABLE, dmc->base_drexi1 + DREX_PMNC_PPC); +} + +/** + * exynos5_dmc_perf_events_calc() - Calculate utilization + * @dmc: device for which the counters are going to be checked + * @diff_ts: time between last interrupt and current one + * + * Function which calculates needed utilization for the devfreq governor. + * It prepares values for 'busy_time' and 'total_time' based on elapsed time + * between interrupts, which approximates utilization. + */ +static void exynos5_dmc_perf_events_calc(struct exynos5_dmc *dmc, u64 diff_ts) +{ + /* + * This is a simple algorithm for managing traffic on DMC. + * When there is almost no load the counters overflow every 4s, + * no mater the DMC frequency. + * The high load might be approximated using linear function. + * Knowing that, simple calculation can provide 'busy_time' and + * 'total_time' to the devfreq governor which picks up target + * frequency. + * We want a fast ramp up and slow decay in frequency change function. + */ + if (diff_ts < PERF_EVENT_UP_DOWN_THRESHOLD) { + /* + * Set higher utilization for the simple_ondemand governor. + * The governor should increase the frequency of the DMC. + */ + dmc->load = 70; + dmc->total = 100; + } else { + /* + * Set low utilization for the simple_ondemand governor. + * The governor should decrease the frequency of the DMC. + */ + dmc->load = 35; + dmc->total = 100; + } + + dev_dbg(dmc->dev, "diff_ts=%llu\n", diff_ts); +} + +/** + * exynos5_dmc_perf_events_check() - Checks the status of the counters + * @dmc: device for which the counters are going to be checked + * + * Function which is called from threaded IRQ to check the counters state + * and to call approximation for the needed utilization. + */ +static void exynos5_dmc_perf_events_check(struct exynos5_dmc *dmc) +{ + u32 val; + u64 diff_ts, ts; + + ts = ktime_get_ns(); + + /* Stop all counters */ + writel(0, dmc->base_drexi0 + DREX_PMNC_PPC); + writel(0, dmc->base_drexi1 + DREX_PMNC_PPC); + + /* Check the source in interrupt flag registers (which channel) */ + val = readl(dmc->base_drexi0 + DREX_FLAG_PPC); + if (val) { + diff_ts = ts - dmc->last_overflow_ts[0]; + dmc->last_overflow_ts[0] = ts; + dev_dbg(dmc->dev, "drex0 0xE050 val= 0x%08x\n", val); + } else { + val = readl(dmc->base_drexi1 + DREX_FLAG_PPC); + diff_ts = ts - dmc->last_overflow_ts[1]; + dmc->last_overflow_ts[1] = ts; + dev_dbg(dmc->dev, "drex1 0xE050 val= 0x%08x\n", val); + } + + exynos5_dmc_perf_events_calc(dmc, diff_ts); + + exynos5_dmc_start_perf_events(dmc, PERF_COUNTER_START_VALUE); +} + +/** + * exynos5_dmc_enable_perf_events() - Enable performance events + * @dmc: device for which the counters are going to be checked + * + * Function which is setup needed environment and enables counters. + */ +static void exynos5_dmc_enable_perf_events(struct exynos5_dmc *dmc) +{ + u64 ts; + + /* Enable Performance Event Clock */ + writel(PEREV_CLK_EN, dmc->base_drexi0 + DREX_PPCCLKCON); + writel(PEREV_CLK_EN, dmc->base_drexi1 + DREX_PPCCLKCON); + + /* Select read transfers as performance event2 */ + writel(READ_TRANSFER_CH0, dmc->base_drexi0 + DREX_PEREV2CONFIG); + writel(READ_TRANSFER_CH1, dmc->base_drexi1 + DREX_PEREV2CONFIG); + + ts = ktime_get_ns(); + dmc->last_overflow_ts[0] = ts; + dmc->last_overflow_ts[1] = ts; + + /* Devfreq shouldn't be faster than initialization, play safe though. */ + dmc->load = 99; + dmc->total = 100; +} + +/** + * exynos5_dmc_disable_perf_events() - Disable performance events + * @dmc: device for which the counters are going to be checked + * + * Function which stops, disables performance event counters and interrupts. + */ +static void exynos5_dmc_disable_perf_events(struct exynos5_dmc *dmc) +{ + /* Stop all counters */ + writel(0, dmc->base_drexi0 + DREX_PMNC_PPC); + writel(0, dmc->base_drexi1 + DREX_PMNC_PPC); + + /* Disable interrupts for counter 2 */ + writel(PERF_CNT2, dmc->base_drexi0 + DREX_INTENC_PPC); + writel(PERF_CNT2, dmc->base_drexi1 + DREX_INTENC_PPC); + + /* Disable counter 2 and CCNT */ + writel(PERF_CNT2 | PERF_CCNT, dmc->base_drexi0 + DREX_CNTENC_PPC); + writel(PERF_CNT2 | PERF_CCNT, dmc->base_drexi1 + DREX_CNTENC_PPC); + + /* Clear overflow flag for all counters */ + writel(PERF_CNT2 | PERF_CCNT, dmc->base_drexi0 + DREX_FLAG_PPC); + writel(PERF_CNT2 | PERF_CCNT, dmc->base_drexi1 + DREX_FLAG_PPC); +} + /** * exynos5_dmc_get_status() - Read current DMC performance statistics. * @dev: device for which the statistics are requested @@ -669,18 +896,24 @@ static int exynos5_dmc_get_status(struct device *dev, unsigned long load, total; int ret; - ret = exynos5_counters_get(dmc, &load, &total); - if (ret < 0) - return -EINVAL; + if (dmc->in_irq_mode) { + stat->current_frequency = dmc->curr_rate; + stat->busy_time = dmc->load; + stat->total_time = dmc->total; + } else { + ret = exynos5_counters_get(dmc, &load, &total); + if (ret < 0) + return -EINVAL; - /* To protect from overflow in calculation ratios, divide by 1024 */ - stat->busy_time = load >> 10; - stat->total_time = total >> 10; + /* To protect from overflow, divide by 1024 */ + stat->busy_time = load >> 10; + stat->total_time = total >> 10; - ret = exynos5_counters_set_event(dmc); - if (ret < 0) { - dev_err(dev, "could not set event counter\n"); - return ret; + ret = exynos5_counters_set_event(dmc); + if (ret < 0) { + dev_err(dev, "could not set event counter\n"); + return ret; + } } return 0; @@ -712,7 +945,6 @@ static int exynos5_dmc_get_cur_freq(struct device *dev, unsigned long *freq) * It provides to the devfreq framework needed functions and polling period. */ static struct devfreq_dev_profile exynos5_dmc_df_profile = { - .polling_ms = 500, .target = exynos5_dmc_target, .get_dev_status = exynos5_dmc_get_status, .get_cur_freq = exynos5_dmc_get_cur_freq, @@ -1108,6 +1340,24 @@ static inline int exynos5_dmc_set_pause_on_switching(struct exynos5_dmc *dmc) return 0; } +static irqreturn_t dmc_irq_thread(int irq, void *priv) +{ + int res; + struct exynos5_dmc *dmc = priv; + + mutex_lock(&dmc->df->lock); + + exynos5_dmc_perf_events_check(dmc); + + res = update_devfreq(dmc->df); + if (res) + dev_warn(dmc->dev, "devfreq failed with %d\n", res); + + mutex_unlock(&dmc->df->lock); + + return IRQ_HANDLED; +} + /** * exynos5_dmc_probe() - Probe function for the DMC driver * @pdev: platform device for which the driver is going to be initialized @@ -1125,6 +1375,7 @@ static int exynos5_dmc_probe(struct platform_device *pdev) struct device_node *np = dev->of_node; struct exynos5_dmc *dmc; struct resource *res; + int irq[2]; dmc = devm_kzalloc(dev, sizeof(*dmc), GFP_KERNEL); if (!dmc) @@ -1172,24 +1423,59 @@ static int exynos5_dmc_probe(struct platform_device *pdev) goto remove_clocks; } - ret = exynos5_performance_counters_init(dmc); + ret = exynos5_dmc_set_pause_on_switching(dmc); if (ret) { - dev_warn(dev, "couldn't probe performance counters\n"); + dev_warn(dev, "couldn't get access to PAUSE register\n"); goto remove_clocks; } - ret = exynos5_dmc_set_pause_on_switching(dmc); - if (ret) { - dev_warn(dev, "couldn't get access to PAUSE register\n"); - goto err_devfreq_add; + /* There is two modes in which the driver works: polling or IRQ */ + irq[0] = platform_get_irq_byname(pdev, "drex_0"); + irq[1] = platform_get_irq_byname(pdev, "drex_1"); + if (irq[0] > 0 && irq[1] > 0) { + ret = devm_request_threaded_irq(dev, irq[0], NULL, + dmc_irq_thread, IRQF_ONESHOT, + dev_name(dev), dmc); + if (ret) { + dev_err(dev, "couldn't grab IRQ\n"); + goto remove_clocks; + } + + ret = devm_request_threaded_irq(dev, irq[1], NULL, + dmc_irq_thread, IRQF_ONESHOT, + dev_name(dev), dmc); + if (ret) { + dev_err(dev, "couldn't grab IRQ\n"); + goto remove_clocks; + } + + /* + * Setup default thresholds for the devfreq governor. + * The values are chosen based on experiments. + */ + dmc->gov_data.upthreshold = 55; + dmc->gov_data.downdifferential = 5; + + exynos5_dmc_enable_perf_events(dmc); + + dmc->in_irq_mode = 1; + } else { + ret = exynos5_performance_counters_init(dmc); + if (ret) { + dev_warn(dev, "couldn't probe performance counters\n"); + goto remove_clocks; + } + + /* + * Setup default thresholds for the devfreq governor. + * The values are chosen based on experiments. + */ + dmc->gov_data.upthreshold = 30; + dmc->gov_data.downdifferential = 5; + + exynos5_dmc_df_profile.polling_ms = 500; } - /* - * Setup default thresholds for the devfreq governor. - * The values are chosen based on experiments. - */ - dmc->gov_data.upthreshold = 30; - dmc->gov_data.downdifferential = 5; dmc->df = devm_devfreq_add_device(dev, &exynos5_dmc_df_profile, DEVFREQ_GOV_SIMPLE_ONDEMAND, @@ -1200,12 +1486,18 @@ static int exynos5_dmc_probe(struct platform_device *pdev) goto err_devfreq_add; } + if (dmc->in_irq_mode) + exynos5_dmc_start_perf_events(dmc, PERF_COUNTER_START_VALUE); + dev_info(dev, "DMC initialized\n"); return 0; err_devfreq_add: - exynos5_counters_disable_edev(dmc); + if (dmc->in_irq_mode) + exynos5_dmc_disable_perf_events(dmc); + else + exynos5_counters_disable_edev(dmc); remove_clocks: clk_disable_unprepare(dmc->mout_bpll); clk_disable_unprepare(dmc->fout_bpll); @@ -1225,7 +1517,10 @@ static int exynos5_dmc_remove(struct platform_device *pdev) { struct exynos5_dmc *dmc = dev_get_drvdata(&pdev->dev); - exynos5_counters_disable_edev(dmc); + if (dmc->in_irq_mode) + exynos5_dmc_disable_perf_events(dmc); + else + exynos5_counters_disable_edev(dmc); clk_disable_unprepare(dmc->mout_bpll); clk_disable_unprepare(dmc->fout_bpll);