From patchwork Wed Oct 2 10:08:18 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Biju Das X-Patchwork-Id: 11170707 X-Patchwork-Delegate: geert@linux-m68k.org Return-Path: Received: from mail.kernel.org (pdx-korg-mail-1.web.codeaurora.org [172.30.200.123]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id DFF52112B for ; Wed, 2 Oct 2019 10:08:57 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.kernel.org (Postfix) with ESMTP id BF79721929 for ; Wed, 2 Oct 2019 10:08:57 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1727581AbfJBKI5 (ORCPT ); Wed, 2 Oct 2019 06:08:57 -0400 Received: from relmlor2.renesas.com ([210.160.252.172]:62117 "EHLO relmlie6.idc.renesas.com" rhost-flags-OK-OK-OK-FAIL) by vger.kernel.org with ESMTP id S1726742AbfJBKI5 (ORCPT ); Wed, 2 Oct 2019 06:08:57 -0400 X-IronPort-AV: E=Sophos;i="5.64,573,1559487600"; d="scan'208";a="27885181" Received: from unknown (HELO relmlir6.idc.renesas.com) ([10.200.68.152]) by relmlie6.idc.renesas.com with ESMTP; 02 Oct 2019 19:08:54 +0900 Received: from be1yocto.ree.adwin.renesas.com (unknown [172.29.43.62]) by relmlir6.idc.renesas.com (Postfix) with ESMTP id D42B342034EB; Wed, 2 Oct 2019 19:08:51 +0900 (JST) From: Biju Das To: Rob Herring , Mark Rutland Cc: Biju Das , Simon Horman , Laurent Pinchart , Kieran Bingham , Geert Uytterhoeven , Magnus Damm , linux-renesas-soc@vger.kernel.org, devicetree@vger.kernel.org, Chris Paterson , Fabrizio Castro Subject: [PATCH v2 1/9] arm64: dts: renesas: hihope-common: Move du clk properties out of common dtsi Date: Wed, 2 Oct 2019 11:08:18 +0100 Message-Id: <1570010906-47486-2-git-send-email-biju.das@bp.renesas.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1570010906-47486-1-git-send-email-biju.das@bp.renesas.com> References: <1570010906-47486-1-git-send-email-biju.das@bp.renesas.com> Sender: linux-renesas-soc-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-renesas-soc@vger.kernel.org RZ/G2N board is pin compatible with RZ/G2M board. However on the SoC side RZ/G2N uses DU3 where as RZ/G2M uses DU2 for the DPAD. In order to reuse the common dtsi for both the boards, it is required to move du clock properties from common dtsi to board specific dts. Signed-off-by: Biju Das Reviewed-by: Laurent Pinchart --- V1-->V2 * No change * Added Laurent's Reviewed-by tag. --- arch/arm64/boot/dts/renesas/hihope-common.dtsi | 8 -------- arch/arm64/boot/dts/renesas/r8a774a1-hihope-rzg2m.dts | 11 +++++++++++ 2 files changed, 11 insertions(+), 8 deletions(-) diff --git a/arch/arm64/boot/dts/renesas/hihope-common.dtsi b/arch/arm64/boot/dts/renesas/hihope-common.dtsi index 3e376d2..355d0a2 100644 --- a/arch/arm64/boot/dts/renesas/hihope-common.dtsi +++ b/arch/arm64/boot/dts/renesas/hihope-common.dtsi @@ -142,14 +142,6 @@ }; &du { - clocks = <&cpg CPG_MOD 724>, - <&cpg CPG_MOD 723>, - <&cpg CPG_MOD 722>, - <&versaclock5 1>, - <&x302_clk>, - <&versaclock5 2>; - clock-names = "du.0", "du.1", "du.2", - "dclkin.0", "dclkin.1", "dclkin.2"; status = "okay"; }; diff --git a/arch/arm64/boot/dts/renesas/r8a774a1-hihope-rzg2m.dts b/arch/arm64/boot/dts/renesas/r8a774a1-hihope-rzg2m.dts index 93ca973..96f2fb0 100644 --- a/arch/arm64/boot/dts/renesas/r8a774a1-hihope-rzg2m.dts +++ b/arch/arm64/boot/dts/renesas/r8a774a1-hihope-rzg2m.dts @@ -24,3 +24,14 @@ reg = <0x6 0x00000000 0x0 0x80000000>; }; }; + +&du { + clocks = <&cpg CPG_MOD 724>, + <&cpg CPG_MOD 723>, + <&cpg CPG_MOD 722>, + <&versaclock5 1>, + <&x302_clk>, + <&versaclock5 2>; + clock-names = "du.0", "du.1", "du.2", + "dclkin.0", "dclkin.1", "dclkin.2"; +}; From patchwork Wed Oct 2 10:08:19 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Biju Das X-Patchwork-Id: 11170711 X-Patchwork-Delegate: geert@linux-m68k.org Return-Path: Received: from mail.kernel.org (pdx-korg-mail-1.web.codeaurora.org [172.30.200.123]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id 2531C17E1 for ; Wed, 2 Oct 2019 10:09:00 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.kernel.org (Postfix) with ESMTP id 053B021929 for ; Wed, 2 Oct 2019 10:09:00 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1727585AbfJBKI7 (ORCPT ); Wed, 2 Oct 2019 06:08:59 -0400 Received: from relmlor2.renesas.com ([210.160.252.172]:62117 "EHLO relmlie6.idc.renesas.com" rhost-flags-OK-OK-OK-FAIL) by vger.kernel.org with ESMTP id S1726742AbfJBKI7 (ORCPT ); Wed, 2 Oct 2019 06:08:59 -0400 X-IronPort-AV: E=Sophos;i="5.64,573,1559487600"; d="scan'208";a="27885192" Received: from unknown (HELO relmlir6.idc.renesas.com) ([10.200.68.152]) by relmlie6.idc.renesas.com with ESMTP; 02 Oct 2019 19:08:57 +0900 Received: from be1yocto.ree.adwin.renesas.com (unknown [172.29.43.62]) by relmlir6.idc.renesas.com (Postfix) with ESMTP id 0DA6842034EB; Wed, 2 Oct 2019 19:08:54 +0900 (JST) From: Biju Das To: Rob Herring , Mark Rutland Cc: Biju Das , Simon Horman , Laurent Pinchart , Kieran Bingham , Geert Uytterhoeven , Magnus Damm , linux-renesas-soc@vger.kernel.org, devicetree@vger.kernel.org, Chris Paterson , Fabrizio Castro Subject: [PATCH v2 2/9] arm64: dts: renesas: r8a774b1: Add DU device to DT Date: Wed, 2 Oct 2019 11:08:19 +0100 Message-Id: <1570010906-47486-3-git-send-email-biju.das@bp.renesas.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1570010906-47486-1-git-send-email-biju.das@bp.renesas.com> References: <1570010906-47486-1-git-send-email-biju.das@bp.renesas.com> Sender: linux-renesas-soc-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-renesas-soc@vger.kernel.org Add the DU device to r8a774b1 SoC DT. Signed-off-by: Biju Das Reviewed-by: Laurent Pinchart --- V1-->V2 * No change * Added Laurent's Reviewed-by tag. --- arch/arm64/boot/dts/renesas/r8a774b1.dtsi | 38 +++++++++++++++++++++++++++++++ 1 file changed, 38 insertions(+) diff --git a/arch/arm64/boot/dts/renesas/r8a774b1.dtsi b/arch/arm64/boot/dts/renesas/r8a774b1.dtsi index 9d5630a..777b45d 100644 --- a/arch/arm64/boot/dts/renesas/r8a774b1.dtsi +++ b/arch/arm64/boot/dts/renesas/r8a774b1.dtsi @@ -1285,7 +1285,18 @@ }; du: display@feb00000 { + compatible = "renesas,du-r8a774b1"; reg = <0 0xfeb00000 0 0x80000>; + interrupts = , + , + ; + clocks = <&cpg CPG_MOD 724>, + <&cpg CPG_MOD 723>, + <&cpg CPG_MOD 721>; + clock-names = "du.0", "du.1", "du.3"; + status = "disabled"; + + vsps = <&vspd0 0>, <&vspd1 0>, <&vspd0 1>; ports { #address-cells = <1>; @@ -1304,6 +1315,33 @@ port@2 { reg = <2>; du_out_lvds0: endpoint { + remote-endpoint = <&lvds0_in>; + }; + }; + }; + }; + + lvds0: lvds@feb90000 { + compatible = "renesas,r8a774b1-lvds"; + reg = <0 0xfeb90000 0 0x14>; + clocks = <&cpg CPG_MOD 727>; + power-domains = <&sysc R8A774B1_PD_ALWAYS_ON>; + resets = <&cpg 727>; + status = "disabled"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + lvds0_in: endpoint { + remote-endpoint = <&du_out_lvds0>; + }; + }; + port@1 { + reg = <1>; + lvds0_out: endpoint { }; }; }; From patchwork Wed Oct 2 10:08:20 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Biju Das X-Patchwork-Id: 11170713 X-Patchwork-Delegate: geert@linux-m68k.org Return-Path: Received: from mail.kernel.org (pdx-korg-mail-1.web.codeaurora.org [172.30.200.123]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id E0940112B for ; Wed, 2 Oct 2019 10:09:03 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.kernel.org (Postfix) with ESMTP id C026C21920 for ; Wed, 2 Oct 2019 10:09:03 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1727591AbfJBKJD (ORCPT ); Wed, 2 Oct 2019 06:09:03 -0400 Received: from relmlor1.renesas.com ([210.160.252.171]:55208 "EHLO relmlie5.idc.renesas.com" rhost-flags-OK-OK-OK-FAIL) by vger.kernel.org with ESMTP id S1726742AbfJBKJD (ORCPT ); Wed, 2 Oct 2019 06:09:03 -0400 X-IronPort-AV: E=Sophos;i="5.64,574,1559487600"; d="scan'208";a="28103932" Received: from unknown (HELO relmlir6.idc.renesas.com) ([10.200.68.152]) by relmlie5.idc.renesas.com with ESMTP; 02 Oct 2019 19:09:00 +0900 Received: from be1yocto.ree.adwin.renesas.com (unknown [172.29.43.62]) by relmlir6.idc.renesas.com (Postfix) with ESMTP id 39D2342034EB; Wed, 2 Oct 2019 19:08:58 +0900 (JST) From: Biju Das To: Rob Herring , Mark Rutland Cc: Biju Das , Simon Horman , Laurent Pinchart , Kieran Bingham , Geert Uytterhoeven , Magnus Damm , linux-renesas-soc@vger.kernel.org, devicetree@vger.kernel.org, Chris Paterson , Fabrizio Castro Subject: [PATCH v2 3/9] arm64: dts: renesas: r8a774b1: Add HDMI encoder instance Date: Wed, 2 Oct 2019 11:08:20 +0100 Message-Id: <1570010906-47486-4-git-send-email-biju.das@bp.renesas.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1570010906-47486-1-git-send-email-biju.das@bp.renesas.com> References: <1570010906-47486-1-git-send-email-biju.das@bp.renesas.com> Sender: linux-renesas-soc-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-renesas-soc@vger.kernel.org Add the HDMI encoder to the R8A774B1 DT in disabled state. Signed-off-by: Biju Das Reviewed-by: Laurent Pinchart --- V1-->V2 * No change * Added Laurent's Reviewed-by tag. --- arch/arm64/boot/dts/renesas/r8a774b1.dtsi | 15 +++++++++++++++ 1 file changed, 15 insertions(+) diff --git a/arch/arm64/boot/dts/renesas/r8a774b1.dtsi b/arch/arm64/boot/dts/renesas/r8a774b1.dtsi index 777b45d..979be5a 100644 --- a/arch/arm64/boot/dts/renesas/r8a774b1.dtsi +++ b/arch/arm64/boot/dts/renesas/r8a774b1.dtsi @@ -1267,7 +1267,16 @@ }; hdmi0: hdmi@fead0000 { + compatible = "renesas,r8a774b1-hdmi", + "renesas,rcar-gen3-hdmi"; reg = <0 0xfead0000 0 0x10000>; + interrupts = ; + clocks = <&cpg CPG_MOD 729>, + <&cpg CPG_CORE R8A774B1_CLK_HDMI>; + clock-names = "iahb", "isfr"; + power-domains = <&sysc R8A774B1_PD_ALWAYS_ON>; + resets = <&cpg 729>; + status = "disabled"; ports { #address-cells = <1>; @@ -1276,11 +1285,16 @@ port@0 { reg = <0>; dw_hdmi0_in: endpoint { + remote-endpoint = <&du_out_hdmi0>; }; }; port@1 { reg = <1>; }; + port@2 { + /* HDMI sound */ + reg = <2>; + }; }; }; @@ -1310,6 +1324,7 @@ port@1 { reg = <1>; du_out_hdmi0: endpoint { + remote-endpoint = <&dw_hdmi0_in>; }; }; port@2 { From patchwork Wed Oct 2 10:08:21 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Biju Das X-Patchwork-Id: 11170715 X-Patchwork-Delegate: geert@linux-m68k.org Return-Path: Received: from mail.kernel.org (pdx-korg-mail-1.web.codeaurora.org [172.30.200.123]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id A6BA6112B for ; Wed, 2 Oct 2019 10:09:05 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.kernel.org (Postfix) with ESMTP id 8621221929 for ; Wed, 2 Oct 2019 10:09:05 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1727611AbfJBKJF (ORCPT ); Wed, 2 Oct 2019 06:09:05 -0400 Received: from relmlor1.renesas.com ([210.160.252.171]:55208 "EHLO relmlie5.idc.renesas.com" rhost-flags-OK-OK-OK-FAIL) by vger.kernel.org with ESMTP id S1726742AbfJBKJF (ORCPT ); Wed, 2 Oct 2019 06:09:05 -0400 X-IronPort-AV: E=Sophos;i="5.64,574,1559487600"; d="scan'208";a="28103937" Received: from unknown (HELO relmlir6.idc.renesas.com) ([10.200.68.152]) by relmlie5.idc.renesas.com with ESMTP; 02 Oct 2019 19:09:04 +0900 Received: from be1yocto.ree.adwin.renesas.com (unknown [172.29.43.62]) by relmlir6.idc.renesas.com (Postfix) with ESMTP id 6693742034EB; Wed, 2 Oct 2019 19:09:01 +0900 (JST) From: Biju Das To: Rob Herring , Mark Rutland Cc: Biju Das , Simon Horman , Laurent Pinchart , Kieran Bingham , Geert Uytterhoeven , Magnus Damm , linux-renesas-soc@vger.kernel.org, devicetree@vger.kernel.org, Chris Paterson , Fabrizio Castro Subject: [PATCH v2 4/9] arm64: dts: renesas: r8a774b1-hihope-rzg2n: Add display clock properties Date: Wed, 2 Oct 2019 11:08:21 +0100 Message-Id: <1570010906-47486-5-git-send-email-biju.das@bp.renesas.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1570010906-47486-1-git-send-email-biju.das@bp.renesas.com> References: <1570010906-47486-1-git-send-email-biju.das@bp.renesas.com> Sender: linux-renesas-soc-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-renesas-soc@vger.kernel.org Add display clock properties for the HiHope RZ/G2N board. Signed-off-by: Biju Das Reviewed-by: Laurent Pinchart --- V1-->V2 * No change * Added Laurent's Reviewed-by tag. --- arch/arm64/boot/dts/renesas/r8a774b1-hihope-rzg2n.dts | 11 +++++++++++ 1 file changed, 11 insertions(+) diff --git a/arch/arm64/boot/dts/renesas/r8a774b1-hihope-rzg2n.dts b/arch/arm64/boot/dts/renesas/r8a774b1-hihope-rzg2n.dts index c9e2119..9910c1a 100644 --- a/arch/arm64/boot/dts/renesas/r8a774b1-hihope-rzg2n.dts +++ b/arch/arm64/boot/dts/renesas/r8a774b1-hihope-rzg2n.dts @@ -25,6 +25,17 @@ }; }; +&du { + clocks = <&cpg CPG_MOD 724>, + <&cpg CPG_MOD 723>, + <&cpg CPG_MOD 721>, + <&versaclock5 1>, + <&x302_clk>, + <&versaclock5 2>; + clock-names = "du.0", "du.1", "du.3", + "dclkin.0", "dclkin.1", "dclkin.3"; +}; + &sdhi3 { mmc-hs400-1_8v; }; From patchwork Wed Oct 2 10:08:22 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Biju Das X-Patchwork-Id: 11170717 X-Patchwork-Delegate: geert@linux-m68k.org Return-Path: Received: from mail.kernel.org (pdx-korg-mail-1.web.codeaurora.org [172.30.200.123]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id EC0E616B1 for ; Wed, 2 Oct 2019 10:09:08 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.kernel.org (Postfix) with ESMTP id CB79F21920 for ; Wed, 2 Oct 2019 10:09:08 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1727612AbfJBKJI (ORCPT ); Wed, 2 Oct 2019 06:09:08 -0400 Received: from relmlor1.renesas.com ([210.160.252.171]:55208 "EHLO relmlie5.idc.renesas.com" rhost-flags-OK-OK-OK-FAIL) by vger.kernel.org with ESMTP id S1726742AbfJBKJI (ORCPT ); Wed, 2 Oct 2019 06:09:08 -0400 X-IronPort-AV: E=Sophos;i="5.64,574,1559487600"; d="scan'208";a="28103947" Received: from unknown (HELO relmlir6.idc.renesas.com) ([10.200.68.152]) by relmlie5.idc.renesas.com with ESMTP; 02 Oct 2019 19:09:07 +0900 Received: from be1yocto.ree.adwin.renesas.com (unknown [172.29.43.62]) by relmlir6.idc.renesas.com (Postfix) with ESMTP id 910B242034EB; Wed, 2 Oct 2019 19:09:04 +0900 (JST) From: Biju Das To: Rob Herring , Mark Rutland Cc: Biju Das , Simon Horman , Laurent Pinchart , Kieran Bingham , Geert Uytterhoeven , Magnus Damm , linux-renesas-soc@vger.kernel.org, devicetree@vger.kernel.org, Chris Paterson , Fabrizio Castro Subject: [PATCH v2 5/9] arm64: dts: renesas: r8a774b1: Add FDP1 device nodes Date: Wed, 2 Oct 2019 11:08:22 +0100 Message-Id: <1570010906-47486-6-git-send-email-biju.das@bp.renesas.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1570010906-47486-1-git-send-email-biju.das@bp.renesas.com> References: <1570010906-47486-1-git-send-email-biju.das@bp.renesas.com> Sender: linux-renesas-soc-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-renesas-soc@vger.kernel.org The r8a774b1 has a single FDP1 instance. Signed-off-by: Biju Das Reviewed-by: Laurent Pinchart --- V1-->V2 * No change * Added Laurent's Reviewed-by tag. --- arch/arm64/boot/dts/renesas/r8a774b1.dtsi | 10 ++++++++++ 1 file changed, 10 insertions(+) diff --git a/arch/arm64/boot/dts/renesas/r8a774b1.dtsi b/arch/arm64/boot/dts/renesas/r8a774b1.dtsi index 979be5a..93b2e88 100644 --- a/arch/arm64/boot/dts/renesas/r8a774b1.dtsi +++ b/arch/arm64/boot/dts/renesas/r8a774b1.dtsi @@ -1182,6 +1182,16 @@ /* placeholder */ }; + fdp1@fe940000 { + compatible = "renesas,fdp1"; + reg = <0 0xfe940000 0 0x2400>; + interrupts = ; + clocks = <&cpg CPG_MOD 119>; + power-domains = <&sysc R8A774B1_PD_A3VP>; + resets = <&cpg 119>; + renesas,fcp = <&fcpf0>; + }; + fcpf0: fcp@fe950000 { compatible = "renesas,fcpf"; reg = <0 0xfe950000 0 0x200>; From patchwork Wed Oct 2 10:08:23 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Biju Das X-Patchwork-Id: 11170719 X-Patchwork-Delegate: geert@linux-m68k.org Return-Path: Received: from mail.kernel.org (pdx-korg-mail-1.web.codeaurora.org [172.30.200.123]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id 8D7FE16B1 for ; Wed, 2 Oct 2019 10:09:13 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.kernel.org (Postfix) with ESMTP id 7794921920 for ; Wed, 2 Oct 2019 10:09:13 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1727451AbfJBKJN (ORCPT ); Wed, 2 Oct 2019 06:09:13 -0400 Received: from relmlor2.renesas.com ([210.160.252.172]:38123 "EHLO relmlie6.idc.renesas.com" rhost-flags-OK-OK-OK-FAIL) by vger.kernel.org with ESMTP id S1727409AbfJBKJN (ORCPT ); Wed, 2 Oct 2019 06:09:13 -0400 X-IronPort-AV: E=Sophos;i="5.64,573,1559487600"; d="scan'208";a="27885216" Received: from unknown (HELO relmlir6.idc.renesas.com) ([10.200.68.152]) by relmlie6.idc.renesas.com with ESMTP; 02 Oct 2019 19:09:10 +0900 Received: from be1yocto.ree.adwin.renesas.com (unknown [172.29.43.62]) by relmlir6.idc.renesas.com (Postfix) with ESMTP id BCF2941EB064; Wed, 2 Oct 2019 19:09:07 +0900 (JST) From: Biju Das To: Rob Herring , Mark Rutland Cc: Biju Das , Simon Horman , Laurent Pinchart , Kieran Bingham , Geert Uytterhoeven , Magnus Damm , linux-renesas-soc@vger.kernel.org, devicetree@vger.kernel.org, Chris Paterson , Fabrizio Castro Subject: [PATCH v2 6/9] arm64: dts: renesas: r8a774b1: Add PWM device nodes Date: Wed, 2 Oct 2019 11:08:23 +0100 Message-Id: <1570010906-47486-7-git-send-email-biju.das@bp.renesas.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1570010906-47486-1-git-send-email-biju.das@bp.renesas.com> References: <1570010906-47486-1-git-send-email-biju.das@bp.renesas.com> Sender: linux-renesas-soc-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-renesas-soc@vger.kernel.org This patch adds PWM device nodes to r8a774b1 SoC DT. Signed-off-by: Biju Das Reviewed-by: Laurent Pinchart --- V1-->V2 * No change * Added Laurent's Reviewed-by tag. --- arch/arm64/boot/dts/renesas/r8a774b1.dtsi | 70 +++++++++++++++++++++++++++++++ 1 file changed, 70 insertions(+) diff --git a/arch/arm64/boot/dts/renesas/r8a774b1.dtsi b/arch/arm64/boot/dts/renesas/r8a774b1.dtsi index 93b2e88..538e9ce 100644 --- a/arch/arm64/boot/dts/renesas/r8a774b1.dtsi +++ b/arch/arm64/boot/dts/renesas/r8a774b1.dtsi @@ -940,6 +940,76 @@ /* placeholder */ }; + pwm0: pwm@e6e30000 { + compatible = "renesas,pwm-r8a774b1", "renesas,pwm-rcar"; + reg = <0 0xe6e30000 0 0x8>; + #pwm-cells = <2>; + clocks = <&cpg CPG_MOD 523>; + resets = <&cpg 523>; + power-domains = <&sysc R8A774B1_PD_ALWAYS_ON>; + status = "disabled"; + }; + + pwm1: pwm@e6e31000 { + compatible = "renesas,pwm-r8a774b1", "renesas,pwm-rcar"; + reg = <0 0xe6e31000 0 0x8>; + #pwm-cells = <2>; + clocks = <&cpg CPG_MOD 523>; + resets = <&cpg 523>; + power-domains = <&sysc R8A774B1_PD_ALWAYS_ON>; + status = "disabled"; + }; + + pwm2: pwm@e6e32000 { + compatible = "renesas,pwm-r8a774b1", "renesas,pwm-rcar"; + reg = <0 0xe6e32000 0 0x8>; + #pwm-cells = <2>; + clocks = <&cpg CPG_MOD 523>; + resets = <&cpg 523>; + power-domains = <&sysc R8A774B1_PD_ALWAYS_ON>; + status = "disabled"; + }; + + pwm3: pwm@e6e33000 { + compatible = "renesas,pwm-r8a774b1", "renesas,pwm-rcar"; + reg = <0 0xe6e33000 0 0x8>; + #pwm-cells = <2>; + clocks = <&cpg CPG_MOD 523>; + resets = <&cpg 523>; + power-domains = <&sysc R8A774B1_PD_ALWAYS_ON>; + status = "disabled"; + }; + + pwm4: pwm@e6e34000 { + compatible = "renesas,pwm-r8a774b1", "renesas,pwm-rcar"; + reg = <0 0xe6e34000 0 0x8>; + #pwm-cells = <2>; + clocks = <&cpg CPG_MOD 523>; + resets = <&cpg 523>; + power-domains = <&sysc R8A774B1_PD_ALWAYS_ON>; + status = "disabled"; + }; + + pwm5: pwm@e6e35000 { + compatible = "renesas,pwm-r8a774b1", "renesas,pwm-rcar"; + reg = <0 0xe6e35000 0 0x8>; + #pwm-cells = <2>; + clocks = <&cpg CPG_MOD 523>; + resets = <&cpg 523>; + power-domains = <&sysc R8A774B1_PD_ALWAYS_ON>; + status = "disabled"; + }; + + pwm6: pwm@e6e36000 { + compatible = "renesas,pwm-r8a774b1", "renesas,pwm-rcar"; + reg = <0 0xe6e36000 0 0x8>; + #pwm-cells = <2>; + clocks = <&cpg CPG_MOD 523>; + resets = <&cpg 523>; + power-domains = <&sysc R8A774B1_PD_ALWAYS_ON>; + status = "disabled"; + }; + scif0: serial@e6e60000 { compatible = "renesas,scif-r8a774b1", "renesas,rcar-gen3-scif", "renesas,scif"; From patchwork Wed Oct 2 10:08:24 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Biju Das X-Patchwork-Id: 11170721 X-Patchwork-Delegate: geert@linux-m68k.org Return-Path: Received: from mail.kernel.org (pdx-korg-mail-1.web.codeaurora.org [172.30.200.123]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id 44024112B for ; Wed, 2 Oct 2019 10:09:15 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.kernel.org (Postfix) with ESMTP id 21E2221783 for ; Wed, 2 Oct 2019 10:09:15 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1727620AbfJBKJO (ORCPT ); Wed, 2 Oct 2019 06:09:14 -0400 Received: from relmlor2.renesas.com ([210.160.252.172]:38123 "EHLO relmlie6.idc.renesas.com" rhost-flags-OK-OK-OK-FAIL) by vger.kernel.org with ESMTP id S1727409AbfJBKJO (ORCPT ); Wed, 2 Oct 2019 06:09:14 -0400 X-IronPort-AV: E=Sophos;i="5.64,573,1559487600"; d="scan'208";a="27885221" Received: from unknown (HELO relmlir6.idc.renesas.com) ([10.200.68.152]) by relmlie6.idc.renesas.com with ESMTP; 02 Oct 2019 19:09:13 +0900 Received: from be1yocto.ree.adwin.renesas.com (unknown [172.29.43.62]) by relmlir6.idc.renesas.com (Postfix) with ESMTP id EC54642034EB; Wed, 2 Oct 2019 19:09:10 +0900 (JST) From: Biju Das To: Rob Herring , Mark Rutland Cc: Biju Das , Simon Horman , Laurent Pinchart , Kieran Bingham , Geert Uytterhoeven , Magnus Damm , linux-renesas-soc@vger.kernel.org, devicetree@vger.kernel.org, Chris Paterson , Fabrizio Castro Subject: [PATCH v2 7/9] arm64: dts: renesas: hihope-rzg2-ex: Enable backlight Date: Wed, 2 Oct 2019 11:08:24 +0100 Message-Id: <1570010906-47486-8-git-send-email-biju.das@bp.renesas.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1570010906-47486-1-git-send-email-biju.das@bp.renesas.com> References: <1570010906-47486-1-git-send-email-biju.das@bp.renesas.com> Sender: linux-renesas-soc-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-renesas-soc@vger.kernel.org This patch enables backlight support. Signed-off-by: Biju Das Reviewed-by: Laurent Pinchart --- V1-->V2 * No change * Added Laurent's Reviewed-by tag. --- arch/arm64/boot/dts/renesas/hihope-rzg2-ex.dtsi | 20 ++++++++++++++++++++ 1 file changed, 20 insertions(+) diff --git a/arch/arm64/boot/dts/renesas/hihope-rzg2-ex.dtsi b/arch/arm64/boot/dts/renesas/hihope-rzg2-ex.dtsi index 4280b19..70f9a2a 100644 --- a/arch/arm64/boot/dts/renesas/hihope-rzg2-ex.dtsi +++ b/arch/arm64/boot/dts/renesas/hihope-rzg2-ex.dtsi @@ -13,6 +13,14 @@ chosen { bootargs = "ignore_loglevel rw root=/dev/nfs ip=on"; }; + + backlight { + compatible = "pwm-backlight"; + pwms = <&pwm0 0 50000>; + + brightness-levels = <0 2 8 16 32 64 128 255>; + default-brightness-level = <6>; + }; }; &avb { @@ -82,4 +90,16 @@ groups = "can1_data"; function = "can1"; }; + + pwm0_pins: pwm0 { + groups = "pwm0"; + function = "pwm0"; + }; +}; + +&pwm0 { + pinctrl-0 = <&pwm0_pins>; + pinctrl-names = "default"; + + status = "okay"; }; From patchwork Wed Oct 2 10:08:25 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Biju Das X-Patchwork-Id: 11170723 X-Patchwork-Delegate: geert@linux-m68k.org Return-Path: Received: from mail.kernel.org (pdx-korg-mail-1.web.codeaurora.org [172.30.200.123]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id 747C0112B for ; Wed, 2 Oct 2019 10:09:18 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.kernel.org (Postfix) with ESMTP id 53CA221783 for ; Wed, 2 Oct 2019 10:09:18 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1727632AbfJBKJS (ORCPT ); Wed, 2 Oct 2019 06:09:18 -0400 Received: from relmlor2.renesas.com ([210.160.252.172]:38123 "EHLO relmlie6.idc.renesas.com" rhost-flags-OK-OK-OK-FAIL) by vger.kernel.org with ESMTP id S1727409AbfJBKJR (ORCPT ); Wed, 2 Oct 2019 06:09:17 -0400 X-IronPort-AV: E=Sophos;i="5.64,573,1559487600"; d="scan'208";a="27885230" Received: from unknown (HELO relmlir6.idc.renesas.com) ([10.200.68.152]) by relmlie6.idc.renesas.com with ESMTP; 02 Oct 2019 19:09:16 +0900 Received: from be1yocto.ree.adwin.renesas.com (unknown [172.29.43.62]) by relmlir6.idc.renesas.com (Postfix) with ESMTP id 2415542050A5; Wed, 2 Oct 2019 19:09:13 +0900 (JST) From: Biju Das To: Rob Herring , Mark Rutland Cc: Biju Das , Simon Horman , Laurent Pinchart , Kieran Bingham , Geert Uytterhoeven , Magnus Damm , linux-renesas-soc@vger.kernel.org, devicetree@vger.kernel.org, Chris Paterson , Fabrizio Castro Subject: [PATCH v2 8/9] arm64: dts: renesas: hihope-rzg2-ex: Add LVDS support Date: Wed, 2 Oct 2019 11:08:25 +0100 Message-Id: <1570010906-47486-9-git-send-email-biju.das@bp.renesas.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1570010906-47486-1-git-send-email-biju.das@bp.renesas.com> References: <1570010906-47486-1-git-send-email-biju.das@bp.renesas.com> Sender: linux-renesas-soc-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-renesas-soc@vger.kernel.org This patch adds LVDS support for RZ/G2[MN] boards. Signed-off-by: Biju Das Reviewed-by: Laurent Pinchart --- V1-->V2 * Incorporated Laurent's review comments --- arch/arm64/boot/dts/renesas/hihope-rzg2-ex.dtsi | 29 +++++++++++++++++++++++++ 1 file changed, 29 insertions(+) diff --git a/arch/arm64/boot/dts/renesas/hihope-rzg2-ex.dtsi b/arch/arm64/boot/dts/renesas/hihope-rzg2-ex.dtsi index 70f9a2a..1c7ef69 100644 --- a/arch/arm64/boot/dts/renesas/hihope-rzg2-ex.dtsi +++ b/arch/arm64/boot/dts/renesas/hihope-rzg2-ex.dtsi @@ -51,6 +51,34 @@ status = "okay"; }; +&gpio1 { + /* + * When GP1_20 is LOW LVDS0 is connected to the LVDS connector + * When GP1_20 is HIGH LVDS0 is connected to the LT8918L + */ + lvds-connector-en-gpio { + gpio-hog; + gpios = <20 GPIO_ACTIVE_HIGH>; + output-low; + line-name = "lvds-connector-en-gpio"; + }; +}; + +&lvds0 { + /* Please include the lvds panel dtsi file and uncomment the below line + * to enable lvds panel connected to RZ/G2[MN] boards. + */ + + /* status = "okay"; */ + + ports { + port@1 { + lvds_connector: endpoint { + }; + }; + }; +}; + &pciec0 { status = "okay"; }; @@ -103,3 +131,4 @@ status = "okay"; }; + From patchwork Wed Oct 2 10:08:26 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Biju Das X-Patchwork-Id: 11170725 X-Patchwork-Delegate: geert@linux-m68k.org Return-Path: Received: from mail.kernel.org (pdx-korg-mail-1.web.codeaurora.org [172.30.200.123]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id 962BE16B1 for ; Wed, 2 Oct 2019 10:09:22 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.kernel.org (Postfix) with ESMTP id 760F621783 for ; Wed, 2 Oct 2019 10:09:22 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1727633AbfJBKJW (ORCPT ); Wed, 2 Oct 2019 06:09:22 -0400 Received: from relmlor1.renesas.com ([210.160.252.171]:16376 "EHLO relmlie5.idc.renesas.com" rhost-flags-OK-OK-OK-FAIL) by vger.kernel.org with ESMTP id S1727409AbfJBKJW (ORCPT ); Wed, 2 Oct 2019 06:09:22 -0400 X-IronPort-AV: E=Sophos;i="5.64,574,1559487600"; d="scan'208";a="28103967" Received: from unknown (HELO relmlir6.idc.renesas.com) ([10.200.68.152]) by relmlie5.idc.renesas.com with ESMTP; 02 Oct 2019 19:09:20 +0900 Received: from be1yocto.ree.adwin.renesas.com (unknown [172.29.43.62]) by relmlir6.idc.renesas.com (Postfix) with ESMTP id 5111A42050A5; Wed, 2 Oct 2019 19:09:17 +0900 (JST) From: Biju Das To: Rob Herring , Mark Rutland Cc: Biju Das , Simon Horman , Laurent Pinchart , Kieran Bingham , Geert Uytterhoeven , Magnus Damm , linux-renesas-soc@vger.kernel.org, devicetree@vger.kernel.org, Chris Paterson , Fabrizio Castro Subject: [PATCH v2 9/9] arm64: dts: renesas: Add support for Advantech idk-1110wr LVDS panel Date: Wed, 2 Oct 2019 11:08:26 +0100 Message-Id: <1570010906-47486-10-git-send-email-biju.das@bp.renesas.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1570010906-47486-1-git-send-email-biju.das@bp.renesas.com> References: <1570010906-47486-1-git-send-email-biju.das@bp.renesas.com> Sender: linux-renesas-soc-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-renesas-soc@vger.kernel.org This patch adds support for Advantech idk-1110wr LVDS panel. The HiHope RZ/G2[MN] is advertised as compatible with panel idk-1110wr from Advantech, however the panel isn't sold alongside the board. Signed-off-by: Biju Das Signed-off-by: Fabrizio Castro Reviewed-by: Laurent Pinchart --- V1-->V2 * Incorporated Laurent's review comments --- .../renesas/rzg2-advantech-idk-1110wr-panel.dtsi | 42 ++++++++++++++++++++++ 1 file changed, 42 insertions(+) create mode 100644 arch/arm64/boot/dts/renesas/rzg2-advantech-idk-1110wr-panel.dtsi diff --git a/arch/arm64/boot/dts/renesas/rzg2-advantech-idk-1110wr-panel.dtsi b/arch/arm64/boot/dts/renesas/rzg2-advantech-idk-1110wr-panel.dtsi new file mode 100644 index 0000000..4f876df --- /dev/null +++ b/arch/arm64/boot/dts/renesas/rzg2-advantech-idk-1110wr-panel.dtsi @@ -0,0 +1,42 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Device Tree Source for the Advantech idk-1110wr LVDS panel connected + * to RZ/G2 boards + * + * Copyright (C) 2019 Renesas Electronics Corp. + */ + +/ { + + panel-lvds { + compatible = "advantech,idk-1110wr", "panel-lvds"; + + width-mm = <223>; + height-mm = <125>; + + data-mapping = "jeida-24"; + + panel-timing { + /* 1024x600 @60Hz */ + clock-frequency = <51200000>; + hactive = <1024>; + vactive = <600>; + hsync-len = <240>; + hfront-porch = <40>; + hback-porch = <40>; + vfront-porch = <15>; + vback-porch = <10>; + vsync-len = <10>; + }; + + port { + panel_in: endpoint { + remote-endpoint = <&lvds_connector>; + }; + }; + }; +}; + +&lvds_connector { + remote-endpoint = <&panel_in>; +};