From patchwork Thu Oct 3 05:06:37 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Anup Patel X-Patchwork-Id: 11172097 Return-Path: Received: from mail.kernel.org (pdx-korg-mail-1.web.codeaurora.org [172.30.200.123]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id 47A3F14DB for ; Thu, 3 Oct 2019 05:07:14 +0000 (UTC) Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id 2221021D81 for ; Thu, 3 Oct 2019 05:07:14 +0000 (UTC) Authentication-Results: mail.kernel.org; dkim=pass (2048-bit key) header.d=lists.infradead.org header.i=@lists.infradead.org header.b="BeUcnygh"; dkim=fail reason="signature verification failed" (2048-bit key) header.d=wdc.com header.i=@wdc.com header.b="JJ17tZiZ"; dkim=fail reason="signature verification failed" (1024-bit key) header.d=sharedspace.onmicrosoft.com header.i=@sharedspace.onmicrosoft.com header.b="OO2JwJgX" DMARC-Filter: OpenDMARC Filter v1.3.2 mail.kernel.org 2221021D81 Authentication-Results: mail.kernel.org; dmarc=fail (p=none dis=none) header.from=wdc.com Authentication-Results: mail.kernel.org; spf=none smtp.mailfrom=linux-riscv-bounces+patchwork-linux-riscv=patchwork.kernel.org@lists.infradead.org DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=bombadil.20170209; h=Sender: Content-Transfer-Encoding:Content-Type:Cc:List-Subscribe:List-Help:List-Post: List-Archive:List-Unsubscribe:List-Id:MIME-Version:In-Reply-To:References: Message-ID:Date:Subject:To:From:Reply-To:Content-ID:Content-Description: Resent-Date:Resent-From:Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID: List-Owner; bh=6LPn42pkW+APQToE+ofIVFIjddxwG5IKiZ1ekriMvhw=; b=BeUcnyghY++3pW 2Ny3JRyeAFAsy4M0oTgPzQp64FoAjUfKyXIzaM2Jc7PRK7JjJtSorhigmPUARTKonnFxjZbSe+efo FZjS0UrV1ibBnaY5z3MKwZvDzifJTr0QZtpTy6X2GxGmqqS1u5GTEpyjj2YCo71YTSlgEbGQWKzUj xTebUKSXgyZ6KTQGszrQSV7/DaVh5PVVtXpVo3ifmflMo0rgeQFiYBrGwy3kErZzzaFLzbokITaQp nVf/CemYhDvI8Ls/NSytwhWc93yt+ZYS81o4mgQdD5jp8Sxh6ptV7ZsC3FWMYDEUWt6uT2XnLTaRP W2Inw8f6pqprVPOUfMJw==; Received: from localhost ([127.0.0.1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.92.2 #3 (Red Hat Linux)) id 1iFtKI-0003Fm-FX; Thu, 03 Oct 2019 05:06:54 +0000 Received: from esa5.hgst.iphmx.com ([216.71.153.144]) by bombadil.infradead.org with esmtps (Exim 4.92.2 #3 (Red Hat Linux)) id 1iFtKE-0003AN-GI for linux-riscv@lists.infradead.org; Thu, 03 Oct 2019 05:06:52 +0000 DKIM-Signature: v=1; a=rsa-sha256; c=simple/simple; d=wdc.com; i=@wdc.com; q=dns/txt; s=dkim.wdc.com; t=1570079210; x=1601615210; h=from:to:cc:subject:date:message-id:references: in-reply-to:content-transfer-encoding:mime-version; bh=+A2ZJ1+Du23SnbGIDSEykGTOoe9pFTwS8AcSw1fUgkI=; b=JJ17tZiZjRa1IYHLxyFkxVB9qUTAtINTtJmHH307Su9l0qinyCb4YZtc kCBnmIJSsOoK4oU4N67rNebxLZwe24L6acxVnb980uMblRfSuCjTS2V9J kOYjZRpZk5YvdInp2TNQ/f7BNSE/90PR/cXB5ulR8XsUwNh5v912EAqvp r1CwQp+36gUfT4TXT+yBc7QXAVFExsaFqUaUypPCjMMM3oY4Eo8xoLliy sDdhs9WgnJkSsVOUeEA6I8ExC8DRx2Hcd5QYwm58j32u/4g8H0xFOLIcA MgX5KzzQq137cF+tkvI/VwLWMgwH62WuS1Aqkz7PQRB943nZp28sBAGW8 A==; IronPort-SDR: NdMo9tYXvIUOwn5GdJKOHwb/IkEbwxFCaG9hIQZqkWF3xGCuk0+LYS6zIYj20t+h82YzINjMo9 +OVb4hEhB5LVdnDwdUsxClqw8teYPuWz/f/99YAictx42OqH8t2L8RYhx4vyslgIgny9PC05CH VvELTlk97o9WZdR+KsRiDyaUm0UXSzq8OHaN3gorXiRv6K+S4xq9j0Xia/O3SmozgaIpzKdxuj EGNNHq6i1kSGYZvPbVrTAEhKAveGgd56S62aahF4rF4UT9x81sVbdPuNzIvYQR7onsk+lgD5YJ gCU= X-IronPort-AV: E=Sophos;i="5.67,251,1566835200"; d="scan'208";a="120461283" Received: from mail-co1nam03lp2059.outbound.protection.outlook.com (HELO NAM03-CO1-obe.outbound.protection.outlook.com) ([104.47.40.59]) by ob1.hgst.iphmx.com with ESMTP; 03 Oct 2019 13:06:38 +0800 ARC-Seal: i=1; a=rsa-sha256; s=arcselector9901; d=microsoft.com; cv=none; b=fXw9EQS4+CA2cM93mraUGxxOVcpxS/UV4ROvy4vhKGm406Lg2JT0A1zXI8JpFDHhhs6mvlwp8A9E/1NCwrPomSv2r7QJqwNr3mw4ncpGOvZBwHSwAHozhvWX4CCqRW0a/1ZcNGEZwCOmQV96DF4LrtG/RDyL4QSubu9DhwOGWHFUiowI418CsdnM4awDC3mt2KJuMGVeSN6eflc+JCYHKJ71Vq3intq7e5VtD91/lpMEhlaOCFw398v4rQu5Eucsos6eoOUk+Ra/n5i63HB6Umj5paoikLd6uFehxIUkFCLN2dHT/nwxVcAVO63MF574m2/smojUet/hcow0b0hNfg== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=microsoft.com; s=arcselector9901; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-SenderADCheck; bh=+ng04hoOzq57TGmSmTLrnTpV7rjJVazlrDmWeCuRHiw=; b=QklvUWOmKZen3q1vc7gG0b7xdLw69dpzbFE4fkiTw6Sb+DVk0MCHtHy7mv99SJBJ3neGpLvUz01HlvQsaVKtdpwQvN91w8UXZwQSa060amj8mQpAtJ1VLFujgd60psIZoYy/Q/HNG/8RRB1buBH6kKPRwQLuXY1JDfjTkUVwxw+2Sob7j7lj4P896jSUqry1qiJzCc6SW2wmyzcnKM1Sy4EWiCA1uVugLb9Aa0wno8xdd92WJfJJLY1+LU2oC7p1Y7Vzzi9MAQaFW1ZBeyQkPmDEZjNFGSPWnwnBR9tuVBjTXeTXkLfGuEtDGbygL0qgzLhRZOcTcyymP6Huoex8hg== ARC-Authentication-Results: i=1; mx.microsoft.com 1; spf=pass smtp.mailfrom=wdc.com; dmarc=pass action=none header.from=wdc.com; dkim=pass header.d=wdc.com; arc=none DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=sharedspace.onmicrosoft.com; s=selector2-sharedspace-onmicrosoft-com; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-SenderADCheck; bh=+ng04hoOzq57TGmSmTLrnTpV7rjJVazlrDmWeCuRHiw=; b=OO2JwJgXUfvKTdxiyb7HxIS7QNjqKDx/Wj2MrQXtJBKzQf/8+0CD1sDN9yMsJFXn/qiumGOr+DQ/QEMbhI7HT8mysilxin5o6jUQ2ZYCoWOHkGKpIUfMBGmjk5fHvvsnV4lSeViHAT31UWYs3m6FLNkNVEUF/IHepbUtv5bZom0= Received: from MN2PR04MB6061.namprd04.prod.outlook.com (20.178.246.15) by MN2PR04MB6991.namprd04.prod.outlook.com (10.186.144.209) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.2305.18; Thu, 3 Oct 2019 05:06:37 +0000 Received: from MN2PR04MB6061.namprd04.prod.outlook.com ([fe80::1454:87a:13b0:d3a]) by MN2PR04MB6061.namprd04.prod.outlook.com ([fe80::1454:87a:13b0:d3a%7]) with mapi id 15.20.2305.023; Thu, 3 Oct 2019 05:06:37 +0000 From: Anup Patel To: Palmer Dabbelt , Paul Walmsley , Paolo Bonzini , Radim K Subject: [PATCH v8 01/19] RISC-V: Add bitmap reprensenting ISA features common across CPUs Thread-Topic: [PATCH v8 01/19] RISC-V: Add bitmap reprensenting ISA features common across CPUs Thread-Index: AQHVeahV15EOT3PPQ0aY9a6zOfeW3g== Date: Thu, 3 Oct 2019 05:06:37 +0000 Message-ID: <20191003050558.9031-2-anup.patel@wdc.com> References: <20191003050558.9031-1-anup.patel@wdc.com> In-Reply-To: <20191003050558.9031-1-anup.patel@wdc.com> Accept-Language: en-US Content-Language: en-US X-MS-Has-Attach: X-MS-TNEF-Correlator: x-clientproxiedby: BMXPR01CA0030.INDPRD01.PROD.OUTLOOK.COM (2603:1096:b00:c::16) To MN2PR04MB6061.namprd04.prod.outlook.com (2603:10b6:208:d8::15) authentication-results: spf=none (sender IP is ) smtp.mailfrom=Anup.Patel@wdc.com; x-ms-exchange-messagesentrepresentingtype: 1 x-mailer: git-send-email 2.17.1 x-originating-ip: [111.235.74.37] x-ms-publictraffictype: Email x-ms-office365-filtering-correlation-id: c53c98c7-807a-4444-1645-08d747bf77ca x-ms-office365-filtering-ht: Tenant x-ms-traffictypediagnostic: MN2PR04MB6991: x-ms-exchange-transport-forked: True x-microsoft-antispam-prvs: wdcipoutbound: EOP-TRUE x-ms-oob-tlc-oobclassifiers: OLM:317; x-forefront-prvs: 01792087B6 x-forefront-antispam-report: SFV:NSPM; SFS:(10019020)(4636009)(366004)(346002)(39860400002)(136003)(376002)(396003)(189003)(199004)(7416002)(52116002)(25786009)(102836004)(76176011)(54906003)(6506007)(1076003)(386003)(7736002)(44832011)(6436002)(486006)(66066001)(71190400001)(71200400001)(11346002)(446003)(6116002)(3846002)(476003)(2616005)(26005)(305945005)(6512007)(36756003)(186003)(14454004)(110136005)(5660300002)(6486002)(66446008)(66476007)(8936002)(66556008)(256004)(64756008)(66946007)(86362001)(8676002)(81156014)(81166006)(99286004)(316002)(4326008)(2906002)(478600001)(50226002); DIR:OUT; SFP:1102; SCL:1; SRVR:MN2PR04MB6991; H:MN2PR04MB6061.namprd04.prod.outlook.com; FPR:; SPF:None; LANG:en; PTR:InfoNoRecords; MX:1; A:1; x-ms-exchange-senderadcheck: 1 x-microsoft-antispam: BCL:0; x-microsoft-antispam-message-info: 47rSjwKH9seA2/WYOnTe9bSYjQc85Q/ZbCi35nyYr1XKnrd385UtwTTD7L3PcRJTtAdlFRZ80Jr8dZMznBwD2F67quyYfqIXvXLaqjL1yaFXQ8fBB6iNRrN7iRVzMnEoAvcJHwZUoOcfShOEI8dN9KMJVF6GSTEAWW5jigOqDSRpKrvjKix2wvZcwtuT3tyiKsrdRtpc1wWaF/qKiA2c3Nh3rK4Rz9EHYmWe836MRHJylRTEefWDWq/Dj8is7zza6ms2/L5lycWTk8+R0j8ETG4GQ3gVEsc93xbaldolQmAvmEIqm9UX7hN5G7oqJaD8FOZ40dv2z4fnmmRL0RF2joIC3W1YVIfLnuRiPQdqLvdYF0DTX6zkmxSFJWF6wShLFZ36h4JayxBeCKg6XUs7tQ/iAWvnLKVN3mLuHxMVWHM= MIME-Version: 1.0 X-OriginatorOrg: wdc.com X-MS-Exchange-CrossTenant-Network-Message-Id: c53c98c7-807a-4444-1645-08d747bf77ca X-MS-Exchange-CrossTenant-originalarrivaltime: 03 Oct 2019 05:06:37.4060 (UTC) X-MS-Exchange-CrossTenant-fromentityheader: Hosted X-MS-Exchange-CrossTenant-id: b61c8803-16f3-4c35-9b17-6f65f441df86 X-MS-Exchange-CrossTenant-mailboxtype: HOSTED X-MS-Exchange-CrossTenant-userprincipalname: npHe2RquDDEhjV4eYQXEvIbzFmemdbA2lw6GCf9TvegjqQfCPSYe5gP9askCkZoKterommmSdWHlIm41Sim6zw== X-MS-Exchange-Transport-CrossTenantHeadersStamped: MN2PR04MB6991 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20191002_220650_565487_8A9D1A20 X-CRM114-Status: GOOD ( 17.52 ) X-Spam-Score: -2.5 (--) X-Spam-Report: SpamAssassin version 3.4.2 on bombadil.infradead.org summary: Content analysis details: (-2.5 points) pts rule name description ---- ---------------------- -------------------------------------------------- -2.3 RCVD_IN_DNSWL_MED RBL: Sender listed at https://www.dnswl.org/, medium trust [216.71.153.144 listed in list.dnswl.org] -0.0 SPF_PASS SPF: sender matches SPF record 0.0 SPF_HELO_NONE SPF: HELO does not publish an SPF Record -0.1 DKIM_VALID_EF Message has a valid DKIM or DK signature from envelope-from domain 0.1 DKIM_SIGNED Message has a DKIM or DK signature, not necessarily valid -0.1 DKIM_VALID_AU Message has a valid DKIM or DK signature from author's domain -0.1 DKIM_VALID Message has at least one valid DKIM or DK signature X-BeenThere: linux-riscv@lists.infradead.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Damien Le Moal , Anup Patel , "kvm@vger.kernel.org" , Anup Patel , Daniel Lezcano , "linux-kernel@vger.kernel.org" , Christoph Hellwig , Atish Patra , Alexander Graf , Alistair Francis , Thomas Gleixner , "linux-riscv@lists.infradead.org" Sender: "linux-riscv" Errors-To: linux-riscv-bounces+patchwork-linux-riscv=patchwork.kernel.org@lists.infradead.org This patch adds riscv_isa bitmap which represents Host ISA features common across all Host CPUs. The riscv_isa is not same as elf_hwcap because elf_hwcap will only have ISA features relevant for user-space apps whereas riscv_isa will have ISA features relevant to both kernel and user-space apps. One of the use-case for riscv_isa bitmap is in KVM hypervisor where we will use it to do following operations: 1. Check whether hypervisor extension is available 2. Find ISA features that need to be virtualized (e.g. floating point support, vector extension, etc.) Signed-off-by: Anup Patel Signed-off-by: Atish Patra Reviewed-by: Alexander Graf --- arch/riscv/include/asm/hwcap.h | 22 +++++++++ arch/riscv/kernel/cpufeature.c | 83 ++++++++++++++++++++++++++++++++-- 2 files changed, 102 insertions(+), 3 deletions(-) diff --git a/arch/riscv/include/asm/hwcap.h b/arch/riscv/include/asm/hwcap.h index 7ecb7c6a57b1..5989dd4426d1 100644 --- a/arch/riscv/include/asm/hwcap.h +++ b/arch/riscv/include/asm/hwcap.h @@ -8,6 +8,7 @@ #ifndef __ASM_HWCAP_H #define __ASM_HWCAP_H +#include #include #ifndef __ASSEMBLY__ @@ -22,5 +23,26 @@ enum { }; extern unsigned long elf_hwcap; + +#define RISCV_ISA_EXT_a ('a' - 'a') +#define RISCV_ISA_EXT_c ('c' - 'a') +#define RISCV_ISA_EXT_d ('d' - 'a') +#define RISCV_ISA_EXT_f ('f' - 'a') +#define RISCV_ISA_EXT_h ('h' - 'a') +#define RISCV_ISA_EXT_i ('i' - 'a') +#define RISCV_ISA_EXT_m ('m' - 'a') +#define RISCV_ISA_EXT_s ('s' - 'a') +#define RISCV_ISA_EXT_u ('u' - 'a') + +#define RISCV_ISA_EXT_MAX 256 + +unsigned long riscv_isa_extension_base(const unsigned long *isa_bitmap); + +#define riscv_isa_extension_mask(ext) BIT_MASK(RISCV_ISA_EXT_##ext) + +bool __riscv_isa_extension_available(const unsigned long *isa_bitmap, int bit); +#define riscv_isa_extension_available(isa_bitmap, ext) \ + __riscv_isa_extension_available(isa_bitmap, RISCV_ISA_EXT_##ext) + #endif #endif diff --git a/arch/riscv/kernel/cpufeature.c b/arch/riscv/kernel/cpufeature.c index b1ade9a49347..941aeb33f85b 100644 --- a/arch/riscv/kernel/cpufeature.c +++ b/arch/riscv/kernel/cpufeature.c @@ -6,21 +6,64 @@ * Copyright (C) 2017 SiFive */ +#include #include #include #include #include unsigned long elf_hwcap __read_mostly; + +/* Host ISA bitmap */ +static DECLARE_BITMAP(riscv_isa, RISCV_ISA_EXT_MAX) __read_mostly; + #ifdef CONFIG_FPU bool has_fpu __read_mostly; #endif +/** + * riscv_isa_extension_base() - Get base extension word + * + * @isa_bitmap: ISA bitmap to use + * Return: base extension word as unsigned long value + * + * NOTE: If isa_bitmap is NULL then Host ISA bitmap will be used. + */ +unsigned long riscv_isa_extension_base(const unsigned long *isa_bitmap) +{ + if (!isa_bitmap) + return riscv_isa[0]; + return isa_bitmap[0]; +} +EXPORT_SYMBOL_GPL(riscv_isa_extension_base); + +/** + * __riscv_isa_extension_available() - Check whether given extension + * is available or not + * + * @isa_bitmap: ISA bitmap to use + * @bit: bit position of the desired extension + * Return: true or false + * + * NOTE: If isa_bitmap is NULL then Host ISA bitmap will be used. + */ +bool __riscv_isa_extension_available(const unsigned long *isa_bitmap, int bit) +{ + const unsigned long *bmap = (isa_bitmap) ? isa_bitmap : riscv_isa; + + if (bit >= RISCV_ISA_EXT_MAX) + return false; + + return test_bit(bit, bmap) ? true : false; +} +EXPORT_SYMBOL_GPL(__riscv_isa_extension_available); + void riscv_fill_hwcap(void) { struct device_node *node; const char *isa; - size_t i; + char print_str[BITS_PER_LONG+1]; + size_t i, j, isa_len; static unsigned long isa2hwcap[256] = {0}; isa2hwcap['i'] = isa2hwcap['I'] = COMPAT_HWCAP_ISA_I; @@ -32,8 +75,11 @@ void riscv_fill_hwcap(void) elf_hwcap = 0; + bitmap_zero(riscv_isa, RISCV_ISA_EXT_MAX); + for_each_of_cpu_node(node) { unsigned long this_hwcap = 0; + unsigned long this_isa = 0; if (riscv_of_processor_hartid(node) < 0) continue; @@ -43,8 +89,24 @@ void riscv_fill_hwcap(void) continue; } - for (i = 0; i < strlen(isa); ++i) + i = 0; + isa_len = strlen(isa); +#if defined(CONFIG_32BIT) + if (!strncmp(isa, "rv32", 4)) + i += 4; +#elif defined(CONFIG_64BIT) + if (!strncmp(isa, "rv64", 4)) + i += 4; +#endif + for (; i < isa_len; ++i) { this_hwcap |= isa2hwcap[(unsigned char)(isa[i])]; + /* + * TODO: X, Y and Z extension parsing for Host ISA + * bitmap will be added in-future. + */ + if ('a' <= isa[i] && isa[i] < 'x') + this_isa |= (1UL << (isa[i] - 'a')); + } /* * All "okay" hart should have same isa. Set HWCAP based on @@ -55,6 +117,11 @@ void riscv_fill_hwcap(void) elf_hwcap &= this_hwcap; else elf_hwcap = this_hwcap; + + if (riscv_isa[0]) + riscv_isa[0] &= this_isa; + else + riscv_isa[0] = this_isa; } /* We don't support systems with F but without D, so mask those out @@ -64,7 +131,17 @@ void riscv_fill_hwcap(void) elf_hwcap &= ~COMPAT_HWCAP_ISA_F; } - pr_info("elf_hwcap is 0x%lx\n", elf_hwcap); + memset(print_str, 0, sizeof(print_str)); + for (i = 0, j = 0; i < BITS_PER_LONG; i++) + if (riscv_isa[0] & BIT_MASK(i)) + print_str[j++] = (char)('a' + i); + pr_info("riscv: ISA extensions %s\n", print_str); + + memset(print_str, 0, sizeof(print_str)); + for (i = 0, j = 0; i < BITS_PER_LONG; i++) + if (elf_hwcap & BIT_MASK(i)) + print_str[j++] = (char)('a' + i); + pr_info("riscv: ELF capabilities %s\n", print_str); #ifdef CONFIG_FPU if (elf_hwcap & (COMPAT_HWCAP_ISA_F | COMPAT_HWCAP_ISA_D)) From patchwork Thu Oct 3 05:06:44 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Anup Patel X-Patchwork-Id: 11172093 Return-Path: Received: from mail.kernel.org (pdx-korg-mail-1.web.codeaurora.org [172.30.200.123]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id 2FFD117EE for ; Thu, 3 Oct 2019 05:07:13 +0000 (UTC) Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id 0CFFC222C4 for ; Thu, 3 Oct 2019 05:07:13 +0000 (UTC) Authentication-Results: mail.kernel.org; dkim=pass (2048-bit key) header.d=lists.infradead.org header.i=@lists.infradead.org header.b="aF6GLZVJ"; dkim=fail reason="signature verification failed" (2048-bit key) header.d=wdc.com header.i=@wdc.com header.b="TEzVwlBP"; dkim=fail reason="signature verification failed" (1024-bit key) header.d=sharedspace.onmicrosoft.com header.i=@sharedspace.onmicrosoft.com header.b="gC9eXgHH" DMARC-Filter: OpenDMARC Filter v1.3.2 mail.kernel.org 0CFFC222C4 Authentication-Results: mail.kernel.org; dmarc=fail (p=none dis=none) header.from=wdc.com Authentication-Results: mail.kernel.org; spf=none smtp.mailfrom=linux-riscv-bounces+patchwork-linux-riscv=patchwork.kernel.org@lists.infradead.org DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=bombadil.20170209; h=Sender: Content-Transfer-Encoding:Content-Type:Cc:List-Subscribe:List-Help:List-Post: List-Archive:List-Unsubscribe:List-Id:MIME-Version:In-Reply-To:References: Message-ID:Date:Subject:To:From:Reply-To:Content-ID:Content-Description: Resent-Date:Resent-From:Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID: List-Owner; bh=GClZU1WNZC3Wbu3nQgxzVtlT4vHqhiWwdNVSR5KEf0k=; b=aF6GLZVJOlprEA yjwEWDIyWturW57jyHorKOadbPFiFVR6iJOB+02sG0ggQQrvW9KjrMffJrPOV+XQwlEywpRuvFxDU +GT95vyBGDJqYDrcpe93PdwRPi3pJagv5DXcPt/a0xhVYPzyAlPIfGbPVphsoC9Uhyn15v57kVAMM uIEDD88U6zqE5IobTNr5+BSiCG09LPT0g6b+IeWv/AwOOsB7bexqNVIXSvalxyFYGj15Fi24pTDAx HqlrqgOxfsfFsKl6QvGjEG/Y/OBIqb9axMxgcctwieOOxDj30g1eKd5377E0hD52kSDxr16BPZkDg 5usnHOLeeHXUJdF5f9jQ==; Received: from localhost ([127.0.0.1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.92.2 #3 (Red Hat Linux)) id 1iFtKF-0003CH-FC; Thu, 03 Oct 2019 05:06:51 +0000 Received: from esa1.hgst.iphmx.com ([68.232.141.245]) by bombadil.infradead.org with esmtps (Exim 4.92.2 #3 (Red Hat Linux)) id 1iFtKC-0003AT-JP for linux-riscv@lists.infradead.org; Thu, 03 Oct 2019 05:06:50 +0000 DKIM-Signature: v=1; a=rsa-sha256; c=simple/simple; d=wdc.com; i=@wdc.com; q=dns/txt; s=dkim.wdc.com; t=1570079208; x=1601615208; h=from:to:cc:subject:date:message-id:references: in-reply-to:content-transfer-encoding:mime-version; bh=ZmzTfG5qj0/ShH8NlNjNMPphgeVWAziCNJJHP4F1jcg=; b=TEzVwlBP90g/rY6VvJETiF0SgQq7OF6RtB+dOl+QCx4IY2y5L9dH536j HWv1PZtgcoD1trZ2y6LOuFmDh/DCcBg0ExU6rwm0wamljl1J/Lku/9cBq pB64bJJYVl7hd51JnyKClazfO5VVcb0jE84CDi5UnPWzuGeeLOR6ULkR3 Ji2KbzJgmCPuWfMVFiGi++h/xpMXG/KzVDwfk33Ftvbt6N2tmCfVfNI48 MAvKnuTXbtjpNMtCRugq/oHNwqiSMqAD24miNvMmd1zDn70fs62cnLSiG ClBHR7NREe1C+0av1o8Tw639Go7HW+7ToFU8PVUrUfhNgq58gytWbp8qg A==; IronPort-SDR: VWs5s1WIBcnbAUE9UimAgCTRBiZ5dgoZqOsC4p/UtXI8PdRy/+ywEo5cuFhbklEQgfM+bo6Kkl hTZyh80xWuSe95Iq5LUfZzIRIPS3h86V2Ji0gcbTgG6gmhECe7Z+wX0mFUDEjOqS9fcM+JlTlH c+Sk6FegnCwxXM94nyIqMgVcBuMkwUhaoFvCCZKWR255jwed7T5RerrQ0n7b0wHTC4088++MuR sgw6ptk8ruvCaUpWTbZwrc1UinTwsOTKJH0QCP+eLhh1cb+MM1JVrVAW4iMvyat2qEuIYNS4py WYU= X-IronPort-AV: E=Sophos;i="5.67,251,1566835200"; d="scan'208";a="226621541" Received: from mail-co1nam03lp2055.outbound.protection.outlook.com (HELO NAM03-CO1-obe.outbound.protection.outlook.com) ([104.47.40.55]) by ob1.hgst.iphmx.com with ESMTP; 03 Oct 2019 13:06:45 +0800 ARC-Seal: i=1; a=rsa-sha256; s=arcselector9901; d=microsoft.com; cv=none; b=LMmfYskzTtIgiwPIM5gPhUZCh5ekM8kZ6NC97H5mY44D2wdArodDTfkoZaMWU6r+2ujlFJszlOjcEICaCak9bZPDkRHFz/CRXd2k+dYkwMA+3aHN/KUbPZBMuoWYt4MT37PzcgKmFeapRy81s9xR4vXuVq+M/RTEKFDxxATZwsCWZiJlsS4ojxgCNH4T6cvRYA8X+hUF33ZFtRyUXfOz6/w6afH7FIMeeIvJNgU9bVqSvvSPCXCoI34uADNoxbsf4ZHnxsHiCjcXkyK9ZbLnHN4Q60qnoXdaMmBHLR8zz4Gl2Ak6yxIf5Wggg28uJM7WkxwPZh7kKL5JpvOM4mST0g== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=microsoft.com; s=arcselector9901; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-SenderADCheck; bh=sd8iv6eUevGkw+GvTJYLdZ1DAx6Bzra73a6Mzs1JQDE=; b=A0S/yYz7520Iqcjh33FyL6ThNaxhb8UNX5VNlAQhyh6QT7qfxbq35H1NBFZ2Kn4brLWoZbQ8glkg28nIq2kGpAJ/24NR7ISk1/OIh5xzXNEJld8tn6KbpJFNEpVY7reW1+FMQk4dlNU5DnZLGIsxh1wA8eIqdZdLiMrK5IgADdI1wSF+MO27VkwtyMtaONy+uKSgBdq35/TOvwqxmnXqp6y6zo9ALShR9q++bnenI5mvP+tDnXV+OtClCA7qwJ5x26DPn5OuyAJVjOdJYXBArGpkiC7xUJndOw6U2tSMQ82PUmnk8rbODST4QZPHKYl40jFgHknlNazNsedZqViCwg== ARC-Authentication-Results: i=1; mx.microsoft.com 1; spf=pass smtp.mailfrom=wdc.com; dmarc=pass action=none header.from=wdc.com; dkim=pass header.d=wdc.com; arc=none DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=sharedspace.onmicrosoft.com; s=selector2-sharedspace-onmicrosoft-com; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-SenderADCheck; bh=sd8iv6eUevGkw+GvTJYLdZ1DAx6Bzra73a6Mzs1JQDE=; b=gC9eXgHH2g6RlDLJwd6iLdsniXrJKCsJMAqoMZs70dv5fZj9RKKcqyUNz4hgk2jD+leLM1i4phB6E/tYolVa8AYPqwQyRH/T026+n2gwgbM9/ZAj4IYnBal46Jg7ObQ8NgOB4C82tOcmO5zexM6PGlfdGrIXLt8rss0ls05mFjg= Received: from MN2PR04MB6061.namprd04.prod.outlook.com (20.178.246.15) by MN2PR04MB6991.namprd04.prod.outlook.com (10.186.144.209) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.2305.18; Thu, 3 Oct 2019 05:06:44 +0000 Received: from MN2PR04MB6061.namprd04.prod.outlook.com ([fe80::1454:87a:13b0:d3a]) by MN2PR04MB6061.namprd04.prod.outlook.com ([fe80::1454:87a:13b0:d3a%7]) with mapi id 15.20.2305.023; Thu, 3 Oct 2019 05:06:44 +0000 From: Anup Patel To: Palmer Dabbelt , Paul Walmsley , Paolo Bonzini , Radim K Subject: [PATCH v8 02/19] RISC-V: Add hypervisor extension related CSR defines Thread-Topic: [PATCH v8 02/19] RISC-V: Add hypervisor extension related CSR defines Thread-Index: AQHVeahZFXaJUz1wFE6Q5kz/rSOTjw== Date: Thu, 3 Oct 2019 05:06:44 +0000 Message-ID: <20191003050558.9031-3-anup.patel@wdc.com> References: <20191003050558.9031-1-anup.patel@wdc.com> In-Reply-To: <20191003050558.9031-1-anup.patel@wdc.com> Accept-Language: en-US Content-Language: en-US X-MS-Has-Attach: X-MS-TNEF-Correlator: x-clientproxiedby: BMXPR01CA0030.INDPRD01.PROD.OUTLOOK.COM (2603:1096:b00:c::16) To MN2PR04MB6061.namprd04.prod.outlook.com (2603:10b6:208:d8::15) authentication-results: spf=none (sender IP is ) smtp.mailfrom=Anup.Patel@wdc.com; x-ms-exchange-messagesentrepresentingtype: 1 x-mailer: git-send-email 2.17.1 x-originating-ip: [111.235.74.37] x-ms-publictraffictype: Email x-ms-office365-filtering-correlation-id: cd6c0d28-2bcb-4d2d-1797-08d747bf7c1d x-ms-office365-filtering-ht: Tenant x-ms-traffictypediagnostic: MN2PR04MB6991: x-ms-exchange-transport-forked: True x-microsoft-antispam-prvs: wdcipoutbound: EOP-TRUE x-ms-oob-tlc-oobclassifiers: OLM:5; x-forefront-prvs: 01792087B6 x-forefront-antispam-report: SFV:NSPM; SFS:(10019020)(4636009)(366004)(346002)(39860400002)(136003)(376002)(396003)(189003)(199004)(7416002)(52116002)(25786009)(102836004)(76176011)(54906003)(6506007)(1076003)(386003)(7736002)(44832011)(6436002)(486006)(66066001)(71190400001)(71200400001)(11346002)(446003)(6116002)(3846002)(476003)(2616005)(26005)(305945005)(6512007)(36756003)(186003)(14454004)(110136005)(5660300002)(6486002)(66446008)(66476007)(8936002)(66556008)(256004)(64756008)(66946007)(86362001)(8676002)(81156014)(81166006)(99286004)(316002)(4326008)(2906002)(478600001)(50226002); DIR:OUT; SFP:1102; SCL:1; SRVR:MN2PR04MB6991; H:MN2PR04MB6061.namprd04.prod.outlook.com; FPR:; SPF:None; LANG:en; PTR:InfoNoRecords; MX:1; A:1; x-ms-exchange-senderadcheck: 1 x-microsoft-antispam: BCL:0; x-microsoft-antispam-message-info: 1yP2or5FIqIMN5EEhO54HOca2pS0YTMRlcKHuezojpV8okmWF3/LQZhbcpQBxKiv9nt5Yhked8t1QfX/PlYn+ug0aKa0i6Xw5RoNLh5cxAr7Ul7VkMR6dFUOsgyt2q/pmH9tcw4N4mcC7CnqfXHXtyjOPWeS+8kc325XA5q6CthL+5omGz7QNM0HWm+B8AbYPjyPN29EnXyE7C+ZDxCVjb+bjWVQnItlYWMupWDqg3gzYuCTKG3VoL1jat1cHoIJfIetwWuik6xxzYu4CvbS5Y01lRVIoWFWXXW+QgdamYMP5z/Mt1W8Yn1f109HsIRp6laMFOYBotv7bdWQ1QarOMVOikaEypo80HLVjQy4t4sQ795jna3j2Qtvnao/5ko3PziwnqqMJj8kZxxHoZ83N1KE8XWzG9c+gwUHzPCFgIA= MIME-Version: 1.0 X-OriginatorOrg: wdc.com X-MS-Exchange-CrossTenant-Network-Message-Id: cd6c0d28-2bcb-4d2d-1797-08d747bf7c1d X-MS-Exchange-CrossTenant-originalarrivaltime: 03 Oct 2019 05:06:44.6339 (UTC) X-MS-Exchange-CrossTenant-fromentityheader: Hosted X-MS-Exchange-CrossTenant-id: b61c8803-16f3-4c35-9b17-6f65f441df86 X-MS-Exchange-CrossTenant-mailboxtype: HOSTED X-MS-Exchange-CrossTenant-userprincipalname: vnn23MGWRZbJivuYQZx66taWAVwnwMLoMT9RSil+srQCJG0ja6g9wYPkQC1uj+VDVtAVw1CJkz+iXzwJF3/CKw== X-MS-Exchange-Transport-CrossTenantHeadersStamped: MN2PR04MB6991 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20191002_220648_647831_CF40B2EC X-CRM114-Status: GOOD ( 10.04 ) X-Spam-Score: -2.5 (--) X-Spam-Report: SpamAssassin version 3.4.2 on bombadil.infradead.org summary: Content analysis details: (-2.5 points) pts rule name description ---- ---------------------- -------------------------------------------------- -2.3 RCVD_IN_DNSWL_MED RBL: Sender listed at https://www.dnswl.org/, medium trust [68.232.141.245 listed in list.dnswl.org] -0.0 SPF_PASS SPF: sender matches SPF record 0.0 SPF_HELO_NONE SPF: HELO does not publish an SPF Record -0.1 DKIM_VALID_EF Message has a valid DKIM or DK signature from envelope-from domain 0.1 DKIM_SIGNED Message has a DKIM or DK signature, not necessarily valid -0.1 DKIM_VALID_AU Message has a valid DKIM or DK signature from author's domain -0.1 DKIM_VALID Message has at least one valid DKIM or DK signature X-BeenThere: linux-riscv@lists.infradead.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Damien Le Moal , Anup Patel , "kvm@vger.kernel.org" , Anup Patel , Daniel Lezcano , "linux-kernel@vger.kernel.org" , Christoph Hellwig , Atish Patra , Alexander Graf , Alistair Francis , Thomas Gleixner , "linux-riscv@lists.infradead.org" Sender: "linux-riscv" Errors-To: linux-riscv-bounces+patchwork-linux-riscv=patchwork.kernel.org@lists.infradead.org This patch extends asm/csr.h by adding RISC-V hypervisor extension related defines. Signed-off-by: Anup Patel Acked-by: Paolo Bonzini Reviewed-by: Paolo Bonzini Reviewed-by: Alexander Graf --- arch/riscv/include/asm/csr.h | 58 ++++++++++++++++++++++++++++++++++++ 1 file changed, 58 insertions(+) diff --git a/arch/riscv/include/asm/csr.h b/arch/riscv/include/asm/csr.h index a18923fa23c8..059c5cb22aaf 100644 --- a/arch/riscv/include/asm/csr.h +++ b/arch/riscv/include/asm/csr.h @@ -27,6 +27,8 @@ #define SR_XS_CLEAN _AC(0x00010000, UL) #define SR_XS_DIRTY _AC(0x00018000, UL) +#define SR_MXR _AC(0x00080000, UL) + #ifndef CONFIG_64BIT #define SR_SD _AC(0x80000000, UL) /* FS/XS dirty */ #else @@ -59,10 +61,13 @@ #define EXC_INST_MISALIGNED 0 #define EXC_INST_ACCESS 1 +#define EXC_INST_ILLEGAL 2 #define EXC_BREAKPOINT 3 #define EXC_LOAD_ACCESS 5 #define EXC_STORE_ACCESS 7 #define EXC_SYSCALL 8 +#define EXC_HYPERVISOR_SYSCALL 9 +#define EXC_SUPERVISOR_SYSCALL 10 #define EXC_INST_PAGE_FAULT 12 #define EXC_LOAD_PAGE_FAULT 13 #define EXC_STORE_PAGE_FAULT 15 @@ -72,6 +77,43 @@ #define SIE_STIE (_AC(0x1, UL) << IRQ_S_TIMER) #define SIE_SEIE (_AC(0x1, UL) << IRQ_S_EXT) +/* HSTATUS flags */ +#define HSTATUS_VTSR _AC(0x00400000, UL) +#define HSTATUS_VTVM _AC(0x00100000, UL) +#define HSTATUS_SP2V _AC(0x00000200, UL) +#define HSTATUS_SP2P _AC(0x00000100, UL) +#define HSTATUS_SPV _AC(0x00000080, UL) +#define HSTATUS_STL _AC(0x00000040, UL) +#define HSTATUS_SPRV _AC(0x00000001, UL) + +/* HGATP flags */ +#define HGATP_MODE_OFF _AC(0, UL) +#define HGATP_MODE_SV32X4 _AC(1, UL) +#define HGATP_MODE_SV39X4 _AC(8, UL) +#define HGATP_MODE_SV48X4 _AC(9, UL) + +#define HGATP32_MODE_SHIFT 31 +#define HGATP32_VMID_SHIFT 22 +#define HGATP32_VMID_MASK _AC(0x1FC00000, UL) +#define HGATP32_PPN _AC(0x003FFFFF, UL) + +#define HGATP64_MODE_SHIFT 60 +#define HGATP64_VMID_SHIFT 44 +#define HGATP64_VMID_MASK _AC(0x03FFF00000000000, UL) +#define HGATP64_PPN _AC(0x00000FFFFFFFFFFF, UL) + +#ifdef CONFIG_64BIT +#define HGATP_PPN HGATP64_PPN +#define HGATP_VMID_SHIFT HGATP64_VMID_SHIFT +#define HGATP_VMID_MASK HGATP64_VMID_MASK +#define HGATP_MODE (HGATP_MODE_SV39X4 << HGATP64_MODE_SHIFT) +#else +#define HGATP_PPN HGATP32_PPN +#define HGATP_VMID_SHIFT HGATP32_VMID_SHIFT +#define HGATP_VMID_MASK HGATP32_VMID_MASK +#define HGATP_MODE (HGATP_MODE_SV32X4 << HGATP32_MODE_SHIFT) +#endif + #define CSR_CYCLE 0xc00 #define CSR_TIME 0xc01 #define CSR_INSTRET 0xc02 @@ -85,6 +127,22 @@ #define CSR_STVAL 0x143 #define CSR_SIP 0x144 #define CSR_SATP 0x180 + +#define CSR_VSSTATUS 0x200 +#define CSR_VSIE 0x204 +#define CSR_VSTVEC 0x205 +#define CSR_VSSCRATCH 0x240 +#define CSR_VSEPC 0x241 +#define CSR_VSCAUSE 0x242 +#define CSR_VSTVAL 0x243 +#define CSR_VSIP 0x244 +#define CSR_VSATP 0x280 + +#define CSR_HSTATUS 0x600 +#define CSR_HEDELEG 0x602 +#define CSR_HIDELEG 0x603 +#define CSR_HGATP 0x680 + #define CSR_CYCLEH 0xc80 #define CSR_TIMEH 0xc81 #define CSR_INSTRETH 0xc82 From patchwork Thu Oct 3 05:06:51 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Anup Patel X-Patchwork-Id: 11172095 Return-Path: Received: from mail.kernel.org (pdx-korg-mail-1.web.codeaurora.org [172.30.200.123]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id 51AA814DB for ; Thu, 3 Oct 2019 05:07:13 +0000 (UTC) Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id 2828C222CA for ; Thu, 3 Oct 2019 05:07:13 +0000 (UTC) Authentication-Results: mail.kernel.org; dkim=pass (2048-bit key) header.d=lists.infradead.org header.i=@lists.infradead.org header.b="KNxYAa9P"; dkim=fail reason="signature verification failed" (2048-bit key) header.d=wdc.com header.i=@wdc.com header.b="A4RtObx9"; dkim=fail reason="signature verification failed" (1024-bit key) header.d=sharedspace.onmicrosoft.com header.i=@sharedspace.onmicrosoft.com header.b="S9tmN1Gw" DMARC-Filter: OpenDMARC Filter v1.3.2 mail.kernel.org 2828C222CA Authentication-Results: mail.kernel.org; dmarc=fail (p=none dis=none) header.from=wdc.com Authentication-Results: mail.kernel.org; spf=none smtp.mailfrom=linux-riscv-bounces+patchwork-linux-riscv=patchwork.kernel.org@lists.infradead.org DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=bombadil.20170209; h=Sender: Content-Transfer-Encoding:Content-Type:Cc:List-Subscribe:List-Help:List-Post: List-Archive:List-Unsubscribe:List-Id:MIME-Version:In-Reply-To:References: Message-ID:Date:Subject:To:From:Reply-To:Content-ID:Content-Description: Resent-Date:Resent-From:Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID: List-Owner; bh=CjDWpfdSyADfnft3sKyJMtVM6SgW6tOnFGe+Re/WWiw=; b=KNxYAa9PAUFU04 V0GGDJOSJu3Lm7wZ6yKwWlh5FX7QWsQ65UQKOxA8jIeFX0b5hWCJ+Tn7gQGZ65W1bHoUMrWWsCEJO 2WtLH8HgEPX3Phzpsp2kOtw+NdgcQExRlloJIEMD2ZAgeU0DayR2eoMdu4iO+BrK6VrURnLXmXHdo 1TM0mI8JNLiR8gyKMIvY8mlOlrTZRnMIzZ/QROs8sDkqKTJXnyA7a2suygeuCWwMt9RctVzr56JqI rSV7xP2LI2g8dXDPFka0reD3SF9hBfGMctukNqDSR2sXH5WzkCkQfJPAzQpGOhGfBhZ/tw924DBKC WKSbfOsCf7uE+Nmw1a1Q==; Received: from localhost ([127.0.0.1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.92.2 #3 (Red Hat Linux)) id 1iFtKM-0003LO-7R; Thu, 03 Oct 2019 05:06:58 +0000 Received: from esa5.hgst.iphmx.com ([216.71.153.144]) by bombadil.infradead.org with esmtps (Exim 4.92.2 #3 (Red Hat Linux)) id 1iFtKI-0003AN-4f for linux-riscv@lists.infradead.org; Thu, 03 Oct 2019 05:06:56 +0000 DKIM-Signature: v=1; a=rsa-sha256; c=simple/simple; d=wdc.com; i=@wdc.com; q=dns/txt; s=dkim.wdc.com; t=1570079214; x=1601615214; h=from:to:cc:subject:date:message-id:references: in-reply-to:content-transfer-encoding:mime-version; bh=7FZn/Z+HIRxCixhLH6M76hdPz17NbXEEQfVpANT7lH0=; b=A4RtObx9gMUn4aY5OvYGcMXNLIZgIeGZdfy+VXUQl+mdAR+fUYxaUcy4 tvINRWGa8K1uRHHr2lVMH6MM7RCEy0TK0/R5weAYXrjbS1v9oy5/RZWgw 7faLX9hWq3DNHHNrCuw6VQXE+39+yZWRqSch9jXopFLQJrpNJBn2q0Mch CYJ1Ou6wd3PjSQTa4yvPmOtjT7Bkt1bMmta2TtvVDZNTJAbbKujdFASsv 6hhqnClfM77Cj/phppFfmI194GxfYEFsoZNgaq4t5e+XpMjiMTA3kkSE0 UGlcCV5Al9jWsURuhjSWvsj9CkpscuS9r8TnRtnbXQpfkKineqIyxqK6p w==; IronPort-SDR: +z0TytNKH3xbKKle0aSDLn3Hn8/7S1+XBqP0WcSSQVJRZO/4V1O7nuQL6k1czfRc4c+Mw0Pl8j bfztQ9inxpnpOAadjoGDWWiC1AFuhxXdSl8eWEbkQNdXpDJR7l5aA52t1tUd3wrCYRdcNMHtpO +lYqOWvem73Lt2I8Q2nA1oaE0jZ8fVNA9Meucuavadl6zui1C2ZzuvY9KqYP5XOUQ4paJMa+bb BkQHO+WR/TYBd8FIhMrPTKbkWHpLP74335BhQrhyDAhmNyfO+LXU+5c+2HGAwiZGbC+tCpHRDV Qqs= X-IronPort-AV: E=Sophos;i="5.67,251,1566835200"; d="scan'208";a="120461300" Received: from mail-co1nam03lp2054.outbound.protection.outlook.com (HELO NAM03-CO1-obe.outbound.protection.outlook.com) ([104.47.40.54]) by ob1.hgst.iphmx.com with ESMTP; 03 Oct 2019 13:06:53 +0800 ARC-Seal: i=1; a=rsa-sha256; s=arcselector9901; d=microsoft.com; cv=none; b=PE4JvKiCoHZ4CTd4AoCD+d636QtmZr9iKXTCKj+2WX9HfK5o0p9yVR0MgUhL/fRZzfTV7tbE9C8sXTI4mJjdTVOOXJUVUGVt5AU4XjCGA+bS6Jtsmsg87oEUt9aivO5Wgtltog/3Oua6KxEnPmBifF29KZ0q1KTMgrQ/7Mc8QK1qTczNHs/O6xp+C7lRzmqYH1JFJrf+dOOTQGuAETpnokEcpFLY9kh3UcxL9fVcoSNUO/E4C/yiFsNewLAnfVw20A7rCg1o6hUbOUODU68XwKV7xdJFIzyANyjWK+xi1NL53CMg5vy3yP3ZFKiOvjSKAGrwmr8CuL6AC5Fn1bCqjQ== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=microsoft.com; s=arcselector9901; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-SenderADCheck; bh=XLQVrJTao85t433FR/+D2mcXLfOfPjn48mgrsYPJ98Q=; b=QCeP9sdg3PGAmXWJpQ0e6XnQXuo4kca0Mp5k3ue5iZVyEFTG13Ge08z7Ow6Fyf60lGOGKzi6rdvEYSE9vso9k9nwrRqn0H/vofaDOQFLjuiLZt7bNoy2TM8lNqIk9gB0q8zwsEsJNK5mNCjaKpMj9I9rC6dE1ifgmv0bjhvgOaEPPOE7xayxqQKNPdn53Abiu48ohema6crs35Zq/GshVhCuCJbq+twXZjmASXYwkpVuwIcXeYl8jqgpxQF6ds1BUfrrSc3vc9TR22uTAGu6ePy8eEh/gE9IP0nT/D4J1+qB4wr382O1j425RoAUG09sCWXscm7uJCcJtphBKpFJAQ== ARC-Authentication-Results: i=1; mx.microsoft.com 1; spf=pass smtp.mailfrom=wdc.com; dmarc=pass action=none header.from=wdc.com; dkim=pass header.d=wdc.com; arc=none DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=sharedspace.onmicrosoft.com; s=selector2-sharedspace-onmicrosoft-com; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-SenderADCheck; bh=XLQVrJTao85t433FR/+D2mcXLfOfPjn48mgrsYPJ98Q=; b=S9tmN1GwUdTGMtNcd6j60tL7N9p8ABDOKDQ3szLvvgSb6wQVzqarub/MbGrrxlpLbtsa3kdds4g8u8mfHtfvqKVKhdiCaiHLpwSn3fi1dzV8et2Y0LxRyW+4K8qFmFnOCs625BmNF4yLPEWlVV2IMnyg6fIHlzm8qODm2rnIvfY= Received: from MN2PR04MB6061.namprd04.prod.outlook.com (20.178.246.15) by MN2PR04MB6991.namprd04.prod.outlook.com (10.186.144.209) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.2305.18; Thu, 3 Oct 2019 05:06:51 +0000 Received: from MN2PR04MB6061.namprd04.prod.outlook.com ([fe80::1454:87a:13b0:d3a]) by MN2PR04MB6061.namprd04.prod.outlook.com ([fe80::1454:87a:13b0:d3a%7]) with mapi id 15.20.2305.023; Thu, 3 Oct 2019 05:06:51 +0000 From: Anup Patel To: Palmer Dabbelt , Paul Walmsley , Paolo Bonzini , Radim K Subject: [PATCH v8 03/19] RISC-V: Add initial skeletal KVM support Thread-Topic: [PATCH v8 03/19] RISC-V: Add initial skeletal KVM support Thread-Index: AQHVeahdx45DAlZZFEqzOZRp1migYA== Date: Thu, 3 Oct 2019 05:06:51 +0000 Message-ID: <20191003050558.9031-4-anup.patel@wdc.com> References: <20191003050558.9031-1-anup.patel@wdc.com> In-Reply-To: <20191003050558.9031-1-anup.patel@wdc.com> Accept-Language: en-US Content-Language: en-US X-MS-Has-Attach: X-MS-TNEF-Correlator: x-clientproxiedby: BMXPR01CA0030.INDPRD01.PROD.OUTLOOK.COM (2603:1096:b00:c::16) To MN2PR04MB6061.namprd04.prod.outlook.com (2603:10b6:208:d8::15) authentication-results: spf=none (sender IP is ) smtp.mailfrom=Anup.Patel@wdc.com; x-ms-exchange-messagesentrepresentingtype: 1 x-mailer: git-send-email 2.17.1 x-originating-ip: [111.235.74.37] x-ms-publictraffictype: Email x-ms-office365-filtering-correlation-id: aba24932-5eab-4b46-ecae-08d747bf803d x-ms-office365-filtering-ht: Tenant x-ms-traffictypediagnostic: MN2PR04MB6991: x-ms-exchange-transport-forked: True x-microsoft-antispam-prvs: wdcipoutbound: EOP-TRUE x-ms-oob-tlc-oobclassifiers: OLM:164; x-forefront-prvs: 01792087B6 x-forefront-antispam-report: SFV:NSPM; SFS:(10019020)(4636009)(366004)(346002)(39860400002)(136003)(376002)(396003)(189003)(199004)(7416002)(52116002)(25786009)(102836004)(76176011)(30864003)(54906003)(6506007)(1076003)(386003)(7736002)(44832011)(6436002)(486006)(66066001)(71190400001)(71200400001)(11346002)(446003)(6116002)(3846002)(476003)(2616005)(26005)(305945005)(6512007)(36756003)(186003)(14454004)(110136005)(5660300002)(6486002)(66446008)(66476007)(8936002)(66556008)(256004)(64756008)(14444005)(66946007)(86362001)(8676002)(81156014)(81166006)(99286004)(316002)(4326008)(2906002)(478600001)(50226002)(579004); DIR:OUT; SFP:1102; SCL:1; SRVR:MN2PR04MB6991; H:MN2PR04MB6061.namprd04.prod.outlook.com; FPR:; SPF:None; LANG:en; PTR:InfoNoRecords; MX:1; A:1; x-ms-exchange-senderadcheck: 1 x-microsoft-antispam: BCL:0; x-microsoft-antispam-message-info: iltpt7UufMIoT3mLOzDE6LCDe3W3gLBriZIVRY2EHhkjVTVWWBTgXQprADXFgcGKLWethGrpeuBJtyPBn9FwMyVR1wTeQfsDAuolVuZburFHbqycD19+C8MLK38/bTVoFlwy64l3VjEI0QA1s1uVC9K1IwE6GRLEt97HoMF9tq+NVg9mvUQaQ/9+5q4rfEnuVFLGPg49Q8ztIKrk0ThWz/h2phq3nnFRQRpiqYdYvmB9/jeDfDOQWzeX6o0lsXnoHCsksoPF9Wy2sxaqNtW52uRkmbbBLEtajHNt6aD0TtQ/MUCYbwH6oBRUMSen39UiuNceb3teyvtBAo9kU/w8lJxn/iZ3uE9EEcZrnmMU+GZGisThSiUfYbpFcMuEQxlFGtV6Vnsh01LhEt2y5ZUK1pf5HXzlo5UXAnGOmPJ7+Hk= MIME-Version: 1.0 X-OriginatorOrg: wdc.com X-MS-Exchange-CrossTenant-Network-Message-Id: aba24932-5eab-4b46-ecae-08d747bf803d X-MS-Exchange-CrossTenant-originalarrivaltime: 03 Oct 2019 05:06:51.5760 (UTC) X-MS-Exchange-CrossTenant-fromentityheader: Hosted X-MS-Exchange-CrossTenant-id: b61c8803-16f3-4c35-9b17-6f65f441df86 X-MS-Exchange-CrossTenant-mailboxtype: HOSTED X-MS-Exchange-CrossTenant-userprincipalname: OUdk2DEHSvP90pkcIcRh1eKZTKFSiwf28NXhjETBjx/D49oIk2+Nmrr1xVbMNiKBXR7gsNONa2pJvUlCa/Ze+Q== X-MS-Exchange-Transport-CrossTenantHeadersStamped: MN2PR04MB6991 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20191002_220654_217071_200EE08E X-CRM114-Status: GOOD ( 18.52 ) X-Spam-Score: -2.5 (--) X-Spam-Report: SpamAssassin version 3.4.2 on bombadil.infradead.org summary: Content analysis details: (-2.5 points) pts rule name description ---- ---------------------- -------------------------------------------------- -2.3 RCVD_IN_DNSWL_MED RBL: Sender listed at https://www.dnswl.org/, medium trust [216.71.153.144 listed in list.dnswl.org] -0.0 SPF_PASS SPF: sender matches SPF record 0.0 SPF_HELO_NONE SPF: HELO does not publish an SPF Record -0.1 DKIM_VALID_EF Message has a valid DKIM or DK signature from envelope-from domain 0.1 DKIM_SIGNED Message has a DKIM or DK signature, not necessarily valid -0.1 DKIM_VALID_AU Message has a valid DKIM or DK signature from author's domain -0.1 DKIM_VALID Message has at least one valid DKIM or DK signature X-BeenThere: linux-riscv@lists.infradead.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Damien Le Moal , Anup Patel , "kvm@vger.kernel.org" , Anup Patel , Daniel Lezcano , "linux-kernel@vger.kernel.org" , Christoph Hellwig , Atish Patra , Alexander Graf , Alistair Francis , Thomas Gleixner , "linux-riscv@lists.infradead.org" Sender: "linux-riscv" Errors-To: linux-riscv-bounces+patchwork-linux-riscv=patchwork.kernel.org@lists.infradead.org This patch adds initial skeletal KVM RISC-V support which has: 1. A simple implementation of arch specific VM functions except kvm_vm_ioctl_get_dirty_log() which will implemeted in-future as part of stage2 page loging. 2. Stubs of required arch specific VCPU functions except kvm_arch_vcpu_ioctl_run() which is semi-complete and extended by subsequent patches. 3. Stubs for required arch specific stage2 MMU functions. Signed-off-by: Anup Patel Acked-by: Paolo Bonzini Reviewed-by: Paolo Bonzini Reviewed-by: Alexander Graf --- arch/riscv/Kconfig | 2 + arch/riscv/Makefile | 2 + arch/riscv/include/asm/kvm_host.h | 81 ++++++++ arch/riscv/include/uapi/asm/kvm.h | 47 +++++ arch/riscv/kvm/Kconfig | 33 ++++ arch/riscv/kvm/Makefile | 13 ++ arch/riscv/kvm/main.c | 80 ++++++++ arch/riscv/kvm/mmu.c | 83 ++++++++ arch/riscv/kvm/vcpu.c | 312 ++++++++++++++++++++++++++++++ arch/riscv/kvm/vcpu_exit.c | 35 ++++ arch/riscv/kvm/vm.c | 79 ++++++++ 11 files changed, 767 insertions(+) create mode 100644 arch/riscv/include/asm/kvm_host.h create mode 100644 arch/riscv/include/uapi/asm/kvm.h create mode 100644 arch/riscv/kvm/Kconfig create mode 100644 arch/riscv/kvm/Makefile create mode 100644 arch/riscv/kvm/main.c create mode 100644 arch/riscv/kvm/mmu.c create mode 100644 arch/riscv/kvm/vcpu.c create mode 100644 arch/riscv/kvm/vcpu_exit.c create mode 100644 arch/riscv/kvm/vm.c diff --git a/arch/riscv/Kconfig b/arch/riscv/Kconfig index 3815808f95fa..2744b50eaeea 100644 --- a/arch/riscv/Kconfig +++ b/arch/riscv/Kconfig @@ -327,3 +327,5 @@ menu "Power management options" source "kernel/power/Kconfig" endmenu + +source "arch/riscv/kvm/Kconfig" diff --git a/arch/riscv/Makefile b/arch/riscv/Makefile index f5e914210245..a2067cdae2cd 100644 --- a/arch/riscv/Makefile +++ b/arch/riscv/Makefile @@ -77,6 +77,8 @@ head-y := arch/riscv/kernel/head.o core-y += arch/riscv/ +core-$(CONFIG_KVM) += arch/riscv/kvm/ + libs-y += arch/riscv/lib/ PHONY += vdso_install diff --git a/arch/riscv/include/asm/kvm_host.h b/arch/riscv/include/asm/kvm_host.h new file mode 100644 index 000000000000..9459709656be --- /dev/null +++ b/arch/riscv/include/asm/kvm_host.h @@ -0,0 +1,81 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +/* + * Copyright (C) 2019 Western Digital Corporation or its affiliates. + * + * Authors: + * Anup Patel + */ + +#ifndef __RISCV_KVM_HOST_H__ +#define __RISCV_KVM_HOST_H__ + +#include +#include +#include + +#ifdef CONFIG_64BIT +#define KVM_MAX_VCPUS (1U << 16) +#else +#define KVM_MAX_VCPUS (1U << 9) +#endif + +#define KVM_USER_MEM_SLOTS 512 +#define KVM_HALT_POLL_NS_DEFAULT 500000 + +#define KVM_VCPU_MAX_FEATURES 0 + +#define KVM_REQ_SLEEP \ + KVM_ARCH_REQ_FLAGS(0, KVM_REQUEST_WAIT | KVM_REQUEST_NO_WAKEUP) +#define KVM_REQ_VCPU_RESET KVM_ARCH_REQ(1) + +struct kvm_vm_stat { + ulong remote_tlb_flush; +}; + +struct kvm_vcpu_stat { + u64 halt_successful_poll; + u64 halt_attempted_poll; + u64 halt_poll_invalid; + u64 halt_wakeup; + u64 ecall_exit_stat; + u64 wfi_exit_stat; + u64 mmio_exit_user; + u64 mmio_exit_kernel; + u64 exits; +}; + +struct kvm_arch_memory_slot { +}; + +struct kvm_arch { + /* stage2 page table */ + pgd_t *pgd; + phys_addr_t pgd_phys; +}; + +struct kvm_vcpu_arch { + /* Don't run the VCPU (blocked) */ + bool pause; + + /* SRCU lock index for in-kernel run loop */ + int srcu_idx; +}; + +static inline void kvm_arch_hardware_unsetup(void) {} +static inline void kvm_arch_sync_events(struct kvm *kvm) {} +static inline void kvm_arch_vcpu_uninit(struct kvm_vcpu *vcpu) {} +static inline void kvm_arch_sched_in(struct kvm_vcpu *vcpu, int cpu) {} +static inline void kvm_arch_vcpu_block_finish(struct kvm_vcpu *vcpu) {} + +void kvm_riscv_stage2_flush_cache(struct kvm_vcpu *vcpu); +int kvm_riscv_stage2_alloc_pgd(struct kvm *kvm); +void kvm_riscv_stage2_free_pgd(struct kvm *kvm); +void kvm_riscv_stage2_update_hgatp(struct kvm_vcpu *vcpu); + +int kvm_riscv_vcpu_mmio_return(struct kvm_vcpu *vcpu, struct kvm_run *run); +int kvm_riscv_vcpu_exit(struct kvm_vcpu *vcpu, struct kvm_run *run, + unsigned long scause, unsigned long stval); + +static inline void __kvm_riscv_switch_to(struct kvm_vcpu_arch *vcpu_arch) {} + +#endif /* __RISCV_KVM_HOST_H__ */ diff --git a/arch/riscv/include/uapi/asm/kvm.h b/arch/riscv/include/uapi/asm/kvm.h new file mode 100644 index 000000000000..d15875818b6e --- /dev/null +++ b/arch/riscv/include/uapi/asm/kvm.h @@ -0,0 +1,47 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +/* + * Copyright (C) 2019 Western Digital Corporation or its affiliates. + * + * Authors: + * Anup Patel + */ + +#ifndef __LINUX_KVM_RISCV_H +#define __LINUX_KVM_RISCV_H + +#ifndef __ASSEMBLY__ + +#include +#include + +#define __KVM_HAVE_READONLY_MEM + +#define KVM_COALESCED_MMIO_PAGE_OFFSET 1 + +/* for KVM_GET_REGS and KVM_SET_REGS */ +struct kvm_regs { +}; + +/* for KVM_GET_FPU and KVM_SET_FPU */ +struct kvm_fpu { +}; + +/* KVM Debug exit structure */ +struct kvm_debug_exit_arch { +}; + +/* for KVM_SET_GUEST_DEBUG */ +struct kvm_guest_debug_arch { +}; + +/* definition of registers in kvm_run */ +struct kvm_sync_regs { +}; + +/* dummy definition */ +struct kvm_sregs { +}; + +#endif + +#endif /* __LINUX_KVM_RISCV_H */ diff --git a/arch/riscv/kvm/Kconfig b/arch/riscv/kvm/Kconfig new file mode 100644 index 000000000000..9cca98c4673b --- /dev/null +++ b/arch/riscv/kvm/Kconfig @@ -0,0 +1,33 @@ +# SPDX-License-Identifier: GPL-2.0 +# +# KVM configuration +# + +source "virt/kvm/Kconfig" + +menuconfig VIRTUALIZATION + bool "Virtualization" + help + Say Y here to get to see options for using your Linux host to run + other operating systems inside virtual machines (guests). + This option alone does not add any kernel code. + + If you say N, all options in this submenu will be skipped and + disabled. + +if VIRTUALIZATION + +config KVM + tristate "Kernel-based Virtual Machine (KVM) support (EXPERIMENTAL)" + depends on OF + select PREEMPT_NOTIFIERS + select ANON_INODES + select KVM_MMIO + select HAVE_KVM_VCPU_ASYNC_IOCTL + select SRCU + help + Support hosting virtualized guest machines. + + If unsure, say N. + +endif # VIRTUALIZATION diff --git a/arch/riscv/kvm/Makefile b/arch/riscv/kvm/Makefile new file mode 100644 index 000000000000..37b5a59d4f4f --- /dev/null +++ b/arch/riscv/kvm/Makefile @@ -0,0 +1,13 @@ +# SPDX-License-Identifier: GPL-2.0 +# Makefile for RISC-V KVM support +# + +common-objs-y = $(addprefix ../../../virt/kvm/, kvm_main.o coalesced_mmio.o) + +ccflags-y := -Ivirt/kvm -Iarch/riscv/kvm + +kvm-objs := $(common-objs-y) + +kvm-objs += main.o vm.o mmu.o vcpu.o vcpu_exit.o + +obj-$(CONFIG_KVM) += kvm.o diff --git a/arch/riscv/kvm/main.c b/arch/riscv/kvm/main.c new file mode 100644 index 000000000000..e1ffe6d42f39 --- /dev/null +++ b/arch/riscv/kvm/main.c @@ -0,0 +1,80 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Copyright (C) 2019 Western Digital Corporation or its affiliates. + * + * Authors: + * Anup Patel + */ + +#include +#include +#include +#include +#include +#include + +long kvm_arch_dev_ioctl(struct file *filp, + unsigned int ioctl, unsigned long arg) +{ + return -EINVAL; +} + +int kvm_arch_check_processor_compat(void) +{ + return 0; +} + +int kvm_arch_hardware_setup(void) +{ + return 0; +} + +int kvm_arch_hardware_enable(void) +{ + unsigned long hideleg, hedeleg; + + hedeleg = 0; + hedeleg |= (1UL << EXC_INST_MISALIGNED); + hedeleg |= (1UL << EXC_BREAKPOINT); + hedeleg |= (1UL << EXC_SYSCALL); + hedeleg |= (1UL << EXC_INST_PAGE_FAULT); + hedeleg |= (1UL << EXC_LOAD_PAGE_FAULT); + hedeleg |= (1UL << EXC_STORE_PAGE_FAULT); + csr_write(CSR_HEDELEG, hedeleg); + + hideleg = 0; + hideleg |= SIE_SSIE; + hideleg |= SIE_STIE; + hideleg |= SIE_SEIE; + csr_write(CSR_HIDELEG, hideleg); + + return 0; +} + +void kvm_arch_hardware_disable(void) +{ + csr_write(CSR_HEDELEG, 0); + csr_write(CSR_HIDELEG, 0); +} + +int kvm_arch_init(void *opaque) +{ + if (!riscv_isa_extension_available(NULL, h)) { + kvm_info("hypervisor extension not available\n"); + return -ENODEV; + } + + kvm_info("hypervisor extension available\n"); + + return 0; +} + +void kvm_arch_exit(void) +{ +} + +static int riscv_kvm_init(void) +{ + return kvm_init(NULL, sizeof(struct kvm_vcpu), 0, THIS_MODULE); +} +module_init(riscv_kvm_init); diff --git a/arch/riscv/kvm/mmu.c b/arch/riscv/kvm/mmu.c new file mode 100644 index 000000000000..04dd089b86ff --- /dev/null +++ b/arch/riscv/kvm/mmu.c @@ -0,0 +1,83 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Copyright (C) 2019 Western Digital Corporation or its affiliates. + * + * Authors: + * Anup Patel + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +void kvm_arch_free_memslot(struct kvm *kvm, struct kvm_memory_slot *free, + struct kvm_memory_slot *dont) +{ +} + +int kvm_arch_create_memslot(struct kvm *kvm, struct kvm_memory_slot *slot, + unsigned long npages) +{ + return 0; +} + +void kvm_arch_memslots_updated(struct kvm *kvm, u64 gen) +{ +} + +void kvm_arch_flush_shadow_all(struct kvm *kvm) +{ + /* TODO: */ +} + +void kvm_arch_flush_shadow_memslot(struct kvm *kvm, + struct kvm_memory_slot *slot) +{ +} + +void kvm_arch_commit_memory_region(struct kvm *kvm, + const struct kvm_userspace_memory_region *mem, + const struct kvm_memory_slot *old, + const struct kvm_memory_slot *new, + enum kvm_mr_change change) +{ + /* TODO: */ +} + +int kvm_arch_prepare_memory_region(struct kvm *kvm, + struct kvm_memory_slot *memslot, + const struct kvm_userspace_memory_region *mem, + enum kvm_mr_change change) +{ + /* TODO: */ + return 0; +} + +void kvm_riscv_stage2_flush_cache(struct kvm_vcpu *vcpu) +{ + /* TODO: */ +} + +int kvm_riscv_stage2_alloc_pgd(struct kvm *kvm) +{ + /* TODO: */ + return 0; +} + +void kvm_riscv_stage2_free_pgd(struct kvm *kvm) +{ + /* TODO: */ +} + +void kvm_riscv_stage2_update_hgatp(struct kvm_vcpu *vcpu) +{ + /* TODO: */ +} diff --git a/arch/riscv/kvm/vcpu.c b/arch/riscv/kvm/vcpu.c new file mode 100644 index 000000000000..48536cb0c8e7 --- /dev/null +++ b/arch/riscv/kvm/vcpu.c @@ -0,0 +1,312 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Copyright (C) 2019 Western Digital Corporation or its affiliates. + * + * Authors: + * Anup Patel + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#define VCPU_STAT(x) { #x, offsetof(struct kvm_vcpu, stat.x), KVM_STAT_VCPU } + +struct kvm_stats_debugfs_item debugfs_entries[] = { + VCPU_STAT(ecall_exit_stat), + VCPU_STAT(wfi_exit_stat), + VCPU_STAT(mmio_exit_user), + VCPU_STAT(mmio_exit_kernel), + VCPU_STAT(exits), + { NULL } +}; + +struct kvm_vcpu *kvm_arch_vcpu_create(struct kvm *kvm, unsigned int id) +{ + /* TODO: */ + return NULL; +} + +int kvm_arch_vcpu_setup(struct kvm_vcpu *vcpu) +{ + return 0; +} + +void kvm_arch_vcpu_postcreate(struct kvm_vcpu *vcpu) +{ +} + +int kvm_arch_vcpu_init(struct kvm_vcpu *vcpu) +{ + /* TODO: */ + return 0; +} + +void kvm_arch_vcpu_destroy(struct kvm_vcpu *vcpu) +{ + /* TODO: */ +} + +int kvm_cpu_has_pending_timer(struct kvm_vcpu *vcpu) +{ + /* TODO: */ + return 0; +} + +void kvm_arch_vcpu_blocking(struct kvm_vcpu *vcpu) +{ +} + +void kvm_arch_vcpu_unblocking(struct kvm_vcpu *vcpu) +{ +} + +int kvm_arch_vcpu_runnable(struct kvm_vcpu *vcpu) +{ + /* TODO: */ + return 0; +} + +int kvm_arch_vcpu_should_kick(struct kvm_vcpu *vcpu) +{ + /* TODO: */ + return 0; +} + +bool kvm_arch_vcpu_in_kernel(struct kvm_vcpu *vcpu) +{ + /* TODO: */ + return false; +} + +bool kvm_arch_has_vcpu_debugfs(void) +{ + return false; +} + +int kvm_arch_create_vcpu_debugfs(struct kvm_vcpu *vcpu) +{ + return 0; +} + +vm_fault_t kvm_arch_vcpu_fault(struct kvm_vcpu *vcpu, struct vm_fault *vmf) +{ + return VM_FAULT_SIGBUS; +} + +long kvm_arch_vcpu_async_ioctl(struct file *filp, + unsigned int ioctl, unsigned long arg) +{ + /* TODO; */ + return -ENOIOCTLCMD; +} + +long kvm_arch_vcpu_ioctl(struct file *filp, + unsigned int ioctl, unsigned long arg) +{ + /* TODO: */ + return -EINVAL; +} + +int kvm_arch_vcpu_ioctl_get_sregs(struct kvm_vcpu *vcpu, + struct kvm_sregs *sregs) +{ + return -EINVAL; +} + +int kvm_arch_vcpu_ioctl_set_sregs(struct kvm_vcpu *vcpu, + struct kvm_sregs *sregs) +{ + return -EINVAL; +} + +int kvm_arch_vcpu_ioctl_get_fpu(struct kvm_vcpu *vcpu, struct kvm_fpu *fpu) +{ + return -EINVAL; +} + +int kvm_arch_vcpu_ioctl_set_fpu(struct kvm_vcpu *vcpu, struct kvm_fpu *fpu) +{ + return -EINVAL; +} + +int kvm_arch_vcpu_ioctl_translate(struct kvm_vcpu *vcpu, + struct kvm_translation *tr) +{ + return -EINVAL; +} + +int kvm_arch_vcpu_ioctl_get_regs(struct kvm_vcpu *vcpu, struct kvm_regs *regs) +{ + return -EINVAL; +} + +int kvm_arch_vcpu_ioctl_set_regs(struct kvm_vcpu *vcpu, struct kvm_regs *regs) +{ + return -EINVAL; +} + +int kvm_arch_vcpu_ioctl_get_mpstate(struct kvm_vcpu *vcpu, + struct kvm_mp_state *mp_state) +{ + /* TODO: */ + return 0; +} + +int kvm_arch_vcpu_ioctl_set_mpstate(struct kvm_vcpu *vcpu, + struct kvm_mp_state *mp_state) +{ + /* TODO: */ + return 0; +} + +int kvm_arch_vcpu_ioctl_set_guest_debug(struct kvm_vcpu *vcpu, + struct kvm_guest_debug *dbg) +{ + /* TODO; To be implemented later. */ + return -EINVAL; +} + +void kvm_arch_vcpu_load(struct kvm_vcpu *vcpu, int cpu) +{ + /* TODO: */ + + kvm_riscv_stage2_update_hgatp(vcpu); +} + +void kvm_arch_vcpu_put(struct kvm_vcpu *vcpu) +{ + /* TODO: */ +} + +static void kvm_riscv_check_vcpu_requests(struct kvm_vcpu *vcpu) +{ + /* TODO: */ +} + +int kvm_arch_vcpu_ioctl_run(struct kvm_vcpu *vcpu, struct kvm_run *run) +{ + int ret; + unsigned long scause, stval; + + vcpu->arch.srcu_idx = srcu_read_lock(&vcpu->kvm->srcu); + + /* Process MMIO value returned from user-space */ + if (run->exit_reason == KVM_EXIT_MMIO) { + ret = kvm_riscv_vcpu_mmio_return(vcpu, vcpu->run); + if (ret) { + srcu_read_unlock(&vcpu->kvm->srcu, vcpu->arch.srcu_idx); + return ret; + } + } + + if (run->immediate_exit) { + srcu_read_unlock(&vcpu->kvm->srcu, vcpu->arch.srcu_idx); + return -EINTR; + } + + vcpu_load(vcpu); + + kvm_sigset_activate(vcpu); + + ret = 1; + run->exit_reason = KVM_EXIT_UNKNOWN; + while (ret > 0) { + /* Check conditions before entering the guest */ + cond_resched(); + + kvm_riscv_check_vcpu_requests(vcpu); + + preempt_disable(); + + local_irq_disable(); + + /* + * Exit if we have a signal pending so that we can deliver + * the signal to user space. + */ + if (signal_pending(current)) { + ret = -EINTR; + run->exit_reason = KVM_EXIT_INTR; + } + + /* + * Ensure we set mode to IN_GUEST_MODE after we disable + * interrupts and before the final VCPU requests check. + * See the comment in kvm_vcpu_exiting_guest_mode() and + * Documentation/virtual/kvm/vcpu-requests.rst + */ + vcpu->mode = IN_GUEST_MODE; + + srcu_read_unlock(&vcpu->kvm->srcu, vcpu->arch.srcu_idx); + smp_mb__after_srcu_read_unlock(); + + if (ret <= 0 || + kvm_request_pending(vcpu)) { + vcpu->mode = OUTSIDE_GUEST_MODE; + local_irq_enable(); + preempt_enable(); + vcpu->arch.srcu_idx = srcu_read_lock(&vcpu->kvm->srcu); + continue; + } + + guest_enter_irqoff(); + + __kvm_riscv_switch_to(&vcpu->arch); + + vcpu->mode = OUTSIDE_GUEST_MODE; + vcpu->stat.exits++; + + /* Save SCAUSE and STVAL because we might get an interrupt + * between __kvm_riscv_switch_to() and local_irq_enable() + * which can potentially overwrite SCAUSE and STVAL. + */ + scause = csr_read(CSR_SCAUSE); + stval = csr_read(CSR_STVAL); + + /* + * We may have taken a host interrupt in VS/VU-mode (i.e. + * while executing the guest). This interrupt is still + * pending, as we haven't serviced it yet! + * + * We're now back in HS-mode with interrupts disabled + * so enabling the interrupts now will have the effect + * of taking the interrupt again, in HS-mode this time. + */ + local_irq_enable(); + + /* + * We do local_irq_enable() before calling guest_exit() so + * that if a timer interrupt hits while running the guest + * we account that tick as being spent in the guest. We + * enable preemption after calling guest_exit() so that if + * we get preempted we make sure ticks after that is not + * counted as guest time. + */ + guest_exit(); + + preempt_enable(); + + vcpu->arch.srcu_idx = srcu_read_lock(&vcpu->kvm->srcu); + + ret = kvm_riscv_vcpu_exit(vcpu, run, scause, stval); + } + + kvm_sigset_deactivate(vcpu); + + vcpu_put(vcpu); + + srcu_read_unlock(&vcpu->kvm->srcu, vcpu->arch.srcu_idx); + + return ret; +} diff --git a/arch/riscv/kvm/vcpu_exit.c b/arch/riscv/kvm/vcpu_exit.c new file mode 100644 index 000000000000..e4d7c8f0807a --- /dev/null +++ b/arch/riscv/kvm/vcpu_exit.c @@ -0,0 +1,35 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Copyright (C) 2019 Western Digital Corporation or its affiliates. + * + * Authors: + * Anup Patel + */ + +#include +#include +#include + +/** + * kvm_riscv_vcpu_mmio_return -- Handle MMIO loads after user space emulation + * or in-kernel IO emulation + * + * @vcpu: The VCPU pointer + * @run: The VCPU run struct containing the mmio data + */ +int kvm_riscv_vcpu_mmio_return(struct kvm_vcpu *vcpu, struct kvm_run *run) +{ + /* TODO: */ + return 0; +} + +/* + * Return > 0 to return to guest, < 0 on error, 0 (and set exit_reason) on + * proper exit to userspace. + */ +int kvm_riscv_vcpu_exit(struct kvm_vcpu *vcpu, struct kvm_run *run, + unsigned long scause, unsigned long stval) +{ + /* TODO: */ + return 0; +} diff --git a/arch/riscv/kvm/vm.c b/arch/riscv/kvm/vm.c new file mode 100644 index 000000000000..ac0211820521 --- /dev/null +++ b/arch/riscv/kvm/vm.c @@ -0,0 +1,79 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Copyright (C) 2019 Western Digital Corporation or its affiliates. + * + * Authors: + * Anup Patel + */ + +#include +#include +#include +#include +#include + +int kvm_vm_ioctl_get_dirty_log(struct kvm *kvm, struct kvm_dirty_log *log) +{ + /* TODO: To be added later. */ + return -ENOTSUPP; +} + +int kvm_arch_init_vm(struct kvm *kvm, unsigned long type) +{ + int r; + + r = kvm_riscv_stage2_alloc_pgd(kvm); + if (r) + return r; + + return 0; +} + +void kvm_arch_destroy_vm(struct kvm *kvm) +{ + int i; + + for (i = 0; i < KVM_MAX_VCPUS; ++i) { + if (kvm->vcpus[i]) { + kvm_arch_vcpu_destroy(kvm->vcpus[i]); + kvm->vcpus[i] = NULL; + } + } +} + +int kvm_vm_ioctl_check_extension(struct kvm *kvm, long ext) +{ + int r; + + switch (ext) { + case KVM_CAP_DEVICE_CTRL: + case KVM_CAP_USER_MEMORY: + case KVM_CAP_DESTROY_MEMORY_REGION_WORKS: + case KVM_CAP_ONE_REG: + case KVM_CAP_READONLY_MEM: + case KVM_CAP_MP_STATE: + case KVM_CAP_IMMEDIATE_EXIT: + r = 1; + break; + case KVM_CAP_NR_VCPUS: + r = num_online_cpus(); + break; + case KVM_CAP_MAX_VCPUS: + r = KVM_MAX_VCPUS; + break; + case KVM_CAP_NR_MEMSLOTS: + r = KVM_USER_MEM_SLOTS; + break; + default: + r = 0; + break; + } + + return r; +} + +long kvm_arch_vm_ioctl(struct file *filp, + unsigned int ioctl, unsigned long arg) +{ + return -EINVAL; +} From patchwork Thu Oct 3 05:07:01 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Anup Patel X-Patchwork-Id: 11172099 Return-Path: Received: from mail.kernel.org (pdx-korg-mail-1.web.codeaurora.org [172.30.200.123]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id 7C41D1902 for ; Thu, 3 Oct 2019 05:07:15 +0000 (UTC) Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id 5694321D81 for ; Thu, 3 Oct 2019 05:07:15 +0000 (UTC) Authentication-Results: mail.kernel.org; dkim=pass (2048-bit key) header.d=lists.infradead.org header.i=@lists.infradead.org header.b="u4gxkQw1"; dkim=fail reason="signature verification failed" (2048-bit key) header.d=wdc.com header.i=@wdc.com header.b="GzBGd9fW"; dkim=fail reason="signature verification failed" (1024-bit key) header.d=sharedspace.onmicrosoft.com header.i=@sharedspace.onmicrosoft.com header.b="dDIulKoF" DMARC-Filter: OpenDMARC Filter v1.3.2 mail.kernel.org 5694321D81 Authentication-Results: mail.kernel.org; dmarc=fail (p=none dis=none) header.from=wdc.com Authentication-Results: mail.kernel.org; spf=none smtp.mailfrom=linux-riscv-bounces+patchwork-linux-riscv=patchwork.kernel.org@lists.infradead.org DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=bombadil.20170209; h=Sender: Content-Transfer-Encoding:Content-Type:Cc:List-Subscribe:List-Help:List-Post: List-Archive:List-Unsubscribe:List-Id:MIME-Version:In-Reply-To:References: Message-ID:Date:Subject:To:From:Reply-To:Content-ID:Content-Description: Resent-Date:Resent-From:Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID: List-Owner; bh=WXuYGbz3SupoHI9vVwuyetLQCKBidZhHh2rT0BaMxRE=; b=u4gxkQw1GwxKeO I7NTYhCSyRn0C+vdZS4uD1YEN3K13NQZ4fkZ3S2a6LKJx6nXtPUsj8nRFk/req6Gimgnh3xyFNrzT 40Ll6yhmzTLWN8C52cnZEs5rLkc844xn6qY2iFV/Zz4E9vCOZhzNUukQi0o12Fz98SRpxeNuIS40H 9hGIUOnlfVVpILbRfe+0OOtshHlsDj2An4NMTmMzhWuSRPZuyFZZ5hXHVX9aFc026wGLD9FEPCzbu oVtNihZItNDcEojSy8HzytoiptE0g3fqyy85YinrJC8qbIhfuH2Qsv7IQBFc9KtHSp15Bb2WYARin RU59tirTLpgpH54qdwvw==; Received: from localhost ([127.0.0.1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.92.2 #3 (Red Hat Linux)) id 1iFtKU-0003S3-Iq; Thu, 03 Oct 2019 05:07:06 +0000 Received: from esa5.hgst.iphmx.com ([216.71.153.144]) by bombadil.infradead.org with esmtps (Exim 4.92.2 #3 (Red Hat Linux)) id 1iFtKR-0003QU-Vq for linux-riscv@lists.infradead.org; Thu, 03 Oct 2019 05:07:05 +0000 DKIM-Signature: v=1; a=rsa-sha256; c=simple/simple; d=wdc.com; i=@wdc.com; q=dns/txt; s=dkim.wdc.com; t=1570079224; x=1601615224; h=from:to:cc:subject:date:message-id:references: in-reply-to:content-transfer-encoding:mime-version; bh=fDLT/tvUtxZor/pyJ7arbei5F/B1X1c5CWdgm4TQvIE=; b=GzBGd9fWTfsFSyPtUxvr8/CiHJLWm99ltL0hZm8eWfHIjOW+s54gDogG iYCB6wkgYqeqKAg4vzP4pNk9tYmGXa2P400PH9+PNztS0Dhzrq7BMGXKc KYTIrxg5+AB80QZOQCt4KUwdf7q3WROmL/rcMVGAU5xOSSNtkAs7IAq9f WcRN+NMfYm/tjEIRwySuzwz4SL6fB5p/aKyIuafBIj2Gawd5yp3LACe7w /RFuAWvoXzfWVahW+mpyAQsGmSkNh+V35UkdCMsHo3SyKIksIMjIX9sFL GBpPvs4m9+usVpw/628H8cMfBRC0wFZvewxfPfFNgoSyoHLfYs3ESvMRJ w==; IronPort-SDR: hPDB85gqcOZkUb2fE6hqZVQnpLKlah90v+Dw/rVLlbZDCND7concAkZq7FXbHnb3KF0Wnhgmsm HXAv0NZ4u8kNWBHqRfqG3tkAbLZ6alGylSu5qrnsv+x/v+3RtlVSt66Bl1z2iFHJc97zp0poL4 /Sn3X89o3V2XHPkqy8cWpx6m3BVoWt1KJW2jBzOSl4QdwFPqD4Y4ovGJF6CabphmjMcmPQz8Ok TMI+Xw33krbPla5nuAEG789ikw7q0A0mkQRe15IXqgNEZ3zIB3JHulnTbKVxBsgytb7QMsyhbd FUY= X-IronPort-AV: E=Sophos;i="5.67,251,1566835200"; d="scan'208";a="120461312" Received: from mail-co1nam03lp2051.outbound.protection.outlook.com (HELO NAM03-CO1-obe.outbound.protection.outlook.com) ([104.47.40.51]) by ob1.hgst.iphmx.com with ESMTP; 03 Oct 2019 13:07:03 +0800 ARC-Seal: i=1; a=rsa-sha256; s=arcselector9901; d=microsoft.com; cv=none; b=UQj3jGpIQ03JR3ufwMKjbsm3gpunf6eZFYKLrxA/EDc0cH/fWjITGalralT5LTrFB7Lk0lwAVlyl0hz5JFztAqCX5TEwdened4QRGlxZCzOF582NNOR1Tgvwq6pzaOa9wr9P1m1B9jNfg4k2JDk1+eYiOj6l7QR28D8NDBLZuXQOw0rrTOOZVCmAxLIwjJ7YHynTLJcUUb0kJua1qlwmbBTQcZiaMSDkcmz1FR2R/IyPfWxIxXqjIZuNdL0dwguNfupX6tcRPF1Ez3ZDEUEbmwsf0p3qBTBFz5kh9CGc8wEgoCw/wIzaohF2iCVc6aq75ZBSoFhGo6oQ714fsYfe+Q== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=microsoft.com; s=arcselector9901; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-SenderADCheck; bh=VqmrXHzIruAcNotF2clWWzYvQNRNRKr+C27TLUx8gRQ=; b=czmuWvjbJe4HgWgEQDlR6toUt7RnY4IRPiCncQvOE3OvP/rpW1jKAVVF4R235wq9DFFOtzJKMgTSo3tig2V3HTWgN8VGehmDWrd6709Z7FhvREywyF70cDxHZttwNg5qpqi/zUUC7/YCaQjL/eiIhZzmGoTs18qME9Pc9N+Le9LLQ3YwyZnwhqsvzL1L0ABpaBTDEMw+60K47v86Do9Q2r899u2dSev8FnhH/N/tMGQyigLh1ulGB2zs05RsHmSAdu9PnytjfpBE3rmRi5yrpdaBrfeb/gJjafUnMxuUG+6rdBS53aXMO8E0LTYsYZaIkeoDM+uOwFO9SffxJsEc0A== ARC-Authentication-Results: i=1; mx.microsoft.com 1; spf=pass smtp.mailfrom=wdc.com; dmarc=pass action=none header.from=wdc.com; dkim=pass header.d=wdc.com; arc=none DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=sharedspace.onmicrosoft.com; s=selector2-sharedspace-onmicrosoft-com; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-SenderADCheck; bh=VqmrXHzIruAcNotF2clWWzYvQNRNRKr+C27TLUx8gRQ=; b=dDIulKoFcNSUppzvUl9UPCVxAtkJQpbLfhMgtFqSOsEERuIihVaPWD4x3xyrWTb4e/AWSYK2cay949/NARkP8UlRyERUU+JqlnjBpo8C1cLgdFRxV4fvzNFu8viTTp010RWBsSlGE+lL6qloiiQQBsE4WGT7q95jseQpiHjjAvE= Received: from MN2PR04MB6061.namprd04.prod.outlook.com (20.178.246.15) by MN2PR04MB6991.namprd04.prod.outlook.com (10.186.144.209) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.2305.18; Thu, 3 Oct 2019 05:07:01 +0000 Received: from MN2PR04MB6061.namprd04.prod.outlook.com ([fe80::1454:87a:13b0:d3a]) by MN2PR04MB6061.namprd04.prod.outlook.com ([fe80::1454:87a:13b0:d3a%7]) with mapi id 15.20.2305.023; Thu, 3 Oct 2019 05:07:01 +0000 From: Anup Patel To: Palmer Dabbelt , Paul Walmsley , Paolo Bonzini , Radim K Subject: [PATCH v8 04/19] RISC-V: KVM: Implement VCPU create, init and destroy functions Thread-Topic: [PATCH v8 04/19] RISC-V: KVM: Implement VCPU create, init and destroy functions Thread-Index: AQHVeahjaOd40LXvJEyLeU+X/Cfsog== Date: Thu, 3 Oct 2019 05:07:01 +0000 Message-ID: <20191003050558.9031-5-anup.patel@wdc.com> References: <20191003050558.9031-1-anup.patel@wdc.com> In-Reply-To: <20191003050558.9031-1-anup.patel@wdc.com> Accept-Language: en-US Content-Language: en-US X-MS-Has-Attach: X-MS-TNEF-Correlator: x-clientproxiedby: BMXPR01CA0030.INDPRD01.PROD.OUTLOOK.COM (2603:1096:b00:c::16) To MN2PR04MB6061.namprd04.prod.outlook.com (2603:10b6:208:d8::15) authentication-results: spf=none (sender IP is ) smtp.mailfrom=Anup.Patel@wdc.com; x-ms-exchange-messagesentrepresentingtype: 1 x-mailer: git-send-email 2.17.1 x-originating-ip: [111.235.74.37] x-ms-publictraffictype: Email x-ms-office365-filtering-correlation-id: ed6237c5-7bda-452e-b1e8-08d747bf863c x-ms-office365-filtering-ht: Tenant x-ms-traffictypediagnostic: MN2PR04MB6991: x-ms-exchange-transport-forked: True x-microsoft-antispam-prvs: wdcipoutbound: EOP-TRUE x-ms-oob-tlc-oobclassifiers: OLM:454; x-forefront-prvs: 01792087B6 x-forefront-antispam-report: SFV:NSPM; SFS:(10019020)(979002)(4636009)(366004)(346002)(39860400002)(136003)(376002)(396003)(189003)(199004)(7416002)(52116002)(25786009)(102836004)(76176011)(54906003)(6506007)(1076003)(386003)(7736002)(44832011)(6436002)(486006)(66066001)(71190400001)(71200400001)(11346002)(446003)(6116002)(3846002)(476003)(2616005)(26005)(305945005)(6512007)(36756003)(186003)(14454004)(110136005)(5660300002)(6486002)(66446008)(66476007)(8936002)(66556008)(256004)(64756008)(14444005)(66946007)(86362001)(8676002)(81156014)(81166006)(99286004)(316002)(4326008)(2906002)(478600001)(50226002)(969003)(989001)(999001)(1009001)(1019001); DIR:OUT; SFP:1102; SCL:1; SRVR:MN2PR04MB6991; H:MN2PR04MB6061.namprd04.prod.outlook.com; FPR:; SPF:None; LANG:en; PTR:InfoNoRecords; MX:1; A:1; x-ms-exchange-senderadcheck: 1 x-microsoft-antispam: BCL:0; x-microsoft-antispam-message-info: R+YBdmRbXisA7fadUnY8B+LcCurm/VXywrkZoFija+oecPnlIJ7SCakUNP43SlAzmElY2WO4ei+A+zgkY2q6AZd2HyvXMKmBw0nFjlMdIp1nkZIc9oUN5omoN9PyzqdZ83BInLn4ryUtGMyJ6YJ8QPQcgn2usJ4D3L9U2H/DFN3nj+N16wrFaz+SkK+pBVlZsd2TL8yIb7dqxGE/NgHXlSs5pvj0W5M+nsEsiooqI7mZE+K4O/GpZC/58GZMiQqtZYqRJoX4GdyqOG/M9yXSqmZJUt9wenfR7j55RN3bxFf4xUr0JZQdmVyuT4SGqAWTSrlKFhPYxfB5cLQ4EM9hhUifs/ylStIrjgUn9aK76n7zaAA7kZp6vS6mb8YvRT4aDc/D1pptRL/m/rFmschUDUBSIWlbqvYo0W8hc+FXdCc= MIME-Version: 1.0 X-OriginatorOrg: wdc.com X-MS-Exchange-CrossTenant-Network-Message-Id: ed6237c5-7bda-452e-b1e8-08d747bf863c X-MS-Exchange-CrossTenant-originalarrivaltime: 03 Oct 2019 05:07:01.6122 (UTC) X-MS-Exchange-CrossTenant-fromentityheader: Hosted X-MS-Exchange-CrossTenant-id: b61c8803-16f3-4c35-9b17-6f65f441df86 X-MS-Exchange-CrossTenant-mailboxtype: HOSTED X-MS-Exchange-CrossTenant-userprincipalname: WEvkuVpR2oQhIKqA1CxaBYQ9ahZGKnBAsfc39n3HUkuTy8dxEA4VzXPEeYePtivPC3Ntx24Rhm5nKCZDEyYSug== X-MS-Exchange-Transport-CrossTenantHeadersStamped: MN2PR04MB6991 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20191002_220704_036042_1B4B9D85 X-CRM114-Status: GOOD ( 14.91 ) X-Spam-Score: -2.5 (--) X-Spam-Report: SpamAssassin version 3.4.2 on bombadil.infradead.org summary: Content analysis details: (-2.5 points) pts rule name description ---- ---------------------- -------------------------------------------------- -2.3 RCVD_IN_DNSWL_MED RBL: Sender listed at https://www.dnswl.org/, medium trust [216.71.153.144 listed in list.dnswl.org] -0.0 SPF_PASS SPF: sender matches SPF record 0.0 SPF_HELO_NONE SPF: HELO does not publish an SPF Record -0.1 DKIM_VALID_EF Message has a valid DKIM or DK signature from envelope-from domain 0.1 DKIM_SIGNED Message has a DKIM or DK signature, not necessarily valid -0.1 DKIM_VALID_AU Message has a valid DKIM or DK signature from author's domain -0.1 DKIM_VALID Message has at least one valid DKIM or DK signature X-BeenThere: linux-riscv@lists.infradead.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Damien Le Moal , Anup Patel , "kvm@vger.kernel.org" , Anup Patel , Daniel Lezcano , "linux-kernel@vger.kernel.org" , Christoph Hellwig , Atish Patra , Alexander Graf , Alistair Francis , Thomas Gleixner , "linux-riscv@lists.infradead.org" Sender: "linux-riscv" Errors-To: linux-riscv-bounces+patchwork-linux-riscv=patchwork.kernel.org@lists.infradead.org This patch implements VCPU create, init and destroy functions required by generic KVM module. We don't have much dynamic resources in struct kvm_vcpu_arch so these functions are quite simple for KVM RISC-V. Signed-off-by: Anup Patel Acked-by: Paolo Bonzini Reviewed-by: Paolo Bonzini Reviewed-by: Alexander Graf --- arch/riscv/include/asm/kvm_host.h | 68 +++++++++++++++++++++++++++++++ arch/riscv/kvm/vcpu.c | 68 +++++++++++++++++++++++++++++-- 2 files changed, 132 insertions(+), 4 deletions(-) diff --git a/arch/riscv/include/asm/kvm_host.h b/arch/riscv/include/asm/kvm_host.h index 9459709656be..dab32c9c3470 100644 --- a/arch/riscv/include/asm/kvm_host.h +++ b/arch/riscv/include/asm/kvm_host.h @@ -53,7 +53,75 @@ struct kvm_arch { phys_addr_t pgd_phys; }; +struct kvm_cpu_context { + unsigned long zero; + unsigned long ra; + unsigned long sp; + unsigned long gp; + unsigned long tp; + unsigned long t0; + unsigned long t1; + unsigned long t2; + unsigned long s0; + unsigned long s1; + unsigned long a0; + unsigned long a1; + unsigned long a2; + unsigned long a3; + unsigned long a4; + unsigned long a5; + unsigned long a6; + unsigned long a7; + unsigned long s2; + unsigned long s3; + unsigned long s4; + unsigned long s5; + unsigned long s6; + unsigned long s7; + unsigned long s8; + unsigned long s9; + unsigned long s10; + unsigned long s11; + unsigned long t3; + unsigned long t4; + unsigned long t5; + unsigned long t6; + unsigned long sepc; + unsigned long sstatus; + unsigned long hstatus; +}; + +struct kvm_vcpu_csr { + unsigned long vsstatus; + unsigned long vsie; + unsigned long vstvec; + unsigned long vsscratch; + unsigned long vsepc; + unsigned long vscause; + unsigned long vstval; + unsigned long vsip; + unsigned long vsatp; +}; + struct kvm_vcpu_arch { + /* VCPU ran atleast once */ + bool ran_atleast_once; + + /* ISA feature bits (similar to MISA) */ + unsigned long isa; + + /* CPU context of Guest VCPU */ + struct kvm_cpu_context guest_context; + + /* CPU CSR context of Guest VCPU */ + struct kvm_vcpu_csr guest_csr; + + /* CPU context upon Guest VCPU reset */ + struct kvm_cpu_context guest_reset_context; + + /* CPU CSR context upon Guest VCPU reset */ + struct kvm_vcpu_csr guest_reset_csr; + /* Don't run the VCPU (blocked) */ bool pause; diff --git a/arch/riscv/kvm/vcpu.c b/arch/riscv/kvm/vcpu.c index 48536cb0c8e7..8272b05d6ce4 100644 --- a/arch/riscv/kvm/vcpu.c +++ b/arch/riscv/kvm/vcpu.c @@ -31,10 +31,48 @@ struct kvm_stats_debugfs_item debugfs_entries[] = { { NULL } }; +#define KVM_RISCV_ISA_ALLOWED (riscv_isa_extension_mask(a) | \ + riscv_isa_extension_mask(c) | \ + riscv_isa_extension_mask(d) | \ + riscv_isa_extension_mask(f) | \ + riscv_isa_extension_mask(i) | \ + riscv_isa_extension_mask(m) | \ + riscv_isa_extension_mask(s) | \ + riscv_isa_extension_mask(u)) + +static void kvm_riscv_reset_vcpu(struct kvm_vcpu *vcpu) +{ + struct kvm_vcpu_csr *csr = &vcpu->arch.guest_csr; + struct kvm_vcpu_csr *reset_csr = &vcpu->arch.guest_reset_csr; + struct kvm_cpu_context *cntx = &vcpu->arch.guest_context; + struct kvm_cpu_context *reset_cntx = &vcpu->arch.guest_reset_context; + + memcpy(csr, reset_csr, sizeof(*csr)); + + memcpy(cntx, reset_cntx, sizeof(*cntx)); +} + struct kvm_vcpu *kvm_arch_vcpu_create(struct kvm *kvm, unsigned int id) { - /* TODO: */ - return NULL; + int err; + struct kvm_vcpu *vcpu; + + vcpu = kmem_cache_zalloc(kvm_vcpu_cache, GFP_KERNEL); + if (!vcpu) { + err = -ENOMEM; + goto out; + } + + err = kvm_vcpu_init(vcpu, kvm, id); + if (err) + goto free_vcpu; + + return vcpu; + +free_vcpu: + kmem_cache_free(kvm_vcpu_cache, vcpu); +out: + return ERR_PTR(err); } int kvm_arch_vcpu_setup(struct kvm_vcpu *vcpu) @@ -48,13 +86,32 @@ void kvm_arch_vcpu_postcreate(struct kvm_vcpu *vcpu) int kvm_arch_vcpu_init(struct kvm_vcpu *vcpu) { - /* TODO: */ + struct kvm_cpu_context *cntx; + + /* Mark this VCPU never ran */ + vcpu->arch.ran_atleast_once = false; + + /* Setup ISA features available to VCPU */ + vcpu->arch.isa = riscv_isa_extension_base(NULL) & KVM_RISCV_ISA_ALLOWED; + + /* Setup reset state of shadow SSTATUS and HSTATUS CSRs */ + cntx = &vcpu->arch.guest_reset_context; + cntx->sstatus = SR_SPP | SR_SPIE; + cntx->hstatus = 0; + cntx->hstatus |= HSTATUS_SP2V; + cntx->hstatus |= HSTATUS_SP2P; + cntx->hstatus |= HSTATUS_SPV; + + /* Reset VCPU */ + kvm_riscv_reset_vcpu(vcpu); + return 0; } void kvm_arch_vcpu_destroy(struct kvm_vcpu *vcpu) { - /* TODO: */ + kvm_riscv_stage2_flush_cache(vcpu); + kmem_cache_free(kvm_vcpu_cache, vcpu); } int kvm_cpu_has_pending_timer(struct kvm_vcpu *vcpu) @@ -199,6 +256,9 @@ int kvm_arch_vcpu_ioctl_run(struct kvm_vcpu *vcpu, struct kvm_run *run) int ret; unsigned long scause, stval; + /* Mark this VCPU ran atleast once */ + vcpu->arch.ran_atleast_once = true; + vcpu->arch.srcu_idx = srcu_read_lock(&vcpu->kvm->srcu); /* Process MMIO value returned from user-space */ From patchwork Thu Oct 3 05:07:10 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Anup Patel X-Patchwork-Id: 11172103 Return-Path: Received: from mail.kernel.org (pdx-korg-mail-1.web.codeaurora.org [172.30.200.123]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id 17CB314DB for ; Thu, 3 Oct 2019 05:07:25 +0000 (UTC) Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id E679621D81 for ; Thu, 3 Oct 2019 05:07:24 +0000 (UTC) Authentication-Results: mail.kernel.org; dkim=pass (2048-bit key) header.d=lists.infradead.org header.i=@lists.infradead.org header.b="pd29MXpv"; dkim=fail reason="signature verification failed" (2048-bit key) header.d=wdc.com header.i=@wdc.com header.b="OmOgs8ov"; dkim=fail reason="signature verification failed" (1024-bit key) header.d=sharedspace.onmicrosoft.com header.i=@sharedspace.onmicrosoft.com header.b="hwKBMytV" DMARC-Filter: OpenDMARC Filter v1.3.2 mail.kernel.org E679621D81 Authentication-Results: mail.kernel.org; dmarc=fail (p=none dis=none) header.from=wdc.com Authentication-Results: mail.kernel.org; spf=none smtp.mailfrom=linux-riscv-bounces+patchwork-linux-riscv=patchwork.kernel.org@lists.infradead.org DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=bombadil.20170209; h=Sender: Content-Transfer-Encoding:Content-Type:Cc:List-Subscribe:List-Help:List-Post: List-Archive:List-Unsubscribe:List-Id:MIME-Version:In-Reply-To:References: Message-ID:Date:Subject:To:From:Reply-To:Content-ID:Content-Description: Resent-Date:Resent-From:Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID: List-Owner; bh=pDRiIaAQOL3rhNgheNni59CwJ/B0EYcRHkdU7cx0NhY=; b=pd29MXpvjiASSW ZmHO82j//sZhawQcnk3zRZoiJvJOoQrn3IwyGwzRt8ZDUSwfgT/Co7mfiDQ5oNziqJanykuuhAFrm RU3KEK641Y5eUWfXd3ojreUDUO0KMmUr7dQZW1ehwgipLb0hY+d4Ge2IXb9gcrMHqVZ1eBI75xoTC dikJhmWNaCcuuX4oDggtbNtKwIlbsBT/dX2FDY9j1CTvBzJYImT9YiA4PU0ZCZgXXouf04n+/nqcx +oBXHO4M2VgSAR1K70BeSRK9vx8vZn1jetkr0FMa5Px1OPap+KFZWGNbDovWYzvzBj2DGKbz5Y+vJ sNVUPmHZ7u00N3dNdYyA==; Received: from localhost ([127.0.0.1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.92.2 #3 (Red Hat Linux)) id 1iFtKd-0003XI-Dz; Thu, 03 Oct 2019 05:07:15 +0000 Received: from esa5.hgst.iphmx.com ([216.71.153.144]) by bombadil.infradead.org with esmtps (Exim 4.92.2 #3 (Red Hat Linux)) id 1iFtKa-0003Wa-Gq for linux-riscv@lists.infradead.org; Thu, 03 Oct 2019 05:07:14 +0000 DKIM-Signature: v=1; a=rsa-sha256; c=simple/simple; d=wdc.com; i=@wdc.com; q=dns/txt; s=dkim.wdc.com; t=1570079232; x=1601615232; h=from:to:cc:subject:date:message-id:references: in-reply-to:content-transfer-encoding:mime-version; bh=m4kyNVZ1rRk2FthfjB8FQ3wOnCKyxKs5UcOO5M5C6gM=; b=OmOgs8ovwBtdsBmZhuB5JqQu7UTOAg8K5bFQYQj5w63gYiF/BkDUziPI HF1G9kJPvErWxBOaJ7qy8fcRtyTIW43VTc91JWesw2HmeAbaQPbQJ+nm/ sjubeRzvNp/B6YOwE0tyItVlukGzw6dMQp5WR/XPd+1L+Pddc/UDF99c3 Pja9hJs4/dEnaDi8ofh0IAeTYyGB0NNfcU9MGCHfPDqc9QQQ7p3nWzfcI LeS6rHOEkpHszZH1FcP77W88C0iSJIa3w/QsmrTIPI9cbFR/WRuT7ULBn QL9JK5ox82kfGE5yU6D9RV5nyl2pukQ/REHx92hqIk6TG7uhvl/UBV0DT w==; IronPort-SDR: NK6MB3nZdbFTwoHEoOanLztDT/85p5YEKDGmN0s1mlECvlgUAMryXnktOVzsYjPpgYROFCSGcP SdacNmrBOz9ATqMtqKCj7qxdSEopWXqtntLRl6S/7nNIjiZ5rGPnse4KH9pMwskAraJ8bOHJ9t jHAF2/0/tDiGpCxkQ3jDjU0hhsH3sy1vHlwqM14fQivUA4tnz9tmLRG8iK7dPgAWg63WIGEEZg 6ER8RvffaSwa0hEbHggIPsrPMI4PeqacBihnRUC5Et2Fc7j3OuRTgNIzo3pzPsw3+xM4Ce0F89 rRE= X-IronPort-AV: E=Sophos;i="5.67,251,1566835200"; d="scan'208";a="120461317" Received: from mail-co1nam03lp2054.outbound.protection.outlook.com (HELO NAM03-CO1-obe.outbound.protection.outlook.com) ([104.47.40.54]) by ob1.hgst.iphmx.com with ESMTP; 03 Oct 2019 13:07:11 +0800 ARC-Seal: i=1; a=rsa-sha256; s=arcselector9901; d=microsoft.com; cv=none; b=np83v2m6rzevHwvthdTZeAYjgXhsqplZ7J8qMeVq5jGz9ukSuMSIj5Xsnso/O9Fu2KUpbco/xiFP9kweJFifJKPVYDh9HU+NZrd72qO+njgJoF/iAxXAu7rxQa+C7Wb1eDQJkOijBCfvwFze1jeclCzRWUSRbzpUsieuZ/OW7dP1D9lLSCoLkW5tDsbSSXjF4eM6LWVJCP7clg967cp+z9n2LgRKJD6HzWhNbvUzwwP5cRquPfNPXLwKxocNlsmGI/j9B3gC0KNxbV++HvdXElPsffxEy8u8yHfd+pQ8OmQr3/Wav+HC0CJa++Sf9OBzi731KTY/VKASVaDsxu2uqw== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=microsoft.com; s=arcselector9901; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-SenderADCheck; bh=G4F+pObVzraWgbSZALmMMV+JHw/3vp3JEuzXyWTcRck=; b=EZcgE/6fGznPrWA1krTHHSx6tY0s+9Xmke2ABUy23wYvFhWT44cynuwG0nhgltl9fckOxEIc5wgUsuBC3pZlnPOz3TmHKz8NRy2sivCvhVRDv24H9oaD6+7cetOPSHqts4AFo2MnM3U5nvuMHYzTS0CghEVh0ZiEWOTTVRdwxvLlyDYhbvGof1rsWRxUSHhvETgYTQMflEYKYQvbj3gXiWosXXkekUBdtX5UHACxoKFIFvQdJOZCr/DoaA1S2bGW3VnUET0Hz8IIdgGAk87Z3HxjO0f7XP3Jn5lFW30+a+BDvtfsosUYgjgWPmJTHmMAE44qT3ie0PXTqtBdHJpP6g== ARC-Authentication-Results: i=1; mx.microsoft.com 1; spf=pass smtp.mailfrom=wdc.com; dmarc=pass action=none header.from=wdc.com; dkim=pass header.d=wdc.com; arc=none DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=sharedspace.onmicrosoft.com; s=selector2-sharedspace-onmicrosoft-com; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-SenderADCheck; bh=G4F+pObVzraWgbSZALmMMV+JHw/3vp3JEuzXyWTcRck=; b=hwKBMytVMAkKLSPckW6SxPnx8z7aMNjetICZtKZ/F1p52cEEun7SpZeFtNnST/Ety6vCx7VWeffBZ4mCJ2D7az4XzpJmey8vw9ocIvb2Xf/r9YguimJNm9MpSsk86OPZdW+YuVaiQcW8G4Llv7UXifGgnnRQ5HXboY08w03ukrc= Received: from MN2PR04MB6061.namprd04.prod.outlook.com (20.178.246.15) by MN2PR04MB6991.namprd04.prod.outlook.com (10.186.144.209) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.2305.18; Thu, 3 Oct 2019 05:07:10 +0000 Received: from MN2PR04MB6061.namprd04.prod.outlook.com ([fe80::1454:87a:13b0:d3a]) by MN2PR04MB6061.namprd04.prod.outlook.com ([fe80::1454:87a:13b0:d3a%7]) with mapi id 15.20.2305.023; Thu, 3 Oct 2019 05:07:10 +0000 From: Anup Patel To: Palmer Dabbelt , Paul Walmsley , Paolo Bonzini , Radim K Subject: [PATCH v8 05/19] RISC-V: KVM: Implement VCPU interrupts and requests handling Thread-Topic: [PATCH v8 05/19] RISC-V: KVM: Implement VCPU interrupts and requests handling Thread-Index: AQHVeahpBqUrT2H1h0eHMHR53hrOKQ== Date: Thu, 3 Oct 2019 05:07:10 +0000 Message-ID: <20191003050558.9031-6-anup.patel@wdc.com> References: <20191003050558.9031-1-anup.patel@wdc.com> In-Reply-To: <20191003050558.9031-1-anup.patel@wdc.com> Accept-Language: en-US Content-Language: en-US X-MS-Has-Attach: X-MS-TNEF-Correlator: x-clientproxiedby: BMXPR01CA0030.INDPRD01.PROD.OUTLOOK.COM (2603:1096:b00:c::16) To MN2PR04MB6061.namprd04.prod.outlook.com (2603:10b6:208:d8::15) authentication-results: spf=none (sender IP is ) smtp.mailfrom=Anup.Patel@wdc.com; x-ms-exchange-messagesentrepresentingtype: 1 x-mailer: git-send-email 2.17.1 x-originating-ip: [111.235.74.37] x-ms-publictraffictype: Email x-ms-office365-filtering-correlation-id: c5103f44-e29a-40ac-94d3-08d747bf8b4b x-ms-office365-filtering-ht: Tenant x-ms-traffictypediagnostic: MN2PR04MB6991: x-ms-exchange-transport-forked: True x-microsoft-antispam-prvs: wdcipoutbound: EOP-TRUE x-ms-oob-tlc-oobclassifiers: OLM:3044; x-forefront-prvs: 01792087B6 x-forefront-antispam-report: SFV:NSPM; SFS:(10019020)(4636009)(366004)(346002)(39860400002)(136003)(376002)(396003)(189003)(199004)(7416002)(52116002)(25786009)(102836004)(76176011)(30864003)(54906003)(6506007)(1076003)(386003)(7736002)(44832011)(6436002)(486006)(66066001)(71190400001)(71200400001)(11346002)(446003)(6116002)(3846002)(476003)(2616005)(26005)(305945005)(6512007)(36756003)(186003)(14454004)(110136005)(5660300002)(6486002)(66446008)(66476007)(8936002)(66556008)(256004)(64756008)(14444005)(66946007)(86362001)(8676002)(81156014)(81166006)(99286004)(316002)(4326008)(2906002)(478600001)(50226002); DIR:OUT; SFP:1102; SCL:1; SRVR:MN2PR04MB6991; H:MN2PR04MB6061.namprd04.prod.outlook.com; FPR:; SPF:None; LANG:en; PTR:InfoNoRecords; MX:1; A:1; x-ms-exchange-senderadcheck: 1 x-microsoft-antispam: BCL:0; x-microsoft-antispam-message-info: tgqNgR+6mS8rZPq17QsKo3QuAXtya4Pqa5QKKMXF58XmxghRwiPlMrR0SkiSmiuD/nv+viR057cVBxXPB25Zx7YV/26UHh18RIoGak/wMN3P1h0+LA2JqGDOmXMig8adXdZcM6edVBFR2O0QwuMUsEU5FZZgeLOSYlmLxk8AJ8d3UzWt31zb1oT8tKT5lq090aumoT0JBqdnkG9zcylyejRG0OhzIJyZXodj3haZpybtvfq6bbJuzny4E0A4ZiB+0CTwuWqBBCPbUHe4aA1rmFCn7bTnKEKxsS2PiYpsvbJ1fW/GexX1MZiaDTcubR9PcdPIax4v+HJvXU9yrNgHCpk4laeiqgZ4eE3PH/nVoZO5ewwQ675qQ630HkfpblmtSA+bmFKYWOmn5sit1dUmEyi3MJBI4TD+rX/SF5EcnWE= MIME-Version: 1.0 X-OriginatorOrg: wdc.com X-MS-Exchange-CrossTenant-Network-Message-Id: c5103f44-e29a-40ac-94d3-08d747bf8b4b X-MS-Exchange-CrossTenant-originalarrivaltime: 03 Oct 2019 05:07:10.1104 (UTC) X-MS-Exchange-CrossTenant-fromentityheader: Hosted X-MS-Exchange-CrossTenant-id: b61c8803-16f3-4c35-9b17-6f65f441df86 X-MS-Exchange-CrossTenant-mailboxtype: HOSTED X-MS-Exchange-CrossTenant-userprincipalname: m/m33yGGeyMhEMOrk370poOLnu1F00cxKHVbCvHm2yeCv5f/UhA/B2o4Q8aMXpZS6YS53nkngCoHPfezlZe4aQ== X-MS-Exchange-Transport-CrossTenantHeadersStamped: MN2PR04MB6991 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20191002_220712_586513_74948440 X-CRM114-Status: GOOD ( 20.35 ) X-Spam-Score: -2.5 (--) X-Spam-Report: SpamAssassin version 3.4.2 on bombadil.infradead.org summary: Content analysis details: (-2.5 points) pts rule name description ---- ---------------------- -------------------------------------------------- -2.3 RCVD_IN_DNSWL_MED RBL: Sender listed at https://www.dnswl.org/, medium trust [216.71.153.144 listed in list.dnswl.org] -0.0 SPF_PASS SPF: sender matches SPF record 0.0 SPF_HELO_NONE SPF: HELO does not publish an SPF Record -0.1 DKIM_VALID_EF Message has a valid DKIM or DK signature from envelope-from domain 0.1 DKIM_SIGNED Message has a DKIM or DK signature, not necessarily valid -0.1 DKIM_VALID_AU Message has a valid DKIM or DK signature from author's domain -0.1 DKIM_VALID Message has at least one valid DKIM or DK signature X-BeenThere: linux-riscv@lists.infradead.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Damien Le Moal , Anup Patel , "kvm@vger.kernel.org" , Anup Patel , Daniel Lezcano , "linux-kernel@vger.kernel.org" , Christoph Hellwig , Atish Patra , Alexander Graf , Alistair Francis , Thomas Gleixner , "linux-riscv@lists.infradead.org" Sender: "linux-riscv" Errors-To: linux-riscv-bounces+patchwork-linux-riscv=patchwork.kernel.org@lists.infradead.org This patch implements VCPU interrupts and requests which are both asynchronous events. The VCPU interrupts can be set/unset using KVM_INTERRUPT ioctl from user-space. In future, the in-kernel IRQCHIP emulation will use kvm_riscv_vcpu_set_interrupt() and kvm_riscv_vcpu_unset_interrupt() functions to set/unset VCPU interrupts. Important VCPU requests implemented by this patch are: KVM_REQ_SLEEP - set whenever VCPU itself goes to sleep state KVM_REQ_VCPU_RESET - set whenever VCPU reset is requested The WFI trap-n-emulate (added later) will use KVM_REQ_SLEEP request and kvm_riscv_vcpu_has_interrupt() function. The KVM_REQ_VCPU_RESET request will be used by SBI emulation (added later) to power-up a VCPU in power-off state. The user-space can use the GET_MPSTATE/SET_MPSTATE ioctls to get/set power state of a VCPU. Signed-off-by: Anup Patel Acked-by: Paolo Bonzini Reviewed-by: Paolo Bonzini Reviewed-by: Alexander Graf --- arch/riscv/include/asm/kvm_host.h | 26 ++++ arch/riscv/include/uapi/asm/kvm.h | 3 + arch/riscv/kvm/main.c | 8 ++ arch/riscv/kvm/vcpu.c | 193 ++++++++++++++++++++++++++++-- 4 files changed, 217 insertions(+), 13 deletions(-) diff --git a/arch/riscv/include/asm/kvm_host.h b/arch/riscv/include/asm/kvm_host.h index dab32c9c3470..d801216da6d0 100644 --- a/arch/riscv/include/asm/kvm_host.h +++ b/arch/riscv/include/asm/kvm_host.h @@ -122,6 +122,21 @@ struct kvm_vcpu_arch { /* CPU CSR context upon Guest VCPU reset */ struct kvm_vcpu_csr guest_reset_csr; + /* + * VCPU interrupts + * + * We have a lockless approach for tracking pending VCPU interrupts + * implemented using atomic bitops. The irqs_pending bitmap represent + * pending interrupts whereas irqs_pending_mask represent bits changed + * in irqs_pending. Our approach is modeled around multiple producer + * and single consumer problem where the consumer is the VCPU itself. + */ + unsigned long irqs_pending; + unsigned long irqs_pending_mask; + + /* VCPU power-off state */ + bool power_off; + /* Don't run the VCPU (blocked) */ bool pause; @@ -135,6 +150,9 @@ static inline void kvm_arch_vcpu_uninit(struct kvm_vcpu *vcpu) {} static inline void kvm_arch_sched_in(struct kvm_vcpu *vcpu, int cpu) {} static inline void kvm_arch_vcpu_block_finish(struct kvm_vcpu *vcpu) {} +int kvm_riscv_setup_vsip(void); +void kvm_riscv_cleanup_vsip(void); + void kvm_riscv_stage2_flush_cache(struct kvm_vcpu *vcpu); int kvm_riscv_stage2_alloc_pgd(struct kvm *kvm); void kvm_riscv_stage2_free_pgd(struct kvm *kvm); @@ -146,4 +164,12 @@ int kvm_riscv_vcpu_exit(struct kvm_vcpu *vcpu, struct kvm_run *run, static inline void __kvm_riscv_switch_to(struct kvm_vcpu_arch *vcpu_arch) {} +int kvm_riscv_vcpu_set_interrupt(struct kvm_vcpu *vcpu, unsigned int irq); +int kvm_riscv_vcpu_unset_interrupt(struct kvm_vcpu *vcpu, unsigned int irq); +void kvm_riscv_vcpu_flush_interrupts(struct kvm_vcpu *vcpu); +void kvm_riscv_vcpu_sync_interrupts(struct kvm_vcpu *vcpu); +bool kvm_riscv_vcpu_has_interrupt(struct kvm_vcpu *vcpu); +void kvm_riscv_vcpu_power_off(struct kvm_vcpu *vcpu); +void kvm_riscv_vcpu_power_on(struct kvm_vcpu *vcpu); + #endif /* __RISCV_KVM_HOST_H__ */ diff --git a/arch/riscv/include/uapi/asm/kvm.h b/arch/riscv/include/uapi/asm/kvm.h index d15875818b6e..6dbc056d58ba 100644 --- a/arch/riscv/include/uapi/asm/kvm.h +++ b/arch/riscv/include/uapi/asm/kvm.h @@ -18,6 +18,9 @@ #define KVM_COALESCED_MMIO_PAGE_OFFSET 1 +#define KVM_INTERRUPT_SET -1U +#define KVM_INTERRUPT_UNSET -2U + /* for KVM_GET_REGS and KVM_SET_REGS */ struct kvm_regs { }; diff --git a/arch/riscv/kvm/main.c b/arch/riscv/kvm/main.c index e1ffe6d42f39..d088247843c5 100644 --- a/arch/riscv/kvm/main.c +++ b/arch/riscv/kvm/main.c @@ -48,6 +48,8 @@ int kvm_arch_hardware_enable(void) hideleg |= SIE_SEIE; csr_write(CSR_HIDELEG, hideleg); + csr_write(CSR_VSIP, 0); + return 0; } @@ -59,11 +61,17 @@ void kvm_arch_hardware_disable(void) int kvm_arch_init(void *opaque) { + int ret; + if (!riscv_isa_extension_available(NULL, h)) { kvm_info("hypervisor extension not available\n"); return -ENODEV; } + ret = kvm_riscv_setup_vsip(); + if (ret) + return ret; + kvm_info("hypervisor extension available\n"); return 0; diff --git a/arch/riscv/kvm/vcpu.c b/arch/riscv/kvm/vcpu.c index 8272b05d6ce4..3223f723f79e 100644 --- a/arch/riscv/kvm/vcpu.c +++ b/arch/riscv/kvm/vcpu.c @@ -11,6 +11,7 @@ #include #include #include +#include #include #include #include @@ -40,6 +41,8 @@ struct kvm_stats_debugfs_item debugfs_entries[] = { riscv_isa_extension_mask(s) | \ riscv_isa_extension_mask(u)) +static unsigned long __percpu *vsip_shadow; + static void kvm_riscv_reset_vcpu(struct kvm_vcpu *vcpu) { struct kvm_vcpu_csr *csr = &vcpu->arch.guest_csr; @@ -50,6 +53,9 @@ static void kvm_riscv_reset_vcpu(struct kvm_vcpu *vcpu) memcpy(csr, reset_csr, sizeof(*csr)); memcpy(cntx, reset_cntx, sizeof(*cntx)); + + WRITE_ONCE(vcpu->arch.irqs_pending, 0); + WRITE_ONCE(vcpu->arch.irqs_pending_mask, 0); } struct kvm_vcpu *kvm_arch_vcpu_create(struct kvm *kvm, unsigned int id) @@ -116,8 +122,8 @@ void kvm_arch_vcpu_destroy(struct kvm_vcpu *vcpu) int kvm_cpu_has_pending_timer(struct kvm_vcpu *vcpu) { - /* TODO: */ - return 0; + return READ_ONCE(vcpu->arch.irqs_pending) & + vcpu->arch.guest_csr.vsie & (1UL << IRQ_S_TIMER); } void kvm_arch_vcpu_blocking(struct kvm_vcpu *vcpu) @@ -130,20 +136,18 @@ void kvm_arch_vcpu_unblocking(struct kvm_vcpu *vcpu) int kvm_arch_vcpu_runnable(struct kvm_vcpu *vcpu) { - /* TODO: */ - return 0; + return (kvm_riscv_vcpu_has_interrupt(vcpu) && + !vcpu->arch.power_off && !vcpu->arch.pause); } int kvm_arch_vcpu_should_kick(struct kvm_vcpu *vcpu) { - /* TODO: */ - return 0; + return kvm_vcpu_exiting_guest_mode(vcpu) == IN_GUEST_MODE; } bool kvm_arch_vcpu_in_kernel(struct kvm_vcpu *vcpu) { - /* TODO: */ - return false; + return (vcpu->arch.guest_context.sstatus & SR_SPP) ? true : false; } bool kvm_arch_has_vcpu_debugfs(void) @@ -164,7 +168,21 @@ vm_fault_t kvm_arch_vcpu_fault(struct kvm_vcpu *vcpu, struct vm_fault *vmf) long kvm_arch_vcpu_async_ioctl(struct file *filp, unsigned int ioctl, unsigned long arg) { - /* TODO; */ + struct kvm_vcpu *vcpu = filp->private_data; + void __user *argp = (void __user *)arg; + + if (ioctl == KVM_INTERRUPT) { + struct kvm_interrupt irq; + + if (copy_from_user(&irq, argp, sizeof(irq))) + return -EFAULT; + + if (irq.irq == KVM_INTERRUPT_SET) + return kvm_riscv_vcpu_set_interrupt(vcpu, IRQ_S_EXT); + else + return kvm_riscv_vcpu_unset_interrupt(vcpu, IRQ_S_EXT); + } + return -ENOIOCTLCMD; } @@ -213,18 +231,111 @@ int kvm_arch_vcpu_ioctl_set_regs(struct kvm_vcpu *vcpu, struct kvm_regs *regs) return -EINVAL; } +void kvm_riscv_vcpu_flush_interrupts(struct kvm_vcpu *vcpu) +{ + struct kvm_vcpu_csr *csr = &vcpu->arch.guest_csr; + unsigned long mask, val; + + if (READ_ONCE(vcpu->arch.irqs_pending_mask)) { + mask = xchg_acquire(&vcpu->arch.irqs_pending_mask, 0); + val = READ_ONCE(vcpu->arch.irqs_pending) & mask; + + csr->vsip &= ~mask; + csr->vsip |= val; + } +} + +void kvm_riscv_vcpu_sync_interrupts(struct kvm_vcpu *vcpu) +{ + vcpu->arch.guest_csr.vsip = csr_read(CSR_VSIP); + vcpu->arch.guest_csr.vsie = csr_read(CSR_VSIE); + + /* Guest can directly update VSIP software interrupt bits */ + if (vcpu->arch.guest_csr.vsip ^ READ_ONCE(vcpu->arch.irqs_pending)) { + if (vcpu->arch.guest_csr.vsip & (1UL << IRQ_S_SOFT)) + kvm_riscv_vcpu_set_interrupt(vcpu, IRQ_S_SOFT); + else + kvm_riscv_vcpu_unset_interrupt(vcpu, IRQ_S_SOFT); + } +} + +int kvm_riscv_vcpu_set_interrupt(struct kvm_vcpu *vcpu, unsigned int irq) +{ + if (irq != IRQ_S_SOFT && + irq != IRQ_S_TIMER && + irq != IRQ_S_EXT) + return -EINVAL; + + set_bit(irq, &vcpu->arch.irqs_pending); + smp_mb__before_atomic(); + set_bit(irq, &vcpu->arch.irqs_pending_mask); + + kvm_vcpu_kick(vcpu); + + return 0; +} + +int kvm_riscv_vcpu_unset_interrupt(struct kvm_vcpu *vcpu, unsigned int irq) +{ + if (irq != IRQ_S_SOFT && + irq != IRQ_S_TIMER && + irq != IRQ_S_EXT) + return -EINVAL; + + clear_bit(irq, &vcpu->arch.irqs_pending); + smp_mb__before_atomic(); + set_bit(irq, &vcpu->arch.irqs_pending_mask); + + return 0; +} + +bool kvm_riscv_vcpu_has_interrupt(struct kvm_vcpu *vcpu) +{ + return (READ_ONCE(vcpu->arch.irqs_pending) & + vcpu->arch.guest_csr.vsie) ? true : false; +} + +void kvm_riscv_vcpu_power_off(struct kvm_vcpu *vcpu) +{ + vcpu->arch.power_off = true; + kvm_make_request(KVM_REQ_SLEEP, vcpu); + kvm_vcpu_kick(vcpu); +} + +void kvm_riscv_vcpu_power_on(struct kvm_vcpu *vcpu) +{ + vcpu->arch.power_off = false; + kvm_vcpu_wake_up(vcpu); +} + int kvm_arch_vcpu_ioctl_get_mpstate(struct kvm_vcpu *vcpu, struct kvm_mp_state *mp_state) { - /* TODO: */ + if (vcpu->arch.power_off) + mp_state->mp_state = KVM_MP_STATE_STOPPED; + else + mp_state->mp_state = KVM_MP_STATE_RUNNABLE; + return 0; } int kvm_arch_vcpu_ioctl_set_mpstate(struct kvm_vcpu *vcpu, struct kvm_mp_state *mp_state) { - /* TODO: */ - return 0; + int ret = 0; + + switch (mp_state->mp_state) { + case KVM_MP_STATE_RUNNABLE: + vcpu->arch.power_off = false; + break; + case KVM_MP_STATE_STOPPED: + kvm_riscv_vcpu_power_off(vcpu); + break; + default: + ret = -EINVAL; + } + + return ret; } int kvm_arch_vcpu_ioctl_set_guest_debug(struct kvm_vcpu *vcpu, @@ -248,7 +359,51 @@ void kvm_arch_vcpu_put(struct kvm_vcpu *vcpu) static void kvm_riscv_check_vcpu_requests(struct kvm_vcpu *vcpu) { - /* TODO: */ + struct swait_queue_head *wq = kvm_arch_vcpu_wq(vcpu); + + if (kvm_request_pending(vcpu)) { + if (kvm_check_request(KVM_REQ_SLEEP, vcpu)) { + swait_event_interruptible_exclusive(*wq, + ((!vcpu->arch.power_off) && + (!vcpu->arch.pause))); + + if (vcpu->arch.power_off || vcpu->arch.pause) { + /* + * Awaken to handle a signal, request to + * sleep again later. + */ + kvm_make_request(KVM_REQ_SLEEP, vcpu); + } + } + + if (kvm_check_request(KVM_REQ_VCPU_RESET, vcpu)) + kvm_riscv_reset_vcpu(vcpu); + } +} + +static void kvm_riscv_update_vsip(struct kvm_vcpu *vcpu) +{ + struct kvm_vcpu_csr *csr = &vcpu->arch.guest_csr; + unsigned long *vsip = raw_cpu_ptr(vsip_shadow); + + if (*vsip != csr->vsip) { + csr_write(CSR_VSIP, csr->vsip); + *vsip = csr->vsip; + } +} + +int kvm_riscv_setup_vsip(void) +{ + vsip_shadow = alloc_percpu(unsigned long); + if (!vsip_shadow) + return -ENOMEM; + + return 0; +} + +void kvm_riscv_cleanup_vsip(void) +{ + free_percpu(vsip_shadow); } int kvm_arch_vcpu_ioctl_run(struct kvm_vcpu *vcpu, struct kvm_run *run) @@ -311,6 +466,15 @@ int kvm_arch_vcpu_ioctl_run(struct kvm_vcpu *vcpu, struct kvm_run *run) srcu_read_unlock(&vcpu->kvm->srcu, vcpu->arch.srcu_idx); smp_mb__after_srcu_read_unlock(); + /* + * We might have got VCPU interrupts updated asynchronously + * so update it in HW. + */ + kvm_riscv_vcpu_flush_interrupts(vcpu); + + /* Update VSIP CSR for current CPU */ + kvm_riscv_update_vsip(vcpu); + if (ret <= 0 || kvm_request_pending(vcpu)) { vcpu->mode = OUTSIDE_GUEST_MODE; @@ -334,6 +498,9 @@ int kvm_arch_vcpu_ioctl_run(struct kvm_vcpu *vcpu, struct kvm_run *run) scause = csr_read(CSR_SCAUSE); stval = csr_read(CSR_STVAL); + /* Syncup interrupts state with HW */ + kvm_riscv_vcpu_sync_interrupts(vcpu); + /* * We may have taken a host interrupt in VS/VU-mode (i.e. * while executing the guest). This interrupt is still From patchwork Thu Oct 3 05:07:17 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Anup Patel X-Patchwork-Id: 11172109 Return-Path: Received: from mail.kernel.org (pdx-korg-mail-1.web.codeaurora.org [172.30.200.123]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id ECC9814DB for ; Thu, 3 Oct 2019 05:07:46 +0000 (UTC) Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id C469921D81 for ; Thu, 3 Oct 2019 05:07:46 +0000 (UTC) Authentication-Results: mail.kernel.org; dkim=pass (2048-bit key) header.d=lists.infradead.org header.i=@lists.infradead.org header.b="oD6SMXe7"; dkim=fail reason="signature verification failed" (2048-bit key) header.d=wdc.com header.i=@wdc.com header.b="ks8t0wrT"; dkim=fail reason="signature verification failed" (1024-bit key) header.d=sharedspace.onmicrosoft.com header.i=@sharedspace.onmicrosoft.com header.b="rIJKiKto" DMARC-Filter: OpenDMARC Filter v1.3.2 mail.kernel.org C469921D81 Authentication-Results: mail.kernel.org; dmarc=fail (p=none dis=none) header.from=wdc.com Authentication-Results: mail.kernel.org; spf=none smtp.mailfrom=linux-riscv-bounces+patchwork-linux-riscv=patchwork.kernel.org@lists.infradead.org DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=bombadil.20170209; h=Sender: Content-Transfer-Encoding:Content-Type:Cc:List-Subscribe:List-Help:List-Post: List-Archive:List-Unsubscribe:List-Id:MIME-Version:In-Reply-To:References: Message-ID:Date:Subject:To:From:Reply-To:Content-ID:Content-Description: Resent-Date:Resent-From:Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID: List-Owner; bh=HvdPHeUxWrCOoTq7krGfYSs9zc95j0HNyZ2hzqDp7Dc=; b=oD6SMXe78+aUN0 2zZF10nSo2GIPBB1IhG13HdO7sehbVhZGErHsor7ijCQHoVPCPIedflqTtJcaCYX/4laNW4AH9G1i 4CKl9cNRxboQa49b0i8527ikKKxtr7yR7BCWcqXr31uYiKl/ssgOd9bte14ueXH6x4nlSkg6uICeM 5VzDhzfrEv8A9TiOs5XKIy9uOsr4eOhPWG1mqj02/g+kD91Hxn3+vmKOFyGtZUGumI/sKvfExhhhx bxwgOTEYczDcoIbYBddtDksakzOjmR38vDxPIxr6FCf+/4zTx9uc35ch37lbj0TOKP0JG1I06x4ha 6x3mZ5IJDfeKennmX24Q==; Received: from localhost ([127.0.0.1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.92.2 #3 (Red Hat Linux)) id 1iFtKz-0003e3-Ah; Thu, 03 Oct 2019 05:07:37 +0000 Received: from esa6.hgst.iphmx.com ([216.71.154.45]) by bombadil.infradead.org with esmtps (Exim 4.92.2 #3 (Red Hat Linux)) id 1iFtKw-0003co-4n for linux-riscv@lists.infradead.org; Thu, 03 Oct 2019 05:07:36 +0000 DKIM-Signature: v=1; a=rsa-sha256; c=simple/simple; d=wdc.com; i=@wdc.com; q=dns/txt; s=dkim.wdc.com; t=1570079255; x=1601615255; h=from:to:cc:subject:date:message-id:references: in-reply-to:content-transfer-encoding:mime-version; bh=3L3tbrLZGY9OA3M1l/myO3mWffr8BF50tw9LFKu/76o=; b=ks8t0wrTfyrtyf8m2PEO2M+RSswWZ16yev7MvY4Z7ax+Lu00MWIP3no6 Hlc90+85VgNCirT8oP2KHnRlV6+e/FGxmlE3JwQio9miJ0f1EWO7CIBh1 N+78K31WjOTpW4qI4PEm2qljQcx12uk5GaOmz4ONBTlQzP6fIE/nXyqhS dfRN613DENtHEvQ7VvgPtBg9cstB14Q8X3dZZobnu3ZKkPQxYTCZpG5U7 wHmsilnNe9WeD1m9KXqk//yj5VtBum59oLaY6dYBwtqJHCvHvnWd7JS8O EiePykTFlkT6Kv2GZWrLtcy31+8+M1fAkKSoN6ogkdaPowyWjNCzkJm5D A==; IronPort-SDR: jw2Ig6TMLLVYYQdLtCgxvw6vYTBenROCCT/HhklIToRHyLtrlo1LxUTAd/xYRkcqj34rz69vgY JfRzBYCkuRpIetyYCivhBdBgi45THZZiCZwVm88b4LNoWy4nn7ThEd66dJ3JZIDihRiE65Zi36 xU0PbRcYvBEugvVM4QErUexp3PVqriAaanBNVn3iwX6OvjlQBC9EVG7P5LiS6bC1/vbgNZIpGw r7NWpAuqrR1miAEhY5GGAmKZg5eYaA0X2r7U6ms6XYClPsmBXhPWk+eDCMaxLUrhEo/+jKU0gN IWc= X-IronPort-AV: E=Sophos;i="5.67,251,1566835200"; d="scan'208";a="121261217" Received: from mail-co1nam05lp2056.outbound.protection.outlook.com (HELO NAM05-CO1-obe.outbound.protection.outlook.com) ([104.47.48.56]) by ob1.hgst.iphmx.com with ESMTP; 03 Oct 2019 13:07:20 +0800 ARC-Seal: i=1; a=rsa-sha256; s=arcselector9901; d=microsoft.com; cv=none; b=QGzqwyupKykztBQALJI/WxjLI1KfhW4maTPbHMVHNf98omh9reHi0qxQCzHWr0kHWefE0jrOhPJhHwcZaWbN129NVg96+h0BoRucnR4rCOmwwm0baqvROiIKbNSpzZ16pHwGwCM+UkJ9hQJJhIHiEvoe11QRYZ4kOZCTkCRiRKFRmQaezXCizANcJSOdU5tXMzVNO2kHGMLVwB8z1bwMP7kig8OiRsYq/3IYjMmwv+aiCaokUCmEpPwZfjTyv1oAVhw7XaMecpx+mKkQ16yPd61es/sc4rLtfrwokui1fiaMT0OeAjmWblBCNTP9uMMVrwZdJUHk7lOmR/GLAAd0iw== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=microsoft.com; s=arcselector9901; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-SenderADCheck; bh=TTOdV5U+GSScwbSxEuGviPZTxeUnv45lhfabiSpKBZ0=; b=Cgw3fWYH9JjmYhjn9MH9s5PhLeLxf8o6SGHChgEZ1hYVlm+uXPBU1rATLOqZjmzcsbSTCp8wHnERW0+JErfaz6i/g9yipg3l72HRSlGzgzWGzPHUjBZYD/hP1UgLdL6H2HQUBz+bBzXdfTtmk8/q32TRIYEheUEbrC2x+BdUoKHhMKtkHUp5xJdEwQNGgnNNQih6BZ//UtZ4Kw3SvTzkK0QVSWOQUkY1RiLWRQJyjslNAVmnLLYiJSDj0iZb4vfaJ3YzEwJU8cVfmSnxy5oSf+pI+fqfqYYiKpPpL7bWdMQyVXcb9k1wp8GDywZ1BNEnWAPs9Tc7rwo9wUM5RnY9Mw== ARC-Authentication-Results: i=1; mx.microsoft.com 1; spf=pass smtp.mailfrom=wdc.com; dmarc=pass action=none header.from=wdc.com; dkim=pass header.d=wdc.com; arc=none DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=sharedspace.onmicrosoft.com; s=selector2-sharedspace-onmicrosoft-com; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-SenderADCheck; bh=TTOdV5U+GSScwbSxEuGviPZTxeUnv45lhfabiSpKBZ0=; b=rIJKiKtoEF35pc59Y36gitn7ZYIe9TaWV6ZOfONSiY8z3H/GYOoHOCuhj1diURZfcrRw5GTTwIMmoomkRhHmadGkmippAMimFpLuDfGoy2ACIJbRgei9y3EncGozEQqp1t1FyfUEvrDW4+LAys7qCF4mErPs2gVmdEIz21hqO98= Received: from MN2PR04MB6061.namprd04.prod.outlook.com (20.178.246.15) by MN2PR04MB6272.namprd04.prod.outlook.com (20.178.248.27) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.2305.17; Thu, 3 Oct 2019 05:07:17 +0000 Received: from MN2PR04MB6061.namprd04.prod.outlook.com ([fe80::1454:87a:13b0:d3a]) by MN2PR04MB6061.namprd04.prod.outlook.com ([fe80::1454:87a:13b0:d3a%7]) with mapi id 15.20.2305.023; Thu, 3 Oct 2019 05:07:17 +0000 From: Anup Patel To: Palmer Dabbelt , Paul Walmsley , Paolo Bonzini , Radim K Subject: [PATCH v8 06/19] RISC-V: KVM: Implement KVM_GET_ONE_REG/KVM_SET_ONE_REG ioctls Thread-Topic: [PATCH v8 06/19] RISC-V: KVM: Implement KVM_GET_ONE_REG/KVM_SET_ONE_REG ioctls Thread-Index: AQHVeahtzjTmXVA+FUCp6W5fdffk2Q== Date: Thu, 3 Oct 2019 05:07:17 +0000 Message-ID: <20191003050558.9031-7-anup.patel@wdc.com> References: <20191003050558.9031-1-anup.patel@wdc.com> In-Reply-To: <20191003050558.9031-1-anup.patel@wdc.com> Accept-Language: en-US Content-Language: en-US X-MS-Has-Attach: X-MS-TNEF-Correlator: x-clientproxiedby: BMXPR01CA0030.INDPRD01.PROD.OUTLOOK.COM (2603:1096:b00:c::16) To MN2PR04MB6061.namprd04.prod.outlook.com (2603:10b6:208:d8::15) authentication-results: spf=none (sender IP is ) smtp.mailfrom=Anup.Patel@wdc.com; x-ms-exchange-messagesentrepresentingtype: 1 x-mailer: git-send-email 2.17.1 x-originating-ip: [111.235.74.37] x-ms-publictraffictype: Email x-ms-office365-filtering-correlation-id: 1162b02d-5812-4a02-b627-08d747bf8fc4 x-ms-office365-filtering-ht: Tenant x-ms-traffictypediagnostic: MN2PR04MB6272: x-ms-exchange-transport-forked: True x-microsoft-antispam-prvs: wdcipoutbound: EOP-TRUE x-ms-oob-tlc-oobclassifiers: OLM:5236; x-forefront-prvs: 01792087B6 x-forefront-antispam-report: SFV:NSPM; SFS:(10019020)(4636009)(136003)(376002)(346002)(366004)(396003)(39860400002)(189003)(199004)(6512007)(6486002)(81166006)(81156014)(8936002)(6116002)(3846002)(8676002)(50226002)(2906002)(110136005)(66066001)(6436002)(316002)(66476007)(66556008)(7416002)(66446008)(36756003)(1076003)(5660300002)(54906003)(7736002)(305945005)(76176011)(30864003)(25786009)(52116002)(256004)(14444005)(71190400001)(86362001)(99286004)(71200400001)(2616005)(446003)(14454004)(476003)(102836004)(186003)(26005)(11346002)(44832011)(6506007)(486006)(478600001)(4326008)(66946007)(386003)(64756008); DIR:OUT; SFP:1102; SCL:1; SRVR:MN2PR04MB6272; H:MN2PR04MB6061.namprd04.prod.outlook.com; FPR:; SPF:None; LANG:en; PTR:InfoNoRecords; MX:1; A:1; x-ms-exchange-senderadcheck: 1 x-microsoft-antispam: BCL:0; x-microsoft-antispam-message-info: bnTRVn6gXSueUYF6zAbt5enV5hHuDbAk2ALeip3RE54g0bPdTFIoOGJwG/0blqNDGeCTFqF8cAoUH/R/wWmN/8KMwKARRKKqO8Cgi1tA2uXUlocRnv/eHb8v6KFshg621u+kv9tU+OqpqBeXYL9VJqtae2y4Z2rBbGg12oBg+ucCgVX9m1YYRbimLvVzoFp6vf+nbubr+BRpcZX+2JKJAbCCxmgm/I+0OK3ZxTGGp0Y7F2sGIPCiSqX+dH8i1a+fGVoAWn3nOVAyfy3EOMLo2VGnCCMIgdtbvZHes2njE7j/CANi7OYmL1WB7PF7np71A/xvBxBdk7/Ubf8woPhQuxXtWV7MPH3XPqtWMRnWV3ZdMREzShcKxr4s3Q4yzsKPiOB9SDu1G6ydexH+Q8oJZxanJvXw8NTuWll6innB6NI= MIME-Version: 1.0 X-OriginatorOrg: wdc.com X-MS-Exchange-CrossTenant-Network-Message-Id: 1162b02d-5812-4a02-b627-08d747bf8fc4 X-MS-Exchange-CrossTenant-originalarrivaltime: 03 Oct 2019 05:07:17.6211 (UTC) X-MS-Exchange-CrossTenant-fromentityheader: Hosted X-MS-Exchange-CrossTenant-id: b61c8803-16f3-4c35-9b17-6f65f441df86 X-MS-Exchange-CrossTenant-mailboxtype: HOSTED X-MS-Exchange-CrossTenant-userprincipalname: 7T6/6LGR3N26oDe2fhiAT1J5keMnK0yj4KFOzzaGCJtXpPlMOEXitVZ4Peae2679/Ow7v0UjBGH/QWDKGCjnmA== X-MS-Exchange-Transport-CrossTenantHeadersStamped: MN2PR04MB6272 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20191002_220734_243206_EAE11736 X-CRM114-Status: GOOD ( 16.66 ) X-Spam-Score: -2.5 (--) X-Spam-Report: SpamAssassin version 3.4.2 on bombadil.infradead.org summary: Content analysis details: (-2.5 points) pts rule name description ---- ---------------------- -------------------------------------------------- -0.0 SPF_PASS SPF: sender matches SPF record 0.0 SPF_HELO_NONE SPF: HELO does not publish an SPF Record -2.3 RCVD_IN_DNSWL_MED RBL: Sender listed at https://www.dnswl.org/, medium trust [216.71.154.45 listed in list.dnswl.org] -0.1 DKIM_VALID_EF Message has a valid DKIM or DK signature from envelope-from domain 0.1 DKIM_SIGNED Message has a DKIM or DK signature, not necessarily valid -0.1 DKIM_VALID_AU Message has a valid DKIM or DK signature from author's domain -0.1 DKIM_VALID Message has at least one valid DKIM or DK signature X-BeenThere: linux-riscv@lists.infradead.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Damien Le Moal , Anup Patel , "kvm@vger.kernel.org" , Anup Patel , Daniel Lezcano , "linux-kernel@vger.kernel.org" , Christoph Hellwig , Atish Patra , Alexander Graf , Alistair Francis , Thomas Gleixner , "linux-riscv@lists.infradead.org" Sender: "linux-riscv" Errors-To: linux-riscv-bounces+patchwork-linux-riscv=patchwork.kernel.org@lists.infradead.org For KVM RISC-V, we use KVM_GET_ONE_REG/KVM_SET_ONE_REG ioctls to access VCPU config and registers from user-space. We have three types of VCPU registers: 1. CONFIG - these are VCPU config and capabilities 2. CORE - these are VCPU general purpose registers 3. CSR - these are VCPU control and status registers The CONFIG registers available to user-space are ISA and TIMEBASE. Out of these, TIMEBASE is a read-only register which inform user-space about VCPU timer base frequency. The ISA register is a read and write register where user-space can only write the desired VCPU ISA capabilities before running the VCPU. The CORE registers available to user-space are PC, RA, SP, GP, TP, A0-A7, T0-T6, S0-S11 and MODE. Most of these are RISC-V general registers except PC and MODE. The PC register represents program counter whereas the MODE register represent VCPU privilege mode (i.e. S/U-mode). The CSRs available to user-space are SSTATUS, SIE, STVEC, SSCRATCH, SEPC, SCAUSE, STVAL, SIP, and SATP. All of these are read/write registers. In future, more VCPU register types will be added (such as FP) for the KVM_GET_ONE_REG/KVM_SET_ONE_REG ioctls. Signed-off-by: Anup Patel Acked-by: Paolo Bonzini Reviewed-by: Paolo Bonzini --- arch/riscv/include/uapi/asm/kvm.h | 53 ++++++- arch/riscv/kvm/vcpu.c | 239 +++++++++++++++++++++++++++++- 2 files changed, 289 insertions(+), 3 deletions(-) diff --git a/arch/riscv/include/uapi/asm/kvm.h b/arch/riscv/include/uapi/asm/kvm.h index 6dbc056d58ba..997b85f6fded 100644 --- a/arch/riscv/include/uapi/asm/kvm.h +++ b/arch/riscv/include/uapi/asm/kvm.h @@ -41,10 +41,61 @@ struct kvm_guest_debug_arch { struct kvm_sync_regs { }; -/* dummy definition */ +/* for KVM_GET_SREGS and KVM_SET_SREGS */ struct kvm_sregs { }; +/* CONFIG registers for KVM_GET_ONE_REG and KVM_SET_ONE_REG */ +struct kvm_riscv_config { + unsigned long isa; + unsigned long tbfreq; +}; + +/* CORE registers for KVM_GET_ONE_REG and KVM_SET_ONE_REG */ +struct kvm_riscv_core { + struct user_regs_struct regs; + unsigned long mode; +}; + +/* Possible privilege modes for kvm_riscv_core */ +#define KVM_RISCV_MODE_S 1 +#define KVM_RISCV_MODE_U 0 + +/* CSR registers for KVM_GET_ONE_REG and KVM_SET_ONE_REG */ +struct kvm_riscv_csr { + unsigned long sstatus; + unsigned long sie; + unsigned long stvec; + unsigned long sscratch; + unsigned long sepc; + unsigned long scause; + unsigned long stval; + unsigned long sip; + unsigned long satp; +}; + +#define KVM_REG_SIZE(id) \ + (1U << (((id) & KVM_REG_SIZE_MASK) >> KVM_REG_SIZE_SHIFT)) + +/* If you need to interpret the index values, here is the key: */ +#define KVM_REG_RISCV_TYPE_MASK 0x00000000FF000000 +#define KVM_REG_RISCV_TYPE_SHIFT 24 + +/* Config registers are mapped as type 1 */ +#define KVM_REG_RISCV_CONFIG (0x01 << KVM_REG_RISCV_TYPE_SHIFT) +#define KVM_REG_RISCV_CONFIG_REG(name) \ + (offsetof(struct kvm_riscv_config, name) / sizeof(unsigned long)) + +/* Core registers are mapped as type 2 */ +#define KVM_REG_RISCV_CORE (0x02 << KVM_REG_RISCV_TYPE_SHIFT) +#define KVM_REG_RISCV_CORE_REG(name) \ + (offsetof(struct kvm_riscv_core, name) / sizeof(unsigned long)) + +/* Control and status registers are mapped as type 3 */ +#define KVM_REG_RISCV_CSR (0x03 << KVM_REG_RISCV_TYPE_SHIFT) +#define KVM_REG_RISCV_CSR_REG(name) \ + (offsetof(struct kvm_riscv_csr, name) / sizeof(unsigned long)) + #endif #endif /* __LINUX_KVM_RISCV_H */ diff --git a/arch/riscv/kvm/vcpu.c b/arch/riscv/kvm/vcpu.c index 3223f723f79e..c9faca14f8cd 100644 --- a/arch/riscv/kvm/vcpu.c +++ b/arch/riscv/kvm/vcpu.c @@ -165,6 +165,219 @@ vm_fault_t kvm_arch_vcpu_fault(struct kvm_vcpu *vcpu, struct vm_fault *vmf) return VM_FAULT_SIGBUS; } +static int kvm_riscv_vcpu_get_reg_config(struct kvm_vcpu *vcpu, + const struct kvm_one_reg *reg) +{ + unsigned long __user *uaddr = + (unsigned long __user *)(unsigned long)reg->addr; + unsigned long reg_num = reg->id & ~(KVM_REG_ARCH_MASK | + KVM_REG_SIZE_MASK | + KVM_REG_RISCV_CONFIG); + unsigned long reg_val; + + if (KVM_REG_SIZE(reg->id) != sizeof(unsigned long)) + return -EINVAL; + + switch (reg_num) { + case KVM_REG_RISCV_CONFIG_REG(isa): + reg_val = vcpu->arch.isa; + break; + case KVM_REG_RISCV_CONFIG_REG(tbfreq): + reg_val = riscv_timebase; + break; + default: + return -EINVAL; + }; + + if (copy_to_user(uaddr, ®_val, KVM_REG_SIZE(reg->id))) + return -EFAULT; + + return 0; +} + +static int kvm_riscv_vcpu_set_reg_config(struct kvm_vcpu *vcpu, + const struct kvm_one_reg *reg) +{ + unsigned long __user *uaddr = + (unsigned long __user *)(unsigned long)reg->addr; + unsigned long reg_num = reg->id & ~(KVM_REG_ARCH_MASK | + KVM_REG_SIZE_MASK | + KVM_REG_RISCV_CONFIG); + unsigned long reg_val; + + if (KVM_REG_SIZE(reg->id) != sizeof(unsigned long)) + return -EINVAL; + + if (copy_from_user(®_val, uaddr, KVM_REG_SIZE(reg->id))) + return -EFAULT; + + switch (reg_num) { + case KVM_REG_RISCV_CONFIG_REG(isa): + if (!vcpu->arch.ran_atleast_once) { + vcpu->arch.isa = reg_val; + vcpu->arch.isa &= riscv_isa_extension_base(NULL); + vcpu->arch.isa &= KVM_RISCV_ISA_ALLOWED; + } else { + return -ENOTSUPP; + } + break; + case KVM_REG_RISCV_CONFIG_REG(tbfreq): + return -ENOTSUPP; + default: + return -EINVAL; + }; + + return 0; +} + +static int kvm_riscv_vcpu_get_reg_core(struct kvm_vcpu *vcpu, + const struct kvm_one_reg *reg) +{ + struct kvm_cpu_context *cntx = &vcpu->arch.guest_context; + unsigned long __user *uaddr = + (unsigned long __user *)(unsigned long)reg->addr; + unsigned long reg_num = reg->id & ~(KVM_REG_ARCH_MASK | + KVM_REG_SIZE_MASK | + KVM_REG_RISCV_CORE); + unsigned long reg_val; + + if (KVM_REG_SIZE(reg->id) != sizeof(unsigned long)) + return -EINVAL; + if (reg_num >= sizeof(struct kvm_riscv_core) / sizeof(unsigned long)) + return -EINVAL; + + if (reg_num == KVM_REG_RISCV_CORE_REG(regs.pc)) + reg_val = cntx->sepc; + else if (KVM_REG_RISCV_CORE_REG(regs.pc) < reg_num && + reg_num <= KVM_REG_RISCV_CORE_REG(regs.t6)) + reg_val = ((unsigned long *)cntx)[reg_num]; + else if (reg_num == KVM_REG_RISCV_CORE_REG(mode)) + reg_val = (cntx->sstatus & SR_SPP) ? + KVM_RISCV_MODE_S : KVM_RISCV_MODE_U; + else + return -EINVAL; + + if (copy_to_user(uaddr, ®_val, KVM_REG_SIZE(reg->id))) + return -EFAULT; + + return 0; +} + +static int kvm_riscv_vcpu_set_reg_core(struct kvm_vcpu *vcpu, + const struct kvm_one_reg *reg) +{ + struct kvm_cpu_context *cntx = &vcpu->arch.guest_context; + unsigned long __user *uaddr = + (unsigned long __user *)(unsigned long)reg->addr; + unsigned long reg_num = reg->id & ~(KVM_REG_ARCH_MASK | + KVM_REG_SIZE_MASK | + KVM_REG_RISCV_CORE); + unsigned long reg_val; + + if (KVM_REG_SIZE(reg->id) != sizeof(unsigned long)) + return -EINVAL; + if (reg_num >= sizeof(struct kvm_riscv_core) / sizeof(unsigned long)) + return -EINVAL; + + if (copy_from_user(®_val, uaddr, KVM_REG_SIZE(reg->id))) + return -EFAULT; + + if (reg_num == KVM_REG_RISCV_CORE_REG(regs.pc)) + cntx->sepc = reg_val; + else if (KVM_REG_RISCV_CORE_REG(regs.pc) < reg_num && + reg_num <= KVM_REG_RISCV_CORE_REG(regs.t6)) + ((unsigned long *)cntx)[reg_num] = reg_val; + else if (reg_num == KVM_REG_RISCV_CORE_REG(mode)) { + if (reg_val == KVM_RISCV_MODE_S) + cntx->sstatus |= SR_SPP; + else + cntx->sstatus &= ~SR_SPP; + } else + return -EINVAL; + + return 0; +} + +static int kvm_riscv_vcpu_get_reg_csr(struct kvm_vcpu *vcpu, + const struct kvm_one_reg *reg) +{ + struct kvm_vcpu_csr *csr = &vcpu->arch.guest_csr; + unsigned long __user *uaddr = + (unsigned long __user *)(unsigned long)reg->addr; + unsigned long reg_num = reg->id & ~(KVM_REG_ARCH_MASK | + KVM_REG_SIZE_MASK | + KVM_REG_RISCV_CSR); + unsigned long reg_val; + + if (KVM_REG_SIZE(reg->id) != sizeof(unsigned long)) + return -EINVAL; + if (reg_num >= sizeof(struct kvm_riscv_csr) / sizeof(unsigned long)) + return -EINVAL; + + if (reg_num == KVM_REG_RISCV_CSR_REG(sip)) + kvm_riscv_vcpu_flush_interrupts(vcpu); + + reg_val = ((unsigned long *)csr)[reg_num]; + + if (copy_to_user(uaddr, ®_val, KVM_REG_SIZE(reg->id))) + return -EFAULT; + + return 0; +} + +static int kvm_riscv_vcpu_set_reg_csr(struct kvm_vcpu *vcpu, + const struct kvm_one_reg *reg) +{ + struct kvm_vcpu_csr *csr = &vcpu->arch.guest_csr; + unsigned long __user *uaddr = + (unsigned long __user *)(unsigned long)reg->addr; + unsigned long reg_num = reg->id & ~(KVM_REG_ARCH_MASK | + KVM_REG_SIZE_MASK | + KVM_REG_RISCV_CSR); + unsigned long reg_val; + + if (KVM_REG_SIZE(reg->id) != sizeof(unsigned long)) + return -EINVAL; + if (reg_num >= sizeof(struct kvm_riscv_csr) / sizeof(unsigned long)) + return -EINVAL; + + if (copy_from_user(®_val, uaddr, KVM_REG_SIZE(reg->id))) + return -EFAULT; + + ((unsigned long *)csr)[reg_num] = reg_val; + + if (reg_num == KVM_REG_RISCV_CSR_REG(sip)) + WRITE_ONCE(vcpu->arch.irqs_pending_mask, 0); + + return 0; +} + +static int kvm_riscv_vcpu_set_reg(struct kvm_vcpu *vcpu, + const struct kvm_one_reg *reg) +{ + if ((reg->id & KVM_REG_RISCV_TYPE_MASK) == KVM_REG_RISCV_CONFIG) + return kvm_riscv_vcpu_set_reg_config(vcpu, reg); + else if ((reg->id & KVM_REG_RISCV_TYPE_MASK) == KVM_REG_RISCV_CORE) + return kvm_riscv_vcpu_set_reg_core(vcpu, reg); + else if ((reg->id & KVM_REG_RISCV_TYPE_MASK) == KVM_REG_RISCV_CSR) + return kvm_riscv_vcpu_set_reg_csr(vcpu, reg); + + return -EINVAL; +} + +static int kvm_riscv_vcpu_get_reg(struct kvm_vcpu *vcpu, + const struct kvm_one_reg *reg) +{ + if ((reg->id & KVM_REG_RISCV_TYPE_MASK) == KVM_REG_RISCV_CONFIG) + return kvm_riscv_vcpu_get_reg_config(vcpu, reg); + else if ((reg->id & KVM_REG_RISCV_TYPE_MASK) == KVM_REG_RISCV_CORE) + return kvm_riscv_vcpu_get_reg_core(vcpu, reg); + else if ((reg->id & KVM_REG_RISCV_TYPE_MASK) == KVM_REG_RISCV_CSR) + return kvm_riscv_vcpu_get_reg_csr(vcpu, reg); + + return -EINVAL; +} + long kvm_arch_vcpu_async_ioctl(struct file *filp, unsigned int ioctl, unsigned long arg) { @@ -189,8 +402,30 @@ long kvm_arch_vcpu_async_ioctl(struct file *filp, long kvm_arch_vcpu_ioctl(struct file *filp, unsigned int ioctl, unsigned long arg) { - /* TODO: */ - return -EINVAL; + struct kvm_vcpu *vcpu = filp->private_data; + void __user *argp = (void __user *)arg; + long r = -EINVAL; + + switch (ioctl) { + case KVM_SET_ONE_REG: + case KVM_GET_ONE_REG: { + struct kvm_one_reg reg; + + r = -EFAULT; + if (copy_from_user(®, argp, sizeof(reg))) + break; + + if (ioctl == KVM_SET_ONE_REG) + r = kvm_riscv_vcpu_set_reg(vcpu, ®); + else + r = kvm_riscv_vcpu_get_reg(vcpu, ®); + break; + } + default: + break; + } + + return r; } int kvm_arch_vcpu_ioctl_get_sregs(struct kvm_vcpu *vcpu, From patchwork Thu Oct 3 05:07:24 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Anup Patel X-Patchwork-Id: 11172113 Return-Path: Received: from mail.kernel.org (pdx-korg-mail-1.web.codeaurora.org [172.30.200.123]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id 6E06E195A for ; Thu, 3 Oct 2019 05:07:47 +0000 (UTC) Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id 4804A222C9 for ; Thu, 3 Oct 2019 05:07:47 +0000 (UTC) Authentication-Results: mail.kernel.org; dkim=pass (2048-bit key) header.d=lists.infradead.org header.i=@lists.infradead.org header.b="FqYJAOea"; dkim=fail reason="signature verification failed" (2048-bit key) header.d=wdc.com header.i=@wdc.com header.b="SXSFKc1F"; dkim=fail reason="signature verification failed" (1024-bit key) header.d=sharedspace.onmicrosoft.com header.i=@sharedspace.onmicrosoft.com header.b="k+RfI2M1" DMARC-Filter: OpenDMARC Filter v1.3.2 mail.kernel.org 4804A222C9 Authentication-Results: mail.kernel.org; dmarc=fail (p=none dis=none) header.from=wdc.com Authentication-Results: mail.kernel.org; spf=none smtp.mailfrom=linux-riscv-bounces+patchwork-linux-riscv=patchwork.kernel.org@lists.infradead.org DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=bombadil.20170209; h=Sender: Content-Transfer-Encoding:Content-Type:Cc:List-Subscribe:List-Help:List-Post: List-Archive:List-Unsubscribe:List-Id:MIME-Version:In-Reply-To:References: Message-ID:Date:Subject:To:From:Reply-To:Content-ID:Content-Description: Resent-Date:Resent-From:Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID: List-Owner; bh=+PMUe9NzY937v9hMsOZHA/aJjAsMhFvwNtZX3NPmO1o=; b=FqYJAOeap8kYg0 0QJckHeWAfVq6NFkCrzp9TE3m4jzt/Pg7sNSEtwWXMeQ0PqEOy0FHNNkUDV4S/OZf42ZKNJLOSywc BzXK6StBu+vH/ClnIOuXllW6Ml0IjJjuiOZ9Gfm9amg88f1D18nqFVTq7nS5bX6HKIq3kbeuEZeW2 mSOOGv3nAW9/K/TmEXfPjayVO29tWT9YKj6imU6324CZUP2p4zbEVpSOlHxisrLzkxvDSjWUrP5rx zJMGcSFv7pbOdtx4AC27Cd6+cfjd1Q/vasU0nrVhCc9bqlezUIr7qLG/UfR1Sj6bhjmHsta0D4T8C QoqBjmhr/lbNdEczI6xg==; Received: from localhost ([127.0.0.1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.92.2 #3 (Red Hat Linux)) id 1iFtL0-0003fK-5p; Thu, 03 Oct 2019 05:07:38 +0000 Received: from esa2.hgst.iphmx.com ([68.232.143.124]) by bombadil.infradead.org with esmtps (Exim 4.92.2 #3 (Red Hat Linux)) id 1iFtKw-0003cn-EK for linux-riscv@lists.infradead.org; Thu, 03 Oct 2019 05:07:36 +0000 DKIM-Signature: v=1; a=rsa-sha256; c=simple/simple; d=wdc.com; i=@wdc.com; q=dns/txt; s=dkim.wdc.com; t=1570079277; x=1601615277; h=from:to:cc:subject:date:message-id:references: in-reply-to:content-transfer-encoding:mime-version; bh=5k3R3lBtRzaA/YpHow1pYfa9Y/snax9LFp52mhx9E3Q=; b=SXSFKc1FxFxOERGCZSYkGIMkiByK8Ligus4r3iRYRXpjFgrqXEWkW5CK AYy6ntjpmylt4gcEny4qMbyqQTjsyg5QZZ0LzyUQWhN8Ivda48qFJWP4Z whfY3V9dDMXbWvdPZi5UQ5LL4C4L2x+4GkOLUjTN0WK/35+f4H6r8lQNA cFJJcqvAPqEW/HO5AHDLpdLu2fuTopYQLD9lfxuCcgFRuPaPgAsDDdy/X Z41z83OWpmqE7vDYJWzuYuxiPP0wenm/PuDzX++TZ0gLwphGj6oBO09M3 IbVBwUU6cIEiflI95Lzt2a9AC6gMe/rlQBi8cJHYtSc9B5jrjbHTf9Q/n Q==; IronPort-SDR: ZXgNnmZloQ83bQMKPYvHPR8T0tnci3noAdpUQ1svoihgjmz6Jr+t0YBGw+Uee3be+rLKgM+NA9 nLqPWWLXOuIM6srhSe4VY7tQVFm8mFNej37f0J3pKFwTSfSP2Z8xdYZKLjdnllOrjiLBUw9mpE wIBz6Zgo55PljbTyWa7ODdrpNl1bi6saKrObJ3U4aKdQ9A+A9sN84H2tgJpMOng6yh7sYMMIV+ vhpEMKyIalC/jsPiMS1SFUUvEt8LXR53t13NZyZYMGv0GjVi0b1OS7zTH0wobXpqS7rEyIbCh8 oJU= X-IronPort-AV: E=Sophos;i="5.67,251,1566835200"; d="scan'208";a="220620873" Received: from mail-co1nam05lp2054.outbound.protection.outlook.com (HELO NAM05-CO1-obe.outbound.protection.outlook.com) ([104.47.48.54]) by ob1.hgst.iphmx.com with ESMTP; 03 Oct 2019 13:07:47 +0800 ARC-Seal: i=1; a=rsa-sha256; s=arcselector9901; d=microsoft.com; cv=none; b=OmneHoh7L5PJfWvWWkbOR7EqGJ0ArtfKzfKj+PJNDAuA8u46vi7b6Truf1TvK2Whmhb0dkrEkeDI69uGuY/Rs+6W4hq12gDeirI2U0ZV7Tbh20x9IIcrH4+++h/GqKqolwKylvojOkOwcCUKGz7HhaGL+Rht+i0RYW3SobDqQxPhOFFl1OThOKXSAQ4aYBV6FgWTGHe31vEQH+9Z/roKxmJKzlt0hJ6oD7WQcU6DnjsQY7MtgibqzV5R4LGNnQpNH2n+Eih77VV49RrnYKWrSui8pmJ2yV3UWYH5EoFQiwSffohfBpp89jf5Cri4CPixYWw8ZZokEXYS0IXIi4Ytjg== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=microsoft.com; s=arcselector9901; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-SenderADCheck; bh=o70Mm2OTkDFO+QMXWQ0QXSv7a+GkAj0XGMfUeIbTFI4=; b=MwzyiJlW3+DR5ts29nQiDTF/cHFKt5CDXxWdfOl/E8rzH7/WLZ6JxVTAutBttF/+IfELSabJ4XKIBvyhVBMD/zAY+Wx+INuWw2LK4v+ckPZVtsjCJa273PdCq4Ix6bvdHkIujGCh4yj4wLgjkEs9rdt9wy3KrtLrbm15LEb5/WUtfXisWBVOq+E3ZJsERylM4JtzlwquORQdijliE0JUTK/3idfIkSs2aGsMLuNIJ2o2li7SESm4GIaxTyDpjYa/ewEAXzHzC/ROA5PTMBstShsk5wK50CBzn1S0Meiy++SQNDsBY+pmLaUINA39dCIuatzJv2UpbSCK8PIu+3vLdw== ARC-Authentication-Results: i=1; mx.microsoft.com 1; spf=pass smtp.mailfrom=wdc.com; dmarc=pass action=none header.from=wdc.com; dkim=pass header.d=wdc.com; arc=none DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=sharedspace.onmicrosoft.com; s=selector2-sharedspace-onmicrosoft-com; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-SenderADCheck; bh=o70Mm2OTkDFO+QMXWQ0QXSv7a+GkAj0XGMfUeIbTFI4=; b=k+RfI2M1NFy8uQfz0JdIiLSKvmGpZk5XA9MNAOHM8XDH5aRQ3RMxSCTVwk5YMEvG0mJaueTCTDfGME8arEDUg/W3BTBkKlFVM2aJrZJ9kWqmp/dCz6hn/c6+hYLjy2bibPrCFo/Ns6MgEB+ARA9LzFqi3Adq+9YiGFUgpCfekGM= Received: from MN2PR04MB6061.namprd04.prod.outlook.com (20.178.246.15) by MN2PR04MB6272.namprd04.prod.outlook.com (20.178.248.27) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.2305.17; Thu, 3 Oct 2019 05:07:24 +0000 Received: from MN2PR04MB6061.namprd04.prod.outlook.com ([fe80::1454:87a:13b0:d3a]) by MN2PR04MB6061.namprd04.prod.outlook.com ([fe80::1454:87a:13b0:d3a%7]) with mapi id 15.20.2305.023; Thu, 3 Oct 2019 05:07:24 +0000 From: Anup Patel To: Palmer Dabbelt , Paul Walmsley , Paolo Bonzini , Radim K Subject: [PATCH v8 07/19] RISC-V: KVM: Implement VCPU world-switch Thread-Topic: [PATCH v8 07/19] RISC-V: KVM: Implement VCPU world-switch Thread-Index: AQHVeahxksyFojjmTk+gS6kpnBx3Mw== Date: Thu, 3 Oct 2019 05:07:24 +0000 Message-ID: <20191003050558.9031-8-anup.patel@wdc.com> References: <20191003050558.9031-1-anup.patel@wdc.com> In-Reply-To: <20191003050558.9031-1-anup.patel@wdc.com> Accept-Language: en-US Content-Language: en-US X-MS-Has-Attach: X-MS-TNEF-Correlator: x-clientproxiedby: BMXPR01CA0030.INDPRD01.PROD.OUTLOOK.COM (2603:1096:b00:c::16) To MN2PR04MB6061.namprd04.prod.outlook.com (2603:10b6:208:d8::15) authentication-results: spf=none (sender IP is ) smtp.mailfrom=Anup.Patel@wdc.com; x-ms-exchange-messagesentrepresentingtype: 1 x-mailer: git-send-email 2.17.1 x-originating-ip: [111.235.74.37] x-ms-publictraffictype: Email x-ms-office365-filtering-correlation-id: 65f85462-374a-4cfb-793c-08d747bf93ed x-ms-office365-filtering-ht: Tenant x-ms-traffictypediagnostic: MN2PR04MB6272: x-ms-exchange-transport-forked: True x-microsoft-antispam-prvs: wdcipoutbound: EOP-TRUE x-ms-oob-tlc-oobclassifiers: OLM:7219; x-forefront-prvs: 01792087B6 x-forefront-antispam-report: SFV:NSPM; SFS:(10019020)(4636009)(136003)(376002)(346002)(366004)(396003)(39860400002)(189003)(199004)(6512007)(6486002)(81166006)(81156014)(8936002)(6116002)(3846002)(8676002)(50226002)(2906002)(110136005)(66066001)(6436002)(316002)(66476007)(66556008)(7416002)(66446008)(36756003)(1076003)(5660300002)(54906003)(7736002)(305945005)(76176011)(30864003)(25786009)(52116002)(256004)(14444005)(71190400001)(86362001)(99286004)(71200400001)(2616005)(446003)(14454004)(476003)(102836004)(186003)(26005)(11346002)(44832011)(6506007)(486006)(478600001)(4326008)(66946007)(386003)(64756008); DIR:OUT; SFP:1102; SCL:1; SRVR:MN2PR04MB6272; H:MN2PR04MB6061.namprd04.prod.outlook.com; FPR:; SPF:None; LANG:en; PTR:InfoNoRecords; MX:1; A:1; x-ms-exchange-senderadcheck: 1 x-microsoft-antispam: BCL:0; x-microsoft-antispam-message-info: tTVFy46JhD+YL3pgTSuEevCiaJEd77pMiV7uFfWThqy972lN1djC7I/xg6FoIzaNVN5z9D0uyyCQDGPvlzFGRHdcJ/CPTFKmqGuOay1i1HqUhbotQOkdbyKjhcHj9nMIjjMF9tXjuf41RiBPTe7JIpCQmKeJ63BvRgPX4mLm8CcVgNE/8EEqR6xU91GrDbVXSP/1r9ClnlSmaGSlad3y9JlzxkBQLYduPocFkKHFxhiiXLvldKoQbY4PcXyyx+xdV4rn9aoFI6lZA4/z8xSlZEETxWgoV9Q2M4c9064tjYcsZW6iBAqwrcq5AwwEB6PnR7WNDVA/A9Or6DHHqgGZMoLJ9utAKyFW8JskOehhBi0SZ4qHq6s/yUL7GD8i8SYGVhlfRaOTkO2/VyiePu8z9zROas3vrMWg5XkaS9bHovk= MIME-Version: 1.0 X-OriginatorOrg: wdc.com X-MS-Exchange-CrossTenant-Network-Message-Id: 65f85462-374a-4cfb-793c-08d747bf93ed X-MS-Exchange-CrossTenant-originalarrivaltime: 03 Oct 2019 05:07:24.5762 (UTC) X-MS-Exchange-CrossTenant-fromentityheader: Hosted X-MS-Exchange-CrossTenant-id: b61c8803-16f3-4c35-9b17-6f65f441df86 X-MS-Exchange-CrossTenant-mailboxtype: HOSTED X-MS-Exchange-CrossTenant-userprincipalname: kmyg3kWpK7+b/o5yf0JwCNkkcTEBbGEkp389LoiS7LlLx2CBlbJrrn+FYb0LMEvwfaURHZQ+QggiCign2TxCGw== X-MS-Exchange-Transport-CrossTenantHeadersStamped: MN2PR04MB6272 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20191002_220734_567987_7239CB63 X-CRM114-Status: GOOD ( 14.39 ) X-Spam-Score: -2.5 (--) X-Spam-Report: SpamAssassin version 3.4.2 on bombadil.infradead.org summary: Content analysis details: (-2.5 points) pts rule name description ---- ---------------------- -------------------------------------------------- -2.3 RCVD_IN_DNSWL_MED RBL: Sender listed at https://www.dnswl.org/, medium trust [68.232.143.124 listed in list.dnswl.org] -0.0 SPF_PASS SPF: sender matches SPF record 0.0 SPF_HELO_NONE SPF: HELO does not publish an SPF Record -0.1 DKIM_VALID_EF Message has a valid DKIM or DK signature from envelope-from domain 0.1 DKIM_SIGNED Message has a DKIM or DK signature, not necessarily valid -0.1 DKIM_VALID_AU Message has a valid DKIM or DK signature from author's domain -0.1 DKIM_VALID Message has at least one valid DKIM or DK signature X-BeenThere: linux-riscv@lists.infradead.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Damien Le Moal , Anup Patel , "kvm@vger.kernel.org" , Anup Patel , Daniel Lezcano , "linux-kernel@vger.kernel.org" , Christoph Hellwig , Atish Patra , Alexander Graf , Alistair Francis , Thomas Gleixner , "linux-riscv@lists.infradead.org" Sender: "linux-riscv" Errors-To: linux-riscv-bounces+patchwork-linux-riscv=patchwork.kernel.org@lists.infradead.org This patch implements the VCPU world-switch for KVM RISC-V. The KVM RISC-V world-switch (i.e. __kvm_riscv_switch_to()) mostly switches general purpose registers, SSTATUS, STVEC, SSCRATCH and HSTATUS CSRs. Other CSRs are switched via vcpu_load() and vcpu_put() interface in kvm_arch_vcpu_load() and kvm_arch_vcpu_put() functions respectively. Signed-off-by: Anup Patel Acked-by: Paolo Bonzini Reviewed-by: Paolo Bonzini Reviewed-by: Alexander Graf --- arch/riscv/include/asm/kvm_host.h | 9 +- arch/riscv/kernel/asm-offsets.c | 76 ++++++++++++ arch/riscv/kvm/Makefile | 2 +- arch/riscv/kvm/vcpu.c | 32 ++++- arch/riscv/kvm/vcpu_switch.S | 194 ++++++++++++++++++++++++++++++ 5 files changed, 309 insertions(+), 4 deletions(-) create mode 100644 arch/riscv/kvm/vcpu_switch.S diff --git a/arch/riscv/include/asm/kvm_host.h b/arch/riscv/include/asm/kvm_host.h index d801216da6d0..18f1097f1d8d 100644 --- a/arch/riscv/include/asm/kvm_host.h +++ b/arch/riscv/include/asm/kvm_host.h @@ -110,6 +110,13 @@ struct kvm_vcpu_arch { /* ISA feature bits (similar to MISA) */ unsigned long isa; + /* SSCRATCH and STVEC of Host */ + unsigned long host_sscratch; + unsigned long host_stvec; + + /* CPU context of Host */ + struct kvm_cpu_context host_context; + /* CPU context of Guest VCPU */ struct kvm_cpu_context guest_context; @@ -162,7 +169,7 @@ int kvm_riscv_vcpu_mmio_return(struct kvm_vcpu *vcpu, struct kvm_run *run); int kvm_riscv_vcpu_exit(struct kvm_vcpu *vcpu, struct kvm_run *run, unsigned long scause, unsigned long stval); -static inline void __kvm_riscv_switch_to(struct kvm_vcpu_arch *vcpu_arch) {} +void __kvm_riscv_switch_to(struct kvm_vcpu_arch *vcpu_arch); int kvm_riscv_vcpu_set_interrupt(struct kvm_vcpu *vcpu, unsigned int irq); int kvm_riscv_vcpu_unset_interrupt(struct kvm_vcpu *vcpu, unsigned int irq); diff --git a/arch/riscv/kernel/asm-offsets.c b/arch/riscv/kernel/asm-offsets.c index 9f5628c38ac9..711656710190 100644 --- a/arch/riscv/kernel/asm-offsets.c +++ b/arch/riscv/kernel/asm-offsets.c @@ -7,7 +7,9 @@ #define GENERATING_ASM_OFFSETS #include +#include #include +#include #include #include @@ -109,6 +111,80 @@ void asm_offsets(void) OFFSET(PT_SBADADDR, pt_regs, sbadaddr); OFFSET(PT_SCAUSE, pt_regs, scause); + OFFSET(KVM_ARCH_GUEST_ZERO, kvm_vcpu_arch, guest_context.zero); + OFFSET(KVM_ARCH_GUEST_RA, kvm_vcpu_arch, guest_context.ra); + OFFSET(KVM_ARCH_GUEST_SP, kvm_vcpu_arch, guest_context.sp); + OFFSET(KVM_ARCH_GUEST_GP, kvm_vcpu_arch, guest_context.gp); + OFFSET(KVM_ARCH_GUEST_TP, kvm_vcpu_arch, guest_context.tp); + OFFSET(KVM_ARCH_GUEST_T0, kvm_vcpu_arch, guest_context.t0); + OFFSET(KVM_ARCH_GUEST_T1, kvm_vcpu_arch, guest_context.t1); + OFFSET(KVM_ARCH_GUEST_T2, kvm_vcpu_arch, guest_context.t2); + OFFSET(KVM_ARCH_GUEST_S0, kvm_vcpu_arch, guest_context.s0); + OFFSET(KVM_ARCH_GUEST_S1, kvm_vcpu_arch, guest_context.s1); + OFFSET(KVM_ARCH_GUEST_A0, kvm_vcpu_arch, guest_context.a0); + OFFSET(KVM_ARCH_GUEST_A1, kvm_vcpu_arch, guest_context.a1); + OFFSET(KVM_ARCH_GUEST_A2, kvm_vcpu_arch, guest_context.a2); + OFFSET(KVM_ARCH_GUEST_A3, kvm_vcpu_arch, guest_context.a3); + OFFSET(KVM_ARCH_GUEST_A4, kvm_vcpu_arch, guest_context.a4); + OFFSET(KVM_ARCH_GUEST_A5, kvm_vcpu_arch, guest_context.a5); + OFFSET(KVM_ARCH_GUEST_A6, kvm_vcpu_arch, guest_context.a6); + OFFSET(KVM_ARCH_GUEST_A7, kvm_vcpu_arch, guest_context.a7); + OFFSET(KVM_ARCH_GUEST_S2, kvm_vcpu_arch, guest_context.s2); + OFFSET(KVM_ARCH_GUEST_S3, kvm_vcpu_arch, guest_context.s3); + OFFSET(KVM_ARCH_GUEST_S4, kvm_vcpu_arch, guest_context.s4); + OFFSET(KVM_ARCH_GUEST_S5, kvm_vcpu_arch, guest_context.s5); + OFFSET(KVM_ARCH_GUEST_S6, kvm_vcpu_arch, guest_context.s6); + OFFSET(KVM_ARCH_GUEST_S7, kvm_vcpu_arch, guest_context.s7); + OFFSET(KVM_ARCH_GUEST_S8, kvm_vcpu_arch, guest_context.s8); + OFFSET(KVM_ARCH_GUEST_S9, kvm_vcpu_arch, guest_context.s9); + OFFSET(KVM_ARCH_GUEST_S10, kvm_vcpu_arch, guest_context.s10); + OFFSET(KVM_ARCH_GUEST_S11, kvm_vcpu_arch, guest_context.s11); + OFFSET(KVM_ARCH_GUEST_T3, kvm_vcpu_arch, guest_context.t3); + OFFSET(KVM_ARCH_GUEST_T4, kvm_vcpu_arch, guest_context.t4); + OFFSET(KVM_ARCH_GUEST_T5, kvm_vcpu_arch, guest_context.t5); + OFFSET(KVM_ARCH_GUEST_T6, kvm_vcpu_arch, guest_context.t6); + OFFSET(KVM_ARCH_GUEST_SEPC, kvm_vcpu_arch, guest_context.sepc); + OFFSET(KVM_ARCH_GUEST_SSTATUS, kvm_vcpu_arch, guest_context.sstatus); + OFFSET(KVM_ARCH_GUEST_HSTATUS, kvm_vcpu_arch, guest_context.hstatus); + + OFFSET(KVM_ARCH_HOST_ZERO, kvm_vcpu_arch, host_context.zero); + OFFSET(KVM_ARCH_HOST_RA, kvm_vcpu_arch, host_context.ra); + OFFSET(KVM_ARCH_HOST_SP, kvm_vcpu_arch, host_context.sp); + OFFSET(KVM_ARCH_HOST_GP, kvm_vcpu_arch, host_context.gp); + OFFSET(KVM_ARCH_HOST_TP, kvm_vcpu_arch, host_context.tp); + OFFSET(KVM_ARCH_HOST_T0, kvm_vcpu_arch, host_context.t0); + OFFSET(KVM_ARCH_HOST_T1, kvm_vcpu_arch, host_context.t1); + OFFSET(KVM_ARCH_HOST_T2, kvm_vcpu_arch, host_context.t2); + OFFSET(KVM_ARCH_HOST_S0, kvm_vcpu_arch, host_context.s0); + OFFSET(KVM_ARCH_HOST_S1, kvm_vcpu_arch, host_context.s1); + OFFSET(KVM_ARCH_HOST_A0, kvm_vcpu_arch, host_context.a0); + OFFSET(KVM_ARCH_HOST_A1, kvm_vcpu_arch, host_context.a1); + OFFSET(KVM_ARCH_HOST_A2, kvm_vcpu_arch, host_context.a2); + OFFSET(KVM_ARCH_HOST_A3, kvm_vcpu_arch, host_context.a3); + OFFSET(KVM_ARCH_HOST_A4, kvm_vcpu_arch, host_context.a4); + OFFSET(KVM_ARCH_HOST_A5, kvm_vcpu_arch, host_context.a5); + OFFSET(KVM_ARCH_HOST_A6, kvm_vcpu_arch, host_context.a6); + OFFSET(KVM_ARCH_HOST_A7, kvm_vcpu_arch, host_context.a7); + OFFSET(KVM_ARCH_HOST_S2, kvm_vcpu_arch, host_context.s2); + OFFSET(KVM_ARCH_HOST_S3, kvm_vcpu_arch, host_context.s3); + OFFSET(KVM_ARCH_HOST_S4, kvm_vcpu_arch, host_context.s4); + OFFSET(KVM_ARCH_HOST_S5, kvm_vcpu_arch, host_context.s5); + OFFSET(KVM_ARCH_HOST_S6, kvm_vcpu_arch, host_context.s6); + OFFSET(KVM_ARCH_HOST_S7, kvm_vcpu_arch, host_context.s7); + OFFSET(KVM_ARCH_HOST_S8, kvm_vcpu_arch, host_context.s8); + OFFSET(KVM_ARCH_HOST_S9, kvm_vcpu_arch, host_context.s9); + OFFSET(KVM_ARCH_HOST_S10, kvm_vcpu_arch, host_context.s10); + OFFSET(KVM_ARCH_HOST_S11, kvm_vcpu_arch, host_context.s11); + OFFSET(KVM_ARCH_HOST_T3, kvm_vcpu_arch, host_context.t3); + OFFSET(KVM_ARCH_HOST_T4, kvm_vcpu_arch, host_context.t4); + OFFSET(KVM_ARCH_HOST_T5, kvm_vcpu_arch, host_context.t5); + OFFSET(KVM_ARCH_HOST_T6, kvm_vcpu_arch, host_context.t6); + OFFSET(KVM_ARCH_HOST_SEPC, kvm_vcpu_arch, host_context.sepc); + OFFSET(KVM_ARCH_HOST_SSTATUS, kvm_vcpu_arch, host_context.sstatus); + OFFSET(KVM_ARCH_HOST_HSTATUS, kvm_vcpu_arch, host_context.hstatus); + OFFSET(KVM_ARCH_HOST_SSCRATCH, kvm_vcpu_arch, host_sscratch); + OFFSET(KVM_ARCH_HOST_STVEC, kvm_vcpu_arch, host_stvec); + /* * THREAD_{F,X}* might be larger than a S-type offset can handle, but * these are used in performance-sensitive assembly so we can't resort diff --git a/arch/riscv/kvm/Makefile b/arch/riscv/kvm/Makefile index 37b5a59d4f4f..845579273727 100644 --- a/arch/riscv/kvm/Makefile +++ b/arch/riscv/kvm/Makefile @@ -8,6 +8,6 @@ ccflags-y := -Ivirt/kvm -Iarch/riscv/kvm kvm-objs := $(common-objs-y) -kvm-objs += main.o vm.o mmu.o vcpu.o vcpu_exit.o +kvm-objs += main.o vm.o mmu.o vcpu.o vcpu_exit.o vcpu_switch.o obj-$(CONFIG_KVM) += kvm.o diff --git a/arch/riscv/kvm/vcpu.c b/arch/riscv/kvm/vcpu.c index c9faca14f8cd..38a35367fb83 100644 --- a/arch/riscv/kvm/vcpu.c +++ b/arch/riscv/kvm/vcpu.c @@ -582,14 +582,42 @@ int kvm_arch_vcpu_ioctl_set_guest_debug(struct kvm_vcpu *vcpu, void kvm_arch_vcpu_load(struct kvm_vcpu *vcpu, int cpu) { - /* TODO: */ + struct kvm_vcpu_csr *csr = &vcpu->arch.guest_csr; + unsigned long *vsip = raw_cpu_ptr(vsip_shadow); + + csr_write(CSR_VSSTATUS, csr->vsstatus); + csr_write(CSR_VSIE, csr->vsie); + csr_write(CSR_VSTVEC, csr->vstvec); + csr_write(CSR_VSSCRATCH, csr->vsscratch); + csr_write(CSR_VSEPC, csr->vsepc); + csr_write(CSR_VSCAUSE, csr->vscause); + csr_write(CSR_VSTVAL, csr->vstval); + csr_write(CSR_VSIP, csr->vsip); + *vsip = csr->vsip; + csr_write(CSR_VSATP, csr->vsatp); kvm_riscv_stage2_update_hgatp(vcpu); + + vcpu->cpu = cpu; } void kvm_arch_vcpu_put(struct kvm_vcpu *vcpu) { - /* TODO: */ + struct kvm_vcpu_csr *csr = &vcpu->arch.guest_csr; + + vcpu->cpu = -1; + + csr_write(CSR_HGATP, 0); + + csr->vsstatus = csr_read(CSR_VSSTATUS); + csr->vsie = csr_read(CSR_VSIE); + csr->vstvec = csr_read(CSR_VSTVEC); + csr->vsscratch = csr_read(CSR_VSSCRATCH); + csr->vsepc = csr_read(CSR_VSEPC); + csr->vscause = csr_read(CSR_VSCAUSE); + csr->vstval = csr_read(CSR_VSTVAL); + csr->vsip = csr_read(CSR_VSIP); + csr->vsatp = csr_read(CSR_VSATP); } static void kvm_riscv_check_vcpu_requests(struct kvm_vcpu *vcpu) diff --git a/arch/riscv/kvm/vcpu_switch.S b/arch/riscv/kvm/vcpu_switch.S new file mode 100644 index 000000000000..e1a17df1b379 --- /dev/null +++ b/arch/riscv/kvm/vcpu_switch.S @@ -0,0 +1,194 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +/* + * Copyright (C) 2019 Western Digital Corporation or its affiliates. + * + * Authors: + * Anup Patel + */ + +#include +#include +#include +#include + + .text + .altmacro + .option norelax + +ENTRY(__kvm_riscv_switch_to) + /* Save Host GPRs (except A0 and T0-T6) */ + REG_S ra, (KVM_ARCH_HOST_RA)(a0) + REG_S sp, (KVM_ARCH_HOST_SP)(a0) + REG_S gp, (KVM_ARCH_HOST_GP)(a0) + REG_S tp, (KVM_ARCH_HOST_TP)(a0) + REG_S s0, (KVM_ARCH_HOST_S0)(a0) + REG_S s1, (KVM_ARCH_HOST_S1)(a0) + REG_S a1, (KVM_ARCH_HOST_A1)(a0) + REG_S a2, (KVM_ARCH_HOST_A2)(a0) + REG_S a3, (KVM_ARCH_HOST_A3)(a0) + REG_S a4, (KVM_ARCH_HOST_A4)(a0) + REG_S a5, (KVM_ARCH_HOST_A5)(a0) + REG_S a6, (KVM_ARCH_HOST_A6)(a0) + REG_S a7, (KVM_ARCH_HOST_A7)(a0) + REG_S s2, (KVM_ARCH_HOST_S2)(a0) + REG_S s3, (KVM_ARCH_HOST_S3)(a0) + REG_S s4, (KVM_ARCH_HOST_S4)(a0) + REG_S s5, (KVM_ARCH_HOST_S5)(a0) + REG_S s6, (KVM_ARCH_HOST_S6)(a0) + REG_S s7, (KVM_ARCH_HOST_S7)(a0) + REG_S s8, (KVM_ARCH_HOST_S8)(a0) + REG_S s9, (KVM_ARCH_HOST_S9)(a0) + REG_S s10, (KVM_ARCH_HOST_S10)(a0) + REG_S s11, (KVM_ARCH_HOST_S11)(a0) + + /* Save Host SSTATUS, HSTATUS, SCRATCH and STVEC */ + csrr t0, CSR_SSTATUS + REG_S t0, (KVM_ARCH_HOST_SSTATUS)(a0) + csrr t1, CSR_HSTATUS + REG_S t1, (KVM_ARCH_HOST_HSTATUS)(a0) + csrr t2, CSR_SSCRATCH + REG_S t2, (KVM_ARCH_HOST_SSCRATCH)(a0) + csrr t3, CSR_STVEC + REG_S t3, (KVM_ARCH_HOST_STVEC)(a0) + + /* Change Host exception vector to return path */ + la t4, __kvm_switch_return + csrw CSR_STVEC, t4 + + /* Restore Guest HSTATUS, SSTATUS and SEPC */ + REG_L t4, (KVM_ARCH_GUEST_SEPC)(a0) + csrw CSR_SEPC, t4 + REG_L t5, (KVM_ARCH_GUEST_SSTATUS)(a0) + csrw CSR_SSTATUS, t5 + REG_L t6, (KVM_ARCH_GUEST_HSTATUS)(a0) + csrw CSR_HSTATUS, t6 + + /* Restore Guest GPRs (except A0) */ + REG_L ra, (KVM_ARCH_GUEST_RA)(a0) + REG_L sp, (KVM_ARCH_GUEST_SP)(a0) + REG_L gp, (KVM_ARCH_GUEST_GP)(a0) + REG_L tp, (KVM_ARCH_GUEST_TP)(a0) + REG_L t0, (KVM_ARCH_GUEST_T0)(a0) + REG_L t1, (KVM_ARCH_GUEST_T1)(a0) + REG_L t2, (KVM_ARCH_GUEST_T2)(a0) + REG_L s0, (KVM_ARCH_GUEST_S0)(a0) + REG_L s1, (KVM_ARCH_GUEST_S1)(a0) + REG_L a1, (KVM_ARCH_GUEST_A1)(a0) + REG_L a2, (KVM_ARCH_GUEST_A2)(a0) + REG_L a3, (KVM_ARCH_GUEST_A3)(a0) + REG_L a4, (KVM_ARCH_GUEST_A4)(a0) + REG_L a5, (KVM_ARCH_GUEST_A5)(a0) + REG_L a6, (KVM_ARCH_GUEST_A6)(a0) + REG_L a7, (KVM_ARCH_GUEST_A7)(a0) + REG_L s2, (KVM_ARCH_GUEST_S2)(a0) + REG_L s3, (KVM_ARCH_GUEST_S3)(a0) + REG_L s4, (KVM_ARCH_GUEST_S4)(a0) + REG_L s5, (KVM_ARCH_GUEST_S5)(a0) + REG_L s6, (KVM_ARCH_GUEST_S6)(a0) + REG_L s7, (KVM_ARCH_GUEST_S7)(a0) + REG_L s8, (KVM_ARCH_GUEST_S8)(a0) + REG_L s9, (KVM_ARCH_GUEST_S9)(a0) + REG_L s10, (KVM_ARCH_GUEST_S10)(a0) + REG_L s11, (KVM_ARCH_GUEST_S11)(a0) + REG_L t3, (KVM_ARCH_GUEST_T3)(a0) + REG_L t4, (KVM_ARCH_GUEST_T4)(a0) + REG_L t5, (KVM_ARCH_GUEST_T5)(a0) + REG_L t6, (KVM_ARCH_GUEST_T6)(a0) + + /* Save Host A0 in SSCRATCH */ + csrw CSR_SSCRATCH, a0 + + /* Restore Guest A0 */ + REG_L a0, (KVM_ARCH_GUEST_A0)(a0) + + /* Resume Guest */ + sret + + /* Back to Host */ + .align 2 +__kvm_switch_return: + /* Swap Guest A0 with SSCRATCH */ + csrrw a0, CSR_SSCRATCH, a0 + + /* Save Guest GPRs (except A0) */ + REG_S ra, (KVM_ARCH_GUEST_RA)(a0) + REG_S sp, (KVM_ARCH_GUEST_SP)(a0) + REG_S gp, (KVM_ARCH_GUEST_GP)(a0) + REG_S tp, (KVM_ARCH_GUEST_TP)(a0) + REG_S t0, (KVM_ARCH_GUEST_T0)(a0) + REG_S t1, (KVM_ARCH_GUEST_T1)(a0) + REG_S t2, (KVM_ARCH_GUEST_T2)(a0) + REG_S s0, (KVM_ARCH_GUEST_S0)(a0) + REG_S s1, (KVM_ARCH_GUEST_S1)(a0) + REG_S a1, (KVM_ARCH_GUEST_A1)(a0) + REG_S a2, (KVM_ARCH_GUEST_A2)(a0) + REG_S a3, (KVM_ARCH_GUEST_A3)(a0) + REG_S a4, (KVM_ARCH_GUEST_A4)(a0) + REG_S a5, (KVM_ARCH_GUEST_A5)(a0) + REG_S a6, (KVM_ARCH_GUEST_A6)(a0) + REG_S a7, (KVM_ARCH_GUEST_A7)(a0) + REG_S s2, (KVM_ARCH_GUEST_S2)(a0) + REG_S s3, (KVM_ARCH_GUEST_S3)(a0) + REG_S s4, (KVM_ARCH_GUEST_S4)(a0) + REG_S s5, (KVM_ARCH_GUEST_S5)(a0) + REG_S s6, (KVM_ARCH_GUEST_S6)(a0) + REG_S s7, (KVM_ARCH_GUEST_S7)(a0) + REG_S s8, (KVM_ARCH_GUEST_S8)(a0) + REG_S s9, (KVM_ARCH_GUEST_S9)(a0) + REG_S s10, (KVM_ARCH_GUEST_S10)(a0) + REG_S s11, (KVM_ARCH_GUEST_S11)(a0) + REG_S t3, (KVM_ARCH_GUEST_T3)(a0) + REG_S t4, (KVM_ARCH_GUEST_T4)(a0) + REG_S t5, (KVM_ARCH_GUEST_T5)(a0) + REG_S t6, (KVM_ARCH_GUEST_T6)(a0) + + /* Save Guest A0 */ + csrr t0, CSR_SSCRATCH + REG_S t0, (KVM_ARCH_GUEST_A0)(a0) + + /* Save Guest HSTATUS, SSTATUS, and SEPC */ + csrr t0, CSR_SEPC + REG_S t0, (KVM_ARCH_GUEST_SEPC)(a0) + csrr t1, CSR_SSTATUS + REG_S t1, (KVM_ARCH_GUEST_SSTATUS)(a0) + csrr t2, CSR_HSTATUS + REG_S t2, (KVM_ARCH_GUEST_HSTATUS)(a0) + + /* Restore Host SSTATUS, HSTATUS, SCRATCH and STVEC */ + REG_L t3, (KVM_ARCH_HOST_SSTATUS)(a0) + csrw CSR_SSTATUS, t3 + REG_L t4, (KVM_ARCH_HOST_HSTATUS)(a0) + csrw CSR_HSTATUS, t4 + REG_L t5, (KVM_ARCH_HOST_SSCRATCH)(a0) + csrw CSR_SSCRATCH, t5 + REG_L t6, (KVM_ARCH_HOST_STVEC)(a0) + csrw CSR_STVEC, t6 + + /* Restore Host GPRs (except A0 and T0-T6) */ + REG_L ra, (KVM_ARCH_HOST_RA)(a0) + REG_L sp, (KVM_ARCH_HOST_SP)(a0) + REG_L gp, (KVM_ARCH_HOST_GP)(a0) + REG_L tp, (KVM_ARCH_HOST_TP)(a0) + REG_L s0, (KVM_ARCH_HOST_S0)(a0) + REG_L s1, (KVM_ARCH_HOST_S1)(a0) + REG_L a1, (KVM_ARCH_HOST_A1)(a0) + REG_L a2, (KVM_ARCH_HOST_A2)(a0) + REG_L a3, (KVM_ARCH_HOST_A3)(a0) + REG_L a4, (KVM_ARCH_HOST_A4)(a0) + REG_L a5, (KVM_ARCH_HOST_A5)(a0) + REG_L a6, (KVM_ARCH_HOST_A6)(a0) + REG_L a7, (KVM_ARCH_HOST_A7)(a0) + REG_L s2, (KVM_ARCH_HOST_S2)(a0) + REG_L s3, (KVM_ARCH_HOST_S3)(a0) + REG_L s4, (KVM_ARCH_HOST_S4)(a0) + REG_L s5, (KVM_ARCH_HOST_S5)(a0) + REG_L s6, (KVM_ARCH_HOST_S6)(a0) + REG_L s7, (KVM_ARCH_HOST_S7)(a0) + REG_L s8, (KVM_ARCH_HOST_S8)(a0) + REG_L s9, (KVM_ARCH_HOST_S9)(a0) + REG_L s10, (KVM_ARCH_HOST_S10)(a0) + REG_L s11, (KVM_ARCH_HOST_S11)(a0) + + /* Return to C code */ + ret +ENDPROC(__kvm_riscv_switch_to) From patchwork Thu Oct 3 05:07:31 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Anup Patel X-Patchwork-Id: 11172117 Return-Path: Received: from mail.kernel.org (pdx-korg-mail-1.web.codeaurora.org [172.30.200.123]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id 3341A14DB for ; Thu, 3 Oct 2019 05:07:50 +0000 (UTC) Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id 0D718222CA for ; Thu, 3 Oct 2019 05:07:50 +0000 (UTC) Authentication-Results: mail.kernel.org; dkim=pass (2048-bit key) header.d=lists.infradead.org header.i=@lists.infradead.org header.b="XdwL8wEM"; dkim=fail reason="signature verification failed" (2048-bit key) header.d=wdc.com header.i=@wdc.com header.b="gOw+rOcS"; dkim=fail reason="signature verification failed" (1024-bit key) header.d=sharedspace.onmicrosoft.com header.i=@sharedspace.onmicrosoft.com header.b="a2eLP+QM" DMARC-Filter: OpenDMARC Filter v1.3.2 mail.kernel.org 0D718222CA Authentication-Results: mail.kernel.org; dmarc=fail (p=none dis=none) header.from=wdc.com Authentication-Results: mail.kernel.org; spf=none smtp.mailfrom=linux-riscv-bounces+patchwork-linux-riscv=patchwork.kernel.org@lists.infradead.org DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=bombadil.20170209; h=Sender: Content-Transfer-Encoding:Content-Type:Cc:List-Subscribe:List-Help:List-Post: List-Archive:List-Unsubscribe:List-Id:MIME-Version:In-Reply-To:References: Message-ID:Date:Subject:To:From:Reply-To:Content-ID:Content-Description: Resent-Date:Resent-From:Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID: List-Owner; bh=Qh1LnEcer8ABHAsWhm3OheXRztSipoi5ofXFJB3iJoA=; b=XdwL8wEMGZXLUg yJFbrPJuZ25MDLICaMUvBmOUISREAVkZ4SvEVv03+cxPkECX3ELC8gVs7WoxQKA67F9xoSznN8nBo IEJvfyB/mh5jO+vW10I+b4jf22XiAgsIWLjHhdhDmbD5Jdk1C734KTLclAYZxiOV3fuXuJVy4epVK rt1JrMZ5IuOgUSSq9QXx1uX+xQIzBkoIA0KH9vx4XyM1dgF8npmFoe7NWZnwJHAGnxPtwpN29qyQo jdsT1t94JarsnbA8uD/PJyWPfcDKV+AlDd4GThjP0rFoWDjZjgNHLYoWcL07BxkWg3ofOaf7warO+ kJNA0qs6yZ6lt1D00pzQ==; Received: from localhost ([127.0.0.1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.92.2 #3 (Red Hat Linux)) id 1iFtL2-0003i5-0W; Thu, 03 Oct 2019 05:07:40 +0000 Received: from esa2.hgst.iphmx.com ([68.232.143.124]) by bombadil.infradead.org with esmtps (Exim 4.92.2 #3 (Red Hat Linux)) id 1iFtKy-0003dH-2h for linux-riscv@lists.infradead.org; Thu, 03 Oct 2019 05:07:38 +0000 DKIM-Signature: v=1; a=rsa-sha256; c=simple/simple; d=wdc.com; i=@wdc.com; q=dns/txt; s=dkim.wdc.com; t=1570079256; x=1601615256; h=from:to:cc:subject:date:message-id:references: in-reply-to:content-transfer-encoding:mime-version; bh=yeTgZmurnfamwcX6UuxJciFHoh2x+v73BZaXSl64GXk=; b=gOw+rOcSZv9Rds67tiHKCSQ9BY24Jpn42QUVSVqfE1G3tZMb1+6j1l4W X2raMTH7N3tRH7OlB/XpFvCCsROt4u8C89ms/zoO5XXadHP+kUFJaim8/ fcdvYob4W6/qXolaafY71TtCuEtVyM4yCjQAXaC3OHGW4RXh9+Ewa/nel w+sWWQ3ZC2ffpK62J9XywnlnCKWyA1C35vRPH0ZOHJ4NK92Z0Q8XXJ5Zk kFgLOzd3jueiEj4d9Y7A+rK4r/DMtLCgXvFVbivmwF9AO66L01HfegFfq DxaHht2numcjjbgnHF+p3JBgdR6zOVFGZ6h9GnEsgsCBaohyZ3mf61R7t w==; IronPort-SDR: +TVkSAWuqgTxGOxPZSg09NPqhERiXC2rJ1YTKvgYxIAfN0eZIjaMkkwIVWdQ43BnfiTmP/jx0g VjgbyQJVzq18JUuq7TRIX2SsLGCV4Txoc4n7gy++Onw/VN92i8N4E4j0FRXHnS+fUySUnA0ppS SiYOGQMipHHnxuNzdnMh1jmgREHvXJN7I5mw2Cfcj1r5QBIX48cwkdBHjYhHI7EjtMZPTOEZge BWGEbje/1rMyt1ybgKXENNwWIqk9eHvqaoTeGBnvQC/y4rdNduTBjK9Xi4tB30tUOVf5WV03Zy Blg= X-IronPort-AV: E=Sophos;i="5.67,251,1566835200"; d="scan'208";a="220620883" Received: from mail-co1nam05lp2058.outbound.protection.outlook.com (HELO NAM05-CO1-obe.outbound.protection.outlook.com) ([104.47.48.58]) by ob1.hgst.iphmx.com with ESMTP; 03 Oct 2019 13:07:55 +0800 ARC-Seal: i=1; a=rsa-sha256; s=arcselector9901; d=microsoft.com; cv=none; b=RY0eLlWkxJ/hRwoklC6PuPLZLI5YM/v8xkSEazDSu+SJ8HvxHaox4hJedvMmS+bqeixlQzKEA6ZK7OKj4m4Iu3qRQa1s+JJAwNYAg8m7ZclF2iMtR4WB1bwpziV0v21crvILUaBbMVrJEnd5MLK3oauUsP8Co4SQ1UGU2YnGzabLajOi4M3qHTuc/KcwSs3LBl9wW/h5FWvdWI4nxj9v2fFGoAbucNIlfbyGfkq8dBS575oTkZWgRrcM5Ew4S2I9nF2g9AXQ+TDaPEn1uK7YnHRB2Ph5xv5qt2V+LqDNk7JXgwVYgFsoUZdJTf7R+Pot6GAqwMSfO1y6ZQhfUL/Q9Q== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=microsoft.com; s=arcselector9901; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-SenderADCheck; bh=KJJPIRSI7QFFR3VTlmugjY8kzFN/BUIN0CM01/gDcMA=; b=BUGQQGbDAiS84saYoUORAzd17VHSL9BNgKBMdho4jRXWZQ8GY2Jgrwm4rZ5aCX59OhJtvAAIDHQR8/XSoISp6nuyLZjYiXfD6ALWuZmETxreLKAppEHq46Tv9CUfki1/bG3skZCHh/FzvnD9zXxzpLQP2meG7Z6nP0bnCFn7pStaZQMXC52CyBW7tJ4iQhTg8bR+lskz+JfNCA/5/LHDF6kgHXX326ZZ/bwNtdHlqwkr6ZPJefSsh42/CE4FJGubUFMZYralpIg/v8sVz1kxPAzgcmEkoTStowTXfCrG3Qp8pURqe+ZVBoAww89m+uBaRo8ZJHT0+4zGJ++MmfkJrA== ARC-Authentication-Results: i=1; mx.microsoft.com 1; spf=pass smtp.mailfrom=wdc.com; dmarc=pass action=none header.from=wdc.com; dkim=pass header.d=wdc.com; arc=none DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=sharedspace.onmicrosoft.com; s=selector2-sharedspace-onmicrosoft-com; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-SenderADCheck; bh=KJJPIRSI7QFFR3VTlmugjY8kzFN/BUIN0CM01/gDcMA=; b=a2eLP+QM4isczqHH82uGShwSMAUHneEILZO5rLILdpg4cwQOPwnyVTHOhBTiIagAjD+pGKqNLu9NWusNMcY6S3LggAa0mh76C+jzSccdqslOquUA2Dl7D6sJ0mTtOesqPFFmX8M+LSfzfWLG2YNK8i+p2xX9mXwE0DxqUlZnPVI= Received: from MN2PR04MB6061.namprd04.prod.outlook.com (20.178.246.15) by MN2PR04MB6272.namprd04.prod.outlook.com (20.178.248.27) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.2305.17; Thu, 3 Oct 2019 05:07:31 +0000 Received: from MN2PR04MB6061.namprd04.prod.outlook.com ([fe80::1454:87a:13b0:d3a]) by MN2PR04MB6061.namprd04.prod.outlook.com ([fe80::1454:87a:13b0:d3a%7]) with mapi id 15.20.2305.023; Thu, 3 Oct 2019 05:07:31 +0000 From: Anup Patel To: Palmer Dabbelt , Paul Walmsley , Paolo Bonzini , Radim K Subject: [PATCH v8 08/19] RISC-V: KVM: Handle MMIO exits for VCPU Thread-Topic: [PATCH v8 08/19] RISC-V: KVM: Handle MMIO exits for VCPU Thread-Index: AQHVeah1aaCZEKosQEeFmchvePQfiQ== Date: Thu, 3 Oct 2019 05:07:31 +0000 Message-ID: <20191003050558.9031-9-anup.patel@wdc.com> References: <20191003050558.9031-1-anup.patel@wdc.com> In-Reply-To: <20191003050558.9031-1-anup.patel@wdc.com> Accept-Language: en-US Content-Language: en-US X-MS-Has-Attach: X-MS-TNEF-Correlator: x-clientproxiedby: BMXPR01CA0030.INDPRD01.PROD.OUTLOOK.COM (2603:1096:b00:c::16) To MN2PR04MB6061.namprd04.prod.outlook.com (2603:10b6:208:d8::15) authentication-results: spf=none (sender IP is ) smtp.mailfrom=Anup.Patel@wdc.com; x-ms-exchange-messagesentrepresentingtype: 1 x-mailer: git-send-email 2.17.1 x-originating-ip: [111.235.74.37] x-ms-publictraffictype: Email x-ms-office365-filtering-correlation-id: 98be269c-ab74-49c5-9a72-08d747bf9829 x-ms-office365-filtering-ht: Tenant x-ms-traffictypediagnostic: MN2PR04MB6272: x-ms-exchange-transport-forked: True x-microsoft-antispam-prvs: wdcipoutbound: EOP-TRUE x-ms-oob-tlc-oobclassifiers: OLM:334; x-forefront-prvs: 01792087B6 x-forefront-antispam-report: SFV:NSPM; SFS:(10019020)(979002)(4636009)(136003)(376002)(346002)(366004)(396003)(39860400002)(43544003)(189003)(199004)(6512007)(6486002)(81166006)(81156014)(8936002)(6116002)(3846002)(8676002)(50226002)(2906002)(110136005)(66066001)(6436002)(316002)(66476007)(66556008)(7416002)(66446008)(36756003)(1076003)(5660300002)(54906003)(7736002)(305945005)(76176011)(30864003)(25786009)(52116002)(256004)(14444005)(71190400001)(86362001)(99286004)(71200400001)(2616005)(446003)(14454004)(476003)(102836004)(186003)(26005)(11346002)(44832011)(6506007)(486006)(478600001)(4326008)(66946007)(386003)(64756008)(969003)(989001)(999001)(1009001)(1019001); DIR:OUT; SFP:1102; SCL:1; SRVR:MN2PR04MB6272; H:MN2PR04MB6061.namprd04.prod.outlook.com; FPR:; SPF:None; LANG:en; PTR:InfoNoRecords; MX:1; A:1; x-ms-exchange-senderadcheck: 1 x-microsoft-antispam: BCL:0; x-microsoft-antispam-message-info: 8qYh2fY5z1T6OwhqDXGiTHDbKrltlnOvutTNGydW4TFR97HphD95f0NeLZuWpIBwlYKejl9UTuLV8Kzv0qyqfjfQajQqkfQ0dltwwknEyjOtGoeM7hkGI52frp9bO7n/y2iVbdjBVYy+CMzo3MB/G0TPPfObPgh9wYIh3eDfkmvkP4zVkD895Ji+gBHCSlQOFCXAHC04ivp4Z6vvIummL57l/rhUQF3Xt/VU5b/S7da9bBU7znoCFklLRiwwNnMDg4vRKM6gN6IuUEFfKfz6+YTa6WCK9YxeQ9Bc2hR89onqhl5r8RuBxHgrcZ8PDstcuXfaDJ16R7O0GA/ODVDIuXYf9LZ8/MUCv9u0BVNTejwDJDzdbyhRc8lXJkrTAggyRJUeT/I50P/qfIROegizmTxpuhILOom+vyh1+tOFUBA= MIME-Version: 1.0 X-OriginatorOrg: wdc.com X-MS-Exchange-CrossTenant-Network-Message-Id: 98be269c-ab74-49c5-9a72-08d747bf9829 X-MS-Exchange-CrossTenant-originalarrivaltime: 03 Oct 2019 05:07:31.7001 (UTC) X-MS-Exchange-CrossTenant-fromentityheader: Hosted X-MS-Exchange-CrossTenant-id: b61c8803-16f3-4c35-9b17-6f65f441df86 X-MS-Exchange-CrossTenant-mailboxtype: HOSTED X-MS-Exchange-CrossTenant-userprincipalname: Gj4SGkIVqzjHOqvm/y/C+9F/kFsKCZTSVAUpRLhq+zCjcO5/c6GbnPkrs3jqC8NCULgWcv52mdJuEnxf4MNEDQ== X-MS-Exchange-Transport-CrossTenantHeadersStamped: MN2PR04MB6272 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20191002_220736_179267_1CD75B3F X-CRM114-Status: GOOD ( 17.71 ) X-Spam-Score: -2.5 (--) X-Spam-Report: SpamAssassin version 3.4.2 on bombadil.infradead.org summary: Content analysis details: (-2.5 points) pts rule name description ---- ---------------------- -------------------------------------------------- -2.3 RCVD_IN_DNSWL_MED RBL: Sender listed at https://www.dnswl.org/, medium trust [68.232.143.124 listed in list.dnswl.org] -0.0 SPF_PASS SPF: sender matches SPF record 0.0 SPF_HELO_NONE SPF: HELO does not publish an SPF Record -0.1 DKIM_VALID_EF Message has a valid DKIM or DK signature from envelope-from domain 0.1 DKIM_SIGNED Message has a DKIM or DK signature, not necessarily valid -0.1 DKIM_VALID_AU Message has a valid DKIM or DK signature from author's domain -0.1 DKIM_VALID Message has at least one valid DKIM or DK signature X-BeenThere: linux-riscv@lists.infradead.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Damien Le Moal , Anup Patel , "kvm@vger.kernel.org" , Anup Patel , Daniel Lezcano , "linux-kernel@vger.kernel.org" , Christoph Hellwig , Atish Patra , Alexander Graf , Alistair Francis , Thomas Gleixner , "linux-riscv@lists.infradead.org" Sender: "linux-riscv" Errors-To: linux-riscv-bounces+patchwork-linux-riscv=patchwork.kernel.org@lists.infradead.org We will get stage2 page faults whenever Guest/VM access SW emulated MMIO device or unmapped Guest RAM. This patch implements MMIO read/write emulation by extracting MMIO details from the trapped load/store instruction and forwarding the MMIO read/write to user-space. The actual MMIO emulation will happen in user-space and KVM kernel module will only take care of register updates before resuming the trapped VCPU. The handling for stage2 page faults for unmapped Guest RAM will be implemeted by a separate patch later. Signed-off-by: Anup Patel Acked-by: Paolo Bonzini Reviewed-by: Paolo Bonzini Reviewed-by: Alexander Graf --- arch/riscv/include/asm/kvm_host.h | 20 ++ arch/riscv/kvm/mmu.c | 7 + arch/riscv/kvm/vcpu_exit.c | 505 +++++++++++++++++++++++++++++- arch/riscv/kvm/vcpu_switch.S | 14 + 4 files changed, 543 insertions(+), 3 deletions(-) diff --git a/arch/riscv/include/asm/kvm_host.h b/arch/riscv/include/asm/kvm_host.h index 18f1097f1d8d..2a5209fff68d 100644 --- a/arch/riscv/include/asm/kvm_host.h +++ b/arch/riscv/include/asm/kvm_host.h @@ -53,6 +53,13 @@ struct kvm_arch { phys_addr_t pgd_phys; }; +struct kvm_mmio_decode { + unsigned long insn; + int len; + int shift; + int return_handled; +}; + struct kvm_cpu_context { unsigned long zero; unsigned long ra; @@ -141,6 +148,9 @@ struct kvm_vcpu_arch { unsigned long irqs_pending; unsigned long irqs_pending_mask; + /* MMIO instruction details */ + struct kvm_mmio_decode mmio_decode; + /* VCPU power-off state */ bool power_off; @@ -160,11 +170,21 @@ static inline void kvm_arch_vcpu_block_finish(struct kvm_vcpu *vcpu) {} int kvm_riscv_setup_vsip(void); void kvm_riscv_cleanup_vsip(void); +int kvm_riscv_stage2_map(struct kvm_vcpu *vcpu, gpa_t gpa, unsigned long hva, + bool is_write); void kvm_riscv_stage2_flush_cache(struct kvm_vcpu *vcpu); int kvm_riscv_stage2_alloc_pgd(struct kvm *kvm); void kvm_riscv_stage2_free_pgd(struct kvm *kvm); void kvm_riscv_stage2_update_hgatp(struct kvm_vcpu *vcpu); +void __kvm_riscv_unpriv_trap(void); + +unsigned long kvm_riscv_vcpu_unpriv_read(struct kvm_vcpu *vcpu, + bool read_insn, + unsigned long guest_addr, + unsigned long *trap_scause); +void kvm_riscv_vcpu_trap_redirect(struct kvm_vcpu *vcpu, + unsigned long scause, unsigned long stval); int kvm_riscv_vcpu_mmio_return(struct kvm_vcpu *vcpu, struct kvm_run *run); int kvm_riscv_vcpu_exit(struct kvm_vcpu *vcpu, struct kvm_run *run, unsigned long scause, unsigned long stval); diff --git a/arch/riscv/kvm/mmu.c b/arch/riscv/kvm/mmu.c index 04dd089b86ff..2b965f9aac07 100644 --- a/arch/riscv/kvm/mmu.c +++ b/arch/riscv/kvm/mmu.c @@ -61,6 +61,13 @@ int kvm_arch_prepare_memory_region(struct kvm *kvm, return 0; } +int kvm_riscv_stage2_map(struct kvm_vcpu *vcpu, gpa_t gpa, unsigned long hva, + bool is_write) +{ + /* TODO: */ + return 0; +} + void kvm_riscv_stage2_flush_cache(struct kvm_vcpu *vcpu) { /* TODO: */ diff --git a/arch/riscv/kvm/vcpu_exit.c b/arch/riscv/kvm/vcpu_exit.c index e4d7c8f0807a..f1378c0a447f 100644 --- a/arch/riscv/kvm/vcpu_exit.c +++ b/arch/riscv/kvm/vcpu_exit.c @@ -6,9 +6,430 @@ * Anup Patel */ +#include #include #include #include +#include + +#define INSN_MATCH_LB 0x3 +#define INSN_MASK_LB 0x707f +#define INSN_MATCH_LH 0x1003 +#define INSN_MASK_LH 0x707f +#define INSN_MATCH_LW 0x2003 +#define INSN_MASK_LW 0x707f +#define INSN_MATCH_LD 0x3003 +#define INSN_MASK_LD 0x707f +#define INSN_MATCH_LBU 0x4003 +#define INSN_MASK_LBU 0x707f +#define INSN_MATCH_LHU 0x5003 +#define INSN_MASK_LHU 0x707f +#define INSN_MATCH_LWU 0x6003 +#define INSN_MASK_LWU 0x707f +#define INSN_MATCH_SB 0x23 +#define INSN_MASK_SB 0x707f +#define INSN_MATCH_SH 0x1023 +#define INSN_MASK_SH 0x707f +#define INSN_MATCH_SW 0x2023 +#define INSN_MASK_SW 0x707f +#define INSN_MATCH_SD 0x3023 +#define INSN_MASK_SD 0x707f + +#define INSN_MATCH_C_LD 0x6000 +#define INSN_MASK_C_LD 0xe003 +#define INSN_MATCH_C_SD 0xe000 +#define INSN_MASK_C_SD 0xe003 +#define INSN_MATCH_C_LW 0x4000 +#define INSN_MASK_C_LW 0xe003 +#define INSN_MATCH_C_SW 0xc000 +#define INSN_MASK_C_SW 0xe003 +#define INSN_MATCH_C_LDSP 0x6002 +#define INSN_MASK_C_LDSP 0xe003 +#define INSN_MATCH_C_SDSP 0xe002 +#define INSN_MASK_C_SDSP 0xe003 +#define INSN_MATCH_C_LWSP 0x4002 +#define INSN_MASK_C_LWSP 0xe003 +#define INSN_MATCH_C_SWSP 0xc002 +#define INSN_MASK_C_SWSP 0xe003 + +#define INSN_16BIT_MASK 0x3 + +#define INSN_IS_16BIT(insn) (((insn) & INSN_16BIT_MASK) != INSN_16BIT_MASK) + +#define INSN_LEN(insn) (INSN_IS_16BIT(insn) ? 2 : 4) + +#ifdef CONFIG_64BIT +#define LOG_REGBYTES 3 +#else +#define LOG_REGBYTES 2 +#endif +#define REGBYTES (1 << LOG_REGBYTES) + +#define SH_RD 7 +#define SH_RS1 15 +#define SH_RS2 20 +#define SH_RS2C 2 + +#define RV_X(x, s, n) (((x) >> (s)) & ((1 << (n)) - 1)) +#define RVC_LW_IMM(x) ((RV_X(x, 6, 1) << 2) | \ + (RV_X(x, 10, 3) << 3) | \ + (RV_X(x, 5, 1) << 6)) +#define RVC_LD_IMM(x) ((RV_X(x, 10, 3) << 3) | \ + (RV_X(x, 5, 2) << 6)) +#define RVC_LWSP_IMM(x) ((RV_X(x, 4, 3) << 2) | \ + (RV_X(x, 12, 1) << 5) | \ + (RV_X(x, 2, 2) << 6)) +#define RVC_LDSP_IMM(x) ((RV_X(x, 5, 2) << 3) | \ + (RV_X(x, 12, 1) << 5) | \ + (RV_X(x, 2, 3) << 6)) +#define RVC_SWSP_IMM(x) ((RV_X(x, 9, 4) << 2) | \ + (RV_X(x, 7, 2) << 6)) +#define RVC_SDSP_IMM(x) ((RV_X(x, 10, 3) << 3) | \ + (RV_X(x, 7, 3) << 6)) +#define RVC_RS1S(insn) (8 + RV_X(insn, SH_RD, 3)) +#define RVC_RS2S(insn) (8 + RV_X(insn, SH_RS2C, 3)) +#define RVC_RS2(insn) RV_X(insn, SH_RS2C, 5) + +#define SHIFT_RIGHT(x, y) \ + ((y) < 0 ? ((x) << -(y)) : ((x) >> (y))) + +#define REG_MASK \ + ((1 << (5 + LOG_REGBYTES)) - (1 << LOG_REGBYTES)) + +#define REG_OFFSET(insn, pos) \ + (SHIFT_RIGHT((insn), (pos) - LOG_REGBYTES) & REG_MASK) + +#define REG_PTR(insn, pos, regs) \ + (ulong *)((ulong)(regs) + REG_OFFSET(insn, pos)) + +#define GET_RM(insn) (((insn) >> 12) & 7) + +#define GET_RS1(insn, regs) (*REG_PTR(insn, SH_RS1, regs)) +#define GET_RS2(insn, regs) (*REG_PTR(insn, SH_RS2, regs)) +#define GET_RS1S(insn, regs) (*REG_PTR(RVC_RS1S(insn), 0, regs)) +#define GET_RS2S(insn, regs) (*REG_PTR(RVC_RS2S(insn), 0, regs)) +#define GET_RS2C(insn, regs) (*REG_PTR(insn, SH_RS2C, regs)) +#define GET_SP(regs) (*REG_PTR(2, 0, regs)) +#define SET_RD(insn, regs, val) (*REG_PTR(insn, SH_RD, regs) = (val)) +#define IMM_I(insn) ((s32)(insn) >> 20) +#define IMM_S(insn) (((s32)(insn) >> 25 << 5) | \ + (s32)(((insn) >> 7) & 0x1f)) +#define MASK_FUNCT3 0x7000 + +static int emulate_load(struct kvm_vcpu *vcpu, struct kvm_run *run, + unsigned long fault_addr) +{ + int shift = 0, len = 0; + unsigned long ut_scause = 0; + struct kvm_cpu_context *ct = &vcpu->arch.guest_context; + ulong insn = kvm_riscv_vcpu_unpriv_read(vcpu, true, ct->sepc, + &ut_scause); + + /* Redirect trap if we failed to read instruction */ + if (ut_scause) { + if (ut_scause == EXC_LOAD_PAGE_FAULT) + ut_scause = EXC_INST_PAGE_FAULT; + kvm_riscv_vcpu_trap_redirect(vcpu, ut_scause, ct->sepc); + return 1; + } + + /* Decode length of MMIO and shift */ + if ((insn & INSN_MASK_LW) == INSN_MATCH_LW) { + len = 4; + shift = 8 * (sizeof(ulong) - len); + } else if ((insn & INSN_MASK_LB) == INSN_MATCH_LB) { + len = 1; + shift = 8 * (sizeof(ulong) - len); + } else if ((insn & INSN_MASK_LBU) == INSN_MATCH_LBU) { + len = 1; + shift = 8 * (sizeof(ulong) - len); +#ifdef CONFIG_64BIT + } else if ((insn & INSN_MASK_LD) == INSN_MATCH_LD) { + len = 8; + shift = 8 * (sizeof(ulong) - len); + } else if ((insn & INSN_MASK_LWU) == INSN_MATCH_LWU) { + len = 4; +#endif + } else if ((insn & INSN_MASK_LH) == INSN_MATCH_LH) { + len = 2; + shift = 8 * (sizeof(ulong) - len); + } else if ((insn & INSN_MASK_LHU) == INSN_MATCH_LHU) { + len = 2; +#ifdef CONFIG_64BIT + } else if ((insn & INSN_MASK_C_LD) == INSN_MATCH_C_LD) { + len = 8; + shift = 8 * (sizeof(ulong) - len); + insn = RVC_RS2S(insn) << SH_RD; + } else if ((insn & INSN_MASK_C_LDSP) == INSN_MATCH_C_LDSP && + ((insn >> SH_RD) & 0x1f)) { + len = 8; + shift = 8 * (sizeof(ulong) - len); +#endif + } else if ((insn & INSN_MASK_C_LW) == INSN_MATCH_C_LW) { + len = 4; + shift = 8 * (sizeof(ulong) - len); + insn = RVC_RS2S(insn) << SH_RD; + } else if ((insn & INSN_MASK_C_LWSP) == INSN_MATCH_C_LWSP && + ((insn >> SH_RD) & 0x1f)) { + len = 4; + shift = 8 * (sizeof(ulong) - len); + } else { + return -ENOTSUPP; + } + + /* Fault address should be aligned to length of MMIO */ + if (fault_addr & (len - 1)) + return -EIO; + + /* Save instruction decode info */ + vcpu->arch.mmio_decode.insn = insn; + vcpu->arch.mmio_decode.shift = shift; + vcpu->arch.mmio_decode.len = len; + vcpu->arch.mmio_decode.return_handled = 0; + + /* Exit to userspace for MMIO emulation */ + vcpu->stat.mmio_exit_user++; + run->exit_reason = KVM_EXIT_MMIO; + run->mmio.is_write = false; + run->mmio.phys_addr = fault_addr; + run->mmio.len = len; + + return 0; +} + +static int emulate_store(struct kvm_vcpu *vcpu, struct kvm_run *run, + unsigned long fault_addr) +{ + u8 data8; + u16 data16; + u32 data32; + u64 data64; + ulong data; + int len = 0; + unsigned long ut_scause = 0; + struct kvm_cpu_context *ct = &vcpu->arch.guest_context; + ulong insn = kvm_riscv_vcpu_unpriv_read(vcpu, true, ct->sepc, + &ut_scause); + + /* Redirect trap if we failed to read instruction */ + if (ut_scause) { + if (ut_scause == EXC_LOAD_PAGE_FAULT) + ut_scause = EXC_INST_PAGE_FAULT; + kvm_riscv_vcpu_trap_redirect(vcpu, ut_scause, ct->sepc); + return 1; + } + + data = GET_RS2(insn, &vcpu->arch.guest_context); + data8 = data16 = data32 = data64 = data; + + if ((insn & INSN_MASK_SW) == INSN_MATCH_SW) { + len = 4; + } else if ((insn & INSN_MASK_SB) == INSN_MATCH_SB) { + len = 1; +#ifdef CONFIG_64BIT + } else if ((insn & INSN_MASK_SD) == INSN_MATCH_SD) { + len = 8; +#endif + } else if ((insn & INSN_MASK_SH) == INSN_MATCH_SH) { + len = 2; +#ifdef CONFIG_64BIT + } else if ((insn & INSN_MASK_C_SD) == INSN_MATCH_C_SD) { + len = 8; + data64 = GET_RS2S(insn, &vcpu->arch.guest_context); + } else if ((insn & INSN_MASK_C_SDSP) == INSN_MATCH_C_SDSP && + ((insn >> SH_RD) & 0x1f)) { + len = 8; + data64 = GET_RS2C(insn, &vcpu->arch.guest_context); +#endif + } else if ((insn & INSN_MASK_C_SW) == INSN_MATCH_C_SW) { + len = 4; + data32 = GET_RS2S(insn, &vcpu->arch.guest_context); + } else if ((insn & INSN_MASK_C_SWSP) == INSN_MATCH_C_SWSP && + ((insn >> SH_RD) & 0x1f)) { + len = 4; + data32 = GET_RS2C(insn, &vcpu->arch.guest_context); + } else { + return -ENOTSUPP; + } + + /* Fault address should be aligned to length of MMIO */ + if (fault_addr & (len - 1)) + return -EIO; + + /* Save instruction decode info */ + vcpu->arch.mmio_decode.insn = insn; + vcpu->arch.mmio_decode.shift = 0; + vcpu->arch.mmio_decode.len = len; + vcpu->arch.mmio_decode.return_handled = 0; + + /* Copy data to kvm_run instance */ + switch (len) { + case 1: + *((u8 *)run->mmio.data) = data8; + break; + case 2: + *((u16 *)run->mmio.data) = data16; + break; + case 4: + *((u32 *)run->mmio.data) = data32; + break; + case 8: + *((u64 *)run->mmio.data) = data64; + break; + default: + return -ENOTSUPP; + }; + + /* Exit to userspace for MMIO emulation */ + vcpu->stat.mmio_exit_user++; + run->exit_reason = KVM_EXIT_MMIO; + run->mmio.is_write = true; + run->mmio.phys_addr = fault_addr; + run->mmio.len = len; + + return 0; +} + +static int stage2_page_fault(struct kvm_vcpu *vcpu, struct kvm_run *run, + unsigned long scause, unsigned long stval) +{ + struct kvm_memory_slot *memslot; + unsigned long hva; + bool writable; + gfn_t gfn; + int ret; + + gfn = stval >> PAGE_SHIFT; + memslot = gfn_to_memslot(vcpu->kvm, gfn); + hva = gfn_to_hva_memslot_prot(memslot, gfn, &writable); + + if (kvm_is_error_hva(hva) || + (scause == EXC_STORE_PAGE_FAULT && !writable)) { + switch (scause) { + case EXC_LOAD_PAGE_FAULT: + return emulate_load(vcpu, run, stval); + case EXC_STORE_PAGE_FAULT: + return emulate_store(vcpu, run, stval); + default: + return -ENOTSUPP; + }; + } + + ret = kvm_riscv_stage2_map(vcpu, stval, hva, + (scause == EXC_STORE_PAGE_FAULT) ? true : false); + if (ret < 0) + return ret; + + return 1; +} + +#define STR(x) XSTR(x) +#define XSTR(x) #x + +/** + * kvm_riscv_vcpu_unpriv_read -- Read machine word from Guest memory + * + * @vcpu: The VCPU pointer + * @read_insn: Flag representing whether we are reading instruction + * @guest_addr: Guest address to read + * @trap_scause: Output pointer for unprivilege trap cause + */ +unsigned long kvm_riscv_vcpu_unpriv_read(struct kvm_vcpu *vcpu, + bool read_insn, + unsigned long guest_addr, + unsigned long *trap_scause) +{ + register unsigned long tscause asm("a0"); + register unsigned long val asm("a1"); + register unsigned long addr asm("a2") = guest_addr; + unsigned long guest_sstatus = + vcpu->arch.guest_context.sstatus | ((read_insn) ? SR_MXR : 0); + unsigned long guest_hstatus = + vcpu->arch.guest_context.hstatus | HSTATUS_SPRV; + unsigned long old_stvec, tmp; + + BUG_ON(guest_sstatus & SR_SIE); + + guest_sstatus = csr_swap(CSR_SSTATUS, guest_sstatus); + old_stvec = csr_swap(CSR_STVEC, (ulong)&__kvm_riscv_unpriv_trap); + + if (read_insn) { + asm volatile ("\n" + "csrrw %[hstatus], " STR(CSR_HSTATUS) ", %[hstatus]\n" + "li %[tscause], 0\n" + "lhu %[val], (%[addr])\n" + "andi %[tmp], %[val], 3\n" + "addi %[tmp], %[tmp], -3\n" + "bne %[tmp], zero, 2f\n" + "lhu %[tmp], 2(%[addr])\n" + "sll %[tmp], %[tmp], 16\n" + "add %[val], %[val], %[tmp]\n" + "2: csrw " STR(CSR_HSTATUS) ", %[hstatus]" + : [hstatus] "+&r"(guest_hstatus), [val] "=&r" (val), + [tmp] "=&r" (tmp), [tscause] "+&r" (tscause) + : [addr] "r" (addr)); + } else { + asm volatile ("\n" + "csrrw %[hstatus], " STR(CSR_HSTATUS) ", %[hstatus]\n" + "li %[tscause], 0\n" + ".option push\n" + ".option norvc\n" +#ifdef CONFIG_64BIT + "ld %[val], (%[addr])\n" +#else + "lw %[val], (%[addr])\n" +#endif + ".option pop\n" + "csrw " STR(CSR_HSTATUS) ", %[hstatus]" + : [hstatus] "+&r"(guest_hstatus), + [val] "=&r" (val), [tscause] "+&r" (tscause) + : [addr] "r" (addr)); + } + + csr_write(CSR_STVEC, old_stvec); + csr_write(CSR_SSTATUS, guest_sstatus); + + *trap_scause = tscause; + + return val; +} + +/** + * kvm_riscv_vcpu_trap_redirect -- Redirect trap to Guest + * + * @vcpu: The VCPU pointer + * @scause: Trap exception cause + * @stval: Trap value + */ +void kvm_riscv_vcpu_trap_redirect(struct kvm_vcpu *vcpu, + unsigned long scause, unsigned long stval) +{ + unsigned long vsstatus = csr_read(CSR_VSSTATUS); + + /* Change Guest SSTATUS.SPP bit */ + vsstatus &= ~SR_SPP; + if (vcpu->arch.guest_context.sstatus & SR_SPP) + vsstatus |= SR_SPP; + + /* Change Guest SSTATUS.SPIE bit */ + vsstatus &= ~SR_SPIE; + if (vsstatus & SR_SIE) + vsstatus |= SR_SPIE; + + /* Clear Guest SSTATUS.SIE bit */ + vsstatus &= ~SR_SIE; + + /* Update Guest SSTATUS */ + csr_write(CSR_VSSTATUS, vsstatus); + + /* Update Guest SCAUSE, STVAL, and SEPC */ + csr_write(CSR_VSCAUSE, scause); + csr_write(CSR_VSTVAL, stval); + csr_write(CSR_VSEPC, vcpu->arch.guest_context.sepc); + + /* Set Guest PC to Guest exception vector */ + vcpu->arch.guest_context.sepc = csr_read(CSR_VSTVEC); +} /** * kvm_riscv_vcpu_mmio_return -- Handle MMIO loads after user space emulation @@ -19,7 +440,54 @@ */ int kvm_riscv_vcpu_mmio_return(struct kvm_vcpu *vcpu, struct kvm_run *run) { - /* TODO: */ + u8 data8; + u16 data16; + u32 data32; + u64 data64; + ulong insn; + int len, shift; + + if (vcpu->arch.mmio_decode.return_handled) + return 0; + + vcpu->arch.mmio_decode.return_handled = 1; + insn = vcpu->arch.mmio_decode.insn; + + if (run->mmio.is_write) + goto done; + + len = vcpu->arch.mmio_decode.len; + shift = vcpu->arch.mmio_decode.shift; + + switch (len) { + case 1: + data8 = *((u8 *)run->mmio.data); + SET_RD(insn, &vcpu->arch.guest_context, + (ulong)data8 << shift >> shift); + break; + case 2: + data16 = *((u16 *)run->mmio.data); + SET_RD(insn, &vcpu->arch.guest_context, + (ulong)data16 << shift >> shift); + break; + case 4: + data32 = *((u32 *)run->mmio.data); + SET_RD(insn, &vcpu->arch.guest_context, + (ulong)data32 << shift >> shift); + break; + case 8: + data64 = *((u64 *)run->mmio.data); + SET_RD(insn, &vcpu->arch.guest_context, + (ulong)data64 << shift >> shift); + break; + default: + return -ENOTSUPP; + }; + +done: + /* Move to next instruction */ + vcpu->arch.guest_context.sepc += INSN_LEN(insn); + return 0; } @@ -30,6 +498,37 @@ int kvm_riscv_vcpu_mmio_return(struct kvm_vcpu *vcpu, struct kvm_run *run) int kvm_riscv_vcpu_exit(struct kvm_vcpu *vcpu, struct kvm_run *run, unsigned long scause, unsigned long stval) { - /* TODO: */ - return 0; + int ret; + + /* If we got host interrupt then do nothing */ + if (scause & SCAUSE_IRQ_FLAG) + return 1; + + /* Handle guest traps */ + ret = -EFAULT; + run->exit_reason = KVM_EXIT_UNKNOWN; + switch (scause) { + case EXC_INST_PAGE_FAULT: + case EXC_LOAD_PAGE_FAULT: + case EXC_STORE_PAGE_FAULT: + if ((vcpu->arch.guest_context.hstatus & HSTATUS_SPV) && + (vcpu->arch.guest_context.hstatus & HSTATUS_STL)) + ret = stage2_page_fault(vcpu, run, scause, stval); + break; + default: + break; + }; + + /* Print details in-case of error */ + if (ret < 0) { + kvm_err("VCPU exit error %d\n", ret); + kvm_err("SEPC=0x%lx SSTATUS=0x%lx HSTATUS=0x%lx\n", + vcpu->arch.guest_context.sepc, + vcpu->arch.guest_context.sstatus, + vcpu->arch.guest_context.hstatus); + kvm_err("SCAUSE=0x%lx STVAL=0x%lx\n", + scause, stval); + } + + return ret; } diff --git a/arch/riscv/kvm/vcpu_switch.S b/arch/riscv/kvm/vcpu_switch.S index e1a17df1b379..04b318b9eef8 100644 --- a/arch/riscv/kvm/vcpu_switch.S +++ b/arch/riscv/kvm/vcpu_switch.S @@ -192,3 +192,17 @@ __kvm_switch_return: /* Return to C code */ ret ENDPROC(__kvm_riscv_switch_to) + +ENTRY(__kvm_riscv_unpriv_trap) + /* + * We assume that faulting unpriv load/store instruction is + * is 4-byte long and blindly increment SEPC by 4. + * + * The trap exception cause will be saved in 'A0' register. + */ + csrr a0, CSR_SEPC + addi a0, a0, 4 + csrw CSR_SEPC, a0 + csrr a0, CSR_SCAUSE + sret +ENDPROC(__kvm_riscv_unpriv_trap) From patchwork Thu Oct 3 05:07:39 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Anup Patel X-Patchwork-Id: 11172119 Return-Path: Received: from mail.kernel.org (pdx-korg-mail-1.web.codeaurora.org [172.30.200.123]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id 1055014DB for ; Thu, 3 Oct 2019 05:07:54 +0000 (UTC) Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id DEC0A21D81 for ; Thu, 3 Oct 2019 05:07:53 +0000 (UTC) Authentication-Results: mail.kernel.org; dkim=pass (2048-bit key) header.d=lists.infradead.org header.i=@lists.infradead.org header.b="rmHOhZBP"; dkim=fail reason="signature verification failed" (2048-bit key) header.d=wdc.com header.i=@wdc.com header.b="ihZa693N"; dkim=fail reason="signature verification failed" (1024-bit key) header.d=sharedspace.onmicrosoft.com header.i=@sharedspace.onmicrosoft.com header.b="u7tXJNxz" DMARC-Filter: OpenDMARC Filter v1.3.2 mail.kernel.org DEC0A21D81 Authentication-Results: mail.kernel.org; dmarc=fail (p=none dis=none) header.from=wdc.com Authentication-Results: mail.kernel.org; spf=none smtp.mailfrom=linux-riscv-bounces+patchwork-linux-riscv=patchwork.kernel.org@lists.infradead.org DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=bombadil.20170209; h=Sender: Content-Transfer-Encoding:Content-Type:Cc:List-Subscribe:List-Help:List-Post: List-Archive:List-Unsubscribe:List-Id:MIME-Version:In-Reply-To:References: Message-ID:Date:Subject:To:From:Reply-To:Content-ID:Content-Description: Resent-Date:Resent-From:Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID: List-Owner; bh=WvExAXwyrxMOhLF9cHtkKauRY1gorV7EU0oxbR8AENc=; b=rmHOhZBPrPslXn ntag/Yeq7DFqA+OmKNgzqegVAr6KwEoh7aOJ72WrGYUskWiBZyYQaIsxkkMgMMEILr1JsdmITbt9g jl2Qp3TACN/n6+qnpbJq14es1nI4sI8LZj5xFLFNRUF0TT46HtfKQCC4ayewJZ0ZdHv+Y+sp/yYdU F/FNhZ/1HheL8RTLSOFfUCHj0UFF5zEEcsZvyWvkovws33fl3LxJWhoIQQkbLfTYQXqLqecvjwZ6N Bd8iZHEylr/ouZaf54qWq92Smz8I4urwZFNMiPvinDWZRsepiw8o88MXlddsc9Pfl5FBwB6OEFod3 gl1Mys9cFBgLQW92RaLw==; Received: from localhost ([127.0.0.1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.92.2 #3 (Red Hat Linux)) id 1iFtL8-0003pi-5Q; Thu, 03 Oct 2019 05:07:46 +0000 Received: from esa2.hgst.iphmx.com ([68.232.143.124]) by bombadil.infradead.org with esmtps (Exim 4.92.2 #3 (Red Hat Linux)) id 1iFtL5-0003nU-4t for linux-riscv@lists.infradead.org; Thu, 03 Oct 2019 05:07:44 +0000 DKIM-Signature: v=1; a=rsa-sha256; c=simple/simple; d=wdc.com; i=@wdc.com; q=dns/txt; s=dkim.wdc.com; t=1570079267; x=1601615267; h=from:to:cc:subject:date:message-id:references: in-reply-to:content-transfer-encoding:mime-version; bh=WI2pUum0Vz98zmcCy0oe8jHgcv1NUOJuTi8N6+P2iho=; b=ihZa693N+fUtmuFIdSA8qjL4LgQXI2ZUBgi0ya8YR/2OtrIghN9C+dGF 5CKBgNZTgPRXbbHB4l5bN7kk+Co3H0oRXEARU9fO+A7T8N2FuaiMWY4tf GocpLpY6qsKMKXLqAAGB9U7xR0CdBNXG5UgpiL4oQSQh6h0TBoRU9sKly xc8M0Ss9h/s0c2fls7RCHM3qKyVqMUb3Zqn6Km/UDqgva3NT3Ze12gk3f dFhGvD1P5FwjKqBKwmZuxSbHkOmHH9yXPeMZ+N/O+Pc1bux7GBw8/zaLc Zzv3D6VXJKUudXuCLXS1OVTTjIvbPu75pMas22n2DcCasmGQ2JjU624mb g==; IronPort-SDR: U2rzLpAanPbbLelm2+ARV7KW6T1TiGMSjGbihWhjau+7yQ+vcAfmcZjLpMiOKQ3cb2Nhe7UElw SIOd83QAo6kivA9iH6ezUj/2APku+OixpssS/v4Ej80h+x5cPvTmAJjpPsl79gMTh2YQr7UIrU ol7SGcdVsPgBAbi8+pRTdKKmRye9cgFW0I4qkIyteNaQVV2G2j1CRi+ysvaTYX7F3fPWf61pGX bzt6vlyJZqX9qCFopswBg+J4R9EWbib1H20AS94GOzeabh0O0Y1sVIg3kHlch+NfE6ARLQM6PI Fcw= X-IronPort-AV: E=Sophos;i="5.67,251,1566835200"; d="scan'208";a="220620893" Received: from mail-co1nam05lp2050.outbound.protection.outlook.com (HELO NAM05-CO1-obe.outbound.protection.outlook.com) ([104.47.48.50]) by ob1.hgst.iphmx.com with ESMTP; 03 Oct 2019 13:07:43 +0800 ARC-Seal: i=1; a=rsa-sha256; s=arcselector9901; d=microsoft.com; cv=none; b=CjewzXkqsdczBy6BAQc/jdGkY0RKftjF0p0U8P3nKLRS+srtHAKYosM8QFG4MjU//YQO90ZL06G7NDY5uHPfq9G0NWWMyGzS1sNdsy2bTwA5T22Qu1ZJBV6bcZTJtbw2RdYIU8v/yXN+5uzd/AyvDhqzI+aF31CCVQgeJPS4WLd1cSibdgOfF3Kw40W+5/dx9Gc7Urz6uK8aVp6uDVQewDYZTOAFlneSMo98MKrQFEDLH71JEXXupEIb+bSe43UOoXtsF4EfeWmPa2qN9paBM8bpiTl4Ottyo1Ed0vDq91P3g48jhO1A8YaEbpMYH2vSsqREy48URM0l9KfeLp/a9w== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=microsoft.com; s=arcselector9901; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-SenderADCheck; bh=XA/uq2gGBUDV+apHlvAM4WpvBC/lxz/mAAIlFZjhQgQ=; b=D+w9ZpmjfpabayoktNp9KN0sqVlkjn5PMhUA7o+30u7cFTuWAjuxqvaJix7cLoIgcmqtcBmnth38JOQc2e4apiNgbBLGV88MYgeirYQjw3vcE5Pp7v6Slec8/08tbqXiTj6VmDWC6JGQrTNyIeK6FEKLCfrR5840PmyIctjyorBpfOVIkODKJTJO9WesdZhFLJ8pIB8nc6e6+NzUjNR/8+qWj30rh3myVkrS+uxrC0m+e0Vj+De/Hx/UEoY+oCottzZFMCv4Rh4u0H2ljfj1v0nXPSlSg1x/MJHiNp4Emk48/zMynfEnnlNIKoxruK6Xqa/ZqtFG3T2HxVz75Ojw7g== ARC-Authentication-Results: i=1; mx.microsoft.com 1; spf=pass smtp.mailfrom=wdc.com; dmarc=pass action=none header.from=wdc.com; dkim=pass header.d=wdc.com; arc=none DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=sharedspace.onmicrosoft.com; s=selector2-sharedspace-onmicrosoft-com; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-SenderADCheck; bh=XA/uq2gGBUDV+apHlvAM4WpvBC/lxz/mAAIlFZjhQgQ=; b=u7tXJNxzw8FhT57nMGGzzUEqwsyTBopVYmuU94ZwR27mxLd2VIoF0n6zjgd51ZYJbDZWGKe23L5U9rdPO8ryAMtJviuIHsMsRAqCuVRIsgur62V2kJJyH68PUB9dOxDpjUFuX9wIj3DjdPhLTKb6LMzyybPQFjFXZgUNdUNd57M= Received: from MN2PR04MB6061.namprd04.prod.outlook.com (20.178.246.15) by MN2PR04MB6272.namprd04.prod.outlook.com (20.178.248.27) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.2305.17; Thu, 3 Oct 2019 05:07:39 +0000 Received: from MN2PR04MB6061.namprd04.prod.outlook.com ([fe80::1454:87a:13b0:d3a]) by MN2PR04MB6061.namprd04.prod.outlook.com ([fe80::1454:87a:13b0:d3a%7]) with mapi id 15.20.2305.023; Thu, 3 Oct 2019 05:07:39 +0000 From: Anup Patel To: Palmer Dabbelt , Paul Walmsley , Paolo Bonzini , Radim K Subject: [PATCH v8 09/19] RISC-V: KVM: Handle WFI exits for VCPU Thread-Topic: [PATCH v8 09/19] RISC-V: KVM: Handle WFI exits for VCPU Thread-Index: AQHVeah6Lf401GA7mk68mGfWJjhE6g== Date: Thu, 3 Oct 2019 05:07:39 +0000 Message-ID: <20191003050558.9031-10-anup.patel@wdc.com> References: <20191003050558.9031-1-anup.patel@wdc.com> In-Reply-To: <20191003050558.9031-1-anup.patel@wdc.com> Accept-Language: en-US Content-Language: en-US X-MS-Has-Attach: X-MS-TNEF-Correlator: x-clientproxiedby: BMXPR01CA0030.INDPRD01.PROD.OUTLOOK.COM (2603:1096:b00:c::16) To MN2PR04MB6061.namprd04.prod.outlook.com (2603:10b6:208:d8::15) authentication-results: spf=none (sender IP is ) smtp.mailfrom=Anup.Patel@wdc.com; x-ms-exchange-messagesentrepresentingtype: 1 x-mailer: git-send-email 2.17.1 x-originating-ip: [111.235.74.37] x-ms-publictraffictype: Email x-ms-office365-filtering-correlation-id: fd9371aa-19bd-403d-5a9e-08d747bf9cf9 x-ms-office365-filtering-ht: Tenant x-ms-traffictypediagnostic: MN2PR04MB6272: x-ms-exchange-transport-forked: True x-microsoft-antispam-prvs: wdcipoutbound: EOP-TRUE x-ms-oob-tlc-oobclassifiers: OLM:2887; x-forefront-prvs: 01792087B6 x-forefront-antispam-report: SFV:NSPM; SFS:(10019020)(4636009)(136003)(376002)(346002)(366004)(396003)(39860400002)(189003)(199004)(6512007)(6486002)(81166006)(81156014)(8936002)(6116002)(3846002)(8676002)(50226002)(2906002)(110136005)(66066001)(6436002)(316002)(66476007)(66556008)(7416002)(66446008)(36756003)(1076003)(5660300002)(54906003)(7736002)(305945005)(76176011)(25786009)(52116002)(256004)(14444005)(71190400001)(86362001)(99286004)(71200400001)(2616005)(446003)(14454004)(476003)(102836004)(186003)(26005)(11346002)(44832011)(6506007)(486006)(478600001)(4326008)(66946007)(386003)(64756008); DIR:OUT; SFP:1102; SCL:1; SRVR:MN2PR04MB6272; H:MN2PR04MB6061.namprd04.prod.outlook.com; FPR:; SPF:None; LANG:en; PTR:InfoNoRecords; MX:1; A:1; x-ms-exchange-senderadcheck: 1 x-microsoft-antispam: BCL:0; x-microsoft-antispam-message-info: MA6SXwzBCRPfEQZkRbHDMQldU7r3qql8zAsEJQp4N0xLglzdFOU32klWu/QRyDiATz3UVR1IfzsumG8Hk26c/nqQoRMUGMo2mfJWPyUgxBG38luiXoI2jOOiVhvOhyPrGGTikmw7MwMe4w+1NZ8t59WZeq/mhAgNBA3VCHyxW1u8ummc9Lw4jWJwEF2egZpEJL8Apd17zp9iyrumC+lKlbfYT8QxhR9gl4WdLgmyMLmDIlo5ZfT0HAbQVReaMh5yLXBIgVFNU3h4kZ2Qt3/bogamoR0Suqzx2DPSiST5uAMh4WzEbpheOdtF4Z86ST4J+41b2IRBchRZKlPsyqv6LRy6pQzJqHTIXdMtScEQcli9MVQoi7YinJ4N0oRj04NLPDibJhT6fXfQZ3AB0VMN87Nc8+tbIWvkRI6VKdinn7I= MIME-Version: 1.0 X-OriginatorOrg: wdc.com X-MS-Exchange-CrossTenant-Network-Message-Id: fd9371aa-19bd-403d-5a9e-08d747bf9cf9 X-MS-Exchange-CrossTenant-originalarrivaltime: 03 Oct 2019 05:07:39.7775 (UTC) X-MS-Exchange-CrossTenant-fromentityheader: Hosted X-MS-Exchange-CrossTenant-id: b61c8803-16f3-4c35-9b17-6f65f441df86 X-MS-Exchange-CrossTenant-mailboxtype: HOSTED X-MS-Exchange-CrossTenant-userprincipalname: n1NoNXqElzIik95I4oC1xUbZwVgpFGY30Y/1ExUcfTi0e9VgrMyKL0rIsyw2KBobDhZXWTxkQsrpuIjMweaGDA== X-MS-Exchange-Transport-CrossTenantHeadersStamped: MN2PR04MB6272 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20191002_220743_233300_1F13965F X-CRM114-Status: GOOD ( 14.33 ) X-Spam-Score: -2.5 (--) X-Spam-Report: SpamAssassin version 3.4.2 on bombadil.infradead.org summary: Content analysis details: (-2.5 points) pts rule name description ---- ---------------------- -------------------------------------------------- -2.3 RCVD_IN_DNSWL_MED RBL: Sender listed at https://www.dnswl.org/, medium trust [68.232.143.124 listed in list.dnswl.org] -0.0 SPF_PASS SPF: sender matches SPF record 0.0 SPF_HELO_NONE SPF: HELO does not publish an SPF Record -0.1 DKIM_VALID_EF Message has a valid DKIM or DK signature from envelope-from domain 0.1 DKIM_SIGNED Message has a DKIM or DK signature, not necessarily valid -0.1 DKIM_VALID_AU Message has a valid DKIM or DK signature from author's domain -0.1 DKIM_VALID Message has at least one valid DKIM or DK signature X-BeenThere: linux-riscv@lists.infradead.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Damien Le Moal , Anup Patel , "kvm@vger.kernel.org" , Anup Patel , Daniel Lezcano , "linux-kernel@vger.kernel.org" , Christoph Hellwig , Atish Patra , Alexander Graf , Alistair Francis , Thomas Gleixner , "linux-riscv@lists.infradead.org" Sender: "linux-riscv" Errors-To: linux-riscv-bounces+patchwork-linux-riscv=patchwork.kernel.org@lists.infradead.org We get illegal instruction trap whenever Guest/VM executes WFI instruction. This patch handles WFI trap by blocking the trapped VCPU using kvm_vcpu_block() API. The blocked VCPU will be automatically resumed whenever a VCPU interrupt is injected from user-space or from in-kernel IRQCHIP emulation. Signed-off-by: Anup Patel Acked-by: Paolo Bonzini Reviewed-by: Paolo Bonzini --- arch/riscv/kvm/vcpu_exit.c | 72 ++++++++++++++++++++++++++++++++++++++ 1 file changed, 72 insertions(+) diff --git a/arch/riscv/kvm/vcpu_exit.c b/arch/riscv/kvm/vcpu_exit.c index f1378c0a447f..7507b859246b 100644 --- a/arch/riscv/kvm/vcpu_exit.c +++ b/arch/riscv/kvm/vcpu_exit.c @@ -12,6 +12,13 @@ #include #include +#define INSN_OPCODE_MASK 0x007c +#define INSN_OPCODE_SHIFT 2 +#define INSN_OPCODE_SYSTEM 28 + +#define INSN_MASK_WFI 0xffffff00 +#define INSN_MATCH_WFI 0x10500000 + #define INSN_MATCH_LB 0x3 #define INSN_MASK_LB 0x707f #define INSN_MATCH_LH 0x1003 @@ -116,6 +123,67 @@ (s32)(((insn) >> 7) & 0x1f)) #define MASK_FUNCT3 0x7000 +static int truly_illegal_insn(struct kvm_vcpu *vcpu, + struct kvm_run *run, + ulong insn) +{ + /* Redirect trap to Guest VCPU */ + kvm_riscv_vcpu_trap_redirect(vcpu, EXC_INST_ILLEGAL, insn); + + return 1; +} + +static int system_opcode_insn(struct kvm_vcpu *vcpu, + struct kvm_run *run, + ulong insn) +{ + if ((insn & INSN_MASK_WFI) == INSN_MATCH_WFI) { + vcpu->stat.wfi_exit_stat++; + if (!kvm_arch_vcpu_runnable(vcpu)) { + srcu_read_unlock(&vcpu->kvm->srcu, vcpu->arch.srcu_idx); + kvm_vcpu_block(vcpu); + vcpu->arch.srcu_idx = srcu_read_lock(&vcpu->kvm->srcu); + kvm_clear_request(KVM_REQ_UNHALT, vcpu); + } + vcpu->arch.guest_context.sepc += INSN_LEN(insn); + return 1; + } + + return truly_illegal_insn(vcpu, run, insn); +} + +static int illegal_inst_fault(struct kvm_vcpu *vcpu, struct kvm_run *run, + unsigned long insn) +{ + unsigned long ut_scause = 0; + struct kvm_cpu_context *ct; + + if (unlikely(INSN_IS_16BIT(insn))) { + if (insn == 0) { + ct = &vcpu->arch.guest_context; + insn = kvm_riscv_vcpu_unpriv_read(vcpu, true, + ct->sepc, + &ut_scause); + if (ut_scause) { + if (ut_scause == EXC_LOAD_PAGE_FAULT) + ut_scause = EXC_INST_PAGE_FAULT; + kvm_riscv_vcpu_trap_redirect(vcpu, ut_scause, + ct->sepc); + return 1; + } + } + if (INSN_IS_16BIT(insn)) + return truly_illegal_insn(vcpu, run, insn); + } + + switch ((insn & INSN_OPCODE_MASK) >> INSN_OPCODE_SHIFT) { + case INSN_OPCODE_SYSTEM: + return system_opcode_insn(vcpu, run, insn); + default: + return truly_illegal_insn(vcpu, run, insn); + } +} + static int emulate_load(struct kvm_vcpu *vcpu, struct kvm_run *run, unsigned long fault_addr) { @@ -508,6 +576,10 @@ int kvm_riscv_vcpu_exit(struct kvm_vcpu *vcpu, struct kvm_run *run, ret = -EFAULT; run->exit_reason = KVM_EXIT_UNKNOWN; switch (scause) { + case EXC_INST_ILLEGAL: + if (vcpu->arch.guest_context.hstatus & HSTATUS_SPV) + ret = illegal_inst_fault(vcpu, run, stval); + break; case EXC_INST_PAGE_FAULT: case EXC_LOAD_PAGE_FAULT: case EXC_STORE_PAGE_FAULT: From patchwork Thu Oct 3 05:07:46 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Anup Patel X-Patchwork-Id: 11172125 Return-Path: Received: from mail.kernel.org (pdx-korg-mail-1.web.codeaurora.org [172.30.200.123]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id 7B23B14DB for ; Thu, 3 Oct 2019 05:08:08 +0000 (UTC) Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id 5540E21D81 for ; Thu, 3 Oct 2019 05:08:08 +0000 (UTC) Authentication-Results: mail.kernel.org; dkim=pass (2048-bit key) header.d=lists.infradead.org header.i=@lists.infradead.org header.b="pQI7iC/+"; dkim=fail reason="signature verification failed" (2048-bit key) header.d=wdc.com header.i=@wdc.com header.b="jTgcvQRr"; dkim=fail reason="signature verification failed" (1024-bit key) header.d=sharedspace.onmicrosoft.com header.i=@sharedspace.onmicrosoft.com header.b="VgBcdk+H" DMARC-Filter: OpenDMARC Filter v1.3.2 mail.kernel.org 5540E21D81 Authentication-Results: mail.kernel.org; dmarc=fail (p=none dis=none) header.from=wdc.com Authentication-Results: mail.kernel.org; spf=none smtp.mailfrom=linux-riscv-bounces+patchwork-linux-riscv=patchwork.kernel.org@lists.infradead.org DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=bombadil.20170209; h=Sender: Content-Transfer-Encoding:Content-Type:Cc:List-Subscribe:List-Help:List-Post: List-Archive:List-Unsubscribe:List-Id:MIME-Version:In-Reply-To:References: Message-ID:Date:Subject:To:From:Reply-To:Content-ID:Content-Description: Resent-Date:Resent-From:Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID: List-Owner; bh=8eLLFK0Ij4Re6yc8mZaYh1minHaFG/cPquX5SrCVATQ=; b=pQI7iC/+xiGVYv FJLlnoSg8ci13GoKdi5nxKOtCizoB+kBbCWF1v6aLfhpUdhHqx1UDwCi912vfd11RmGvvJQx4Sxi7 2j4CdG1ti6lhvnBW8CqJJod/S/TtE1/dFlptPx6J7m7qdC3vuK37xRi/ghZUQIWaX3P/9YQy5ybpx AuaeGxrEmi7w6fBTQcsHbWAME88xOdF9oVmtKQPVvMjS0GuVms4smnNQV9yFz+VbAvgUDCS2Qxigz GVMLVyS7rJaAaUc5aKGggUsmDKh48JfmuMvSDwy021GJoddUCpTMagsFXrkuhLjale7QoNkpDFb/h 4CxHBHmP1SRymlwazmOQ==; Received: from localhost ([127.0.0.1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.92.2 #3 (Red Hat Linux)) id 1iFtLG-0003ur-0S; Thu, 03 Oct 2019 05:07:54 +0000 Received: from esa2.hgst.iphmx.com ([68.232.143.124]) by bombadil.infradead.org with esmtps (Exim 4.92.2 #3 (Red Hat Linux)) id 1iFtLC-0003tn-VP for linux-riscv@lists.infradead.org; Thu, 03 Oct 2019 05:07:52 +0000 DKIM-Signature: v=1; a=rsa-sha256; c=simple/simple; d=wdc.com; i=@wdc.com; q=dns/txt; s=dkim.wdc.com; t=1570079279; x=1601615279; h=from:to:cc:subject:date:message-id:references: in-reply-to:content-transfer-encoding:mime-version; bh=dhhRAL/QCUaVmnuGiFw0u+UVlMhi8hZSVM5IM81C7vk=; b=jTgcvQRrcUA8L+D5eFgsgItPmFtiKyF3vkuhbin1QbJFtErx++vozUCj 3BZHxix5X9fR2rnyC2898klPTjMKc+8OVYgjavEgmH40DG9OZTh2IzUlp IvvtezV+lA02IzHxaf8vHarOQ1YZEahYQWuumqC65iD/oBRe0IxQUYrDj VONANOdcpx75TME2auljY+OlDLmZ8v4xTaDzVwUUtLmZYP9JDlEskw/FP pSeLxf3h56Yhh4/BkBiO8R/Qceu9nfymNjsA3WdLBQQ2XHSaB92dQn4Nc P7NwGA4sUeInYGglX8jgP1WOwA1v5krBlgAYBRrCfK/imWFZvOYUUwXDa A==; IronPort-SDR: lHl9mrpd8WM3WjAfq9MbsaoPCsHYdeoTsKAWTlk5D8hLP5yhrY0jglf90gOxnaAiax0QOYc7aA pVHYjz7MA5g9MBf3fHScH/8CEh21EtUQ3WcitUs1ApcaJDtfKioeTOieVBUfozdsVIpFQ9pcXi 8GZbmE0285b+nX7KHMiODo+RFRMdQKzR58JKxOFVeB4S9MCdQmeqqHcySyU29VHo8I7XsEqn4P 0Pm9FsYCddCpmSukRkmLYYnYamKmK4tes04QWd/YZb3pFpPlCQBHhtzc6wvoVGLRYAwBqm4uGW Km8= X-IronPort-AV: E=Sophos;i="5.67,251,1566835200"; d="scan'208";a="220620903" Received: from mail-co1nam05lp2057.outbound.protection.outlook.com (HELO NAM05-CO1-obe.outbound.protection.outlook.com) ([104.47.48.57]) by ob1.hgst.iphmx.com with ESMTP; 03 Oct 2019 13:07:54 +0800 ARC-Seal: i=1; a=rsa-sha256; s=arcselector9901; d=microsoft.com; cv=none; b=ggMZcNeNeZ1+3+Gf94HBhnxddIwtE0B8rNWc8OPpWA8ViaUmW02oVDIhZ71i9cY3us+Kz9M4nQndytBnRDT/DbE7j/oPwrlxjn7d5YJ06jw2nO8Wchhb65esNMlGhPHSiNZ/NmdH7IsbQ9Mp8NzS9xMG/tLH4veWD/o3rHbCeHSDHMKMtl58haipabg/tAXcTvnYq1ct953iIDMt9ntDXKN4Ps+Mbh8G1IYkmLLpldpwdhSRZfzpb0WUrJ+McKUI5eHN29CWgYnb8WfZ6VJfdQRLwkydgzUvhtU2zUne9G+R5DaeStKENU2wUjXc0zUZoHoi83OQ1Tf2xiGRqhlnpA== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=microsoft.com; s=arcselector9901; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-SenderADCheck; bh=BrE+9FbOraoZqJhHfya3QZRHcV1Gfar4bGUAp2KdUjE=; b=Fe2lR/+mFdcC9RjjyApo+Kz/5AiItZsnwiRi7Ch52bev2uRuLgHb6S0Ck+UsM2qvl+vnqex8l8kzwuAxXnPNkgXW73OpDT8y2v5lJxUhH8uB+k/CIDJoCoyWfH5i+etUOxD5cn4g7ZyUC8a+GsJvhMT0dEcIA2LYPaqjZAcTpzz37jnYhCuO1AWPek/T1xFnnRP0S5p2sn+1eJezvl7BxrjRyj8a/vo6K1ohlPGHodJzWNDQVYeCQc3hWSxY7nBazBIjznY2Fyfq6wW/BG1goPVvSARwd2b+ftzLPBMvQUJcEErV3sPEv0VhTCEgOnDxH4VwcxMfnCk/VKaxvf4oCA== ARC-Authentication-Results: i=1; mx.microsoft.com 1; spf=pass smtp.mailfrom=wdc.com; dmarc=pass action=none header.from=wdc.com; dkim=pass header.d=wdc.com; arc=none DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=sharedspace.onmicrosoft.com; s=selector2-sharedspace-onmicrosoft-com; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-SenderADCheck; bh=BrE+9FbOraoZqJhHfya3QZRHcV1Gfar4bGUAp2KdUjE=; b=VgBcdk+HkK+Hriq/aS7GLN2+DAJNANv/0G2DCtcVLl48NSiSNeA5oMKVMTdAoFX5yfFln/OS+fnPDwDx5PuazAwZhYORIYBRk3PWtscdtA5OcQlEfNXn8EC5Cmqi006qD1TiIt/SLrGrYQaVkdbCDhgKIvoA3iW/xT6xiH4DjLI= Received: from MN2PR04MB6061.namprd04.prod.outlook.com (20.178.246.15) by MN2PR04MB6272.namprd04.prod.outlook.com (20.178.248.27) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.2305.17; Thu, 3 Oct 2019 05:07:47 +0000 Received: from MN2PR04MB6061.namprd04.prod.outlook.com ([fe80::1454:87a:13b0:d3a]) by MN2PR04MB6061.namprd04.prod.outlook.com ([fe80::1454:87a:13b0:d3a%7]) with mapi id 15.20.2305.023; Thu, 3 Oct 2019 05:07:47 +0000 From: Anup Patel To: Palmer Dabbelt , Paul Walmsley , Paolo Bonzini , Radim K Subject: [PATCH v8 10/19] RISC-V: KVM: Implement VMID allocator Thread-Topic: [PATCH v8 10/19] RISC-V: KVM: Implement VMID allocator Thread-Index: AQHVeah+N4zRyfkY7kyusNO87Yk5bw== Date: Thu, 3 Oct 2019 05:07:46 +0000 Message-ID: <20191003050558.9031-11-anup.patel@wdc.com> References: <20191003050558.9031-1-anup.patel@wdc.com> In-Reply-To: <20191003050558.9031-1-anup.patel@wdc.com> Accept-Language: en-US Content-Language: en-US X-MS-Has-Attach: X-MS-TNEF-Correlator: x-clientproxiedby: BMXPR01CA0030.INDPRD01.PROD.OUTLOOK.COM (2603:1096:b00:c::16) To MN2PR04MB6061.namprd04.prod.outlook.com (2603:10b6:208:d8::15) authentication-results: spf=none (sender IP is ) smtp.mailfrom=Anup.Patel@wdc.com; x-ms-exchange-messagesentrepresentingtype: 1 x-mailer: git-send-email 2.17.1 x-originating-ip: [111.235.74.37] x-ms-publictraffictype: Email x-ms-office365-filtering-correlation-id: 63c11f5b-3600-485d-db2d-08d747bfa136 x-ms-office365-filtering-ht: Tenant x-ms-traffictypediagnostic: MN2PR04MB6272: x-ms-exchange-transport-forked: True x-microsoft-antispam-prvs: wdcipoutbound: EOP-TRUE x-ms-oob-tlc-oobclassifiers: OLM:8273; x-forefront-prvs: 01792087B6 x-forefront-antispam-report: SFV:NSPM; SFS:(10019020)(4636009)(136003)(376002)(346002)(366004)(396003)(39860400002)(189003)(199004)(6512007)(6486002)(81166006)(81156014)(8936002)(6116002)(3846002)(8676002)(50226002)(2906002)(110136005)(66066001)(6436002)(316002)(66476007)(66556008)(7416002)(66446008)(36756003)(1076003)(5660300002)(54906003)(7736002)(305945005)(76176011)(25786009)(52116002)(256004)(14444005)(71190400001)(86362001)(99286004)(71200400001)(2616005)(446003)(14454004)(476003)(102836004)(186003)(26005)(11346002)(44832011)(6506007)(486006)(478600001)(4326008)(66946007)(386003)(64756008); DIR:OUT; SFP:1102; SCL:1; SRVR:MN2PR04MB6272; H:MN2PR04MB6061.namprd04.prod.outlook.com; FPR:; SPF:None; LANG:en; PTR:InfoNoRecords; MX:1; A:1; x-ms-exchange-senderadcheck: 1 x-microsoft-antispam: BCL:0; x-microsoft-antispam-message-info: WW3KAayJauQUOR0mcCsai1t7mWqaNCem+6x3rwlFjWHEFZB3O4uf06eQMUBsk7hCTmOu59y9yBTOiM4LNJldyBI+UHftf9wuASxpi8XNazNu/NDfLrZ30zecFMt+rooWHgsAbVh0DCxTtm8feixxSLv7h+CqG6tHNeDtVAlfZ+RA5Z8SZkjSKLyZ9PCZzJ/x1ghOM941dkrJxwdq1R0FSoNt47YCOUBHLAhx3/yTdJMHGd5tl9mFXbdZQPVjZo7L72bLov8hl7KKk/dGHeB5mkBYhl42OLTgjRs0Y980vWQcOlW7m30L/l7PVKOBNZsruLesXC9gRn7Qwzq3l7l18lSjnTmY4cxEx2aklxprQVV9ijxjvwQX+/fIwjb9X7vu6IMJqUnyZgF5pbCCGpBd6CFFl954dHm4H9q/mWrCnyo= MIME-Version: 1.0 X-OriginatorOrg: wdc.com X-MS-Exchange-CrossTenant-Network-Message-Id: 63c11f5b-3600-485d-db2d-08d747bfa136 X-MS-Exchange-CrossTenant-originalarrivaltime: 03 Oct 2019 05:07:46.8575 (UTC) X-MS-Exchange-CrossTenant-fromentityheader: Hosted X-MS-Exchange-CrossTenant-id: b61c8803-16f3-4c35-9b17-6f65f441df86 X-MS-Exchange-CrossTenant-mailboxtype: HOSTED X-MS-Exchange-CrossTenant-userprincipalname: s34fuVkrOtPHADx7RyJcPQWn1bfaSuzhGuzucdDjHboa87wRIcwma7WSIo4RUhCU88ONwaP2LX8OUFtrWkvpow== X-MS-Exchange-Transport-CrossTenantHeadersStamped: MN2PR04MB6272 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20191002_220751_081103_F5EDB33A X-CRM114-Status: GOOD ( 19.66 ) X-Spam-Score: -2.5 (--) X-Spam-Report: SpamAssassin version 3.4.2 on bombadil.infradead.org summary: Content analysis details: (-2.5 points) pts rule name description ---- ---------------------- -------------------------------------------------- -2.3 RCVD_IN_DNSWL_MED RBL: Sender listed at https://www.dnswl.org/, medium trust [68.232.143.124 listed in list.dnswl.org] -0.0 SPF_PASS SPF: sender matches SPF record 0.0 SPF_HELO_NONE SPF: HELO does not publish an SPF Record -0.1 DKIM_VALID_EF Message has a valid DKIM or DK signature from envelope-from domain 0.1 DKIM_SIGNED Message has a DKIM or DK signature, not necessarily valid -0.1 DKIM_VALID_AU Message has a valid DKIM or DK signature from author's domain -0.1 DKIM_VALID Message has at least one valid DKIM or DK signature X-BeenThere: linux-riscv@lists.infradead.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Damien Le Moal , Anup Patel , "kvm@vger.kernel.org" , Anup Patel , Daniel Lezcano , "linux-kernel@vger.kernel.org" , Christoph Hellwig , Atish Patra , Alexander Graf , Alistair Francis , Thomas Gleixner , "linux-riscv@lists.infradead.org" Sender: "linux-riscv" Errors-To: linux-riscv-bounces+patchwork-linux-riscv=patchwork.kernel.org@lists.infradead.org We implement a simple VMID allocator for Guests/VMs which: 1. Detects number of VMID bits at boot-time 2. Uses atomic number to track VMID version and increments VMID version whenever we run-out of VMIDs 3. Flushes Guest TLBs on all host CPUs whenever we run-out of VMIDs 4. Force updates HW Stage2 VMID for each Guest VCPU whenever VMID changes using VCPU request KVM_REQ_UPDATE_HGATP Signed-off-by: Anup Patel Acked-by: Paolo Bonzini Reviewed-by: Paolo Bonzini Reviewed-by: Alexander Graf --- arch/riscv/include/asm/kvm_host.h | 25 ++++++ arch/riscv/kvm/Makefile | 3 +- arch/riscv/kvm/main.c | 4 + arch/riscv/kvm/tlb.S | 43 +++++++++++ arch/riscv/kvm/vcpu.c | 9 +++ arch/riscv/kvm/vm.c | 6 ++ arch/riscv/kvm/vmid.c | 123 ++++++++++++++++++++++++++++++ 7 files changed, 212 insertions(+), 1 deletion(-) create mode 100644 arch/riscv/kvm/tlb.S create mode 100644 arch/riscv/kvm/vmid.c diff --git a/arch/riscv/include/asm/kvm_host.h b/arch/riscv/include/asm/kvm_host.h index 2a5209fff68d..8aaf22a900be 100644 --- a/arch/riscv/include/asm/kvm_host.h +++ b/arch/riscv/include/asm/kvm_host.h @@ -27,6 +27,7 @@ #define KVM_REQ_SLEEP \ KVM_ARCH_REQ_FLAGS(0, KVM_REQUEST_WAIT | KVM_REQUEST_NO_WAKEUP) #define KVM_REQ_VCPU_RESET KVM_ARCH_REQ(1) +#define KVM_REQ_UPDATE_HGATP KVM_ARCH_REQ(2) struct kvm_vm_stat { ulong remote_tlb_flush; @@ -47,7 +48,19 @@ struct kvm_vcpu_stat { struct kvm_arch_memory_slot { }; +struct kvm_vmid { + /* + * Writes to vmid_version and vmid happen with vmid_lock held + * whereas reads happen without any lock held. + */ + unsigned long vmid_version; + unsigned long vmid; +}; + struct kvm_arch { + /* stage2 vmid */ + struct kvm_vmid vmid; + /* stage2 page table */ pgd_t *pgd; phys_addr_t pgd_phys; @@ -170,6 +183,12 @@ static inline void kvm_arch_vcpu_block_finish(struct kvm_vcpu *vcpu) {} int kvm_riscv_setup_vsip(void); void kvm_riscv_cleanup_vsip(void); +void __kvm_riscv_hfence_gvma_vmid_gpa(unsigned long vmid, + unsigned long gpa); +void __kvm_riscv_hfence_gvma_vmid(unsigned long vmid); +void __kvm_riscv_hfence_gvma_gpa(unsigned long gpa); +void __kvm_riscv_hfence_gvma_all(void); + int kvm_riscv_stage2_map(struct kvm_vcpu *vcpu, gpa_t gpa, unsigned long hva, bool is_write); void kvm_riscv_stage2_flush_cache(struct kvm_vcpu *vcpu); @@ -177,6 +196,12 @@ int kvm_riscv_stage2_alloc_pgd(struct kvm *kvm); void kvm_riscv_stage2_free_pgd(struct kvm *kvm); void kvm_riscv_stage2_update_hgatp(struct kvm_vcpu *vcpu); +void kvm_riscv_stage2_vmid_detect(void); +unsigned long kvm_riscv_stage2_vmid_bits(void); +int kvm_riscv_stage2_vmid_init(struct kvm *kvm); +bool kvm_riscv_stage2_vmid_ver_changed(struct kvm_vmid *vmid); +void kvm_riscv_stage2_vmid_update(struct kvm_vcpu *vcpu); + void __kvm_riscv_unpriv_trap(void); unsigned long kvm_riscv_vcpu_unpriv_read(struct kvm_vcpu *vcpu, diff --git a/arch/riscv/kvm/Makefile b/arch/riscv/kvm/Makefile index 845579273727..c0f57f26c13d 100644 --- a/arch/riscv/kvm/Makefile +++ b/arch/riscv/kvm/Makefile @@ -8,6 +8,7 @@ ccflags-y := -Ivirt/kvm -Iarch/riscv/kvm kvm-objs := $(common-objs-y) -kvm-objs += main.o vm.o mmu.o vcpu.o vcpu_exit.o vcpu_switch.o +kvm-objs += main.o vm.o vmid.o tlb.o mmu.o +kvm-objs += vcpu.o vcpu_exit.o vcpu_switch.o obj-$(CONFIG_KVM) += kvm.o diff --git a/arch/riscv/kvm/main.c b/arch/riscv/kvm/main.c index d088247843c5..55df85184241 100644 --- a/arch/riscv/kvm/main.c +++ b/arch/riscv/kvm/main.c @@ -72,8 +72,12 @@ int kvm_arch_init(void *opaque) if (ret) return ret; + kvm_riscv_stage2_vmid_detect(); + kvm_info("hypervisor extension available\n"); + kvm_info("host has %ld VMID bits\n", kvm_riscv_stage2_vmid_bits()); + return 0; } diff --git a/arch/riscv/kvm/tlb.S b/arch/riscv/kvm/tlb.S new file mode 100644 index 000000000000..453fca8d7940 --- /dev/null +++ b/arch/riscv/kvm/tlb.S @@ -0,0 +1,43 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +/* + * Copyright (C) 2019 Western Digital Corporation or its affiliates. + * + * Authors: + * Anup Patel + */ + +#include +#include + + .text + .altmacro + .option norelax + + /* + * Instruction encoding of hfence.gvma is: + * 0110001 rs2(5) rs1(5) 000 00000 1110011 + */ + +ENTRY(__kvm_riscv_hfence_gvma_vmid_gpa) + /* hfence.gvma a1, a0 */ + .word 0x62a60073 + ret +ENDPROC(__kvm_riscv_hfence_gvma_vmid_gpa) + +ENTRY(__kvm_riscv_hfence_gvma_vmid) + /* hfence.gvma zero, a0 */ + .word 0x62a00073 + ret +ENDPROC(__kvm_riscv_hfence_gvma_vmid) + +ENTRY(__kvm_riscv_hfence_gvma_gpa) + /* hfence.gvma a0 */ + .word 0x62050073 + ret +ENDPROC(__kvm_riscv_hfence_gvma_gpa) + +ENTRY(__kvm_riscv_hfence_gvma_all) + /* hfence.gvma */ + .word 0x62000073 + ret +ENDPROC(__kvm_riscv_hfence_gvma_all) diff --git a/arch/riscv/kvm/vcpu.c b/arch/riscv/kvm/vcpu.c index 38a35367fb83..12bd837f564a 100644 --- a/arch/riscv/kvm/vcpu.c +++ b/arch/riscv/kvm/vcpu.c @@ -641,6 +641,12 @@ static void kvm_riscv_check_vcpu_requests(struct kvm_vcpu *vcpu) if (kvm_check_request(KVM_REQ_VCPU_RESET, vcpu)) kvm_riscv_reset_vcpu(vcpu); + + if (kvm_check_request(KVM_REQ_UPDATE_HGATP, vcpu)) + kvm_riscv_stage2_update_hgatp(vcpu); + + if (kvm_check_request(KVM_REQ_TLB_FLUSH, vcpu)) + __kvm_riscv_hfence_gvma_all(); } } @@ -703,6 +709,8 @@ int kvm_arch_vcpu_ioctl_run(struct kvm_vcpu *vcpu, struct kvm_run *run) /* Check conditions before entering the guest */ cond_resched(); + kvm_riscv_stage2_vmid_update(vcpu); + kvm_riscv_check_vcpu_requests(vcpu); preempt_disable(); @@ -739,6 +747,7 @@ int kvm_arch_vcpu_ioctl_run(struct kvm_vcpu *vcpu, struct kvm_run *run) kvm_riscv_update_vsip(vcpu); if (ret <= 0 || + kvm_riscv_stage2_vmid_ver_changed(&vcpu->kvm->arch.vmid) || kvm_request_pending(vcpu)) { vcpu->mode = OUTSIDE_GUEST_MODE; local_irq_enable(); diff --git a/arch/riscv/kvm/vm.c b/arch/riscv/kvm/vm.c index ac0211820521..c5aab5478c38 100644 --- a/arch/riscv/kvm/vm.c +++ b/arch/riscv/kvm/vm.c @@ -26,6 +26,12 @@ int kvm_arch_init_vm(struct kvm *kvm, unsigned long type) if (r) return r; + r = kvm_riscv_stage2_vmid_init(kvm); + if (r) { + kvm_riscv_stage2_free_pgd(kvm); + return r; + } + return 0; } diff --git a/arch/riscv/kvm/vmid.c b/arch/riscv/kvm/vmid.c new file mode 100644 index 000000000000..69f770fa4f46 --- /dev/null +++ b/arch/riscv/kvm/vmid.c @@ -0,0 +1,123 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Copyright (C) 2019 Western Digital Corporation or its affiliates. + * + * Authors: + * Anup Patel + */ + +#include +#include +#include +#include +#include +#include +#include + +static unsigned long vmid_version = 1; +static unsigned long vmid_next; +static unsigned long vmid_bits; +static DEFINE_SPINLOCK(vmid_lock); + +void kvm_riscv_stage2_vmid_detect(void) +{ + unsigned long old; + + /* Figure-out number of VMID bits in HW */ + old = csr_read(CSR_HGATP); + csr_write(CSR_HGATP, old | HGATP_VMID_MASK); + vmid_bits = csr_read(CSR_HGATP); + vmid_bits = (vmid_bits & HGATP_VMID_MASK) >> HGATP_VMID_SHIFT; + vmid_bits = fls_long(vmid_bits); + csr_write(CSR_HGATP, old); + + /* We polluted local TLB so flush all guest TLB */ + __kvm_riscv_hfence_gvma_all(); + + /* We don't use VMID bits if they are not sufficient */ + if ((1UL << vmid_bits) < num_possible_cpus()) + vmid_bits = 0; +} + +unsigned long kvm_riscv_stage2_vmid_bits(void) +{ + return vmid_bits; +} + +int kvm_riscv_stage2_vmid_init(struct kvm *kvm) +{ + /* Mark the initial VMID and VMID version invalid */ + kvm->arch.vmid.vmid_version = 0; + kvm->arch.vmid.vmid = 0; + + return 0; +} + +static void local_guest_tlb_flush_all(void *info) +{ + __kvm_riscv_hfence_gvma_all(); +} + +bool kvm_riscv_stage2_vmid_ver_changed(struct kvm_vmid *vmid) +{ + if (!vmid_bits) + return false; + + return unlikely(READ_ONCE(vmid->vmid_version) != + READ_ONCE(vmid_version)); +} + +void kvm_riscv_stage2_vmid_update(struct kvm_vcpu *vcpu) +{ + int i; + struct kvm_vcpu *v; + struct kvm_vmid *vmid = &vcpu->kvm->arch.vmid; + + if (!kvm_riscv_stage2_vmid_ver_changed(vmid)) + return; + + spin_lock(&vmid_lock); + + /* + * We need to re-check the vmid_version here to ensure that if + * another vcpu already allocated a valid vmid for this vm. + */ + if (!kvm_riscv_stage2_vmid_ver_changed(vmid)) { + spin_unlock(&vmid_lock); + return; + } + + /* First user of a new VMID version? */ + if (unlikely(vmid_next == 0)) { + WRITE_ONCE(vmid_version, READ_ONCE(vmid_version) + 1); + vmid_next = 1; + + /* + * We ran out of VMIDs so we increment vmid_version and + * start assigning VMIDs from 1. + * + * This also means existing VMIDs assignement to all Guest + * instances is invalid and we have force VMID re-assignement + * for all Guest instances. The Guest instances that were not + * running will automatically pick-up new VMIDs because will + * call kvm_riscv_stage2_vmid_update() whenever they enter + * in-kernel run loop. For Guest instances that are already + * running, we force VM exits on all host CPUs using IPI and + * flush all Guest TLBs. + */ + smp_call_function_many(cpu_online_mask, + local_guest_tlb_flush_all, NULL, true); + } + + vmid->vmid = vmid_next; + vmid_next++; + vmid_next &= (1 << vmid_bits) - 1; + + WRITE_ONCE(vmid->vmid_version, READ_ONCE(vmid_version)); + + spin_unlock(&vmid_lock); + + /* Request stage2 page table update for all VCPUs */ + kvm_for_each_vcpu(i, v, vcpu->kvm) + kvm_make_request(KVM_REQ_UPDATE_HGATP, v); +} From patchwork Thu Oct 3 05:07:54 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Anup Patel X-Patchwork-Id: 11172129 Return-Path: Received: from mail.kernel.org (pdx-korg-mail-1.web.codeaurora.org [172.30.200.123]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id 8B1E317EE for ; Thu, 3 Oct 2019 05:08:15 +0000 (UTC) Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id 646A421D81 for ; Thu, 3 Oct 2019 05:08:15 +0000 (UTC) Authentication-Results: mail.kernel.org; dkim=pass (2048-bit key) header.d=lists.infradead.org header.i=@lists.infradead.org header.b="uP0PDx7X"; dkim=fail reason="signature verification failed" (2048-bit key) header.d=wdc.com header.i=@wdc.com header.b="CxqHTxnS"; dkim=fail reason="signature verification failed" (1024-bit key) header.d=sharedspace.onmicrosoft.com header.i=@sharedspace.onmicrosoft.com header.b="p0R7M+7l" DMARC-Filter: OpenDMARC Filter v1.3.2 mail.kernel.org 646A421D81 Authentication-Results: mail.kernel.org; dmarc=fail (p=none dis=none) header.from=wdc.com Authentication-Results: mail.kernel.org; spf=none smtp.mailfrom=linux-riscv-bounces+patchwork-linux-riscv=patchwork.kernel.org@lists.infradead.org DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=bombadil.20170209; h=Sender: Content-Transfer-Encoding:Content-Type:Cc:List-Subscribe:List-Help:List-Post: List-Archive:List-Unsubscribe:List-Id:MIME-Version:In-Reply-To:References: Message-ID:Date:Subject:To:From:Reply-To:Content-ID:Content-Description: Resent-Date:Resent-From:Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID: List-Owner; bh=azdBvq/pFjUNpmQGd9zUmyK/qDgV1Ywv6SvdxNG3/Z8=; b=uP0PDx7X4mePrV Irzqzm7KAzethZHVNIBP9st3NrKVMbOdLO4WVBE4rRJZK4clNpbG34O8VqQmamUfN8XxqT/V/+fQE 6Xqe4rUYFyZ7ZwQYq2yOksP7RlGaT8fsxhObBzydibEY8rSaEpikn12P97o8V+sO/YvSCAY216XkA 3xsIWxqDXYiq+O+Pf0ktb/KBRh4tbLy6FBdBQEa6MU7iPBHgwOD11gmHHAtW9mWOZv7Dhp40NWWVr 7teWx7Zl+0A1gGGZyILIrocDHoCaZaoupid/kREYXBVQ8ftayonhIDLlJuu0ENAusp/JYStKHkO5p tqk7kdXr18H3mckoRrag==; Received: from localhost ([127.0.0.1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.92.2 #3 (Red Hat Linux)) id 1iFtLN-0003zN-VG; Thu, 03 Oct 2019 05:08:01 +0000 Received: from esa6.hgst.iphmx.com ([216.71.154.45]) by bombadil.infradead.org with esmtps (Exim 4.92.2 #3 (Red Hat Linux)) id 1iFtLK-0003yh-Ch for linux-riscv@lists.infradead.org; Thu, 03 Oct 2019 05:08:00 +0000 DKIM-Signature: v=1; a=rsa-sha256; c=simple/simple; d=wdc.com; i=@wdc.com; q=dns/txt; s=dkim.wdc.com; t=1570079279; x=1601615279; h=from:to:cc:subject:date:message-id:references: in-reply-to:content-transfer-encoding:mime-version; bh=O86QEd2/Ap83HX4BVDcg/Sbp08Hv2IsfYfDeY1MjDxE=; b=CxqHTxnSyOkxOISOpaC8H/S5vELssqorBHmqh74cK6OaT6RVdrBXWC1k fmpbOn9rdVPhH3udlCTkHMnKXOBiIO69PbKInDSnJWtKHtrdyfxt26B7k BN3flvLyHSX9nYsK/mthnag1a+b5VvStL8ue7oPnMmRqKzEssfqOZhfaS aWLqUwEvox1BrpIEUcCnjTprH2k8LTKEX9XzhEvJjAqnIWKyu43Oab/IR v8XD+oIIJ3xrTUUiI632jIvkEHfOPk20YKYxK0vIAWxU53+gnz3jroAdT f7ea5dEBKOyKFHTniSKQXM6oy63FR7METtjptHWGAeXgyGkeqd9aiuYwR A==; IronPort-SDR: 2ur+IpQfEj6TQuagTEFlf3WHr42gHLb93QJYpPqnqURYUGgKQDYwwX4Kf90ockejJsKJTjpwAb 5fWD592LYeaWLb1E65UQdOdlcu4OG2fXFL+hN6pCpIrQzA67S0SQveLTjzmyWoRS0GhNQcKVq7 xvyWWwvHLzTfPDm5vTphcDTnlQ9d6mV6WImLuPOvJSWtd+/mrfxkgCfqLSanQ6hkYEWZf7rOiz ijqDll/VEizxKPh0yG3Aqp06ig2k2YO/0i2KGrGs4aAjXqCToNzDQ7hSMRmq/ZXLLhDPgRyyw9 g30= X-IronPort-AV: E=Sophos;i="5.67,251,1566835200"; d="scan'208";a="121261251" Received: from mail-co1nam05lp2054.outbound.protection.outlook.com (HELO NAM05-CO1-obe.outbound.protection.outlook.com) ([104.47.48.54]) by ob1.hgst.iphmx.com with ESMTP; 03 Oct 2019 13:07:57 +0800 ARC-Seal: i=1; a=rsa-sha256; s=arcselector9901; d=microsoft.com; cv=none; b=Z0qAiql021B8hOYb7ySthr+72utiXAF7FjIMnCCV3o5Ctvyf1gIbBK4XHqb9VdaHmpuTKdewejAwS7IslxsyBrJz29D1wbsTcw1MGZ+i2MB7vJGtqnRsKlZgJvJ2WL2u5ovgkiqzwqCxMpx1Z4GOj65DSxHO2CdyH21qlVcbkjA0+qHtVU54xHKUsWs/Sy7OITXruBPDjJvO16BK2Fan9NAFv93JwySJBL42Lty2wu54QkmThQlvasnnY7EKyt6TZ+COkm61r91LBhRjKLJQ+jBK5QXnOC4CF+350FLKUzJrlBsBHkxjBe2tbCoiT5YkM5cSGr430cK63oZNlTQ5wA== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=microsoft.com; s=arcselector9901; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-SenderADCheck; bh=jLpgtRZMw1Ojfk9bSlEqp/0+tvj0Ky+rChbEzaumqXQ=; b=Ecu9yax5VFZx9CRiYwcOzbxuP/M7pNscHWffRx82p1UdghnXLmx1ZLFM/frgXXDX+S8oADgT2kaF3d6gnz3FuribBHUlwvDWFrsqp9Vno/rjMsk1t/Pq2Cnt0I6Yc0YJEPtTqHsegaIKkG9a+z09O5698T/B9pCg+PObzdXBoKdMVu0k9GNcG8Ma1gp703jvkggsRax1YueVBITCoqNLseFDQi6uf4vRyEOeX5y+EjpmWGbQN7Zmaz4X6SjoLCiL1Zki5sdeGpm9//4uaXVi7aM5HaHPpAY7V+GH+ZTgDjjh5fXFunb7QG3cCxT/L5tG3L9XltY+BZY/4zLKkz/+BQ== ARC-Authentication-Results: i=1; mx.microsoft.com 1; spf=pass smtp.mailfrom=wdc.com; dmarc=pass action=none header.from=wdc.com; dkim=pass header.d=wdc.com; arc=none DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=sharedspace.onmicrosoft.com; s=selector2-sharedspace-onmicrosoft-com; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-SenderADCheck; bh=jLpgtRZMw1Ojfk9bSlEqp/0+tvj0Ky+rChbEzaumqXQ=; b=p0R7M+7lZkxdKHddWBwWRG1clctqo5yBFkuG2HP7A7atoT/rzI7dqcWAD9HdaJuM10/1lIIiFvCHfkhqW/2+unhfzu/xsXOLrXuf+1NytiHejawj1vSvskYa0HTC0J+bAU3P+NfBM5tCpGSFayaK69AP4agDSluR2bSiiYezikk= Received: from MN2PR04MB6061.namprd04.prod.outlook.com (20.178.246.15) by MN2PR04MB6272.namprd04.prod.outlook.com (20.178.248.27) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.2305.17; Thu, 3 Oct 2019 05:07:54 +0000 Received: from MN2PR04MB6061.namprd04.prod.outlook.com ([fe80::1454:87a:13b0:d3a]) by MN2PR04MB6061.namprd04.prod.outlook.com ([fe80::1454:87a:13b0:d3a%7]) with mapi id 15.20.2305.023; Thu, 3 Oct 2019 05:07:54 +0000 From: Anup Patel To: Palmer Dabbelt , Paul Walmsley , Paolo Bonzini , Radim K Subject: [PATCH v8 11/19] RISC-V: KVM: Implement stage2 page table programming Thread-Topic: [PATCH v8 11/19] RISC-V: KVM: Implement stage2 page table programming Thread-Index: AQHVeaiDdOROD9D9OUqAa/TK6yvaiw== Date: Thu, 3 Oct 2019 05:07:54 +0000 Message-ID: <20191003050558.9031-12-anup.patel@wdc.com> References: <20191003050558.9031-1-anup.patel@wdc.com> In-Reply-To: <20191003050558.9031-1-anup.patel@wdc.com> Accept-Language: en-US Content-Language: en-US X-MS-Has-Attach: X-MS-TNEF-Correlator: x-clientproxiedby: BMXPR01CA0030.INDPRD01.PROD.OUTLOOK.COM (2603:1096:b00:c::16) To MN2PR04MB6061.namprd04.prod.outlook.com (2603:10b6:208:d8::15) authentication-results: spf=none (sender IP is ) smtp.mailfrom=Anup.Patel@wdc.com; x-ms-exchange-messagesentrepresentingtype: 1 x-mailer: git-send-email 2.17.1 x-originating-ip: [111.235.74.37] x-ms-publictraffictype: Email x-ms-office365-filtering-correlation-id: 3c4061c1-e268-4560-1f16-08d747bfa5ef x-ms-office365-filtering-ht: Tenant x-ms-traffictypediagnostic: MN2PR04MB6272: x-ms-exchange-transport-forked: True x-microsoft-antispam-prvs: wdcipoutbound: EOP-TRUE x-ms-oob-tlc-oobclassifiers: OLM:3044; x-forefront-prvs: 01792087B6 x-forefront-antispam-report: SFV:NSPM; SFS:(10019020)(4636009)(136003)(376002)(346002)(366004)(396003)(39860400002)(189003)(199004)(6512007)(6486002)(81166006)(81156014)(8936002)(6116002)(3846002)(8676002)(50226002)(2906002)(110136005)(66066001)(6436002)(316002)(66476007)(66556008)(7416002)(66446008)(36756003)(1076003)(5660300002)(54906003)(7736002)(305945005)(76176011)(30864003)(25786009)(52116002)(256004)(14444005)(71190400001)(86362001)(99286004)(71200400001)(2616005)(446003)(14454004)(476003)(102836004)(186003)(26005)(11346002)(44832011)(6506007)(486006)(478600001)(4326008)(66946007)(386003)(64756008); DIR:OUT; SFP:1102; SCL:1; SRVR:MN2PR04MB6272; H:MN2PR04MB6061.namprd04.prod.outlook.com; FPR:; SPF:None; LANG:en; PTR:InfoNoRecords; MX:1; A:1; x-ms-exchange-senderadcheck: 1 x-microsoft-antispam: BCL:0; x-microsoft-antispam-message-info: pcDEk0TF0iCLsGPG0wL2YcXWABZYrKi7mdKRGYgpDUhHH6J+kcocJZdIn1dN9BgzP1/4RIfRsrQG+ls2qf5gjK/R/HM/Vb024Rbpy8CrkYoSIyH4rg4mrJZLjJsyGl1aMSrLzcr3SHaUalCdFHW6OS+qWJxEx4V65Da6wZfxbaQW2BvA7VI2/9fVKOcFaojVRW4Ejtv+u13z11DlG8Wcmk1Ah4n5J4gbUFF+8LvpJcUYhF0lJxLZW+cxj3QsJzjUs7vJ4dBwrW2p+4rBKRMw9P4sVDCiTpNkkyVx+PGPYDLbNFBEyP+5edPhKWQ87KkcMQU2fyCv4eEFGi2o1M7wENRWao7GPZ9+OUNyvb2dFVTRZEdbWCmKl7wk0wyxMZaAY1eoROwiUU7/Gq1Ee2rV+M0mRc0YL7twfmLphPCJlsE= MIME-Version: 1.0 X-OriginatorOrg: wdc.com X-MS-Exchange-CrossTenant-Network-Message-Id: 3c4061c1-e268-4560-1f16-08d747bfa5ef X-MS-Exchange-CrossTenant-originalarrivaltime: 03 Oct 2019 05:07:54.8219 (UTC) X-MS-Exchange-CrossTenant-fromentityheader: Hosted X-MS-Exchange-CrossTenant-id: b61c8803-16f3-4c35-9b17-6f65f441df86 X-MS-Exchange-CrossTenant-mailboxtype: HOSTED X-MS-Exchange-CrossTenant-userprincipalname: LGfGlZRXOh3nG7Vt6LP5ZGaYtCPTRLYiCE5Cx9Qw4o8X37rp83Mio09vBKM3jXRo8m5phRSz2LZ5gYpC24rTZg== X-MS-Exchange-Transport-CrossTenantHeadersStamped: MN2PR04MB6272 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20191002_220758_496420_07ABA353 X-CRM114-Status: GOOD ( 20.41 ) X-Spam-Score: -2.5 (--) X-Spam-Report: SpamAssassin version 3.4.2 on bombadil.infradead.org summary: Content analysis details: (-2.5 points) pts rule name description ---- ---------------------- -------------------------------------------------- -2.3 RCVD_IN_DNSWL_MED RBL: Sender listed at https://www.dnswl.org/, medium trust [216.71.154.45 listed in list.dnswl.org] -0.0 SPF_PASS SPF: sender matches SPF record 0.0 SPF_HELO_NONE SPF: HELO does not publish an SPF Record -0.1 DKIM_VALID_EF Message has a valid DKIM or DK signature from envelope-from domain 0.1 DKIM_SIGNED Message has a DKIM or DK signature, not necessarily valid -0.1 DKIM_VALID_AU Message has a valid DKIM or DK signature from author's domain -0.1 DKIM_VALID Message has at least one valid DKIM or DK signature X-BeenThere: linux-riscv@lists.infradead.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Damien Le Moal , Anup Patel , "kvm@vger.kernel.org" , Anup Patel , Daniel Lezcano , "linux-kernel@vger.kernel.org" , Christoph Hellwig , Atish Patra , Alexander Graf , Alistair Francis , Thomas Gleixner , "linux-riscv@lists.infradead.org" Sender: "linux-riscv" Errors-To: linux-riscv-bounces+patchwork-linux-riscv=patchwork.kernel.org@lists.infradead.org This patch implements all required functions for programming the stage2 page table for each Guest/VM. At high-level, the flow of stage2 related functions is similar from KVM ARM/ARM64 implementation but the stage2 page table format is quite different for KVM RISC-V. Signed-off-by: Anup Patel Acked-by: Paolo Bonzini Reviewed-by: Paolo Bonzini --- arch/riscv/include/asm/kvm_host.h | 10 + arch/riscv/include/asm/pgtable-bits.h | 1 + arch/riscv/kvm/mmu.c | 643 +++++++++++++++++++++++++- 3 files changed, 644 insertions(+), 10 deletions(-) diff --git a/arch/riscv/include/asm/kvm_host.h b/arch/riscv/include/asm/kvm_host.h index 8aaf22a900be..bc27f664b443 100644 --- a/arch/riscv/include/asm/kvm_host.h +++ b/arch/riscv/include/asm/kvm_host.h @@ -73,6 +73,13 @@ struct kvm_mmio_decode { int return_handled; }; +#define KVM_MMU_PAGE_CACHE_NR_OBJS 32 + +struct kvm_mmu_page_cache { + int nobjs; + void *objects[KVM_MMU_PAGE_CACHE_NR_OBJS]; +}; + struct kvm_cpu_context { unsigned long zero; unsigned long ra; @@ -164,6 +171,9 @@ struct kvm_vcpu_arch { /* MMIO instruction details */ struct kvm_mmio_decode mmio_decode; + /* Cache pages needed to program page tables with spinlock held */ + struct kvm_mmu_page_cache mmu_page_cache; + /* VCPU power-off state */ bool power_off; diff --git a/arch/riscv/include/asm/pgtable-bits.h b/arch/riscv/include/asm/pgtable-bits.h index bbaeb5d35842..be49d62fcc2b 100644 --- a/arch/riscv/include/asm/pgtable-bits.h +++ b/arch/riscv/include/asm/pgtable-bits.h @@ -26,6 +26,7 @@ #define _PAGE_SPECIAL _PAGE_SOFT #define _PAGE_TABLE _PAGE_PRESENT +#define _PAGE_LEAF (_PAGE_READ | _PAGE_WRITE | _PAGE_EXEC) /* * _PAGE_PROT_NONE is set on not-present pages (and ignored by the hardware) to diff --git a/arch/riscv/kvm/mmu.c b/arch/riscv/kvm/mmu.c index 2b965f9aac07..590669290139 100644 --- a/arch/riscv/kvm/mmu.c +++ b/arch/riscv/kvm/mmu.c @@ -18,6 +18,438 @@ #include #include +#ifdef CONFIG_64BIT +#define stage2_have_pmd true +#define stage2_gpa_size ((phys_addr_t)(1ULL << 39)) +#define stage2_cache_min_pages 2 +#else +#define pmd_index(x) 0 +#define pfn_pmd(x, y) ({ pmd_t __x = { 0 }; __x; }) +#define stage2_have_pmd false +#define stage2_gpa_size ((phys_addr_t)(1ULL << 32)) +#define stage2_cache_min_pages 1 +#endif + +static int stage2_cache_topup(struct kvm_mmu_page_cache *pcache, + int min, int max) +{ + void *page; + + BUG_ON(max > KVM_MMU_PAGE_CACHE_NR_OBJS); + if (pcache->nobjs >= min) + return 0; + while (pcache->nobjs < max) { + page = (void *)__get_free_page(GFP_KERNEL | __GFP_ZERO); + if (!page) + return -ENOMEM; + pcache->objects[pcache->nobjs++] = page; + } + + return 0; +} + +static void stage2_cache_flush(struct kvm_mmu_page_cache *pcache) +{ + while (pcache && pcache->nobjs) + free_page((unsigned long)pcache->objects[--pcache->nobjs]); +} + +static void *stage2_cache_alloc(struct kvm_mmu_page_cache *pcache) +{ + void *p; + + if (!pcache) + return NULL; + + BUG_ON(!pcache->nobjs); + p = pcache->objects[--pcache->nobjs]; + + return p; +} + +struct local_guest_tlb_info { + struct kvm_vmid *vmid; + gpa_t addr; +}; + +static void local_guest_tlb_flush_vmid_gpa(void *info) +{ + struct local_guest_tlb_info *infop = info; + + __kvm_riscv_hfence_gvma_vmid_gpa(READ_ONCE(infop->vmid->vmid_version), + infop->addr); +} + +static void stage2_remote_tlb_flush(struct kvm *kvm, gpa_t addr) +{ + struct local_guest_tlb_info info; + struct kvm_vmid *vmid = &kvm->arch.vmid; + + /* + * Ideally, we should have a SBI call OR some remote TLB instruction + * but we don't have it so we explicitly flush TLBs using IPIs. + * + * TODO: Instead of cpu_online_mask, we should only target CPUs + * where the Guest/VM is running. + */ + info.vmid = vmid; + info.addr = addr; + preempt_disable(); + smp_call_function_many(cpu_online_mask, + local_guest_tlb_flush_vmid_gpa, &info, true); + preempt_enable(); +} + +static int stage2_set_pgd(struct kvm *kvm, gpa_t addr, const pgd_t *new_pgd) +{ + pgd_t *pgdp = &kvm->arch.pgd[pgd_index(addr)]; + + *pgdp = *new_pgd; + if (pgd_val(*pgdp) & _PAGE_LEAF) + stage2_remote_tlb_flush(kvm, addr); + + return 0; +} + +static int stage2_set_pmd(struct kvm *kvm, struct kvm_mmu_page_cache *pcache, + gpa_t addr, const pmd_t *new_pmd) +{ + int rc; + pmd_t *pmdp; + pgd_t new_pgd; + pgd_t *pgdp = &kvm->arch.pgd[pgd_index(addr)]; + + if (!pgd_val(*pgdp)) { + pmdp = stage2_cache_alloc(pcache); + if (!pmdp) + return -ENOMEM; + new_pgd = pfn_pgd(PFN_DOWN(__pa(pmdp)), __pgprot(_PAGE_TABLE)); + rc = stage2_set_pgd(kvm, addr, &new_pgd); + if (rc) + return rc; + } + + if (pgd_val(*pgdp) & _PAGE_LEAF) + return -EEXIST; + + pmdp = (void *)pgd_page_vaddr(*pgdp); + pmdp = &pmdp[pmd_index(addr)]; + + *pmdp = *new_pmd; + if (pmd_val(*pmdp) & _PAGE_LEAF) + stage2_remote_tlb_flush(kvm, addr); + + return 0; +} + +static int stage2_set_pte(struct kvm *kvm, + struct kvm_mmu_page_cache *pcache, + gpa_t addr, const pte_t *new_pte) +{ + int rc; + pte_t *ptep; + pmd_t new_pmd; + pmd_t *pmdp; + pgd_t new_pgd; + pgd_t *pgdp = &kvm->arch.pgd[pgd_index(addr)]; + + if (!pgd_val(*pgdp)) { + pmdp = stage2_cache_alloc(pcache); + if (!pmdp) + return -ENOMEM; + new_pgd = pfn_pgd(PFN_DOWN(__pa(pmdp)), __pgprot(_PAGE_TABLE)); + rc = stage2_set_pgd(kvm, addr, &new_pgd); + if (rc) + return rc; + } + + if (pgd_val(*pgdp) & _PAGE_LEAF) + return -EEXIST; + + if (stage2_have_pmd) { + pmdp = (void *)pgd_page_vaddr(*pgdp); + pmdp = &pmdp[pmd_index(addr)]; + if (!pmd_present(*pmdp)) { + ptep = stage2_cache_alloc(pcache); + if (!ptep) + return -ENOMEM; + new_pmd = pfn_pmd(PFN_DOWN(__pa(ptep)), + __pgprot(_PAGE_TABLE)); + rc = stage2_set_pmd(kvm, pcache, addr, &new_pmd); + if (rc) + return rc; + } + + if (pmd_val(*pmdp) & _PAGE_LEAF) + return -EEXIST; + + ptep = (void *)pmd_page_vaddr(*pmdp); + } else { + ptep = (void *)pgd_page_vaddr(*pgdp); + } + + ptep = &ptep[pte_index(addr)]; + + *ptep = *new_pte; + if (pte_val(*ptep) & _PAGE_LEAF) + stage2_remote_tlb_flush(kvm, addr); + + return 0; +} + +static int stage2_map_page(struct kvm *kvm, + struct kvm_mmu_page_cache *pcache, + gpa_t gpa, phys_addr_t hpa, + unsigned long page_size, pgprot_t prot) +{ + pte_t new_pte; + pmd_t new_pmd; + pgd_t new_pgd; + + if (page_size == PAGE_SIZE) { + new_pte = pfn_pte(PFN_DOWN(hpa), prot); + return stage2_set_pte(kvm, pcache, gpa, &new_pte); + } + + if (stage2_have_pmd && page_size == PMD_SIZE) { + new_pmd = pfn_pmd(PFN_DOWN(hpa), prot); + return stage2_set_pmd(kvm, pcache, gpa, &new_pmd); + } + + if (page_size == PGDIR_SIZE) { + new_pgd = pfn_pgd(PFN_DOWN(hpa), prot); + return stage2_set_pgd(kvm, gpa, &new_pgd); + } + + return -EINVAL; +} + +enum stage2_op { + STAGE2_OP_NOP = 0, /* Nothing */ + STAGE2_OP_CLEAR, /* Clear/Unmap */ + STAGE2_OP_WP, /* Write-protect */ +}; + +static void stage2_op_pte(struct kvm *kvm, gpa_t addr, pte_t *ptep, + enum stage2_op op) +{ + BUG_ON(addr & (PAGE_SIZE - 1)); + + if (!pte_present(*ptep)) + return; + + if (op == STAGE2_OP_CLEAR) + set_pte(ptep, __pte(0)); + else if (op == STAGE2_OP_WP) + set_pte(ptep, __pte(pte_val(*ptep) & ~_PAGE_WRITE)); + stage2_remote_tlb_flush(kvm, addr); +} + +static void stage2_op_pmd(struct kvm *kvm, gpa_t addr, pmd_t *pmdp, + enum stage2_op op) +{ + int i; + pte_t *ptep; + + BUG_ON(addr & (PMD_SIZE - 1)); + + if (!pmd_present(*pmdp)) + return; + + if (pmd_val(*pmdp) & _PAGE_LEAF) + ptep = NULL; + else + ptep = (pte_t *)pmd_page_vaddr(*pmdp); + + if (op == STAGE2_OP_CLEAR) + set_pmd(pmdp, __pmd(0)); + + if (ptep) { + for (i = 0; i < PTRS_PER_PTE; i++) + stage2_op_pte(kvm, addr + i * PAGE_SIZE, &ptep[i], op); + if (op == STAGE2_OP_CLEAR) + put_page(virt_to_page(ptep)); + } else { + if (op == STAGE2_OP_WP) + set_pmd(pmdp, __pmd(pmd_val(*pmdp) & ~_PAGE_WRITE)); + stage2_remote_tlb_flush(kvm, addr); + } +} + +static void stage2_op_pgd(struct kvm *kvm, gpa_t addr, pgd_t *pgdp, + enum stage2_op op) +{ + int i; + pte_t *ptep; + pmd_t *pmdp; + + BUG_ON(addr & (PGDIR_SIZE - 1)); + + if (!pgd_val(*pgdp)) + return; + + ptep = NULL; + pmdp = NULL; + if (!(pgd_val(*pgdp) & _PAGE_LEAF)) { + if (stage2_have_pmd) + pmdp = (pmd_t *)pgd_page_vaddr(*pgdp); + else + ptep = (pte_t *)pgd_page_vaddr(*pgdp); + } + + if (op == STAGE2_OP_CLEAR) + set_pgd(pgdp, __pgd(0)); + + if (pmdp) { + for (i = 0; i < PTRS_PER_PMD; i++) + stage2_op_pmd(kvm, addr + i * PMD_SIZE, &pmdp[i], op); + if (op == STAGE2_OP_CLEAR) + put_page(virt_to_page(pmdp)); + } else if (ptep) { + for (i = 0; i < PTRS_PER_PTE; i++) + stage2_op_pte(kvm, addr + i * PAGE_SIZE, &ptep[i], op); + if (op == STAGE2_OP_CLEAR) + put_page(virt_to_page(ptep)); + } else { + if (op == STAGE2_OP_WP) + set_pgd(pgdp, __pgd(pgd_val(*pgdp) & ~_PAGE_WRITE)); + stage2_remote_tlb_flush(kvm, addr); + } +} + +static void stage2_unmap_range(struct kvm *kvm, gpa_t start, gpa_t size) +{ + pmd_t *pmdp; + pte_t *ptep; + pgd_t *pgdp; + gpa_t addr = start, end = start + size; + + while (addr < end) { + pgdp = &kvm->arch.pgd[pgd_index(addr)]; + if (!pgd_val(*pgdp)) { + addr += PGDIR_SIZE; + continue; + } else if (!(addr & (PGDIR_SIZE - 1)) && + ((end - addr) >= PGDIR_SIZE)) { + stage2_op_pgd(kvm, addr, pgdp, STAGE2_OP_CLEAR); + addr += PGDIR_SIZE; + continue; + } + + if (stage2_have_pmd) { + pmdp = (pmd_t *)pgd_page_vaddr(*pgdp); + if (!pmd_present(*pmdp)) { + addr += PMD_SIZE; + continue; + } else if (!(addr & (PMD_SIZE - 1)) && + ((end - addr) >= PMD_SIZE)) { + stage2_op_pmd(kvm, addr, pmdp, + STAGE2_OP_CLEAR); + addr += PMD_SIZE; + continue; + } + ptep = (pte_t *)pmd_page_vaddr(*pmdp); + } else { + ptep = (pte_t *)pgd_page_vaddr(*pgdp); + } + + stage2_op_pte(kvm, addr, ptep, STAGE2_OP_CLEAR); + addr += PAGE_SIZE; + } +} + +static void stage2_wp_range(struct kvm *kvm, gpa_t start, gpa_t end) +{ + pmd_t *pmdp; + pte_t *ptep; + pgd_t *pgdp; + gpa_t addr = start; + + while (addr < end) { + pgdp = &kvm->arch.pgd[pgd_index(addr)]; + if (!pgd_val(*pgdp)) { + addr += PGDIR_SIZE; + continue; + } else if (!(addr & (PGDIR_SIZE - 1)) && + ((end - addr) >= PGDIR_SIZE)) { + stage2_op_pgd(kvm, addr, pgdp, STAGE2_OP_WP); + addr += PGDIR_SIZE; + continue; + } + + if (stage2_have_pmd) { + pmdp = (pmd_t *)pgd_page_vaddr(*pgdp); + if (!pmd_present(*pmdp)) { + addr += PMD_SIZE; + continue; + } else if (!(addr & (PMD_SIZE - 1)) && + ((end - addr) >= PMD_SIZE)) { + stage2_op_pmd(kvm, addr, pmdp, STAGE2_OP_WP); + addr += PMD_SIZE; + continue; + } + ptep = (pte_t *)pmd_page_vaddr(*pmdp); + } else { + ptep = (pte_t *)pgd_page_vaddr(*pgdp); + } + + stage2_op_pte(kvm, addr, ptep, STAGE2_OP_WP); + addr += PAGE_SIZE; + } +} + +void stage2_wp_memory_region(struct kvm *kvm, int slot) +{ + struct kvm_memslots *slots = kvm_memslots(kvm); + struct kvm_memory_slot *memslot = id_to_memslot(slots, slot); + phys_addr_t start = memslot->base_gfn << PAGE_SHIFT; + phys_addr_t end = (memslot->base_gfn + memslot->npages) << PAGE_SHIFT; + + spin_lock(&kvm->mmu_lock); + stage2_wp_range(kvm, start, end); + spin_unlock(&kvm->mmu_lock); + kvm_flush_remote_tlbs(kvm); +} + +int stage2_ioremap(struct kvm *kvm, gpa_t gpa, phys_addr_t hpa, + unsigned long size, bool writable) +{ + pte_t pte; + int ret = 0; + unsigned long pfn; + phys_addr_t addr, end; + struct kvm_mmu_page_cache pcache = { 0, }; + + end = (gpa + size + PAGE_SIZE - 1) & PAGE_MASK; + pfn = __phys_to_pfn(hpa); + + for (addr = gpa; addr < end; addr += PAGE_SIZE) { + pte = pfn_pte(pfn, PAGE_KERNEL); + + if (!writable) + pte = pte_wrprotect(pte); + + ret = stage2_cache_topup(&pcache, + stage2_cache_min_pages, + KVM_MMU_PAGE_CACHE_NR_OBJS); + if (ret) + goto out; + + spin_lock(&kvm->mmu_lock); + ret = stage2_set_pte(kvm, &pcache, addr, &pte); + spin_unlock(&kvm->mmu_lock); + if (ret) + goto out; + + pfn++; + } + +out: + stage2_cache_flush(&pcache); + return ret; + +} + void kvm_arch_free_memslot(struct kvm *kvm, struct kvm_memory_slot *free, struct kvm_memory_slot *dont) { @@ -35,7 +467,7 @@ void kvm_arch_memslots_updated(struct kvm *kvm, u64 gen) void kvm_arch_flush_shadow_all(struct kvm *kvm) { - /* TODO: */ + kvm_riscv_stage2_free_pgd(kvm); } void kvm_arch_flush_shadow_memslot(struct kvm *kvm, @@ -49,7 +481,13 @@ void kvm_arch_commit_memory_region(struct kvm *kvm, const struct kvm_memory_slot *new, enum kvm_mr_change change) { - /* TODO: */ + /* + * At this point memslot has been committed and there is an + * allocated dirty_bitmap[], dirty pages will be be tracked while the + * memory slot is write protected. + */ + if (change != KVM_MR_DELETE && mem->flags & KVM_MEM_LOG_DIRTY_PAGES) + stage2_wp_memory_region(kvm, mem->slot); } int kvm_arch_prepare_memory_region(struct kvm *kvm, @@ -57,34 +495,219 @@ int kvm_arch_prepare_memory_region(struct kvm *kvm, const struct kvm_userspace_memory_region *mem, enum kvm_mr_change change) { - /* TODO: */ - return 0; + hva_t hva = mem->userspace_addr; + hva_t reg_end = hva + mem->memory_size; + bool writable = !(mem->flags & KVM_MEM_READONLY); + int ret = 0; + + if (change != KVM_MR_CREATE && change != KVM_MR_MOVE && + change != KVM_MR_FLAGS_ONLY) + return 0; + + /* + * Prevent userspace from creating a memory region outside of the GPA + * space addressable by the KVM guest GPA space. + */ + if ((memslot->base_gfn + memslot->npages) >= + (stage2_gpa_size >> PAGE_SHIFT)) + return -EFAULT; + + down_read(¤t->mm->mmap_sem); + + /* + * A memory region could potentially cover multiple VMAs, and + * any holes between them, so iterate over all of them to find + * out if we can map any of them right now. + * + * +--------------------------------------------+ + * +---------------+----------------+ +----------------+ + * | : VMA 1 | VMA 2 | | VMA 3 : | + * +---------------+----------------+ +----------------+ + * | memory region | + * +--------------------------------------------+ + */ + do { + struct vm_area_struct *vma = find_vma(current->mm, hva); + hva_t vm_start, vm_end; + + if (!vma || vma->vm_start >= reg_end) + break; + + /* + * Mapping a read-only VMA is only allowed if the + * memory region is configured as read-only. + */ + if (writable && !(vma->vm_flags & VM_WRITE)) { + ret = -EPERM; + break; + } + + /* Take the intersection of this VMA with the memory region */ + vm_start = max(hva, vma->vm_start); + vm_end = min(reg_end, vma->vm_end); + + if (vma->vm_flags & VM_PFNMAP) { + gpa_t gpa = mem->guest_phys_addr + + (vm_start - mem->userspace_addr); + phys_addr_t pa; + + pa = (phys_addr_t)vma->vm_pgoff << PAGE_SHIFT; + pa += vm_start - vma->vm_start; + + /* IO region dirty page logging not allowed */ + if (memslot->flags & KVM_MEM_LOG_DIRTY_PAGES) { + ret = -EINVAL; + goto out; + } + + ret = stage2_ioremap(kvm, gpa, pa, + vm_end - vm_start, writable); + if (ret) + break; + } + hva = vm_end; + } while (hva < reg_end); + + if (change == KVM_MR_FLAGS_ONLY) + goto out; + + spin_lock(&kvm->mmu_lock); + if (ret) + stage2_unmap_range(kvm, mem->guest_phys_addr, + mem->memory_size); + spin_unlock(&kvm->mmu_lock); + +out: + up_read(¤t->mm->mmap_sem); + return ret; } int kvm_riscv_stage2_map(struct kvm_vcpu *vcpu, gpa_t gpa, unsigned long hva, bool is_write) { - /* TODO: */ - return 0; + int ret; + short lsb; + kvm_pfn_t hfn; + bool writeable; + gfn_t gfn = gpa >> PAGE_SHIFT; + struct vm_area_struct *vma; + struct kvm *kvm = vcpu->kvm; + struct kvm_mmu_page_cache *pcache = &vcpu->arch.mmu_page_cache; + unsigned long vma_pagesize; + + down_read(¤t->mm->mmap_sem); + + vma = find_vma_intersection(current->mm, hva, hva + 1); + if (unlikely(!vma)) { + kvm_err("Failed to find VMA for hva 0x%lx\n", hva); + up_read(¤t->mm->mmap_sem); + return -EFAULT; + } + + vma_pagesize = vma_kernel_pagesize(vma); + + up_read(¤t->mm->mmap_sem); + + if (vma_pagesize != PGDIR_SIZE && + vma_pagesize != PMD_SIZE && + vma_pagesize != PAGE_SIZE) { + kvm_err("Invalid VMA page size 0x%lx\n", vma_pagesize); + return -EFAULT; + } + + /* We need minimum second+third level pages */ + ret = stage2_cache_topup(pcache, stage2_cache_min_pages, + KVM_MMU_PAGE_CACHE_NR_OBJS); + if (ret) { + kvm_err("Failed to topup stage2 cache\n"); + return ret; + } + + hfn = gfn_to_pfn_prot(kvm, gfn, is_write, &writeable); + if (hfn == KVM_PFN_ERR_HWPOISON) { + if (is_vm_hugetlb_page(vma)) + lsb = huge_page_shift(hstate_vma(vma)); + else + lsb = PAGE_SHIFT; + + send_sig_mceerr(BUS_MCEERR_AR, (void __user *)hva, + lsb, current); + return 0; + } + if (is_error_noslot_pfn(hfn)) + return -EFAULT; + if (!writeable && is_write) + return -EPERM; + + spin_lock(&kvm->mmu_lock); + + if (writeable) { + kvm_set_pfn_dirty(hfn); + ret = stage2_map_page(kvm, pcache, gpa, hfn << PAGE_SHIFT, + vma_pagesize, PAGE_WRITE_EXEC); + } else { + ret = stage2_map_page(kvm, pcache, gpa, hfn << PAGE_SHIFT, + vma_pagesize, PAGE_READ_EXEC); + } + + if (ret) + kvm_err("Failed to map in stage2\n"); + + spin_unlock(&kvm->mmu_lock); + kvm_set_pfn_accessed(hfn); + kvm_release_pfn_clean(hfn); + return ret; } void kvm_riscv_stage2_flush_cache(struct kvm_vcpu *vcpu) { - /* TODO: */ + stage2_cache_flush(&vcpu->arch.mmu_page_cache); } int kvm_riscv_stage2_alloc_pgd(struct kvm *kvm) { - /* TODO: */ + if (kvm->arch.pgd != NULL) { + kvm_err("kvm_arch already initialized?\n"); + return -EINVAL; + } + + kvm->arch.pgd = alloc_pages_exact(PAGE_SIZE, GFP_KERNEL | __GFP_ZERO); + if (!kvm->arch.pgd) + return -ENOMEM; + kvm->arch.pgd_phys = virt_to_phys(kvm->arch.pgd); + return 0; } void kvm_riscv_stage2_free_pgd(struct kvm *kvm) { - /* TODO: */ + void *pgd = NULL; + + spin_lock(&kvm->mmu_lock); + if (kvm->arch.pgd) { + stage2_unmap_range(kvm, 0UL, stage2_gpa_size); + pgd = READ_ONCE(kvm->arch.pgd); + kvm->arch.pgd = NULL; + kvm->arch.pgd_phys = 0; + } + spin_unlock(&kvm->mmu_lock); + + /* Free the HW pgd, one page at a time */ + if (pgd) + free_pages_exact(pgd, PAGE_SIZE); } void kvm_riscv_stage2_update_hgatp(struct kvm_vcpu *vcpu) { - /* TODO: */ + unsigned long hgatp = HGATP_MODE; + struct kvm_arch *k = &vcpu->kvm->arch; + + hgatp |= (READ_ONCE(k->vmid.vmid) << HGATP_VMID_SHIFT) & + HGATP_VMID_MASK; + hgatp |= (k->pgd_phys >> PAGE_SHIFT) & HGATP_PPN; + + csr_write(CSR_HGATP, hgatp); + + if (!kvm_riscv_stage2_vmid_bits()) + __kvm_riscv_hfence_gvma_all(); } From patchwork Thu Oct 3 05:08:01 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Anup Patel X-Patchwork-Id: 11172133 Return-Path: Received: from mail.kernel.org (pdx-korg-mail-1.web.codeaurora.org [172.30.200.123]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id E1F9E14DB for ; Thu, 3 Oct 2019 05:08:18 +0000 (UTC) Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id BD08021D81 for ; Thu, 3 Oct 2019 05:08:18 +0000 (UTC) Authentication-Results: mail.kernel.org; dkim=pass (2048-bit key) header.d=lists.infradead.org header.i=@lists.infradead.org header.b="Fv1o/4ly"; dkim=fail reason="signature verification failed" (2048-bit key) header.d=wdc.com header.i=@wdc.com header.b="AQ5YDTQN"; dkim=fail reason="signature verification failed" (1024-bit key) header.d=sharedspace.onmicrosoft.com header.i=@sharedspace.onmicrosoft.com header.b="GUyqzbJP" DMARC-Filter: OpenDMARC Filter v1.3.2 mail.kernel.org BD08021D81 Authentication-Results: mail.kernel.org; dmarc=fail (p=none dis=none) header.from=wdc.com Authentication-Results: mail.kernel.org; spf=none smtp.mailfrom=linux-riscv-bounces+patchwork-linux-riscv=patchwork.kernel.org@lists.infradead.org DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=bombadil.20170209; h=Sender: Content-Transfer-Encoding:Content-Type:Cc:List-Subscribe:List-Help:List-Post: List-Archive:List-Unsubscribe:List-Id:MIME-Version:In-Reply-To:References: Message-ID:Date:Subject:To:From:Reply-To:Content-ID:Content-Description: Resent-Date:Resent-From:Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID: List-Owner; bh=Oiv2H/m1umNZX3h4QEA7tW/H5ZaUsSVHLY3cmZdsnUA=; b=Fv1o/4ly5b8bed OzxTQOElf7IQJig+YikvFEr4j2wpqLKehAgKBL3m/71/W8H2FatOmgNItYmk69xOMi7VXLpEoeArY 5YLK5zD79u2C98wyDpr/CxIyDPjgtE5w7iE63GFM0JqOdqmkOhI1mCMLTvEcU4C310fnog8l+QxHL AFoUC2z1bTixKTsRwynqW28GUoHkxsybYRavCu83KEsksfqTPCCD7jHZn7PkGhXQszEz2DC3E1hEk 8NE9FqJrsmfQJH0N1FEzkX8kaw6nEA74Hv9DU/lXhAVIETObsLmCcEZKj691/OD1C7Xz7S6F2sRYQ Q2IpA/OJ9Xr4QL6oEUEA==; Received: from localhost ([127.0.0.1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.92.2 #3 (Red Hat Linux)) id 1iFtLV-00044I-0z; Thu, 03 Oct 2019 05:08:09 +0000 Received: from esa4.hgst.iphmx.com ([216.71.154.42]) by bombadil.infradead.org with esmtps (Exim 4.92.2 #3 (Red Hat Linux)) id 1iFtLS-000431-D7 for linux-riscv@lists.infradead.org; Thu, 03 Oct 2019 05:08:08 +0000 DKIM-Signature: v=1; a=rsa-sha256; c=simple/simple; d=wdc.com; i=@wdc.com; q=dns/txt; s=dkim.wdc.com; t=1570079286; x=1601615286; h=from:to:cc:subject:date:message-id:references: in-reply-to:content-transfer-encoding:mime-version; bh=KHmeUNu4o7Qv9SJU8yz5GpY+lzZoa/S//x7tnh8gtoY=; b=AQ5YDTQNP45GXHcgjLUGbcZ+H8FoLqPEc9uWAvhjrnRu3FPjOvuVAF8I DTpW/OGhp4Pg1w6BXI8RLCINGujlEFw4U7U4PGrNG8lfMKKvjRS+Bqhyw 8T2xFOJjwk3HkUvkHn/Ey6i27sWraQ+TglMlEcLhZ/ZGpKoDCEYJXFJLZ Ci7WWptZqKOgEjIZ64UMVHv8+VJWHAbhhE8FZTDRZ10Jtqh6m1mhTtzB2 xyTYYudshIfpUgC5Gqtu4XtVZYmrfLj0GIF8Y3hWvio8eCxaWkFmO4rMr 1d42Hyz31wuyRpbdsYV+kH1sq+eIlK3JbB4M7qqTA3s6LcLciLZNF/1/x Q==; IronPort-SDR: XC0OcnuakmAT0xCWCmSq7TPl/qtSg5Gbj7KIr6+cVLTyzYRBHVHAX/i35fwInuZwgGOuOnSMxU 1IVMe2d/Rp7V0nR2A4d35NKBp3efba/NvcyP3lT7e9lVHboTVzUZvhjZMlyZnBIsC2+VIOM8Fk EborVb4WrAs1wE8wEl0n4nY2Qt5W2i+lO1gnJT9Pd0/94ktRMuTkWpwvpSEX4yZ9xQdQUOQ9vW sUwDo8r/9kt8+GMsLnkdCjt73ZohTdgFNsM8ueA+5+/FnWxLRVJMj2DwXOJwUyh1zs4YDLfdKi G8Y= X-IronPort-AV: E=Sophos;i="5.67,251,1566835200"; d="scan'208";a="119691050" Received: from mail-by2nam05lp2058.outbound.protection.outlook.com (HELO NAM05-BY2-obe.outbound.protection.outlook.com) ([104.47.50.58]) by ob1.hgst.iphmx.com with ESMTP; 03 Oct 2019 13:08:02 +0800 ARC-Seal: i=1; a=rsa-sha256; s=arcselector9901; d=microsoft.com; cv=none; b=YWMKdL5A0OBEH6Bhur5S13wro/ozosHK+4VEGpxmcH7I0RDcfumInN1ytCi7urTGS+0Fy8qE3KrClVf6uqaCMW+m7+nSw8coZ23jRaPEGan+SwSQTTujUurscWS7f8zEmbLCsVdOaqhUrmPUcapOR0GXWKtz6TwThz+mphB3dYAzeN/chEn9RcOzXRCbdaRZ2IP1DdU/O9tpEhmke97yP/6FKfGT7PUHvXLWbo3LYiiY3qkYajAtnE8VYbxHi3Q8ePfy5uK00USRvexwaxJKFjhDMjS3FIpoPLkhOAdraTs8Y+vfFG3zTZeF18po84axxplaldbFV2BajwPzCMIz5A== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=microsoft.com; s=arcselector9901; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-SenderADCheck; bh=H0FTmiF3I7/uSjBO/rhcpBdrQ3ufOEnEDrFfdthJgGY=; b=M8ofinvLHd+MkbZmwbF1ng3ySdBHjOiJd2h5qONTgbMuVQEaTiUzoojsr5SLTiH+XCB2lhEK7k5n5QHlS11EYfUajpJqjiNwRiWmbN0Yn+TCqVvumsPUQwcUDEu5e6tEWFIdOGIAI23qEQQcZN9JD+5Uj7I5flSkWFh+d1uZMfqJ/wwN9jEZT/AxQLQfDv/JZZvQ+Q6Ju0ANadq9J3cD4mhbSp02DTNWd900OYLcbBO7A5oA/r3UR1/DreM1TiMeBgCwUqyuBWP0yCb/BenZttBCuo0FIu8ss2fTfHVYb8tY647mCkTz7pl4zzh6SCX8eRqQoBalVCgI0fk5UdRvFg== ARC-Authentication-Results: i=1; mx.microsoft.com 1; spf=pass smtp.mailfrom=wdc.com; dmarc=pass action=none header.from=wdc.com; dkim=pass header.d=wdc.com; arc=none DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=sharedspace.onmicrosoft.com; s=selector2-sharedspace-onmicrosoft-com; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-SenderADCheck; bh=H0FTmiF3I7/uSjBO/rhcpBdrQ3ufOEnEDrFfdthJgGY=; b=GUyqzbJPtUFo790lbZg0PY0iLz4+J3u4AE1FwCwztFp2TVGmaStTixJt2JzU6E6clxzsyF8RSWV14bKqyoscQK9CoubbvPQ6oPGNqE3T7WAuCQxf0dlOltX4SYdVdmLQ3yFpuRSk7QqhxBMAKQhXqwuH86Y+xKffwEsRweJRjqQ= Received: from MN2PR04MB6061.namprd04.prod.outlook.com (20.178.246.15) by MN2PR04MB6272.namprd04.prod.outlook.com (20.178.248.27) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.2305.17; Thu, 3 Oct 2019 05:08:01 +0000 Received: from MN2PR04MB6061.namprd04.prod.outlook.com ([fe80::1454:87a:13b0:d3a]) by MN2PR04MB6061.namprd04.prod.outlook.com ([fe80::1454:87a:13b0:d3a%7]) with mapi id 15.20.2305.023; Thu, 3 Oct 2019 05:08:01 +0000 From: Anup Patel To: Palmer Dabbelt , Paul Walmsley , Paolo Bonzini , Radim K Subject: [PATCH v8 12/19] RISC-V: KVM: Implement MMU notifiers Thread-Topic: [PATCH v8 12/19] RISC-V: KVM: Implement MMU notifiers Thread-Index: AQHVeaiHNbN+34smpUyPikGFIuG1xw== Date: Thu, 3 Oct 2019 05:08:01 +0000 Message-ID: <20191003050558.9031-13-anup.patel@wdc.com> References: <20191003050558.9031-1-anup.patel@wdc.com> In-Reply-To: <20191003050558.9031-1-anup.patel@wdc.com> Accept-Language: en-US Content-Language: en-US X-MS-Has-Attach: X-MS-TNEF-Correlator: x-clientproxiedby: BMXPR01CA0030.INDPRD01.PROD.OUTLOOK.COM (2603:1096:b00:c::16) To MN2PR04MB6061.namprd04.prod.outlook.com (2603:10b6:208:d8::15) authentication-results: spf=none (sender IP is ) smtp.mailfrom=Anup.Patel@wdc.com; x-ms-exchange-messagesentrepresentingtype: 1 x-mailer: git-send-email 2.17.1 x-originating-ip: [111.235.74.37] x-ms-publictraffictype: Email x-ms-office365-filtering-correlation-id: aa58dae4-41a9-4eaa-7f93-08d747bfaa06 x-ms-office365-filtering-ht: Tenant x-ms-traffictypediagnostic: MN2PR04MB6272: x-ms-exchange-transport-forked: True x-microsoft-antispam-prvs: wdcipoutbound: EOP-TRUE x-ms-oob-tlc-oobclassifiers: OLM:785; x-forefront-prvs: 01792087B6 x-forefront-antispam-report: SFV:NSPM; SFS:(10019020)(979002)(4636009)(136003)(376002)(346002)(366004)(396003)(39860400002)(189003)(199004)(6512007)(6486002)(81166006)(81156014)(8936002)(6116002)(3846002)(8676002)(50226002)(2906002)(110136005)(66066001)(6436002)(316002)(66476007)(66556008)(7416002)(66446008)(36756003)(1076003)(5660300002)(54906003)(7736002)(305945005)(76176011)(25786009)(52116002)(256004)(14444005)(71190400001)(86362001)(99286004)(71200400001)(2616005)(446003)(14454004)(476003)(102836004)(186003)(26005)(11346002)(44832011)(6506007)(486006)(478600001)(4326008)(66946007)(386003)(64756008)(969003)(989001)(999001)(1009001)(1019001); DIR:OUT; SFP:1102; SCL:1; SRVR:MN2PR04MB6272; H:MN2PR04MB6061.namprd04.prod.outlook.com; FPR:; SPF:None; LANG:en; PTR:InfoNoRecords; MX:1; A:1; x-ms-exchange-senderadcheck: 1 x-microsoft-antispam: BCL:0; x-microsoft-antispam-message-info: YD//03JkK+IsOVLjWUogU+261B8Aam7iIzVA+X/siWxndzAkBsAkEb7az7TKw200cfYSbxFCpEeTAhevjOeLt9dq9pNCHiyj8EJcB4EpGKVi/CskW+swjOTbvFcgYtOjSPwsW38nuh6D0Ch8kjiboly1AksAjemQAXw5J/y/gtCoQaEkEmBGhy7GAM+tR+GGL5yFOi2Bi+CL0KDuaQ/AjB8CpSA0CsxKY05Q7dKM9xF9syYtq3Art74wAeGPfAxS6YTBbd6xaUsWioTfGqeZLE/UkVg4f0GU5b89vOp9JAHIW61YqLJlEpoWvSiyneRhXiHS/GLz2Lw3Nc2czs3mQPVFu2TqSSCm6STOXuEW1x2J1WUoKEvrvAxNpqUDjSySbu3rW/obgt34QHk2WV+5/hTkxdxH6tY7VocLTVqoLqk= MIME-Version: 1.0 X-OriginatorOrg: wdc.com X-MS-Exchange-CrossTenant-Network-Message-Id: aa58dae4-41a9-4eaa-7f93-08d747bfaa06 X-MS-Exchange-CrossTenant-originalarrivaltime: 03 Oct 2019 05:08:01.7780 (UTC) X-MS-Exchange-CrossTenant-fromentityheader: Hosted X-MS-Exchange-CrossTenant-id: b61c8803-16f3-4c35-9b17-6f65f441df86 X-MS-Exchange-CrossTenant-mailboxtype: HOSTED X-MS-Exchange-CrossTenant-userprincipalname: e8JTzvoXVLIR5odYSbfFbKWPgUFmfGUVXmUMFFa1fFVl2MmMss9zxpj8RL6dDufQ4pEwGvbT1LAnEtZV7+Im3A== X-MS-Exchange-Transport-CrossTenantHeadersStamped: MN2PR04MB6272 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20191002_220806_513298_860CF73B X-CRM114-Status: GOOD ( 16.98 ) X-Spam-Score: -2.5 (--) X-Spam-Report: SpamAssassin version 3.4.2 on bombadil.infradead.org summary: Content analysis details: (-2.5 points) pts rule name description ---- ---------------------- -------------------------------------------------- -2.3 RCVD_IN_DNSWL_MED RBL: Sender listed at https://www.dnswl.org/, medium trust [216.71.154.42 listed in list.dnswl.org] -0.0 SPF_PASS SPF: sender matches SPF record 0.0 SPF_HELO_NONE SPF: HELO does not publish an SPF Record -0.1 DKIM_VALID_EF Message has a valid DKIM or DK signature from envelope-from domain 0.1 DKIM_SIGNED Message has a DKIM or DK signature, not necessarily valid -0.1 DKIM_VALID_AU Message has a valid DKIM or DK signature from author's domain -0.1 DKIM_VALID Message has at least one valid DKIM or DK signature X-BeenThere: linux-riscv@lists.infradead.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Damien Le Moal , Anup Patel , "kvm@vger.kernel.org" , Anup Patel , Daniel Lezcano , "linux-kernel@vger.kernel.org" , Christoph Hellwig , Atish Patra , Alexander Graf , Alistair Francis , Thomas Gleixner , "linux-riscv@lists.infradead.org" Sender: "linux-riscv" Errors-To: linux-riscv-bounces+patchwork-linux-riscv=patchwork.kernel.org@lists.infradead.org This patch implements MMU notifiers for KVM RISC-V so that Guest physical address space is in-sync with Host physical address space. This will allow swapping, page migration, etc to work transparently with KVM RISC-V. Signed-off-by: Anup Patel Acked-by: Paolo Bonzini Reviewed-by: Paolo Bonzini Reviewed-by: Alexander Graf --- arch/riscv/include/asm/kvm_host.h | 7 ++ arch/riscv/kvm/Kconfig | 1 + arch/riscv/kvm/mmu.c | 200 +++++++++++++++++++++++++++++- arch/riscv/kvm/vm.c | 1 + 4 files changed, 208 insertions(+), 1 deletion(-) diff --git a/arch/riscv/include/asm/kvm_host.h b/arch/riscv/include/asm/kvm_host.h index bc27f664b443..79ceb2aa8ae6 100644 --- a/arch/riscv/include/asm/kvm_host.h +++ b/arch/riscv/include/asm/kvm_host.h @@ -193,6 +193,13 @@ static inline void kvm_arch_vcpu_block_finish(struct kvm_vcpu *vcpu) {} int kvm_riscv_setup_vsip(void); void kvm_riscv_cleanup_vsip(void); +#define KVM_ARCH_WANT_MMU_NOTIFIER +int kvm_unmap_hva_range(struct kvm *kvm, + unsigned long start, unsigned long end); +int kvm_set_spte_hva(struct kvm *kvm, unsigned long hva, pte_t pte); +int kvm_age_hva(struct kvm *kvm, unsigned long start, unsigned long end); +int kvm_test_age_hva(struct kvm *kvm, unsigned long hva); + void __kvm_riscv_hfence_gvma_vmid_gpa(unsigned long vmid, unsigned long gpa); void __kvm_riscv_hfence_gvma_vmid(unsigned long vmid); diff --git a/arch/riscv/kvm/Kconfig b/arch/riscv/kvm/Kconfig index 9cca98c4673b..d8fa13b0da18 100644 --- a/arch/riscv/kvm/Kconfig +++ b/arch/riscv/kvm/Kconfig @@ -20,6 +20,7 @@ if VIRTUALIZATION config KVM tristate "Kernel-based Virtual Machine (KVM) support (EXPERIMENTAL)" depends on OF + select MMU_NOTIFIER select PREEMPT_NOTIFIERS select ANON_INODES select KVM_MMIO diff --git a/arch/riscv/kvm/mmu.c b/arch/riscv/kvm/mmu.c index 590669290139..d8a692d3e640 100644 --- a/arch/riscv/kvm/mmu.c +++ b/arch/riscv/kvm/mmu.c @@ -67,6 +67,66 @@ static void *stage2_cache_alloc(struct kvm_mmu_page_cache *pcache) return p; } +static int stage2_pgdp_test_and_clear_young(pgd_t *pgd) +{ + return ptep_test_and_clear_young(NULL, 0, (pte_t *)pgd); +} + +static int stage2_pmdp_test_and_clear_young(pmd_t *pmd) +{ + return ptep_test_and_clear_young(NULL, 0, (pte_t *)pmd); +} + +static int stage2_ptep_test_and_clear_young(pte_t *pte) +{ + return ptep_test_and_clear_young(NULL, 0, pte); +} + +static bool stage2_get_leaf_entry(struct kvm *kvm, gpa_t addr, + pgd_t **pgdpp, pmd_t **pmdpp, pte_t **ptepp) +{ + pgd_t *pgdp; + pmd_t *pmdp; + pte_t *ptep; + + *pgdpp = NULL; + *pmdpp = NULL; + *ptepp = NULL; + + pgdp = &kvm->arch.pgd[pgd_index(addr)]; + if (!pgd_val(*pgdp)) + return false; + if (pgd_val(*pgdp) & _PAGE_LEAF) { + *pgdpp = pgdp; + return true; + } + + if (stage2_have_pmd) { + pmdp = (void *)pgd_page_vaddr(*pgdp); + pmdp = &pmdp[pmd_index(addr)]; + if (!pmd_present(*pmdp)) + return false; + if (pmd_val(*pmdp) & _PAGE_LEAF) { + *pmdpp = pmdp; + return true; + } + + ptep = (void *)pmd_page_vaddr(*pmdp); + } else { + ptep = (void *)pgd_page_vaddr(*pgdp); + } + + ptep = &ptep[pte_index(addr)]; + if (!pte_present(*ptep)) + return false; + if (pte_val(*ptep) & _PAGE_LEAF) { + *ptepp = ptep; + return true; + } + + return false; +} + struct local_guest_tlb_info { struct kvm_vmid *vmid; gpa_t addr; @@ -450,6 +510,38 @@ int stage2_ioremap(struct kvm *kvm, gpa_t gpa, phys_addr_t hpa, } +static int handle_hva_to_gpa(struct kvm *kvm, + unsigned long start, + unsigned long end, + int (*handler)(struct kvm *kvm, + gpa_t gpa, u64 size, + void *data), + void *data) +{ + struct kvm_memslots *slots; + struct kvm_memory_slot *memslot; + int ret = 0; + + slots = kvm_memslots(kvm); + + /* we only care about the pages that the guest sees */ + kvm_for_each_memslot(memslot, slots) { + unsigned long hva_start, hva_end; + gfn_t gpa; + + hva_start = max(start, memslot->userspace_addr); + hva_end = min(end, memslot->userspace_addr + + (memslot->npages << PAGE_SHIFT)); + if (hva_start >= hva_end) + continue; + + gpa = hva_to_gfn_memslot(hva_start, memslot) << PAGE_SHIFT; + ret |= handler(kvm, gpa, (u64)(hva_end - hva_start), data); + } + + return ret; +} + void kvm_arch_free_memslot(struct kvm *kvm, struct kvm_memory_slot *free, struct kvm_memory_slot *dont) { @@ -582,6 +674,106 @@ int kvm_arch_prepare_memory_region(struct kvm *kvm, return ret; } +static int kvm_unmap_hva_handler(struct kvm *kvm, + gpa_t gpa, u64 size, void *data) +{ + stage2_unmap_range(kvm, gpa, size); + return 0; +} + +int kvm_unmap_hva_range(struct kvm *kvm, + unsigned long start, unsigned long end) +{ + if (!kvm->arch.pgd) + return 0; + + handle_hva_to_gpa(kvm, start, end, + &kvm_unmap_hva_handler, NULL); + return 0; +} + +static int kvm_set_spte_handler(struct kvm *kvm, + gpa_t gpa, u64 size, void *data) +{ + pte_t *pte = (pte_t *)data; + + WARN_ON(size != PAGE_SIZE); + stage2_set_pte(kvm, NULL, gpa, pte); + + return 0; +} + +int kvm_set_spte_hva(struct kvm *kvm, unsigned long hva, pte_t pte) +{ + unsigned long end = hva + PAGE_SIZE; + kvm_pfn_t pfn = pte_pfn(pte); + pte_t stage2_pte; + + if (!kvm->arch.pgd) + return 0; + + stage2_pte = pfn_pte(pfn, PAGE_WRITE_EXEC); + handle_hva_to_gpa(kvm, hva, end, + &kvm_set_spte_handler, &stage2_pte); + + return 0; +} + +static int kvm_age_hva_handler(struct kvm *kvm, + gpa_t gpa, u64 size, void *data) +{ + pgd_t *pgd; + pmd_t *pmd; + pte_t *pte; + + WARN_ON(size != PAGE_SIZE && size != PMD_SIZE && size != PGDIR_SIZE); + if (!stage2_get_leaf_entry(kvm, gpa, &pgd, &pmd, &pte)) + return 0; + + if (pgd) + return stage2_pgdp_test_and_clear_young(pgd); + else if (pmd) + return stage2_pmdp_test_and_clear_young(pmd); + else + return stage2_ptep_test_and_clear_young(pte); +} + +int kvm_age_hva(struct kvm *kvm, unsigned long start, unsigned long end) +{ + if (!kvm->arch.pgd) + return 0; + + return handle_hva_to_gpa(kvm, start, end, kvm_age_hva_handler, NULL); +} + +static int kvm_test_age_hva_handler(struct kvm *kvm, + gpa_t gpa, u64 size, void *data) +{ + pgd_t *pgd; + pmd_t *pmd; + pte_t *pte; + + WARN_ON(size != PAGE_SIZE && size != PMD_SIZE); + if (!stage2_get_leaf_entry(kvm, gpa, &pgd, &pmd, &pte)) + return 0; + + if (pgd) + return pte_young(*((pte_t *)pgd)); + else if (pmd) + return pte_young(*((pte_t *)pmd)); + else + return pte_young(*pte); +} + +int kvm_test_age_hva(struct kvm *kvm, unsigned long hva) +{ + if (!kvm->arch.pgd) + return 0; + + return handle_hva_to_gpa(kvm, hva, hva, + kvm_test_age_hva_handler, NULL); +} + int kvm_riscv_stage2_map(struct kvm_vcpu *vcpu, gpa_t gpa, unsigned long hva, bool is_write) { @@ -593,7 +785,7 @@ int kvm_riscv_stage2_map(struct kvm_vcpu *vcpu, gpa_t gpa, unsigned long hva, struct vm_area_struct *vma; struct kvm *kvm = vcpu->kvm; struct kvm_mmu_page_cache *pcache = &vcpu->arch.mmu_page_cache; - unsigned long vma_pagesize; + unsigned long vma_pagesize, mmu_seq; down_read(¤t->mm->mmap_sem); @@ -623,6 +815,8 @@ int kvm_riscv_stage2_map(struct kvm_vcpu *vcpu, gpa_t gpa, unsigned long hva, return ret; } + mmu_seq = kvm->mmu_notifier_seq; + hfn = gfn_to_pfn_prot(kvm, gfn, is_write, &writeable); if (hfn == KVM_PFN_ERR_HWPOISON) { if (is_vm_hugetlb_page(vma)) @@ -641,6 +835,9 @@ int kvm_riscv_stage2_map(struct kvm_vcpu *vcpu, gpa_t gpa, unsigned long hva, spin_lock(&kvm->mmu_lock); + if (mmu_notifier_retry(kvm, mmu_seq)) + goto out_unlock; + if (writeable) { kvm_set_pfn_dirty(hfn); ret = stage2_map_page(kvm, pcache, gpa, hfn << PAGE_SHIFT, @@ -653,6 +850,7 @@ int kvm_riscv_stage2_map(struct kvm_vcpu *vcpu, gpa_t gpa, unsigned long hva, if (ret) kvm_err("Failed to map in stage2\n"); +out_unlock: spin_unlock(&kvm->mmu_lock); kvm_set_pfn_accessed(hfn); kvm_release_pfn_clean(hfn); diff --git a/arch/riscv/kvm/vm.c b/arch/riscv/kvm/vm.c index c5aab5478c38..fd84b4d914dc 100644 --- a/arch/riscv/kvm/vm.c +++ b/arch/riscv/kvm/vm.c @@ -54,6 +54,7 @@ int kvm_vm_ioctl_check_extension(struct kvm *kvm, long ext) switch (ext) { case KVM_CAP_DEVICE_CTRL: case KVM_CAP_USER_MEMORY: + case KVM_CAP_SYNC_MMU: case KVM_CAP_DESTROY_MEMORY_REGION_WORKS: case KVM_CAP_ONE_REG: case KVM_CAP_READONLY_MEM: From patchwork Thu Oct 3 05:08:08 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Anup Patel X-Patchwork-Id: 11172137 Return-Path: Received: from mail.kernel.org (pdx-korg-mail-1.web.codeaurora.org [172.30.200.123]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id 047DB14DB for ; Thu, 3 Oct 2019 05:08:25 +0000 (UTC) Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id D3195222BE for ; Thu, 3 Oct 2019 05:08:24 +0000 (UTC) Authentication-Results: mail.kernel.org; dkim=pass (2048-bit key) header.d=lists.infradead.org header.i=@lists.infradead.org header.b="cnKd1av4"; dkim=fail reason="signature verification failed" (2048-bit key) header.d=wdc.com header.i=@wdc.com header.b="bi85nejV"; dkim=fail reason="signature verification failed" (1024-bit key) header.d=sharedspace.onmicrosoft.com header.i=@sharedspace.onmicrosoft.com header.b="DcFBP7op" DMARC-Filter: OpenDMARC Filter v1.3.2 mail.kernel.org D3195222BE Authentication-Results: mail.kernel.org; dmarc=fail (p=none dis=none) header.from=wdc.com Authentication-Results: mail.kernel.org; spf=none smtp.mailfrom=linux-riscv-bounces+patchwork-linux-riscv=patchwork.kernel.org@lists.infradead.org DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=bombadil.20170209; h=Sender: Content-Transfer-Encoding:Content-Type:Cc:List-Subscribe:List-Help:List-Post: List-Archive:List-Unsubscribe:List-Id:MIME-Version:In-Reply-To:References: Message-ID:Date:Subject:To:From:Reply-To:Content-ID:Content-Description: Resent-Date:Resent-From:Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID: List-Owner; bh=0lg7jYjGAmy1ks/1xdJefJf6uwpHeFbpQqbprRYVUfo=; b=cnKd1av4ixdigA zDSEaIdBTWcZAooGuLnO3JzCE1xdogdNazk6YCLLhUAFIniLWRVf/8/hxOIwVMbO3d9LULI47Y8kh 5QTku04KOKwhuo/BRvbfTKNyKoNCblaui3sT/AbeqkfNdGHnvPv1GKmEVkxvDoCZ4BdtK9h+zLff1 BjdqaNImTdBqIcDPbHUoos8sDwGKhBg/DHdMsaFtDdwOvKFfHXuSorh6G/0EWkvuKhguZJzIZhjNf ofjC3spMkoliDbFVagvaBKNwgVPXZzFzX5D84482EJUw/4hnVyiLhTpX46GOJ9R6h3Y9Kw8Rae5/6 Hw1TzamsqryoLDt1IZTA==; Received: from localhost ([127.0.0.1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.92.2 #3 (Red Hat Linux)) id 1iFtLb-0004Iq-Pt; Thu, 03 Oct 2019 05:08:15 +0000 Received: from esa6.hgst.iphmx.com ([216.71.154.45]) by bombadil.infradead.org with esmtps (Exim 4.92.2 #3 (Red Hat Linux)) id 1iFtLY-0004EU-26 for linux-riscv@lists.infradead.org; Thu, 03 Oct 2019 05:08:14 +0000 DKIM-Signature: v=1; a=rsa-sha256; c=simple/simple; d=wdc.com; i=@wdc.com; q=dns/txt; s=dkim.wdc.com; t=1570079293; x=1601615293; h=from:to:cc:subject:date:message-id:references: in-reply-to:content-transfer-encoding:mime-version; bh=lOJAywCHTuOrxDJOG+3ZaH/TCwB411tVPRgTGN6Xj4Y=; b=bi85nejVA3DxZ4C/8yWIGfa4sBa7fUBnnTmw1386OYhejVOBaLT/a1D5 wuKz/S/2ihEjFdTvEApcp3meGyaabo3vYnRUwQhlot32Yag81ZwxvQC6I clNcYrCBpbFQ/AOVtMbUm4EwqRzB2HbchRnffk1sMJJ2gYYGHaWHqh4sl 4lWheYrdg0tL1o7Xa9FQPhAmliqfxXswzRfxU5ZV7nblboShT4jGgmzao iKWoryJXXa7MsEPivXzvuB/+2xAiTLdbRe+s0BxemnwjR0tAITZrl5P2C bihWuuUjCnMnpkWvE56jAtcYouNk/ww9XVpzq0IDDVYzpb3lgI5fLHWkr w==; IronPort-SDR: Hq10t2d+V90LaLYoaGZ0cVaEPJv++MWJt0EmkeLyc52Fmx9H9d6B7dfJ189Cx/ohZRySNou3YS 6nIFM4QaIRyrSibPmjbpOE4vjZ/UKVZ8IBltuLrDalLdl772FXg8IYNqnEJOtcZV/xW4DrJ8J9 7aiEF85DcDWawB7VncYPMYuQi8SDDwi38AcU3ySr5R+j3QH5u3rtwGaFm/NfopS3L1qwnLaOum 9w8pm7bHhiZDL9ZLJaLwL8nzwTlGMsyxAi3j5Hb0QnrGS0FlZItyJVpZlCs/+OGChfPtbZqub8 +5Y= X-IronPort-AV: E=Sophos;i="5.67,251,1566835200"; d="scan'208";a="121261265" Received: from mail-co1nam05lp2052.outbound.protection.outlook.com (HELO NAM05-CO1-obe.outbound.protection.outlook.com) ([104.47.48.52]) by ob1.hgst.iphmx.com with ESMTP; 03 Oct 2019 13:08:11 +0800 ARC-Seal: i=1; a=rsa-sha256; s=arcselector9901; d=microsoft.com; cv=none; b=Z5QkATmwIepfoE57hP4OuxteV0vHTne0Ze6DXOK4/HqTZcWlTqav6t7ozNu5W2hjUFs2FFrHoe+ZT9oxMPoYhgO08LIR+A3ZCCG11HhuoJr4CDE7s9YKVw/9pGeEg2AJLCJo5yK7wP0topPIptEUSzs1rE/6bl+iWA+wKzd05uPxMkhnQd1fy962kzclnTGbmrZ2qFdD/bFG3VPqWjwLwCFQK7Z8TEBbBbjIuJ5uWKnJCrQUiAg6lwe8QefRxhjTSGV9b/pbXa71c86ZEwRHax/81XXdWTtGW+xkCf6lSJ1Gf9pfYl/fEo2Tie0+6hXNEcRgk3ZxFwBOMe6O5A1sRQ== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=microsoft.com; s=arcselector9901; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-SenderADCheck; bh=uv0pNyEq0essSb6JkldgDaPmXnUQriI+W5YmGG8s2gA=; b=VgdLx0H0475+vN4MLgFOAjvoYgu4Qj4A0U2MJSm88odk+x13tIafUYMkLPwBVwYn6aWezY63bQetFr1pRi3TYyc/cc82SJN9l/MfCo1oWtKFg2wggyXRtbdcvUbVeeDN3H45qndFdVM0zdz1c3IP2T2dxt/V4EFOz0O9js7BGF6RoJnxZCMu6u66mzftHGQMtmloWyStbMkW30OxW/7jCU3+3UuLEAl6E3QpG2JAdACMn+7pwSFY3pxkEIS6X8CUh309QmKOKg7U2ciDQJ08qq8AzcNXO3opouWgLbyITASs7KiQ2z/fO95+cHicnm6uzEMj+ON88mZF6/PlPvziYw== ARC-Authentication-Results: i=1; mx.microsoft.com 1; spf=pass smtp.mailfrom=wdc.com; dmarc=pass action=none header.from=wdc.com; dkim=pass header.d=wdc.com; arc=none DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=sharedspace.onmicrosoft.com; s=selector2-sharedspace-onmicrosoft-com; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-SenderADCheck; bh=uv0pNyEq0essSb6JkldgDaPmXnUQriI+W5YmGG8s2gA=; b=DcFBP7opGkG+I10BaghtzQdtr7rtPTpYA7iba6HcVuRz0/sgJOxMdaVnFroFAMaEJLLYGMo7z6cY4AdvFDFa1jM9kmM6aA4Q91DhKw2EJA4gT3pBn7VpcPA/7EXz2z2XEYzH3Gzzt/81X+fTxXGG39wnig8V9pnXyts2oIeha6M= Received: from MN2PR04MB6061.namprd04.prod.outlook.com (20.178.246.15) by MN2PR04MB6272.namprd04.prod.outlook.com (20.178.248.27) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.2305.17; Thu, 3 Oct 2019 05:08:08 +0000 Received: from MN2PR04MB6061.namprd04.prod.outlook.com ([fe80::1454:87a:13b0:d3a]) by MN2PR04MB6061.namprd04.prod.outlook.com ([fe80::1454:87a:13b0:d3a%7]) with mapi id 15.20.2305.023; Thu, 3 Oct 2019 05:08:08 +0000 From: Anup Patel To: Palmer Dabbelt , Paul Walmsley , Paolo Bonzini , Radim K Subject: [PATCH v8 13/19] RISC-V: KVM: Add timer functionality Thread-Topic: [PATCH v8 13/19] RISC-V: KVM: Add timer functionality Thread-Index: AQHVeaiLAuoxqOOF8EGJxcrPYc3oaA== Date: Thu, 3 Oct 2019 05:08:08 +0000 Message-ID: <20191003050558.9031-14-anup.patel@wdc.com> References: <20191003050558.9031-1-anup.patel@wdc.com> In-Reply-To: <20191003050558.9031-1-anup.patel@wdc.com> Accept-Language: en-US Content-Language: en-US X-MS-Has-Attach: X-MS-TNEF-Correlator: x-clientproxiedby: BMXPR01CA0030.INDPRD01.PROD.OUTLOOK.COM (2603:1096:b00:c::16) To MN2PR04MB6061.namprd04.prod.outlook.com (2603:10b6:208:d8::15) authentication-results: spf=none (sender IP is ) smtp.mailfrom=Anup.Patel@wdc.com; x-ms-exchange-messagesentrepresentingtype: 1 x-mailer: git-send-email 2.17.1 x-originating-ip: [111.235.74.37] x-ms-publictraffictype: Email x-ms-office365-filtering-correlation-id: f519fe5b-5afd-4bb3-af69-08d747bfae2a x-ms-office365-filtering-ht: Tenant x-ms-traffictypediagnostic: MN2PR04MB6272: x-ms-exchange-transport-forked: True x-microsoft-antispam-prvs: wdcipoutbound: EOP-TRUE x-ms-oob-tlc-oobclassifiers: OLM:6108; x-forefront-prvs: 01792087B6 x-forefront-antispam-report: SFV:NSPM; SFS:(10019020)(4636009)(136003)(376002)(346002)(366004)(396003)(39860400002)(189003)(199004)(6512007)(6486002)(81166006)(81156014)(8936002)(6116002)(3846002)(8676002)(50226002)(2906002)(110136005)(66066001)(6436002)(316002)(66476007)(66556008)(7416002)(66446008)(36756003)(1076003)(5660300002)(54906003)(7736002)(305945005)(76176011)(25786009)(52116002)(256004)(14444005)(71190400001)(86362001)(99286004)(71200400001)(2616005)(446003)(14454004)(476003)(102836004)(186003)(26005)(11346002)(44832011)(6506007)(486006)(478600001)(4326008)(66946007)(386003)(64756008); DIR:OUT; SFP:1102; SCL:1; SRVR:MN2PR04MB6272; H:MN2PR04MB6061.namprd04.prod.outlook.com; FPR:; SPF:None; LANG:en; PTR:InfoNoRecords; MX:1; A:1; x-ms-exchange-senderadcheck: 1 x-microsoft-antispam: BCL:0; x-microsoft-antispam-message-info: +PNY7gkXIhjMr99u6xSDEWpysGx9Obda8L7gonjOFiIS5RHdIC4lF5QBcvJRIA28TEXq3fPb1kUQTpewh+JLSJN5lmmoE6xoZGc6nmaat0x3LndpU9j1bFBw2BDrjpLNI/tJ8JT4XFLYrU1xJuBCZO1laMRckNx7oBYknBZW7WBbjvN4RfmLBL0pWLMaClboXRTAXaKuzaG3B1FYZS0osmF3ChVdmUmN90zeeB+TY919WhRxckqGFdz/0V4zq6cG7CWdHw0QFkBucW8xYoASFonxTMoEgaaBVs82sjGyP1C0Yta39xh5YxCGTtTrc8XiFsjQb8EpOGFW+4LrSyNC8gCx2cQu7q4eud9k6hBrrDW8zUp7ZzcIhv0tuI6gZxtfXqcrhYfz4tl0L8JuIglAsGNN+gUwHoD9CtjyYKM4EA0= MIME-Version: 1.0 X-OriginatorOrg: wdc.com X-MS-Exchange-CrossTenant-Network-Message-Id: f519fe5b-5afd-4bb3-af69-08d747bfae2a X-MS-Exchange-CrossTenant-originalarrivaltime: 03 Oct 2019 05:08:08.6081 (UTC) X-MS-Exchange-CrossTenant-fromentityheader: Hosted X-MS-Exchange-CrossTenant-id: b61c8803-16f3-4c35-9b17-6f65f441df86 X-MS-Exchange-CrossTenant-mailboxtype: HOSTED X-MS-Exchange-CrossTenant-userprincipalname: LlnQXbKDEerEuu1zI1kbNhFfJCuarJrlvfEQjB3ck4wsjtuMuQOWdG2a3k5ip6cpyfpDmVLfHrO0VjLvMwQheQ== X-MS-Exchange-Transport-CrossTenantHeadersStamped: MN2PR04MB6272 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20191002_220812_701623_6D8653A8 X-CRM114-Status: GOOD ( 22.47 ) X-Spam-Score: -2.5 (--) X-Spam-Report: SpamAssassin version 3.4.2 on bombadil.infradead.org summary: Content analysis details: (-2.5 points) pts rule name description ---- ---------------------- -------------------------------------------------- -2.3 RCVD_IN_DNSWL_MED RBL: Sender listed at https://www.dnswl.org/, medium trust [216.71.154.45 listed in list.dnswl.org] -0.0 SPF_PASS SPF: sender matches SPF record 0.0 SPF_HELO_NONE SPF: HELO does not publish an SPF Record -0.1 DKIM_VALID_EF Message has a valid DKIM or DK signature from envelope-from domain 0.1 DKIM_SIGNED Message has a DKIM or DK signature, not necessarily valid -0.1 DKIM_VALID_AU Message has a valid DKIM or DK signature from author's domain -0.1 DKIM_VALID Message has at least one valid DKIM or DK signature X-BeenThere: linux-riscv@lists.infradead.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Damien Le Moal , Anup Patel , "kvm@vger.kernel.org" , Anup Patel , Daniel Lezcano , "linux-kernel@vger.kernel.org" , Christoph Hellwig , Atish Patra , Alexander Graf , Alistair Francis , Thomas Gleixner , "linux-riscv@lists.infradead.org" Sender: "linux-riscv" Errors-To: linux-riscv-bounces+patchwork-linux-riscv=patchwork.kernel.org@lists.infradead.org From: Atish Patra The RISC-V hypervisor specification doesn't have any virtual timer feature. Due to this, the guest VCPU timer will be programmed via SBI calls. The host will use a separate hrtimer event for each guest VCPU to provide timer functionality. We inject a virtual timer interrupt to the guest VCPU whenever the guest VCPU hrtimer event expires. The following features are not supported yet and will be added in future: 1. A time offset to adjust guest time from host time 2. A saved next event in guest vcpu for vm migration Signed-off-by: Atish Patra Signed-off-by: Anup Patel Acked-by: Paolo Bonzini Reviewed-by: Paolo Bonzini --- arch/riscv/include/asm/kvm_host.h | 4 + arch/riscv/include/asm/kvm_vcpu_timer.h | 30 +++++++ arch/riscv/kvm/Makefile | 2 +- arch/riscv/kvm/vcpu.c | 6 ++ arch/riscv/kvm/vcpu_timer.c | 113 ++++++++++++++++++++++++ drivers/clocksource/timer-riscv.c | 8 ++ include/clocksource/timer-riscv.h | 16 ++++ 7 files changed, 178 insertions(+), 1 deletion(-) create mode 100644 arch/riscv/include/asm/kvm_vcpu_timer.h create mode 100644 arch/riscv/kvm/vcpu_timer.c create mode 100644 include/clocksource/timer-riscv.h diff --git a/arch/riscv/include/asm/kvm_host.h b/arch/riscv/include/asm/kvm_host.h index 79ceb2aa8ae6..9179ff019235 100644 --- a/arch/riscv/include/asm/kvm_host.h +++ b/arch/riscv/include/asm/kvm_host.h @@ -12,6 +12,7 @@ #include #include #include +#include #ifdef CONFIG_64BIT #define KVM_MAX_VCPUS (1U << 16) @@ -168,6 +169,9 @@ struct kvm_vcpu_arch { unsigned long irqs_pending; unsigned long irqs_pending_mask; + /* VCPU Timer */ + struct kvm_vcpu_timer timer; + /* MMIO instruction details */ struct kvm_mmio_decode mmio_decode; diff --git a/arch/riscv/include/asm/kvm_vcpu_timer.h b/arch/riscv/include/asm/kvm_vcpu_timer.h new file mode 100644 index 000000000000..6f904d49e27e --- /dev/null +++ b/arch/riscv/include/asm/kvm_vcpu_timer.h @@ -0,0 +1,30 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* + * Copyright (C) 2019 Western Digital Corporation or its affiliates. + * + * Authors: + * Atish Patra + */ + +#ifndef __KVM_VCPU_RISCV_TIMER_H +#define __KVM_VCPU_RISCV_TIMER_H + +#include + +struct kvm_vcpu_timer { + bool init_done; + /* Check if the timer is programmed */ + bool next_set; + u64 next_cycles; + struct hrtimer hrt; + /* Mult & Shift values to get nanosec from cycles */ + u32 mult; + u32 shift; +}; + +int kvm_riscv_vcpu_timer_init(struct kvm_vcpu *vcpu); +int kvm_riscv_vcpu_timer_deinit(struct kvm_vcpu *vcpu); +int kvm_riscv_vcpu_timer_reset(struct kvm_vcpu *vcpu); +int kvm_riscv_vcpu_timer_next_event(struct kvm_vcpu *vcpu, u64 ncycles); + +#endif diff --git a/arch/riscv/kvm/Makefile b/arch/riscv/kvm/Makefile index c0f57f26c13d..3e0c7558320d 100644 --- a/arch/riscv/kvm/Makefile +++ b/arch/riscv/kvm/Makefile @@ -9,6 +9,6 @@ ccflags-y := -Ivirt/kvm -Iarch/riscv/kvm kvm-objs := $(common-objs-y) kvm-objs += main.o vm.o vmid.o tlb.o mmu.o -kvm-objs += vcpu.o vcpu_exit.o vcpu_switch.o +kvm-objs += vcpu.o vcpu_exit.o vcpu_switch.o vcpu_timer.o obj-$(CONFIG_KVM) += kvm.o diff --git a/arch/riscv/kvm/vcpu.c b/arch/riscv/kvm/vcpu.c index 12bd837f564a..2ca913f00570 100644 --- a/arch/riscv/kvm/vcpu.c +++ b/arch/riscv/kvm/vcpu.c @@ -54,6 +54,8 @@ static void kvm_riscv_reset_vcpu(struct kvm_vcpu *vcpu) memcpy(cntx, reset_cntx, sizeof(*cntx)); + kvm_riscv_vcpu_timer_reset(vcpu); + WRITE_ONCE(vcpu->arch.irqs_pending, 0); WRITE_ONCE(vcpu->arch.irqs_pending_mask, 0); } @@ -108,6 +110,9 @@ int kvm_arch_vcpu_init(struct kvm_vcpu *vcpu) cntx->hstatus |= HSTATUS_SP2P; cntx->hstatus |= HSTATUS_SPV; + /* Setup VCPU timer */ + kvm_riscv_vcpu_timer_init(vcpu); + /* Reset VCPU */ kvm_riscv_reset_vcpu(vcpu); @@ -116,6 +121,7 @@ int kvm_arch_vcpu_init(struct kvm_vcpu *vcpu) void kvm_arch_vcpu_destroy(struct kvm_vcpu *vcpu) { + kvm_riscv_vcpu_timer_deinit(vcpu); kvm_riscv_stage2_flush_cache(vcpu); kmem_cache_free(kvm_vcpu_cache, vcpu); } diff --git a/arch/riscv/kvm/vcpu_timer.c b/arch/riscv/kvm/vcpu_timer.c new file mode 100644 index 000000000000..9ffdd6ff8d6e --- /dev/null +++ b/arch/riscv/kvm/vcpu_timer.c @@ -0,0 +1,113 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Copyright (C) 2019 Western Digital Corporation or its affiliates. + * + * Authors: + * Atish Patra + */ + +#include +#include +#include +#include +#include +#include + +#define VCPU_TIMER_PROGRAM_THRESHOLD_NS 1000 + +static enum hrtimer_restart kvm_riscv_vcpu_hrtimer_expired(struct hrtimer *h) +{ + struct kvm_vcpu_timer *t = container_of(h, struct kvm_vcpu_timer, hrt); + struct kvm_vcpu *vcpu = container_of(t, struct kvm_vcpu, arch.timer); + + t->next_set = false; + kvm_riscv_vcpu_set_interrupt(vcpu, IRQ_S_TIMER); + + return HRTIMER_NORESTART; +} + +static u64 kvm_riscv_delta_cycles2ns(u64 cycles, struct kvm_vcpu_timer *t) +{ + unsigned long flags; + u64 cycles_now, cycles_delta, delta_ns; + + local_irq_save(flags); + cycles_now = get_cycles64(); + if (cycles_now < cycles) + cycles_delta = cycles - cycles_now; + else + cycles_delta = 0; + delta_ns = (cycles_delta * t->mult) >> t->shift; + local_irq_restore(flags); + + return delta_ns; +} + +static int kvm_riscv_vcpu_timer_cancel(struct kvm_vcpu_timer *t) +{ + if (!t->init_done || !t->next_set) + return -EINVAL; + + hrtimer_cancel(&t->hrt); + t->next_set = false; + + return 0; +} + +int kvm_riscv_vcpu_timer_next_event(struct kvm_vcpu *vcpu, u64 ncycles) +{ + struct kvm_vcpu_timer *t = &vcpu->arch.timer; + u64 delta_ns = kvm_riscv_delta_cycles2ns(ncycles, t); + + if (!t->init_done) + return -EINVAL; + + if (t->next_set) { + hrtimer_cancel(&t->hrt); + t->next_set = false; + } + + kvm_riscv_vcpu_unset_interrupt(vcpu, IRQ_S_TIMER); + + if (delta_ns > VCPU_TIMER_PROGRAM_THRESHOLD_NS) { + hrtimer_start(&t->hrt, ktime_add_ns(ktime_get(), delta_ns), + HRTIMER_MODE_ABS); + t->next_cycles = ncycles; + t->next_set = true; + } else + kvm_riscv_vcpu_set_interrupt(vcpu, IRQ_S_TIMER); + + return 0; +} + +int kvm_riscv_vcpu_timer_init(struct kvm_vcpu *vcpu) +{ + struct kvm_vcpu_timer *t = &vcpu->arch.timer; + + if (t->init_done) + return -EINVAL; + + hrtimer_init(&t->hrt, CLOCK_MONOTONIC, HRTIMER_MODE_ABS); + t->hrt.function = kvm_riscv_vcpu_hrtimer_expired; + t->init_done = true; + t->next_set = false; + + riscv_cs_get_mult_shift(&t->mult, &t->shift); + + return 0; +} + +int kvm_riscv_vcpu_timer_deinit(struct kvm_vcpu *vcpu) +{ + int ret; + + ret = kvm_riscv_vcpu_timer_cancel(&vcpu->arch.timer); + vcpu->arch.timer.init_done = false; + + return ret; +} + +int kvm_riscv_vcpu_timer_reset(struct kvm_vcpu *vcpu) +{ + return kvm_riscv_vcpu_timer_cancel(&vcpu->arch.timer); +} diff --git a/drivers/clocksource/timer-riscv.c b/drivers/clocksource/timer-riscv.c index 470c7ef02ea4..a48036459f3c 100644 --- a/drivers/clocksource/timer-riscv.c +++ b/drivers/clocksource/timer-riscv.c @@ -12,6 +12,7 @@ #include #include #include +#include #include #include #include @@ -71,6 +72,13 @@ static int riscv_timer_dying_cpu(unsigned int cpu) return 0; } +void riscv_cs_get_mult_shift(u32 *mult, u32 *shift) +{ + *mult = riscv_clocksource.mult; + *shift = riscv_clocksource.shift; +} +EXPORT_SYMBOL_GPL(riscv_cs_get_mult_shift); + /* called directly from the low-level interrupt handler */ void riscv_timer_interrupt(void) { diff --git a/include/clocksource/timer-riscv.h b/include/clocksource/timer-riscv.h new file mode 100644 index 000000000000..e94e4feecbe8 --- /dev/null +++ b/include/clocksource/timer-riscv.h @@ -0,0 +1,16 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* + * Copyright (C) 2019 Western Digital Corporation or its affiliates. + * + * Authors: + * Atish Patra + */ + +#ifndef __TIMER_RISCV_H +#define __TIMER_RISCV_H + +#include + +void riscv_cs_get_mult_shift(u32 *mult, u32 *shift); + +#endif From patchwork Thu Oct 3 05:08:15 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Anup Patel X-Patchwork-Id: 11172139 Return-Path: Received: from mail.kernel.org (pdx-korg-mail-1.web.codeaurora.org [172.30.200.123]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id 823EF14DB for ; Thu, 3 Oct 2019 05:08:31 +0000 (UTC) Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id 5AD4921D81 for ; Thu, 3 Oct 2019 05:08:31 +0000 (UTC) Authentication-Results: mail.kernel.org; dkim=pass (2048-bit key) header.d=lists.infradead.org header.i=@lists.infradead.org header.b="Z+SBKvkw"; dkim=fail reason="signature verification failed" (2048-bit key) header.d=wdc.com header.i=@wdc.com header.b="WZLqqGzM"; dkim=fail reason="signature verification failed" (1024-bit key) header.d=sharedspace.onmicrosoft.com header.i=@sharedspace.onmicrosoft.com header.b="QuOT0tKu" DMARC-Filter: OpenDMARC Filter v1.3.2 mail.kernel.org 5AD4921D81 Authentication-Results: mail.kernel.org; dmarc=fail (p=none dis=none) header.from=wdc.com Authentication-Results: mail.kernel.org; spf=none smtp.mailfrom=linux-riscv-bounces+patchwork-linux-riscv=patchwork.kernel.org@lists.infradead.org DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=bombadil.20170209; h=Sender: Content-Transfer-Encoding:Content-Type:Cc:List-Subscribe:List-Help:List-Post: List-Archive:List-Unsubscribe:List-Id:MIME-Version:In-Reply-To:References: Message-ID:Date:Subject:To:From:Reply-To:Content-ID:Content-Description: Resent-Date:Resent-From:Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID: List-Owner; bh=f2vJBsHD9l1yCN7aX41M3bzF48eKjcSOBC/SgDMsbl8=; b=Z+SBKvkwoUCGlI 8DPA1GhOTl2K8YVp/b1qLvKHvTuRIoz6hRiHH4w6EeWrXIXbEwOgW3NCLdVSoxFwQPB2628UU1PP9 +utY/qjACdkmLwMbDvTsU8xJcwmCMVZwBQuSepmK7wzdssHzaFITLg/Mf6ZMrQdpZemE8lxY4z0GU 537l8dutG6JqEgwjPAe1RwBiic7QnA7Jd0rc6PfSZ8pyUUgsPnta2y7kXdxAXBU/hQ3YwFVq7jL6Q af1ospKR2u3Kr+wm3J54q9IsamqvEqB5Ot65AUbLEvezjDkrr7cNBTH20jEPRqAk5MRFoNirc1S1q TrvOedqYQPz3/5gcfbKg==; Received: from localhost ([127.0.0.1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.92.2 #3 (Red Hat Linux)) id 1iFtLi-0004O0-46; Thu, 03 Oct 2019 05:08:22 +0000 Received: from esa2.hgst.iphmx.com ([68.232.143.124]) by bombadil.infradead.org with esmtps (Exim 4.92.2 #3 (Red Hat Linux)) id 1iFtLe-0004MH-Hm for linux-riscv@lists.infradead.org; Thu, 03 Oct 2019 05:08:20 +0000 DKIM-Signature: v=1; a=rsa-sha256; c=simple/simple; d=wdc.com; i=@wdc.com; q=dns/txt; s=dkim.wdc.com; t=1570079320; x=1601615320; h=from:to:cc:subject:date:message-id:references: in-reply-to:content-transfer-encoding:mime-version; bh=4Fzk6cVeZIlt4+wIy15EigYjTK36Lj88cmy2rurEG+s=; b=WZLqqGzMF1cZUbp9bp5Ehwd/wZ8bExnct+fNQnolg5MiHEsTXQj/z3A1 A3OrXy58H8kOLweqOmmGFpTmE160dYghmJ6SoRYScQrBYgMGBKOHpkh8s iOehXCcPsuV7z8Gdzg1tQ9hF205Q7fE+y8wAN0MX0yL+TS5+1TRPc+X0/ 6OnoVJNzOEQuw8d554kZIYv9EZ0hXl8ntuRMXPdeXcKSgdzONX9QoQWdW GSSA6e/kJnuxU5D3t69rs7CjdUWyX5xN1ZAsrIf2DzQUrqx3geb0TxNAe G7CxUMvPugVb/wHJ9hnrR4LCrAWK5chgSD5hOSyuJ1Apckfrkmi10iDe3 Q==; IronPort-SDR: S19f8G3ZCyzYDEZsixfo/TcZxc1gTJ7nOWNXPh1hgwKNgVRxI8xXSR5X8qGLyT56BJlGWrcQm1 oSQyTt93agnBpxLRJsf5rUNCYMMhGIsY+JBm+z76WJs/1frLcd2V3DD0c2ABNsMCRdlBDYEEow b9k2jyTkIZoLGlpazRCg4St6sb3CsE4ybB7a9Ie3hBgPxY2UQtnc/ItuT3L07LNUYak/8molfk GIcIOcnHDbr2QOpa557qm8TXFByL8cQ8VpHxs9YVuYcEEUbCMMR+fsABgszSnrKPFBmrNhAn2O L+c= X-IronPort-AV: E=Sophos;i="5.67,251,1566835200"; d="scan'208";a="220620934" Received: from mail-co1nam05lp2051.outbound.protection.outlook.com (HELO NAM05-CO1-obe.outbound.protection.outlook.com) ([104.47.48.51]) by ob1.hgst.iphmx.com with ESMTP; 03 Oct 2019 13:08:37 +0800 ARC-Seal: i=1; a=rsa-sha256; s=arcselector9901; d=microsoft.com; cv=none; b=DGG9LQRiZJK4TvLLhjJ8MB86egVzha2JwsDCvjAYO/001rl0wgIcRu/Y7wIa5mULn/t/wUsQ75V4rkEC5F35H0j2bkmuarc7fsEtIaOPdyGkbZv1M+/Id92v6ZTYMKsUU52cMkqXGSOii1Gvo2OiSb2OZZRpdT6OO9Q1RqODCplC8e9FcecEfHOJbtUughwyF55uSNBJHyI/KT46SZFS3areXMND7THc4biQ8TAv+0usZYis/AZR9A5VDXYJXBpph5wOu0oQBsFcq3GKbyc8YeqEME0Um89mRen9CJLQyUhIHyHi0XpF0P5faaJzDXsNNV4d1lOzqDdDga3kyGqA4g== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=microsoft.com; s=arcselector9901; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-SenderADCheck; bh=LksY8Do1NbLOh7EPPCongBBl9io2U4KMVVtYkDYArco=; b=BNj2XCKY1WM7LHxcLPNthRnzps/rDO7WP/K+vR9wsoPd5KPGadY7+03nfqn0mM0ZOSghYJvJRxuYnYiR0kIocs/4qxG78Wg6dGK/Y87jlkRq3CSlUOQ1aKJQNYf5HBG6swyCPTyAnQnVbj729Eq8OmF4d2/QCJtUdwKDRo9jPvo28upylBCr1NxC9YN7a0R/uI6auFgEIUu+bIg/cj0lchbBeu8zUj7XGFVCRlIW9e5+wVdusx8w6Ii4e3gQsX1At/por1FPWM87yGk++In0cEGMeCspuztiOn9TpnyjQ3Sks+b+joOpYGHax4OVLViioq3MIJ9vql9ADuE2ZCcgeQ== ARC-Authentication-Results: i=1; mx.microsoft.com 1; spf=pass smtp.mailfrom=wdc.com; dmarc=pass action=none header.from=wdc.com; dkim=pass header.d=wdc.com; arc=none DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=sharedspace.onmicrosoft.com; s=selector2-sharedspace-onmicrosoft-com; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-SenderADCheck; bh=LksY8Do1NbLOh7EPPCongBBl9io2U4KMVVtYkDYArco=; b=QuOT0tKusSoaLlHB/cVGBiwoNQdPUHorFTdziR/LXxwxjpe8ptnEj2lqbjfMlaeOqGyCilCCCAWoLMtBIes/QtlybRub/xLX8G4bAsC9R8Ko+nN85U4IDkZLu9qV/FfJfz+Nw/GR1W+ND6s1QV0jjTTRtqM1LPBJc/wvJHqtqd8= Received: from MN2PR04MB6061.namprd04.prod.outlook.com (20.178.246.15) by MN2PR04MB6272.namprd04.prod.outlook.com (20.178.248.27) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.2305.17; Thu, 3 Oct 2019 05:08:15 +0000 Received: from MN2PR04MB6061.namprd04.prod.outlook.com ([fe80::1454:87a:13b0:d3a]) by MN2PR04MB6061.namprd04.prod.outlook.com ([fe80::1454:87a:13b0:d3a%7]) with mapi id 15.20.2305.023; Thu, 3 Oct 2019 05:08:15 +0000 From: Anup Patel To: Palmer Dabbelt , Paul Walmsley , Paolo Bonzini , Radim K Subject: [PATCH v8 14/19] RISC-V: KVM: FP lazy save/restore Thread-Topic: [PATCH v8 14/19] RISC-V: KVM: FP lazy save/restore Thread-Index: AQHVeaiPCHfihXwevkuk2uCxkZFFTw== Date: Thu, 3 Oct 2019 05:08:15 +0000 Message-ID: <20191003050558.9031-15-anup.patel@wdc.com> References: <20191003050558.9031-1-anup.patel@wdc.com> In-Reply-To: <20191003050558.9031-1-anup.patel@wdc.com> Accept-Language: en-US Content-Language: en-US X-MS-Has-Attach: X-MS-TNEF-Correlator: x-clientproxiedby: BMXPR01CA0030.INDPRD01.PROD.OUTLOOK.COM (2603:1096:b00:c::16) To MN2PR04MB6061.namprd04.prod.outlook.com (2603:10b6:208:d8::15) authentication-results: spf=none (sender IP is ) smtp.mailfrom=Anup.Patel@wdc.com; x-ms-exchange-messagesentrepresentingtype: 1 x-mailer: git-send-email 2.17.1 x-originating-ip: [111.235.74.37] x-ms-publictraffictype: Email x-ms-office365-filtering-correlation-id: c0984983-e73f-4117-f6df-08d747bfb232 x-ms-office365-filtering-ht: Tenant x-ms-traffictypediagnostic: MN2PR04MB6272: x-ms-exchange-transport-forked: True x-microsoft-antispam-prvs: wdcipoutbound: EOP-TRUE x-ms-oob-tlc-oobclassifiers: OLM:7219; x-forefront-prvs: 01792087B6 x-forefront-antispam-report: SFV:NSPM; SFS:(10019020)(4636009)(136003)(376002)(346002)(366004)(396003)(39860400002)(189003)(199004)(6512007)(6486002)(81166006)(81156014)(8936002)(6116002)(3846002)(8676002)(50226002)(2906002)(110136005)(66066001)(6436002)(316002)(66476007)(66556008)(7416002)(66446008)(36756003)(1076003)(5660300002)(54906003)(7736002)(305945005)(76176011)(30864003)(25786009)(52116002)(256004)(14444005)(71190400001)(86362001)(99286004)(71200400001)(2616005)(446003)(14454004)(476003)(102836004)(186003)(26005)(11346002)(44832011)(6506007)(486006)(478600001)(4326008)(66946007)(386003)(64756008); DIR:OUT; SFP:1102; SCL:1; SRVR:MN2PR04MB6272; H:MN2PR04MB6061.namprd04.prod.outlook.com; FPR:; SPF:None; LANG:en; PTR:InfoNoRecords; MX:1; A:1; x-ms-exchange-senderadcheck: 1 x-microsoft-antispam: BCL:0; x-microsoft-antispam-message-info: HmOypSdqBDhXhlj+a4MDsr8WovSaWoyf372to7dSf+r666ci55It7wHVpxvo4GY5c7CpoHxXF00M725ysUKOoXmZQwUiFOu93DU79+zbZsjNtEV2Z/kwlqmONp7CPSP+XpxUOTckfTEpvTqFPyGUmzzsf4eIcN1sJSNiQxvpiTYZJwAYYnBH6tY4PYMS2wWZjqS/5EWkm8upD4ddkhYzY50kKRjaF0/KCkIh3YlnwIm6m7s07/lyuXt4lGh22vEBAXpEVrJqBuE0DLbr3qU8IxQHX4FQWDTMK4Ku88vIBjuSXk0i751JHkJOVI5QnYHl6e3HVskdNChH6l/CtL5pGKBSlN7h2lPRfZSlLEDH3yLOPFZajNrX0iccvQNISlGOgih5MdNVxPwgfh1sCQx6RRQgTon/JoPLtbRaCs0+YPg= MIME-Version: 1.0 X-OriginatorOrg: wdc.com X-MS-Exchange-CrossTenant-Network-Message-Id: c0984983-e73f-4117-f6df-08d747bfb232 X-MS-Exchange-CrossTenant-originalarrivaltime: 03 Oct 2019 05:08:15.3812 (UTC) X-MS-Exchange-CrossTenant-fromentityheader: Hosted X-MS-Exchange-CrossTenant-id: b61c8803-16f3-4c35-9b17-6f65f441df86 X-MS-Exchange-CrossTenant-mailboxtype: HOSTED X-MS-Exchange-CrossTenant-userprincipalname: KyUd426R7XPRZjWlCZ73e70owVASexx6OW6DuShDkxsZ9m+Vm10//+RuSyfUMxXoP+AYzqm7sRSTAB9+X6lB9g== X-MS-Exchange-Transport-CrossTenantHeadersStamped: MN2PR04MB6272 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20191002_220818_639413_3833845E X-CRM114-Status: GOOD ( 12.27 ) X-Spam-Score: -2.5 (--) X-Spam-Report: SpamAssassin version 3.4.2 on bombadil.infradead.org summary: Content analysis details: (-2.5 points) pts rule name description ---- ---------------------- -------------------------------------------------- -2.3 RCVD_IN_DNSWL_MED RBL: Sender listed at https://www.dnswl.org/, medium trust [68.232.143.124 listed in list.dnswl.org] -0.0 SPF_PASS SPF: sender matches SPF record 0.0 SPF_HELO_NONE SPF: HELO does not publish an SPF Record -0.1 DKIM_VALID_EF Message has a valid DKIM or DK signature from envelope-from domain 0.1 DKIM_SIGNED Message has a DKIM or DK signature, not necessarily valid -0.1 DKIM_VALID_AU Message has a valid DKIM or DK signature from author's domain -0.1 DKIM_VALID Message has at least one valid DKIM or DK signature X-BeenThere: linux-riscv@lists.infradead.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Damien Le Moal , Anup Patel , "kvm@vger.kernel.org" , Anup Patel , Daniel Lezcano , "linux-kernel@vger.kernel.org" , Christoph Hellwig , Atish Patra , Alexander Graf , Alistair Francis , Thomas Gleixner , "linux-riscv@lists.infradead.org" Sender: "linux-riscv" Errors-To: linux-riscv-bounces+patchwork-linux-riscv=patchwork.kernel.org@lists.infradead.org From: Atish Patra This patch adds floating point (F and D extension) context save/restore for guest VCPUs. The FP context is saved and restored lazily only when kernel enter/exits the in-kernel run loop and not during the KVM world switch. This way FP save/restore has minimal impact on KVM performance. Signed-off-by: Atish Patra Signed-off-by: Anup Patel Acked-by: Paolo Bonzini Reviewed-by: Paolo Bonzini Reviewed-by: Alexander Graf --- arch/riscv/include/asm/kvm_host.h | 5 + arch/riscv/kernel/asm-offsets.c | 72 +++++++++++++ arch/riscv/kvm/vcpu.c | 81 ++++++++++++++ arch/riscv/kvm/vcpu_switch.S | 174 ++++++++++++++++++++++++++++++ 4 files changed, 332 insertions(+) diff --git a/arch/riscv/include/asm/kvm_host.h b/arch/riscv/include/asm/kvm_host.h index 9179ff019235..928c67828b1b 100644 --- a/arch/riscv/include/asm/kvm_host.h +++ b/arch/riscv/include/asm/kvm_host.h @@ -117,6 +117,7 @@ struct kvm_cpu_context { unsigned long sepc; unsigned long sstatus; unsigned long hstatus; + union __riscv_fp_state fp; }; struct kvm_vcpu_csr { @@ -236,6 +237,10 @@ int kvm_riscv_vcpu_exit(struct kvm_vcpu *vcpu, struct kvm_run *run, unsigned long scause, unsigned long stval); void __kvm_riscv_switch_to(struct kvm_vcpu_arch *vcpu_arch); +void __kvm_riscv_fp_f_save(struct kvm_cpu_context *context); +void __kvm_riscv_fp_f_restore(struct kvm_cpu_context *context); +void __kvm_riscv_fp_d_save(struct kvm_cpu_context *context); +void __kvm_riscv_fp_d_restore(struct kvm_cpu_context *context); int kvm_riscv_vcpu_set_interrupt(struct kvm_vcpu *vcpu, unsigned int irq); int kvm_riscv_vcpu_unset_interrupt(struct kvm_vcpu *vcpu, unsigned int irq); diff --git a/arch/riscv/kernel/asm-offsets.c b/arch/riscv/kernel/asm-offsets.c index 711656710190..9980069a1acf 100644 --- a/arch/riscv/kernel/asm-offsets.c +++ b/arch/riscv/kernel/asm-offsets.c @@ -185,6 +185,78 @@ void asm_offsets(void) OFFSET(KVM_ARCH_HOST_SSCRATCH, kvm_vcpu_arch, host_sscratch); OFFSET(KVM_ARCH_HOST_STVEC, kvm_vcpu_arch, host_stvec); + /* F extension */ + + OFFSET(KVM_ARCH_FP_F_F0, kvm_cpu_context, fp.f.f[0]); + OFFSET(KVM_ARCH_FP_F_F1, kvm_cpu_context, fp.f.f[1]); + OFFSET(KVM_ARCH_FP_F_F2, kvm_cpu_context, fp.f.f[2]); + OFFSET(KVM_ARCH_FP_F_F3, kvm_cpu_context, fp.f.f[3]); + OFFSET(KVM_ARCH_FP_F_F4, kvm_cpu_context, fp.f.f[4]); + OFFSET(KVM_ARCH_FP_F_F5, kvm_cpu_context, fp.f.f[5]); + OFFSET(KVM_ARCH_FP_F_F6, kvm_cpu_context, fp.f.f[6]); + OFFSET(KVM_ARCH_FP_F_F7, kvm_cpu_context, fp.f.f[7]); + OFFSET(KVM_ARCH_FP_F_F8, kvm_cpu_context, fp.f.f[8]); + OFFSET(KVM_ARCH_FP_F_F9, kvm_cpu_context, fp.f.f[9]); + OFFSET(KVM_ARCH_FP_F_F10, kvm_cpu_context, fp.f.f[10]); + OFFSET(KVM_ARCH_FP_F_F11, kvm_cpu_context, fp.f.f[11]); + OFFSET(KVM_ARCH_FP_F_F12, kvm_cpu_context, fp.f.f[12]); + OFFSET(KVM_ARCH_FP_F_F13, kvm_cpu_context, fp.f.f[13]); + OFFSET(KVM_ARCH_FP_F_F14, kvm_cpu_context, fp.f.f[14]); + OFFSET(KVM_ARCH_FP_F_F15, kvm_cpu_context, fp.f.f[15]); + OFFSET(KVM_ARCH_FP_F_F16, kvm_cpu_context, fp.f.f[16]); + OFFSET(KVM_ARCH_FP_F_F17, kvm_cpu_context, fp.f.f[17]); + OFFSET(KVM_ARCH_FP_F_F18, kvm_cpu_context, fp.f.f[18]); + OFFSET(KVM_ARCH_FP_F_F19, kvm_cpu_context, fp.f.f[19]); + OFFSET(KVM_ARCH_FP_F_F20, kvm_cpu_context, fp.f.f[20]); + OFFSET(KVM_ARCH_FP_F_F21, kvm_cpu_context, fp.f.f[21]); + OFFSET(KVM_ARCH_FP_F_F22, kvm_cpu_context, fp.f.f[22]); + OFFSET(KVM_ARCH_FP_F_F23, kvm_cpu_context, fp.f.f[23]); + OFFSET(KVM_ARCH_FP_F_F24, kvm_cpu_context, fp.f.f[24]); + OFFSET(KVM_ARCH_FP_F_F25, kvm_cpu_context, fp.f.f[25]); + OFFSET(KVM_ARCH_FP_F_F26, kvm_cpu_context, fp.f.f[26]); + OFFSET(KVM_ARCH_FP_F_F27, kvm_cpu_context, fp.f.f[27]); + OFFSET(KVM_ARCH_FP_F_F28, kvm_cpu_context, fp.f.f[28]); + OFFSET(KVM_ARCH_FP_F_F29, kvm_cpu_context, fp.f.f[29]); + OFFSET(KVM_ARCH_FP_F_F30, kvm_cpu_context, fp.f.f[30]); + OFFSET(KVM_ARCH_FP_F_F31, kvm_cpu_context, fp.f.f[31]); + OFFSET(KVM_ARCH_FP_F_FCSR, kvm_cpu_context, fp.f.fcsr); + + /* D extension */ + + OFFSET(KVM_ARCH_FP_D_F0, kvm_cpu_context, fp.d.f[0]); + OFFSET(KVM_ARCH_FP_D_F1, kvm_cpu_context, fp.d.f[1]); + OFFSET(KVM_ARCH_FP_D_F2, kvm_cpu_context, fp.d.f[2]); + OFFSET(KVM_ARCH_FP_D_F3, kvm_cpu_context, fp.d.f[3]); + OFFSET(KVM_ARCH_FP_D_F4, kvm_cpu_context, fp.d.f[4]); + OFFSET(KVM_ARCH_FP_D_F5, kvm_cpu_context, fp.d.f[5]); + OFFSET(KVM_ARCH_FP_D_F6, kvm_cpu_context, fp.d.f[6]); + OFFSET(KVM_ARCH_FP_D_F7, kvm_cpu_context, fp.d.f[7]); + OFFSET(KVM_ARCH_FP_D_F8, kvm_cpu_context, fp.d.f[8]); + OFFSET(KVM_ARCH_FP_D_F9, kvm_cpu_context, fp.d.f[9]); + OFFSET(KVM_ARCH_FP_D_F10, kvm_cpu_context, fp.d.f[10]); + OFFSET(KVM_ARCH_FP_D_F11, kvm_cpu_context, fp.d.f[11]); + OFFSET(KVM_ARCH_FP_D_F12, kvm_cpu_context, fp.d.f[12]); + OFFSET(KVM_ARCH_FP_D_F13, kvm_cpu_context, fp.d.f[13]); + OFFSET(KVM_ARCH_FP_D_F14, kvm_cpu_context, fp.d.f[14]); + OFFSET(KVM_ARCH_FP_D_F15, kvm_cpu_context, fp.d.f[15]); + OFFSET(KVM_ARCH_FP_D_F16, kvm_cpu_context, fp.d.f[16]); + OFFSET(KVM_ARCH_FP_D_F17, kvm_cpu_context, fp.d.f[17]); + OFFSET(KVM_ARCH_FP_D_F18, kvm_cpu_context, fp.d.f[18]); + OFFSET(KVM_ARCH_FP_D_F19, kvm_cpu_context, fp.d.f[19]); + OFFSET(KVM_ARCH_FP_D_F20, kvm_cpu_context, fp.d.f[20]); + OFFSET(KVM_ARCH_FP_D_F21, kvm_cpu_context, fp.d.f[21]); + OFFSET(KVM_ARCH_FP_D_F22, kvm_cpu_context, fp.d.f[22]); + OFFSET(KVM_ARCH_FP_D_F23, kvm_cpu_context, fp.d.f[23]); + OFFSET(KVM_ARCH_FP_D_F24, kvm_cpu_context, fp.d.f[24]); + OFFSET(KVM_ARCH_FP_D_F25, kvm_cpu_context, fp.d.f[25]); + OFFSET(KVM_ARCH_FP_D_F26, kvm_cpu_context, fp.d.f[26]); + OFFSET(KVM_ARCH_FP_D_F27, kvm_cpu_context, fp.d.f[27]); + OFFSET(KVM_ARCH_FP_D_F28, kvm_cpu_context, fp.d.f[28]); + OFFSET(KVM_ARCH_FP_D_F29, kvm_cpu_context, fp.d.f[29]); + OFFSET(KVM_ARCH_FP_D_F30, kvm_cpu_context, fp.d.f[30]); + OFFSET(KVM_ARCH_FP_D_F31, kvm_cpu_context, fp.d.f[31]); + OFFSET(KVM_ARCH_FP_D_FCSR, kvm_cpu_context, fp.d.fcsr); + /* * THREAD_{F,X}* might be larger than a S-type offset can handle, but * these are used in performance-sensitive assembly so we can't resort diff --git a/arch/riscv/kvm/vcpu.c b/arch/riscv/kvm/vcpu.c index 2ca913f00570..67f9dd66f2db 100644 --- a/arch/riscv/kvm/vcpu.c +++ b/arch/riscv/kvm/vcpu.c @@ -32,6 +32,76 @@ struct kvm_stats_debugfs_item debugfs_entries[] = { { NULL } }; +#ifdef CONFIG_FPU +static void kvm_riscv_vcpu_fp_reset(struct kvm_vcpu *vcpu) +{ + unsigned long isa = vcpu->arch.isa; + struct kvm_cpu_context *cntx = &vcpu->arch.guest_context; + + cntx->sstatus &= ~SR_FS; + if (riscv_isa_extension_available(&isa, f) || + riscv_isa_extension_available(&isa, d)) + cntx->sstatus |= SR_FS_INITIAL; + else + cntx->sstatus |= SR_FS_OFF; +} + +static void kvm_riscv_vcpu_fp_clean(struct kvm_cpu_context *cntx) +{ + cntx->sstatus &= ~SR_FS; + cntx->sstatus |= SR_FS_CLEAN; +} + +static void kvm_riscv_vcpu_guest_fp_save(struct kvm_cpu_context *cntx, + unsigned long isa) +{ + if ((cntx->sstatus & SR_FS) == SR_FS_DIRTY) { + if (riscv_isa_extension_available(&isa, d)) + __kvm_riscv_fp_d_save(cntx); + else if (riscv_isa_extension_available(&isa, f)) + __kvm_riscv_fp_f_save(cntx); + kvm_riscv_vcpu_fp_clean(cntx); + } +} + +static void kvm_riscv_vcpu_guest_fp_restore(struct kvm_cpu_context *cntx, + unsigned long isa) +{ + if ((cntx->sstatus & SR_FS) != SR_FS_OFF) { + if (riscv_isa_extension_available(&isa, d)) + __kvm_riscv_fp_d_restore(cntx); + else if (riscv_isa_extension_available(&isa, f)) + __kvm_riscv_fp_f_restore(cntx); + kvm_riscv_vcpu_fp_clean(cntx); + } +} + +static void kvm_riscv_vcpu_host_fp_save(struct kvm_cpu_context *cntx) +{ + /* No need to check host sstatus as it can be modified outside */ + if (riscv_isa_extension_available(NULL, d)) + __kvm_riscv_fp_d_save(cntx); + else if (riscv_isa_extension_available(NULL, f)) + __kvm_riscv_fp_f_save(cntx); +} + +static void kvm_riscv_vcpu_host_fp_restore(struct kvm_cpu_context *cntx) +{ + if (riscv_isa_extension_available(NULL, d)) + __kvm_riscv_fp_d_restore(cntx); + else if (riscv_isa_extension_available(NULL, f)) + __kvm_riscv_fp_f_restore(cntx); +} +#else +static void kvm_riscv_vcpu_fp_reset(struct kvm_vcpu *vcpu) {} +static void kvm_riscv_vcpu_guest_fp_save(struct kvm_cpu_context *cntx, + unsigned long isa) {} +static void kvm_riscv_vcpu_guest_fp_restore(struct kvm_cpu_context *cntx, + unsigned long isa) {} +static void kvm_riscv_vcpu_host_fp_save(struct kvm_cpu_context *cntx) {} +static void kvm_riscv_vcpu_host_fp_restore(struct kvm_cpu_context *cntx) {} +#endif + #define KVM_RISCV_ISA_ALLOWED (riscv_isa_extension_mask(a) | \ riscv_isa_extension_mask(c) | \ riscv_isa_extension_mask(d) | \ @@ -54,6 +124,8 @@ static void kvm_riscv_reset_vcpu(struct kvm_vcpu *vcpu) memcpy(cntx, reset_cntx, sizeof(*cntx)); + kvm_riscv_vcpu_fp_reset(vcpu); + kvm_riscv_vcpu_timer_reset(vcpu); WRITE_ONCE(vcpu->arch.irqs_pending, 0); @@ -223,6 +295,7 @@ static int kvm_riscv_vcpu_set_reg_config(struct kvm_vcpu *vcpu, vcpu->arch.isa = reg_val; vcpu->arch.isa &= riscv_isa_extension_base(NULL); vcpu->arch.isa &= KVM_RISCV_ISA_ALLOWED; + kvm_riscv_vcpu_fp_reset(vcpu); } else { return -ENOTSUPP; } @@ -604,6 +677,10 @@ void kvm_arch_vcpu_load(struct kvm_vcpu *vcpu, int cpu) kvm_riscv_stage2_update_hgatp(vcpu); + kvm_riscv_vcpu_host_fp_save(&vcpu->arch.host_context); + kvm_riscv_vcpu_guest_fp_restore(&vcpu->arch.guest_context, + vcpu->arch.isa); + vcpu->cpu = cpu; } @@ -613,6 +690,10 @@ void kvm_arch_vcpu_put(struct kvm_vcpu *vcpu) vcpu->cpu = -1; + kvm_riscv_vcpu_guest_fp_save(&vcpu->arch.guest_context, + vcpu->arch.isa); + kvm_riscv_vcpu_host_fp_restore(&vcpu->arch.host_context); + csr_write(CSR_HGATP, 0); csr->vsstatus = csr_read(CSR_VSSTATUS); diff --git a/arch/riscv/kvm/vcpu_switch.S b/arch/riscv/kvm/vcpu_switch.S index 04b318b9eef8..20104b42e833 100644 --- a/arch/riscv/kvm/vcpu_switch.S +++ b/arch/riscv/kvm/vcpu_switch.S @@ -206,3 +206,177 @@ ENTRY(__kvm_riscv_unpriv_trap) csrr a0, CSR_SCAUSE sret ENDPROC(__kvm_riscv_unpriv_trap) + +#ifdef CONFIG_FPU + .align 3 + .global __kvm_riscv_fp_f_save +__kvm_riscv_fp_f_save: + csrr t2, CSR_SSTATUS + li t1, SR_FS + csrs CSR_SSTATUS, t1 + frcsr t0 + fsw f0, KVM_ARCH_FP_F_F0(a0) + fsw f1, KVM_ARCH_FP_F_F1(a0) + fsw f2, KVM_ARCH_FP_F_F2(a0) + fsw f3, KVM_ARCH_FP_F_F3(a0) + fsw f4, KVM_ARCH_FP_F_F4(a0) + fsw f5, KVM_ARCH_FP_F_F5(a0) + fsw f6, KVM_ARCH_FP_F_F6(a0) + fsw f7, KVM_ARCH_FP_F_F7(a0) + fsw f8, KVM_ARCH_FP_F_F8(a0) + fsw f9, KVM_ARCH_FP_F_F9(a0) + fsw f10, KVM_ARCH_FP_F_F10(a0) + fsw f11, KVM_ARCH_FP_F_F11(a0) + fsw f12, KVM_ARCH_FP_F_F12(a0) + fsw f13, KVM_ARCH_FP_F_F13(a0) + fsw f14, KVM_ARCH_FP_F_F14(a0) + fsw f15, KVM_ARCH_FP_F_F15(a0) + fsw f16, KVM_ARCH_FP_F_F16(a0) + fsw f17, KVM_ARCH_FP_F_F17(a0) + fsw f18, KVM_ARCH_FP_F_F18(a0) + fsw f19, KVM_ARCH_FP_F_F19(a0) + fsw f20, KVM_ARCH_FP_F_F20(a0) + fsw f21, KVM_ARCH_FP_F_F21(a0) + fsw f22, KVM_ARCH_FP_F_F22(a0) + fsw f23, KVM_ARCH_FP_F_F23(a0) + fsw f24, KVM_ARCH_FP_F_F24(a0) + fsw f25, KVM_ARCH_FP_F_F25(a0) + fsw f26, KVM_ARCH_FP_F_F26(a0) + fsw f27, KVM_ARCH_FP_F_F27(a0) + fsw f28, KVM_ARCH_FP_F_F28(a0) + fsw f29, KVM_ARCH_FP_F_F29(a0) + fsw f30, KVM_ARCH_FP_F_F30(a0) + fsw f31, KVM_ARCH_FP_F_F31(a0) + sw t0, KVM_ARCH_FP_F_FCSR(a0) + csrw CSR_SSTATUS, t2 + ret + + .align 3 + .global __kvm_riscv_fp_d_save +__kvm_riscv_fp_d_save: + csrr t2, CSR_SSTATUS + li t1, SR_FS + csrs CSR_SSTATUS, t1 + frcsr t0 + fsd f0, KVM_ARCH_FP_D_F0(a0) + fsd f1, KVM_ARCH_FP_D_F1(a0) + fsd f2, KVM_ARCH_FP_D_F2(a0) + fsd f3, KVM_ARCH_FP_D_F3(a0) + fsd f4, KVM_ARCH_FP_D_F4(a0) + fsd f5, KVM_ARCH_FP_D_F5(a0) + fsd f6, KVM_ARCH_FP_D_F6(a0) + fsd f7, KVM_ARCH_FP_D_F7(a0) + fsd f8, KVM_ARCH_FP_D_F8(a0) + fsd f9, KVM_ARCH_FP_D_F9(a0) + fsd f10, KVM_ARCH_FP_D_F10(a0) + fsd f11, KVM_ARCH_FP_D_F11(a0) + fsd f12, KVM_ARCH_FP_D_F12(a0) + fsd f13, KVM_ARCH_FP_D_F13(a0) + fsd f14, KVM_ARCH_FP_D_F14(a0) + fsd f15, KVM_ARCH_FP_D_F15(a0) + fsd f16, KVM_ARCH_FP_D_F16(a0) + fsd f17, KVM_ARCH_FP_D_F17(a0) + fsd f18, KVM_ARCH_FP_D_F18(a0) + fsd f19, KVM_ARCH_FP_D_F19(a0) + fsd f20, KVM_ARCH_FP_D_F20(a0) + fsd f21, KVM_ARCH_FP_D_F21(a0) + fsd f22, KVM_ARCH_FP_D_F22(a0) + fsd f23, KVM_ARCH_FP_D_F23(a0) + fsd f24, KVM_ARCH_FP_D_F24(a0) + fsd f25, KVM_ARCH_FP_D_F25(a0) + fsd f26, KVM_ARCH_FP_D_F26(a0) + fsd f27, KVM_ARCH_FP_D_F27(a0) + fsd f28, KVM_ARCH_FP_D_F28(a0) + fsd f29, KVM_ARCH_FP_D_F29(a0) + fsd f30, KVM_ARCH_FP_D_F30(a0) + fsd f31, KVM_ARCH_FP_D_F31(a0) + sw t0, KVM_ARCH_FP_D_FCSR(a0) + csrw CSR_SSTATUS, t2 + ret + + .align 3 + .global __kvm_riscv_fp_f_restore +__kvm_riscv_fp_f_restore: + csrr t2, CSR_SSTATUS + li t1, SR_FS + lw t0, KVM_ARCH_FP_F_FCSR(a0) + csrs CSR_SSTATUS, t1 + flw f0, KVM_ARCH_FP_F_F0(a0) + flw f1, KVM_ARCH_FP_F_F1(a0) + flw f2, KVM_ARCH_FP_F_F2(a0) + flw f3, KVM_ARCH_FP_F_F3(a0) + flw f4, KVM_ARCH_FP_F_F4(a0) + flw f5, KVM_ARCH_FP_F_F5(a0) + flw f6, KVM_ARCH_FP_F_F6(a0) + flw f7, KVM_ARCH_FP_F_F7(a0) + flw f8, KVM_ARCH_FP_F_F8(a0) + flw f9, KVM_ARCH_FP_F_F9(a0) + flw f10, KVM_ARCH_FP_F_F10(a0) + flw f11, KVM_ARCH_FP_F_F11(a0) + flw f12, KVM_ARCH_FP_F_F12(a0) + flw f13, KVM_ARCH_FP_F_F13(a0) + flw f14, KVM_ARCH_FP_F_F14(a0) + flw f15, KVM_ARCH_FP_F_F15(a0) + flw f16, KVM_ARCH_FP_F_F16(a0) + flw f17, KVM_ARCH_FP_F_F17(a0) + flw f18, KVM_ARCH_FP_F_F18(a0) + flw f19, KVM_ARCH_FP_F_F19(a0) + flw f20, KVM_ARCH_FP_F_F20(a0) + flw f21, KVM_ARCH_FP_F_F21(a0) + flw f22, KVM_ARCH_FP_F_F22(a0) + flw f23, KVM_ARCH_FP_F_F23(a0) + flw f24, KVM_ARCH_FP_F_F24(a0) + flw f25, KVM_ARCH_FP_F_F25(a0) + flw f26, KVM_ARCH_FP_F_F26(a0) + flw f27, KVM_ARCH_FP_F_F27(a0) + flw f28, KVM_ARCH_FP_F_F28(a0) + flw f29, KVM_ARCH_FP_F_F29(a0) + flw f30, KVM_ARCH_FP_F_F30(a0) + flw f31, KVM_ARCH_FP_F_F31(a0) + fscsr t0 + csrw CSR_SSTATUS, t2 + ret + + .align 3 + .global __kvm_riscv_fp_d_restore +__kvm_riscv_fp_d_restore: + csrr t2, CSR_SSTATUS + li t1, SR_FS + lw t0, KVM_ARCH_FP_D_FCSR(a0) + csrs CSR_SSTATUS, t1 + fld f0, KVM_ARCH_FP_D_F0(a0) + fld f1, KVM_ARCH_FP_D_F1(a0) + fld f2, KVM_ARCH_FP_D_F2(a0) + fld f3, KVM_ARCH_FP_D_F3(a0) + fld f4, KVM_ARCH_FP_D_F4(a0) + fld f5, KVM_ARCH_FP_D_F5(a0) + fld f6, KVM_ARCH_FP_D_F6(a0) + fld f7, KVM_ARCH_FP_D_F7(a0) + fld f8, KVM_ARCH_FP_D_F8(a0) + fld f9, KVM_ARCH_FP_D_F9(a0) + fld f10, KVM_ARCH_FP_D_F10(a0) + fld f11, KVM_ARCH_FP_D_F11(a0) + fld f12, KVM_ARCH_FP_D_F12(a0) + fld f13, KVM_ARCH_FP_D_F13(a0) + fld f14, KVM_ARCH_FP_D_F14(a0) + fld f15, KVM_ARCH_FP_D_F15(a0) + fld f16, KVM_ARCH_FP_D_F16(a0) + fld f17, KVM_ARCH_FP_D_F17(a0) + fld f18, KVM_ARCH_FP_D_F18(a0) + fld f19, KVM_ARCH_FP_D_F19(a0) + fld f20, KVM_ARCH_FP_D_F20(a0) + fld f21, KVM_ARCH_FP_D_F21(a0) + fld f22, KVM_ARCH_FP_D_F22(a0) + fld f23, KVM_ARCH_FP_D_F23(a0) + fld f24, KVM_ARCH_FP_D_F24(a0) + fld f25, KVM_ARCH_FP_D_F25(a0) + fld f26, KVM_ARCH_FP_D_F26(a0) + fld f27, KVM_ARCH_FP_D_F27(a0) + fld f28, KVM_ARCH_FP_D_F28(a0) + fld f29, KVM_ARCH_FP_D_F29(a0) + fld f30, KVM_ARCH_FP_D_F30(a0) + fld f31, KVM_ARCH_FP_D_F31(a0) + fscsr t0 + csrw CSR_SSTATUS, t2 + ret +#endif From patchwork Thu Oct 3 05:08:22 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Anup Patel X-Patchwork-Id: 11172145 Return-Path: Received: from mail.kernel.org (pdx-korg-mail-1.web.codeaurora.org [172.30.200.123]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id 994D014DB for ; Thu, 3 Oct 2019 05:08:37 +0000 (UTC) Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id 7367021D81 for ; Thu, 3 Oct 2019 05:08:37 +0000 (UTC) Authentication-Results: mail.kernel.org; dkim=pass (2048-bit key) header.d=lists.infradead.org header.i=@lists.infradead.org header.b="Iu1YaYVD"; dkim=fail reason="signature verification failed" (2048-bit key) header.d=wdc.com header.i=@wdc.com header.b="WaGSHTXK"; dkim=fail reason="signature verification failed" (1024-bit key) header.d=sharedspace.onmicrosoft.com header.i=@sharedspace.onmicrosoft.com header.b="Ql/+gFWW" DMARC-Filter: OpenDMARC Filter v1.3.2 mail.kernel.org 7367021D81 Authentication-Results: mail.kernel.org; dmarc=fail (p=none dis=none) header.from=wdc.com Authentication-Results: mail.kernel.org; spf=none smtp.mailfrom=linux-riscv-bounces+patchwork-linux-riscv=patchwork.kernel.org@lists.infradead.org DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=bombadil.20170209; h=Sender: Content-Transfer-Encoding:Content-Type:Cc:List-Subscribe:List-Help:List-Post: List-Archive:List-Unsubscribe:List-Id:MIME-Version:In-Reply-To:References: Message-ID:Date:Subject:To:From:Reply-To:Content-ID:Content-Description: Resent-Date:Resent-From:Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID: List-Owner; bh=J7q/RbRLOHedetQC/po8ENvyF9vFGRa8bcn1AcMFLQA=; b=Iu1YaYVDEP1Ahy PMe/Em3O8npsM30vC9se3O9AxjSeH6GZr7N+pCHJPzrDq4b+2kbDJvQBt3yWWKknfBUjhKfe25U+X beXH4RWakaty48D4zhGaRD2dM8y0E4Z/WFBEdBYMI4uVUX/6v1tZ4JEci8xd3gEfqxDrMCjX4FayV t2Q2EAzmg9NVRbn5w6yaJz4SliHtR4o5c1k5qNIJa1fZFikoTyj9tXeW7GsFHGJ6qUm0gCG/akCFp Z5gGiGxtCDLgCwcAcKaG6Rlide9FoMztcQfeNG89QzuccvzFVssYP5D8om+NaB+jWA1c/hYgWpxO1 DMncLVfBvUe0SVzHnSaA==; Received: from localhost ([127.0.0.1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.92.2 #3 (Red Hat Linux)) id 1iFtLp-0004Tm-5H; Thu, 03 Oct 2019 05:08:29 +0000 Received: from esa2.hgst.iphmx.com ([68.232.143.124]) by bombadil.infradead.org with esmtps (Exim 4.92.2 #3 (Red Hat Linux)) id 1iFtLm-0004Rp-7X for linux-riscv@lists.infradead.org; Thu, 03 Oct 2019 05:08:27 +0000 DKIM-Signature: v=1; a=rsa-sha256; c=simple/simple; d=wdc.com; i=@wdc.com; q=dns/txt; s=dkim.wdc.com; t=1570079306; x=1601615306; h=from:to:cc:subject:date:message-id:references: in-reply-to:content-transfer-encoding:mime-version; bh=PZBRiBU38f2jrqy1t+akB8Ywq4hOghbEHDzdfzEzS7I=; b=WaGSHTXKTBKQqKT5MmfsfyB9zIs1aPc/tjeosShbyfN8OJrepWMgolk/ emKvNXHxlkzsYhWG818gI5t50RA+1aLZAzT5cx/OxNQMZKalaYLbRcq8D +cJHCcVLZMvuSpFGm+zML0gECLGFpBtxTRUtjD+FzNCgP4IQGDgK2o5qa 4MvLymSUNSw6/bluHWJelJpv20ZvK04A55IPpn1NSa1TPwnd/G7kmjifG uGlM6Iz4d3O98XXBJ6dNSjdnkfC6fYsY6MrTrFD4XKw0+YWktlK9II2+x Mlv4N3R+F/peLmEunL3qGRag8x5lgCijIS0jP0XIT/wSxeRxeAGtbsS+M Q==; IronPort-SDR: 8/uCRcLXvfecHZmife5vIO7C7NUfvORUV9bxf3nFIiarVfl0QSD8SPGg7mlvUjmRWjBcW6lANg PsIZlIDRYx+B+nf7AAMwqmYdo/Jofx3hkzSpzQ7eWtW//mEOO5zZqBhzzDdrV/DuT27QCxzx+b XIn1l6SuSxJPJNtodICPTXaE4M5XIZCHXpfLc9Q+ok3UVts5b84iVxXzEMuqnDhbQhDZi9XNZi HsjFq4+cRfQn19uM0cE+MHp6ZyF/cKagtOfEKUKk1T9iW069P8YXCIMsqAp1l5ox1HE0KBHPrI CUk= X-IronPort-AV: E=Sophos;i="5.67,251,1566835200"; d="scan'208";a="220620941" Received: from mail-by2nam05lp2050.outbound.protection.outlook.com (HELO NAM05-BY2-obe.outbound.protection.outlook.com) ([104.47.50.50]) by ob1.hgst.iphmx.com with ESMTP; 03 Oct 2019 13:08:27 +0800 ARC-Seal: i=1; a=rsa-sha256; s=arcselector9901; d=microsoft.com; cv=none; b=f/cW1ra60LbnVUp7wzF7UgassL1/TBrKdDClE5IdVvMGiEZl/SUkQsMPXFd+aix0V+7bDPTeyI7TCbMlVP/UmXWZynDQlP5D05YGsGQJc+5Y4Zvgv9Dbc0SG6/IZ2UfUhQ3qp8VC5w57eWBAbMqAVNdyd02VZ2XCeiIlkx2E7egSy4r6u9ujZXJUzYCMHcpaBf+E++orf5az/tD0spP16ks2hMqd6KAaRb8f3ypbNZOX5/SXfCTLDduRcHK7Wd5Z9N9j5vKrvbyIIQ0wGCPfDnYj4VPprSlIPmZgkfrxwlx9EJ3qxVFJx0vDvLtqGrxHJORlXjDVYqkviUKBDvbtuw== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=microsoft.com; s=arcselector9901; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-SenderADCheck; bh=IWVrPy7wNf3FXSrWSDl4i48zJNUOG1vq63QfXlJlT2k=; b=MloA96WuFR0lbiKYNwJ/2A8lGiGPISMtr9JMMt4MpYd3S+oFfdGwPboPU11HTfyHpVbHO982iaWFjo5SVHxlZGhLeKSEGuobP3LPd3tWIUqi+WadwPiQs3lS70qi5tt5a5E9LHrjQoCmb23RFNKKZfj3AL2kBU42ed+1N/GPbBP4gNIAc6Pg1B8arpAMHq7ziZoLkZn0aHbjBGuiIOaP/F3qwvSCypshCZrQf+sA1hH+RrEvNUjL9yU0XpMP+n3zgJvpJCVtbRVCB1lWZcailhEEEOUJTSiu3uJuUjM3EDRPwfo2Cgez+wOBgdvFmW7r+xEK961OhZw7xU/nA45BoQ== ARC-Authentication-Results: i=1; mx.microsoft.com 1; spf=pass smtp.mailfrom=wdc.com; dmarc=pass action=none header.from=wdc.com; dkim=pass header.d=wdc.com; arc=none DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=sharedspace.onmicrosoft.com; s=selector2-sharedspace-onmicrosoft-com; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-SenderADCheck; bh=IWVrPy7wNf3FXSrWSDl4i48zJNUOG1vq63QfXlJlT2k=; b=Ql/+gFWWU7YQO1meR3V1+EpIhheIJvdk3eBqx7Iwq0pMhIRrG/k69FRpmdW5cCXpIBF9ZgAYUuuiiruncrad4c/gsrmBVPTIDU+EL7zbkwp/800ihOgc4knhf8EUpZ6aCOXSl1LpWiT93xxMbxxXhO+r98W1+W89aXkl3M+GCrE= Received: from MN2PR04MB6061.namprd04.prod.outlook.com (20.178.246.15) by MN2PR04MB6272.namprd04.prod.outlook.com (20.178.248.27) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.2305.17; Thu, 3 Oct 2019 05:08:22 +0000 Received: from MN2PR04MB6061.namprd04.prod.outlook.com ([fe80::1454:87a:13b0:d3a]) by MN2PR04MB6061.namprd04.prod.outlook.com ([fe80::1454:87a:13b0:d3a%7]) with mapi id 15.20.2305.023; Thu, 3 Oct 2019 05:08:22 +0000 From: Anup Patel To: Palmer Dabbelt , Paul Walmsley , Paolo Bonzini , Radim K Subject: [PATCH v8 15/19] RISC-V: KVM: Implement ONE REG interface for FP registers Thread-Topic: [PATCH v8 15/19] RISC-V: KVM: Implement ONE REG interface for FP registers Thread-Index: AQHVeaiU7of7gPs79kGPLpzrTZ9duw== Date: Thu, 3 Oct 2019 05:08:22 +0000 Message-ID: <20191003050558.9031-16-anup.patel@wdc.com> References: <20191003050558.9031-1-anup.patel@wdc.com> In-Reply-To: <20191003050558.9031-1-anup.patel@wdc.com> Accept-Language: en-US Content-Language: en-US X-MS-Has-Attach: X-MS-TNEF-Correlator: x-clientproxiedby: BMXPR01CA0030.INDPRD01.PROD.OUTLOOK.COM (2603:1096:b00:c::16) To MN2PR04MB6061.namprd04.prod.outlook.com (2603:10b6:208:d8::15) authentication-results: spf=none (sender IP is ) smtp.mailfrom=Anup.Patel@wdc.com; x-ms-exchange-messagesentrepresentingtype: 1 x-mailer: git-send-email 2.17.1 x-originating-ip: [111.235.74.37] x-ms-publictraffictype: Email x-ms-office365-filtering-correlation-id: 09755b12-d369-4b85-79e1-08d747bfb64c x-ms-office365-filtering-ht: Tenant x-ms-traffictypediagnostic: MN2PR04MB6272: x-ms-exchange-transport-forked: True x-microsoft-antispam-prvs: wdcipoutbound: EOP-TRUE x-ms-oob-tlc-oobclassifiers: OLM:854; x-forefront-prvs: 01792087B6 x-forefront-antispam-report: SFV:NSPM; SFS:(10019020)(4636009)(136003)(376002)(346002)(366004)(396003)(39860400002)(189003)(199004)(6512007)(6486002)(81166006)(81156014)(8936002)(6116002)(3846002)(8676002)(50226002)(2906002)(110136005)(66066001)(6436002)(316002)(66476007)(66556008)(7416002)(66446008)(36756003)(1076003)(5660300002)(54906003)(7736002)(305945005)(76176011)(25786009)(52116002)(256004)(71190400001)(86362001)(99286004)(71200400001)(2616005)(446003)(14454004)(476003)(102836004)(186003)(26005)(11346002)(44832011)(6506007)(486006)(478600001)(4326008)(66946007)(386003)(64756008); DIR:OUT; SFP:1102; SCL:1; SRVR:MN2PR04MB6272; H:MN2PR04MB6061.namprd04.prod.outlook.com; FPR:; SPF:None; LANG:en; PTR:InfoNoRecords; MX:1; A:1; x-ms-exchange-senderadcheck: 1 x-microsoft-antispam: BCL:0; x-microsoft-antispam-message-info: aqRh407RMM2EQz8bdsuZ/JJuRxqJuOz2R788kOW2+O1JPMq/rY1AFf2Ymmghtc17v6ONxta/TqEy6MYMljGYbb4mdL+izlDI6pILPjbFMd8eDGxEkRzLRCSlE/I8FJ+juZZG96j9tJ/bOXMqv3QxRIVSDsG09OaHpfrh+ez5yP3vnYnVPcLfzZmx/CIHemjv3MOlwCEoU019tSfwHzbWG2Bvho+brqV5tLa7cjF4Kt2FghOEzjRmS+Qm+EjmkNpa9unkVrnC7ZD+cWWmqBrqmCrvHYlZV/SNte1+CdDqnYAmhngvHG9SLu1kVK9ksikIkw2HWEm+odh3nz1Rh5YWdP4MANK9QFsHE3S15TILG+gykHeNRSgs2NCuboyEnwnJ8HUInOPfmCndOthMdy+GkiNCSut6mGFO0Yhv3gkJ1a0= MIME-Version: 1.0 X-OriginatorOrg: wdc.com X-MS-Exchange-CrossTenant-Network-Message-Id: 09755b12-d369-4b85-79e1-08d747bfb64c X-MS-Exchange-CrossTenant-originalarrivaltime: 03 Oct 2019 05:08:22.2953 (UTC) X-MS-Exchange-CrossTenant-fromentityheader: Hosted X-MS-Exchange-CrossTenant-id: b61c8803-16f3-4c35-9b17-6f65f441df86 X-MS-Exchange-CrossTenant-mailboxtype: HOSTED X-MS-Exchange-CrossTenant-userprincipalname: X4DQU8PaJfwIhIut9ycNi/NYx3Oxufk5lTzC0gaba/2ebFj02+qtZyktJcgF1d2QX58QDsmPQp8GT+SF4m4rlg== X-MS-Exchange-Transport-CrossTenantHeadersStamped: MN2PR04MB6272 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20191002_220826_310632_B0688BF8 X-CRM114-Status: GOOD ( 14.07 ) X-Spam-Score: -2.5 (--) X-Spam-Report: SpamAssassin version 3.4.2 on bombadil.infradead.org summary: Content analysis details: (-2.5 points) pts rule name description ---- ---------------------- -------------------------------------------------- -2.3 RCVD_IN_DNSWL_MED RBL: Sender listed at https://www.dnswl.org/, medium trust [68.232.143.124 listed in list.dnswl.org] -0.0 SPF_PASS SPF: sender matches SPF record 0.0 SPF_HELO_NONE SPF: HELO does not publish an SPF Record -0.1 DKIM_VALID_EF Message has a valid DKIM or DK signature from envelope-from domain 0.1 DKIM_SIGNED Message has a DKIM or DK signature, not necessarily valid -0.1 DKIM_VALID_AU Message has a valid DKIM or DK signature from author's domain -0.1 DKIM_VALID Message has at least one valid DKIM or DK signature X-BeenThere: linux-riscv@lists.infradead.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Damien Le Moal , Anup Patel , "kvm@vger.kernel.org" , Anup Patel , Daniel Lezcano , "linux-kernel@vger.kernel.org" , Christoph Hellwig , Atish Patra , Alexander Graf , Alistair Francis , Thomas Gleixner , "linux-riscv@lists.infradead.org" Sender: "linux-riscv" Errors-To: linux-riscv-bounces+patchwork-linux-riscv=patchwork.kernel.org@lists.infradead.org From: Atish Patra Add a KVM_GET_ONE_REG/KVM_SET_ONE_REG ioctl interface for floating point registers such as F0-F31 and FCSR. This support is added for both 'F' and 'D' extensions. Signed-off-by: Atish Patra Signed-off-by: Anup Patel Acked-by: Paolo Bonzini Reviewed-by: Paolo Bonzini Reviewed-by: Alexander Graf --- arch/riscv/include/uapi/asm/kvm.h | 10 +++ arch/riscv/kvm/vcpu.c | 104 ++++++++++++++++++++++++++++++ 2 files changed, 114 insertions(+) diff --git a/arch/riscv/include/uapi/asm/kvm.h b/arch/riscv/include/uapi/asm/kvm.h index 997b85f6fded..19811823ab70 100644 --- a/arch/riscv/include/uapi/asm/kvm.h +++ b/arch/riscv/include/uapi/asm/kvm.h @@ -96,6 +96,16 @@ struct kvm_riscv_csr { #define KVM_REG_RISCV_CSR_REG(name) \ (offsetof(struct kvm_riscv_csr, name) / sizeof(unsigned long)) +/* F extension registers are mapped as type4 */ +#define KVM_REG_RISCV_FP_F (0x04 << KVM_REG_RISCV_TYPE_SHIFT) +#define KVM_REG_RISCV_FP_F_REG(name) \ + (offsetof(struct __riscv_f_ext_state, name) / sizeof(u32)) + +/* D extension registers are mapped as type 5 */ +#define KVM_REG_RISCV_FP_D (0x05 << KVM_REG_RISCV_TYPE_SHIFT) +#define KVM_REG_RISCV_FP_D_REG(name) \ + (offsetof(struct __riscv_d_ext_state, name) / sizeof(u64)) + #endif #endif /* __LINUX_KVM_RISCV_H */ diff --git a/arch/riscv/kvm/vcpu.c b/arch/riscv/kvm/vcpu.c index 67f9dd66f2db..8f2b058a4714 100644 --- a/arch/riscv/kvm/vcpu.c +++ b/arch/riscv/kvm/vcpu.c @@ -431,6 +431,98 @@ static int kvm_riscv_vcpu_set_reg_csr(struct kvm_vcpu *vcpu, return 0; } +static int kvm_riscv_vcpu_get_reg_fp(struct kvm_vcpu *vcpu, + const struct kvm_one_reg *reg, + unsigned long rtype) +{ + struct kvm_cpu_context *cntx = &vcpu->arch.guest_context; + unsigned long isa = vcpu->arch.isa; + unsigned long __user *uaddr = + (unsigned long __user *)(unsigned long)reg->addr; + unsigned long reg_num = reg->id & ~(KVM_REG_ARCH_MASK | + KVM_REG_SIZE_MASK | + rtype); + void *reg_val; + + if ((rtype == KVM_REG_RISCV_FP_F) && + riscv_isa_extension_available(&isa, f)) { + if (KVM_REG_SIZE(reg->id) != sizeof(u32)) + return -EINVAL; + if (reg_num == KVM_REG_RISCV_FP_F_REG(fcsr)) + reg_val = &cntx->fp.f.fcsr; + else if ((KVM_REG_RISCV_FP_F_REG(f[0]) <= reg_num) && + reg_num <= KVM_REG_RISCV_FP_F_REG(f[31])) + reg_val = &cntx->fp.f.f[reg_num]; + else + return -EINVAL; + } else if ((rtype == KVM_REG_RISCV_FP_D) && + riscv_isa_extension_available(&isa, d)) { + if (reg_num == KVM_REG_RISCV_FP_D_REG(fcsr)) { + if (KVM_REG_SIZE(reg->id) != sizeof(u32)) + return -EINVAL; + reg_val = &cntx->fp.d.fcsr; + } else if ((KVM_REG_RISCV_FP_D_REG(f[0]) <= reg_num) && + reg_num <= KVM_REG_RISCV_FP_D_REG(f[31])) { + if (KVM_REG_SIZE(reg->id) != sizeof(u64)) + return -EINVAL; + reg_val = &cntx->fp.d.f[reg_num]; + } else + return -EINVAL; + } else + return -EINVAL; + + if (copy_to_user(uaddr, reg_val, KVM_REG_SIZE(reg->id))) + return -EFAULT; + + return 0; +} + +static int kvm_riscv_vcpu_set_reg_fp(struct kvm_vcpu *vcpu, + const struct kvm_one_reg *reg, + unsigned long rtype) +{ + struct kvm_cpu_context *cntx = &vcpu->arch.guest_context; + unsigned long isa = vcpu->arch.isa; + unsigned long __user *uaddr = + (unsigned long __user *)(unsigned long)reg->addr; + unsigned long reg_num = reg->id & ~(KVM_REG_ARCH_MASK | + KVM_REG_SIZE_MASK | + rtype); + void *reg_val; + + if ((rtype == KVM_REG_RISCV_FP_F) && + riscv_isa_extension_available(&isa, f)) { + if (KVM_REG_SIZE(reg->id) != sizeof(u32)) + return -EINVAL; + if (reg_num == KVM_REG_RISCV_FP_F_REG(fcsr)) + reg_val = &cntx->fp.f.fcsr; + else if ((KVM_REG_RISCV_FP_F_REG(f[0]) <= reg_num) && + reg_num <= KVM_REG_RISCV_FP_F_REG(f[31])) + reg_val = &cntx->fp.f.f[reg_num]; + else + return -EINVAL; + } else if ((rtype == KVM_REG_RISCV_FP_D) && + riscv_isa_extension_available(&isa, d)) { + if (reg_num == KVM_REG_RISCV_FP_D_REG(fcsr)) { + if (KVM_REG_SIZE(reg->id) != sizeof(u32)) + return -EINVAL; + reg_val = &cntx->fp.d.fcsr; + } else if ((KVM_REG_RISCV_FP_D_REG(f[0]) <= reg_num) && + reg_num <= KVM_REG_RISCV_FP_D_REG(f[31])) { + if (KVM_REG_SIZE(reg->id) != sizeof(u64)) + return -EINVAL; + reg_val = &cntx->fp.d.f[reg_num]; + } else + return -EINVAL; + } else + return -EINVAL; + + if (copy_from_user(reg_val, uaddr, KVM_REG_SIZE(reg->id))) + return -EFAULT; + + return 0; +} + static int kvm_riscv_vcpu_set_reg(struct kvm_vcpu *vcpu, const struct kvm_one_reg *reg) { @@ -440,6 +532,12 @@ static int kvm_riscv_vcpu_set_reg(struct kvm_vcpu *vcpu, return kvm_riscv_vcpu_set_reg_core(vcpu, reg); else if ((reg->id & KVM_REG_RISCV_TYPE_MASK) == KVM_REG_RISCV_CSR) return kvm_riscv_vcpu_set_reg_csr(vcpu, reg); + else if ((reg->id & KVM_REG_RISCV_TYPE_MASK) == KVM_REG_RISCV_FP_F) + return kvm_riscv_vcpu_set_reg_fp(vcpu, reg, + KVM_REG_RISCV_FP_F); + else if ((reg->id & KVM_REG_RISCV_TYPE_MASK) == KVM_REG_RISCV_FP_D) + return kvm_riscv_vcpu_set_reg_fp(vcpu, reg, + KVM_REG_RISCV_FP_D); return -EINVAL; } @@ -453,6 +551,12 @@ static int kvm_riscv_vcpu_get_reg(struct kvm_vcpu *vcpu, return kvm_riscv_vcpu_get_reg_core(vcpu, reg); else if ((reg->id & KVM_REG_RISCV_TYPE_MASK) == KVM_REG_RISCV_CSR) return kvm_riscv_vcpu_get_reg_csr(vcpu, reg); + else if ((reg->id & KVM_REG_RISCV_TYPE_MASK) == KVM_REG_RISCV_FP_F) + return kvm_riscv_vcpu_get_reg_fp(vcpu, reg, + KVM_REG_RISCV_FP_F); + else if ((reg->id & KVM_REG_RISCV_TYPE_MASK) == KVM_REG_RISCV_FP_D) + return kvm_riscv_vcpu_get_reg_fp(vcpu, reg, + KVM_REG_RISCV_FP_D); return -EINVAL; } From patchwork Thu Oct 3 05:08:29 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Anup Patel X-Patchwork-Id: 11172149 Return-Path: Received: from mail.kernel.org (pdx-korg-mail-1.web.codeaurora.org [172.30.200.123]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id A686317EE for ; Thu, 3 Oct 2019 05:08:45 +0000 (UTC) Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id 817A421D81 for ; Thu, 3 Oct 2019 05:08:45 +0000 (UTC) Authentication-Results: mail.kernel.org; dkim=pass (2048-bit key) header.d=lists.infradead.org header.i=@lists.infradead.org header.b="gAqHQIuC"; dkim=fail reason="signature verification failed" (2048-bit key) header.d=wdc.com header.i=@wdc.com header.b="YsE3X/GR"; dkim=fail reason="signature verification failed" (1024-bit key) header.d=sharedspace.onmicrosoft.com header.i=@sharedspace.onmicrosoft.com header.b="HXD6XL1a" DMARC-Filter: OpenDMARC Filter v1.3.2 mail.kernel.org 817A421D81 Authentication-Results: mail.kernel.org; dmarc=fail (p=none dis=none) header.from=wdc.com Authentication-Results: mail.kernel.org; spf=none smtp.mailfrom=linux-riscv-bounces+patchwork-linux-riscv=patchwork.kernel.org@lists.infradead.org DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=bombadil.20170209; h=Sender: Content-Transfer-Encoding:Content-Type:Cc:List-Subscribe:List-Help:List-Post: List-Archive:List-Unsubscribe:List-Id:MIME-Version:In-Reply-To:References: Message-ID:Date:Subject:To:From:Reply-To:Content-ID:Content-Description: Resent-Date:Resent-From:Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID: List-Owner; bh=9QB6EYfyeAKi5IROFd6EvG0IOrRTcGERVac61GIBKLQ=; b=gAqHQIuCAjTjOM Sxv3e7mpoeBZ3do4UUW9nYUS2KIWNhOEKEAFPhLZi+dK2nLglYqC51sxHUK13FUdDSCckc40TucM9 5AhNq3xvRJbRtqdUHFcecHGW+qpAzSKPqHeetYbbhktrjZ8iCK3neY1yFPz3rK34TSqYLBcfUsn6F 409I6EceJq2EwYoq0j6MUXwgE6JRXCXX4O/ST+XS8LEUqsLnRGbXOagTgVc7W5cJdx0UAYdO9rM/h TzQoLG65LFJXIrEEU+ZQA020G8bF34Uowp1jYB6xvgGqF6dZiuKw/SlqxMwbaemEYqGcnqj8nN2fA YYv+d4XP3KXEGOwK9ypA==; Received: from localhost ([127.0.0.1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.92.2 #3 (Red Hat Linux)) id 1iFtLv-0004YM-Ad; Thu, 03 Oct 2019 05:08:35 +0000 Received: from esa4.hgst.iphmx.com ([216.71.154.42]) by bombadil.infradead.org with esmtps (Exim 4.92.2 #3 (Red Hat Linux)) id 1iFtLr-0004Wk-S8 for linux-riscv@lists.infradead.org; Thu, 03 Oct 2019 05:08:33 +0000 DKIM-Signature: v=1; a=rsa-sha256; c=simple/simple; d=wdc.com; i=@wdc.com; q=dns/txt; s=dkim.wdc.com; t=1570079311; x=1601615311; h=from:to:cc:subject:date:message-id:references: in-reply-to:content-transfer-encoding:mime-version; bh=chyHVHdLNxHU0jjESCfhKItyhD0599h36b9f1bjABYI=; b=YsE3X/GR0NWT1heABtWrMbAohgZE2+aYCPUf/bws+iyJf4OY54xAjD1u A4Qxn5AMhLFX4c1DtfcpGj26cfRXNUpAwyN31MF07XfZF2N2jsEJaKN7k UnFE6no+xSgCAGRhKtoKy1I4yluju1pQSlzIa4wY94969jhuvl3/YPCzp SMY0w+Fp1zx7yNLqPmXJzc9UidoOqsA8tisWii+AP27dRb/wMredF3cEe wckxesQRvexpwtJcOOhCnXiaX7YxOQdpHiD6zpvgtu8MvnCUDEagzVinF xFccZ6iEKoUwS8shNoVZuhCOHFKtd4tdawUH78rdXdYrh29G49yxJcRoR w==; IronPort-SDR: 9Cd5rdxt8Vix2firFmz0kHz3vCnPDZDX2UUgRCMRYoaPfJx14paDAaYXtH/PNLxeno6cwxGAXM hiLn1kaYkZ7O5Ve8sLIGPyEIqvk8u66sh3Nsoyko7SFFUIzyue6LdY9GGqGIbpqM9Iq4A0IPOU 1vm2hia0wLEKjlErjzak/U0WeMndBLYptilS4lUmHM9aP8rVjMUhG+f367otbh0H3kV4Nhmsl4 BAVIRrSS+4QDb1y8TCoZQ28WbmuSS7C1Vq4bz181cGBwEQNhgdsMbF7hB0cMxFIyfrTlySH9K9 eOM= X-IronPort-AV: E=Sophos;i="5.67,251,1566835200"; d="scan'208";a="119691066" Received: from mail-bl2nam02lp2059.outbound.protection.outlook.com (HELO NAM02-BL2-obe.outbound.protection.outlook.com) ([104.47.38.59]) by ob1.hgst.iphmx.com with ESMTP; 03 Oct 2019 13:08:30 +0800 ARC-Seal: i=1; a=rsa-sha256; s=arcselector9901; d=microsoft.com; cv=none; b=bPN/53jzTkLMAZZ4B9oG/P/tBAafarNUuUH901Zsp4zoOk98lQ9U48gWnAf7sFqR09Y7rttzi9/LbDjeNx2IdsoZBa//qfmz+T+DNZPvo5oNMOVv0Zws+5A8x9cGXJZULpBu1jTK3GimGHPluwmF6fFzRKY8BX4F33p9DSLZTH+h5//J2+VftsZaSoOzu5ZGMXVnHk2Lg6/AQtl9lmzWqlCi2iipFhJopGr6DbJgPYU8T9TI7PmiaC9S/6/m8o72yZQ8DE5QjEerL+Rnl6TL6GYkYYS7oW3wXOEDn3jgIDCtY2NF+2zHn5qMhJIhmNHs9GDhYoMEFT0nyTDse5lRRA== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=microsoft.com; s=arcselector9901; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-SenderADCheck; bh=eApuqBdCdV8lBrrYRfY6ko039/9vakJe9V5+6COdNxM=; b=QeQTt4CzLKHheiufPqIguDgcPFISAC5HW/c/ad0Ep6uWcvEzMdItadCj2rJHM2L0CJ8CZeT9rDMDDI5pijRoTqxz2odnge6DBB62dieMH8yXuyKDUWQZwtvBjqeVHDI1vEU+bYCVHgFRXMvUcrp2KL91xCPwrC/j0J9FYT6anQZphM0siRZInFv38B43Eg0mh/AR8WkH+X4UbW3jgxxiwHmSYqTXtaUwBk3zA06IdERx/QSAhBa++kkPaSOkPxHS17r2J9WgzZyM7FWdqZWHKv999M+bm+J6+WEIslCvm/jlo/juZPwuxxAuNHe7UXMrZYvs9ZMF/7ACjqLFN7znlg== ARC-Authentication-Results: i=1; mx.microsoft.com 1; spf=pass smtp.mailfrom=wdc.com; dmarc=pass action=none header.from=wdc.com; dkim=pass header.d=wdc.com; arc=none DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=sharedspace.onmicrosoft.com; s=selector2-sharedspace-onmicrosoft-com; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-SenderADCheck; bh=eApuqBdCdV8lBrrYRfY6ko039/9vakJe9V5+6COdNxM=; b=HXD6XL1aHRYXNiy+6rexQMwGB3KbMIUU2lidkfMvUh1k697jqs2sHZLIoex1Qw1uefbsoa0xWKmotLrAVTbHLhXS7PlpRCy6iOd6SkFtntF2MZElRFSAsMNkjhZsC+6TWBYgnhpDnZsPcTjP38NAM2uvkuVh+xHts/6w+6sG58s= Received: from MN2PR04MB6061.namprd04.prod.outlook.com (20.178.246.15) by MN2PR04MB5568.namprd04.prod.outlook.com (20.178.249.85) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.2305.17; Thu, 3 Oct 2019 05:08:29 +0000 Received: from MN2PR04MB6061.namprd04.prod.outlook.com ([fe80::1454:87a:13b0:d3a]) by MN2PR04MB6061.namprd04.prod.outlook.com ([fe80::1454:87a:13b0:d3a%7]) with mapi id 15.20.2305.023; Thu, 3 Oct 2019 05:08:29 +0000 From: Anup Patel To: Palmer Dabbelt , Paul Walmsley , Paolo Bonzini , Radim K Subject: [PATCH v8 16/19] RISC-V: KVM: Add SBI v0.1 support Thread-Topic: [PATCH v8 16/19] RISC-V: KVM: Add SBI v0.1 support Thread-Index: AQHVeaiYYctt3VF8ZkWdNhItg8ZmYQ== Date: Thu, 3 Oct 2019 05:08:29 +0000 Message-ID: <20191003050558.9031-17-anup.patel@wdc.com> References: <20191003050558.9031-1-anup.patel@wdc.com> In-Reply-To: <20191003050558.9031-1-anup.patel@wdc.com> Accept-Language: en-US Content-Language: en-US X-MS-Has-Attach: X-MS-TNEF-Correlator: x-clientproxiedby: BMXPR01CA0030.INDPRD01.PROD.OUTLOOK.COM (2603:1096:b00:c::16) To MN2PR04MB6061.namprd04.prod.outlook.com (2603:10b6:208:d8::15) authentication-results: spf=none (sender IP is ) smtp.mailfrom=Anup.Patel@wdc.com; x-ms-exchange-messagesentrepresentingtype: 1 x-mailer: git-send-email 2.17.1 x-originating-ip: [111.235.74.37] x-ms-publictraffictype: Email x-ms-office365-filtering-correlation-id: 6b4f7ecb-de24-4ee5-47b7-08d747bfba56 x-ms-office365-filtering-ht: Tenant x-ms-traffictypediagnostic: MN2PR04MB5568: x-ms-exchange-transport-forked: True x-microsoft-antispam-prvs: wdcipoutbound: EOP-TRUE x-ms-oob-tlc-oobclassifiers: OLM:6108; x-forefront-prvs: 01792087B6 x-forefront-antispam-report: SFV:NSPM; SFS:(10019020)(4636009)(396003)(346002)(376002)(39850400004)(136003)(366004)(199004)(189003)(71200400001)(6436002)(316002)(2616005)(6486002)(71190400001)(6512007)(110136005)(14444005)(86362001)(36756003)(54906003)(256004)(6506007)(386003)(6116002)(1076003)(5660300002)(7416002)(2906002)(81166006)(81156014)(25786009)(476003)(3846002)(478600001)(7736002)(446003)(11346002)(8676002)(186003)(66476007)(64756008)(66556008)(99286004)(305945005)(66446008)(50226002)(26005)(14454004)(66066001)(8936002)(102836004)(44832011)(76176011)(52116002)(4326008)(66946007)(486006); DIR:OUT; SFP:1102; SCL:1; SRVR:MN2PR04MB5568; H:MN2PR04MB6061.namprd04.prod.outlook.com; FPR:; SPF:None; LANG:en; PTR:InfoNoRecords; A:1; MX:1; x-ms-exchange-senderadcheck: 1 x-microsoft-antispam: BCL:0; x-microsoft-antispam-message-info: H7ZeQkC3NyvGFN9iGeGTXC1hc7ceB7yhNKxwO77/kQS3kTDLJx+QAAayXBuJYgZg8G13Nqk+/YFcMwtrgR1oisYe1l8T9McoNq5vWDoCNrhrS0t7eoXg/YWQIQCS17qpkt7VQX+Np7HCEHmEw4DSK4zevDdahRLdiq0ll+wRm9NERCc5qAuG1qLUvC3WDK24kdvfnvLdW9yzXN07ogx3JY0q7gjXrE1bkyp9wlH6TSE7yX4ARoav97RH/bu9K8kp6FltGox3+8+9Dmbxp6xG2Z3CeCCnWZPIjF/+6ankRW0je8iuU86YsV0Yq9LD4AZ9zlxsBFIw0RS2/0pBsZIpfo5vxb+EazC3t011M9k5x89JOZLi6E2iy3Zc6ft8vibzfbK6AHtdEXdZVjclh15PYmUNdOT97Dw3J11NwIDZBj4= MIME-Version: 1.0 X-OriginatorOrg: wdc.com X-MS-Exchange-CrossTenant-Network-Message-Id: 6b4f7ecb-de24-4ee5-47b7-08d747bfba56 X-MS-Exchange-CrossTenant-originalarrivaltime: 03 Oct 2019 05:08:29.0464 (UTC) X-MS-Exchange-CrossTenant-fromentityheader: Hosted X-MS-Exchange-CrossTenant-id: b61c8803-16f3-4c35-9b17-6f65f441df86 X-MS-Exchange-CrossTenant-mailboxtype: HOSTED X-MS-Exchange-CrossTenant-userprincipalname: T1lKL7c734Q/Ib4UjQeN+wCvq3F+aVhEI3TGM9ibjIXrRCtjIuiWgSDRPl8hChI0R9IVP89/KD04O571xNsnfg== X-MS-Exchange-Transport-CrossTenantHeadersStamped: MN2PR04MB5568 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20191002_220831_965536_61D097F1 X-CRM114-Status: GOOD ( 19.26 ) X-Spam-Score: -2.5 (--) X-Spam-Report: SpamAssassin version 3.4.2 on bombadil.infradead.org summary: Content analysis details: (-2.5 points) pts rule name description ---- ---------------------- -------------------------------------------------- -2.3 RCVD_IN_DNSWL_MED RBL: Sender listed at https://www.dnswl.org/, medium trust [216.71.154.42 listed in list.dnswl.org] -0.0 SPF_PASS SPF: sender matches SPF record 0.0 SPF_HELO_NONE SPF: HELO does not publish an SPF Record -0.1 DKIM_VALID_EF Message has a valid DKIM or DK signature from envelope-from domain 0.1 DKIM_SIGNED Message has a DKIM or DK signature, not necessarily valid -0.1 DKIM_VALID_AU Message has a valid DKIM or DK signature from author's domain -0.1 DKIM_VALID Message has at least one valid DKIM or DK signature X-BeenThere: linux-riscv@lists.infradead.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Damien Le Moal , Anup Patel , "kvm@vger.kernel.org" , Anup Patel , Daniel Lezcano , "linux-kernel@vger.kernel.org" , Christoph Hellwig , Atish Patra , Alexander Graf , Alistair Francis , Thomas Gleixner , "linux-riscv@lists.infradead.org" Sender: "linux-riscv" Errors-To: linux-riscv-bounces+patchwork-linux-riscv=patchwork.kernel.org@lists.infradead.org From: Atish Patra The KVM host kernel running in HS-mode needs to handle SBI calls coming from guest kernel running in VS-mode. This patch adds SBI v0.1 support in KVM RISC-V. All the SBI calls are implemented correctly except remote tlb flushes. For remote TLB flushes, we are doing full TLB flush and this will be optimized in future. Signed-off-by: Atish Patra Signed-off-by: Anup Patel Acked-by: Paolo Bonzini Reviewed-by: Paolo Bonzini --- arch/riscv/include/asm/kvm_host.h | 2 + arch/riscv/kvm/Makefile | 2 +- arch/riscv/kvm/vcpu_exit.c | 4 ++ arch/riscv/kvm/vcpu_sbi.c | 106 ++++++++++++++++++++++++++++++ 4 files changed, 113 insertions(+), 1 deletion(-) create mode 100644 arch/riscv/kvm/vcpu_sbi.c diff --git a/arch/riscv/include/asm/kvm_host.h b/arch/riscv/include/asm/kvm_host.h index 928c67828b1b..74ccd8d00ec5 100644 --- a/arch/riscv/include/asm/kvm_host.h +++ b/arch/riscv/include/asm/kvm_host.h @@ -250,4 +250,6 @@ bool kvm_riscv_vcpu_has_interrupt(struct kvm_vcpu *vcpu); void kvm_riscv_vcpu_power_off(struct kvm_vcpu *vcpu); void kvm_riscv_vcpu_power_on(struct kvm_vcpu *vcpu); +int kvm_riscv_vcpu_sbi_ecall(struct kvm_vcpu *vcpu, struct kvm_run *run); + #endif /* __RISCV_KVM_HOST_H__ */ diff --git a/arch/riscv/kvm/Makefile b/arch/riscv/kvm/Makefile index 3e0c7558320d..b56dc1650d2c 100644 --- a/arch/riscv/kvm/Makefile +++ b/arch/riscv/kvm/Makefile @@ -9,6 +9,6 @@ ccflags-y := -Ivirt/kvm -Iarch/riscv/kvm kvm-objs := $(common-objs-y) kvm-objs += main.o vm.o vmid.o tlb.o mmu.o -kvm-objs += vcpu.o vcpu_exit.o vcpu_switch.o vcpu_timer.o +kvm-objs += vcpu.o vcpu_exit.o vcpu_switch.o vcpu_timer.o vcpu_sbi.o obj-$(CONFIG_KVM) += kvm.o diff --git a/arch/riscv/kvm/vcpu_exit.c b/arch/riscv/kvm/vcpu_exit.c index 7507b859246b..0e9b0ffa169d 100644 --- a/arch/riscv/kvm/vcpu_exit.c +++ b/arch/riscv/kvm/vcpu_exit.c @@ -587,6 +587,10 @@ int kvm_riscv_vcpu_exit(struct kvm_vcpu *vcpu, struct kvm_run *run, (vcpu->arch.guest_context.hstatus & HSTATUS_STL)) ret = stage2_page_fault(vcpu, run, scause, stval); break; + case EXC_SUPERVISOR_SYSCALL: + if (vcpu->arch.guest_context.hstatus & HSTATUS_SPV) + ret = kvm_riscv_vcpu_sbi_ecall(vcpu, run); + break; default: break; }; diff --git a/arch/riscv/kvm/vcpu_sbi.c b/arch/riscv/kvm/vcpu_sbi.c new file mode 100644 index 000000000000..88fa0faa3545 --- /dev/null +++ b/arch/riscv/kvm/vcpu_sbi.c @@ -0,0 +1,106 @@ +// SPDX-License-Identifier: GPL-2.0 +/** + * Copyright (c) 2019 Western Digital Corporation or its affiliates. + * + * Authors: + * Atish Patra + */ + +#include +#include +#include +#include +#include +#include + +#define SBI_VERSION_MAJOR 0 +#define SBI_VERSION_MINOR 1 + +static void kvm_sbi_system_shutdown(struct kvm_vcpu *vcpu, + struct kvm_run *run, u32 type) +{ + int i; + struct kvm_vcpu *tmp; + + kvm_for_each_vcpu(i, tmp, vcpu->kvm) + tmp->arch.power_off = true; + kvm_make_all_cpus_request(vcpu->kvm, KVM_REQ_SLEEP); + + memset(&run->system_event, 0, sizeof(run->system_event)); + run->system_event.type = type; + run->exit_reason = KVM_EXIT_SYSTEM_EVENT; +} + +int kvm_riscv_vcpu_sbi_ecall(struct kvm_vcpu *vcpu, struct kvm_run *run) +{ + int i, ret = 1; + u64 next_cycle; + struct kvm_vcpu *rvcpu; + bool next_sepc = true; + ulong hmask, ut_scause = 0; + struct kvm_cpu_context *cp = &vcpu->arch.guest_context; + + if (!cp) + return -EINVAL; + + switch (cp->a7) { + case SBI_SET_TIMER: +#if __riscv_xlen == 32 + next_cycle = ((u64)cp->a1 << 32) | (u64)cp->a0; +#else + next_cycle = (u64)cp->a0; +#endif + kvm_riscv_vcpu_timer_next_event(vcpu, next_cycle); + break; + case SBI_CLEAR_IPI: + kvm_riscv_vcpu_unset_interrupt(vcpu, IRQ_S_SOFT); + break; + case SBI_SEND_IPI: + hmask = kvm_riscv_vcpu_unpriv_read(vcpu, false, cp->a0, + &ut_scause); + if (ut_scause) { + kvm_riscv_vcpu_trap_redirect(vcpu, ut_scause, + cp->a0); + next_sepc = false; + } else { + for_each_set_bit(i, &hmask, BITS_PER_LONG) { + rvcpu = kvm_get_vcpu_by_id(vcpu->kvm, i); + kvm_riscv_vcpu_set_interrupt(rvcpu, IRQ_S_SOFT); + } + } + break; + case SBI_SHUTDOWN: + kvm_sbi_system_shutdown(vcpu, run, KVM_SYSTEM_EVENT_SHUTDOWN); + ret = 0; + break; + case SBI_REMOTE_FENCE_I: + sbi_remote_fence_i(NULL); + break; + /* + * TODO: There should be a way to call remote hfence.bvma. + * Preferred method is now a SBI call. Until then, just flush + * all tlbs. + */ + case SBI_REMOTE_SFENCE_VMA: + /* TODO: Parse vma range. */ + sbi_remote_sfence_vma(NULL, 0, 0); + break; + case SBI_REMOTE_SFENCE_VMA_ASID: + /* TODO: Parse vma range for given ASID */ + sbi_remote_sfence_vma(NULL, 0, 0); + break; + default: + /* + * For now, just return error to Guest. + * TODO: In-future, we will route unsupported SBI calls + * to user-space. + */ + cp->a0 = -ENOTSUPP; + break; + }; + + if (ret > 0) + cp->sepc += 4; + + return ret; +} From patchwork Thu Oct 3 05:08:35 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Anup Patel X-Patchwork-Id: 11172153 Return-Path: Received: from mail.kernel.org (pdx-korg-mail-1.web.codeaurora.org [172.30.200.123]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id 9AFA814DB for ; Thu, 3 Oct 2019 05:08:54 +0000 (UTC) Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id 75FDA21D81 for ; Thu, 3 Oct 2019 05:08:54 +0000 (UTC) Authentication-Results: mail.kernel.org; dkim=pass (2048-bit key) header.d=lists.infradead.org header.i=@lists.infradead.org header.b="YuetjjN7"; dkim=fail reason="signature verification failed" (2048-bit key) header.d=wdc.com header.i=@wdc.com header.b="EmKl4N8B"; dkim=fail reason="signature verification failed" (1024-bit key) header.d=sharedspace.onmicrosoft.com header.i=@sharedspace.onmicrosoft.com header.b="znTjhndw" DMARC-Filter: OpenDMARC Filter v1.3.2 mail.kernel.org 75FDA21D81 Authentication-Results: mail.kernel.org; dmarc=fail (p=none dis=none) header.from=wdc.com Authentication-Results: mail.kernel.org; spf=none smtp.mailfrom=linux-riscv-bounces+patchwork-linux-riscv=patchwork.kernel.org@lists.infradead.org DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=bombadil.20170209; h=Sender: Content-Transfer-Encoding:Content-Type:Cc:List-Subscribe:List-Help:List-Post: List-Archive:List-Unsubscribe:List-Id:MIME-Version:In-Reply-To:References: Message-ID:Date:Subject:To:From:Reply-To:Content-ID:Content-Description: Resent-Date:Resent-From:Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID: List-Owner; bh=jm3rSKugVWDTS/GLRN8cOC1GWfs9ybCDWQKXGDmGgvs=; b=YuetjjN7p2uN3n 1MfNioipyfJ6t+p9YiPK1LEmzwxlsXPwRUk3q7dkKKkOBddTS40s872W9b0Qo4uCNwPPbUvdRg02R 2g3uWuVNiGNdBW7rklF+YJ0MznmvUX4AQak1+PVt6YLJ4m37ET/KoXc9Fr/vTEz9v0tDpLHASyDzc Xsgx0BJXwrGSyEO1L0CGRWAqkR7ZwLvWwxEhrV4QbSX1evF6SY4mi40ro9SszQPpIEmHGTIXaTnvm X/IABM5qwJWJCkH82IMt8ESS5IFVB348N15+Zdrpqkck6wlzR9A60u7umfkg+NgC9fmjSq2k7BF8J DMOK8jmVsZOv7Fzln/mw==; Received: from localhost ([127.0.0.1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.92.2 #3 (Red Hat Linux)) id 1iFtM1-0004cy-Fe; Thu, 03 Oct 2019 05:08:41 +0000 Received: from esa2.hgst.iphmx.com ([68.232.143.124]) by bombadil.infradead.org with esmtps (Exim 4.92.2 #3 (Red Hat Linux)) id 1iFtLy-0004c2-HM for linux-riscv@lists.infradead.org; Thu, 03 Oct 2019 05:08:40 +0000 DKIM-Signature: v=1; a=rsa-sha256; c=simple/simple; d=wdc.com; i=@wdc.com; q=dns/txt; s=dkim.wdc.com; t=1570079325; x=1601615325; h=from:to:cc:subject:date:message-id:references: in-reply-to:content-transfer-encoding:mime-version; bh=ESFHtviBea+JR+gBup4Tgcx2jwQAoeXMFh5jibdHh6Q=; b=EmKl4N8BQCUOeqPnDlzWl3LhLifq4yvz1ZJOTs1FlD5LN8M5nbcjlpUR VmGUW5fPronwnU7lNXFPycL/kGTpPET5beqp/2qWaz5K4WbNg+XbC37i8 RfuHx//+Rk/1yEFH0JrQgPD49S9mte3hbXgR/yy4/aM0XM0v0BDAnf8zG ZREQAeLngAWdJg5TkMBferz9DiHi05JDXMlgDdivrnmTm3QofbG4BaxHK URwi3dWR/Hyqc4CVwqK1eKaDIVokutFVmrC/S1KO45NQ9PwcOtuVMLpnu o+96F6GI/gfbdntD/ogMF7hfwg7MkPKqyJYl1+lWRvUnW9eOSmzYSlxHA g==; IronPort-SDR: hoJAlWN+pPo5uM1NzZgWV++uVVU1NZb2FiaYwX/S0D3aRxZba2eZ9OBIMt8DtvKu3keF/7lUie grRGBWw5JV1YTp1WOL099jLCjYWxU6ss3unuxBupEOFFi5Bm9y1QtoPTHFaPdDqkOfAupzekqb +vxYkJR4GnTpeTnHHbnHusZodofSONMgopdEV//eIvztvqDBEHQjpRcDJzGMJC5ioTozXnxnN2 kLvZntpHu9E6ONMX3tTEjdk43iRSPFz0PrZUIg+E/VTC3cSm8C/Rx0KTJKrMuSZymKqCb1AVia 4aE= X-IronPort-AV: E=Sophos;i="5.67,251,1566835200"; d="scan'208";a="220620950" Received: from mail-co1nam05lp2051.outbound.protection.outlook.com (HELO NAM05-CO1-obe.outbound.protection.outlook.com) ([104.47.48.51]) by ob1.hgst.iphmx.com with ESMTP; 03 Oct 2019 13:08:42 +0800 ARC-Seal: i=1; a=rsa-sha256; s=arcselector9901; d=microsoft.com; cv=none; b=O3UjjqBaJvcWwOzl8B7Y4O/ZtynApCmASyDc6F7JYEs1maVXpPNLT790nPCjf9ntMtGVAJGK+Qhmv63mK3VpoZr8AABT9QjcXNP99YBjIObIlYPvIPE1MgrMqnoWtyDTJ5/n6Vo3H55Ys/NPEIa4wbuJtoYWl9bU4/yENClNMBt7i/8ZEdV60iEV2HrVdFQi+UI1vC2KD4njsT15bnAljXZ9ied92ozvbrq0QR8RmXj2mUiHOVppV6kXz4YJ5uQZF0WTOkWUD0NOoWus8vKWCP8dVE8rj/FZDD5+9RVTcQjTFmk/sG2ftwB9dSECBAx0J40d2t44fKq6UfMT3x0yaw== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=microsoft.com; s=arcselector9901; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-SenderADCheck; bh=FpSpk2hHGYy+s9hLvF22G4ZffHrpeex2nXK6niW88ok=; b=nYZE2HslKfueoedg23WLztHOmbiPvb7OGAx7MHw9vzJTee4ZkqBWJyYoU3wj4hLWrPRXXUeZHiVeKumD5FXKZb5Tx47NwWpNvPSuz0d+2pS++5WX934qUESnx9dueHrzQlJ+woAwDtlRSbIc2EcuQsGbY9x9AMEkmjRglfjRFPGG/t6yJMtuWE0veDsdoq6DA/TA8GMLY3Qcnu2DEQnc3DYy0k9X3vPr3EZ38xLjZY3U3ea5ZKcg9Hd/HsY67Y/s2xp7BTFkPJIb2c///pUHafXKHTmOdqNy7O+sVmLM1stUKSY1xaYUT1jo+61neGSHWH82KzWufIoSGBvuHr6EwQ== ARC-Authentication-Results: i=1; mx.microsoft.com 1; spf=pass smtp.mailfrom=wdc.com; dmarc=pass action=none header.from=wdc.com; dkim=pass header.d=wdc.com; arc=none DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=sharedspace.onmicrosoft.com; s=selector2-sharedspace-onmicrosoft-com; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-SenderADCheck; bh=FpSpk2hHGYy+s9hLvF22G4ZffHrpeex2nXK6niW88ok=; b=znTjhndw93gJDRjlBd9BFTYGJ6JgG2AwgP4XviaiNXLzjOlhDAFZdGnIt0TLnna+FNvbkKMiUpqT2BkcJP8L4qTQNT9KRFRmjCoe+0zhJ+rVBxLKCurJjI906Stl/K7V064sl+7jKWj2dcPfhqXV6ZmkCaOpfpQfZhuG4DjoIS8= Received: from MN2PR04MB6061.namprd04.prod.outlook.com (20.178.246.15) by MN2PR04MB6272.namprd04.prod.outlook.com (20.178.248.27) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.2305.17; Thu, 3 Oct 2019 05:08:35 +0000 Received: from MN2PR04MB6061.namprd04.prod.outlook.com ([fe80::1454:87a:13b0:d3a]) by MN2PR04MB6061.namprd04.prod.outlook.com ([fe80::1454:87a:13b0:d3a%7]) with mapi id 15.20.2305.023; Thu, 3 Oct 2019 05:08:35 +0000 From: Anup Patel To: Palmer Dabbelt , Paul Walmsley , Paolo Bonzini , Radim K Subject: [PATCH v8 17/19] RISC-V: KVM: Forward unhandled SBI calls to userspace Thread-Topic: [PATCH v8 17/19] RISC-V: KVM: Forward unhandled SBI calls to userspace Thread-Index: AQHVeaibrnyZ/lSFMUO2gp5hDHHZAw== Date: Thu, 3 Oct 2019 05:08:35 +0000 Message-ID: <20191003050558.9031-18-anup.patel@wdc.com> References: <20191003050558.9031-1-anup.patel@wdc.com> In-Reply-To: <20191003050558.9031-1-anup.patel@wdc.com> Accept-Language: en-US Content-Language: en-US X-MS-Has-Attach: X-MS-TNEF-Correlator: x-clientproxiedby: BMXPR01CA0030.INDPRD01.PROD.OUTLOOK.COM (2603:1096:b00:c::16) To MN2PR04MB6061.namprd04.prod.outlook.com (2603:10b6:208:d8::15) authentication-results: spf=none (sender IP is ) smtp.mailfrom=Anup.Patel@wdc.com; x-ms-exchange-messagesentrepresentingtype: 1 x-mailer: git-send-email 2.17.1 x-originating-ip: [111.235.74.37] x-ms-publictraffictype: Email x-ms-office365-filtering-correlation-id: fb090c41-6fec-4b4e-7bec-08d747bfbe3b x-ms-office365-filtering-ht: Tenant x-ms-traffictypediagnostic: MN2PR04MB6272: x-ms-exchange-transport-forked: True x-microsoft-antispam-prvs: wdcipoutbound: EOP-TRUE x-ms-oob-tlc-oobclassifiers: OLM:6790; x-forefront-prvs: 01792087B6 x-forefront-antispam-report: SFV:NSPM; SFS:(10019020)(4636009)(136003)(376002)(346002)(366004)(396003)(39860400002)(189003)(199004)(6512007)(6486002)(81166006)(81156014)(8936002)(6116002)(3846002)(8676002)(50226002)(2906002)(110136005)(66066001)(6436002)(316002)(66476007)(66556008)(7416002)(66446008)(36756003)(1076003)(5660300002)(54906003)(7736002)(305945005)(76176011)(25786009)(52116002)(256004)(14444005)(71190400001)(86362001)(99286004)(71200400001)(2616005)(446003)(14454004)(476003)(102836004)(186003)(26005)(11346002)(44832011)(6506007)(486006)(478600001)(4326008)(66946007)(386003)(64756008); DIR:OUT; SFP:1102; SCL:1; SRVR:MN2PR04MB6272; H:MN2PR04MB6061.namprd04.prod.outlook.com; FPR:; SPF:None; LANG:en; PTR:InfoNoRecords; MX:1; A:1; x-ms-exchange-senderadcheck: 1 x-microsoft-antispam: BCL:0; x-microsoft-antispam-message-info: QUnN037z1zdnbRbMAoTBMjyjkAKrKzXp5Mp/Akia71NO8wX2Ej71UkqNbtkbByCEukd1zczeUfTHJUqB6uK5yVNPYlOOdh4kVNHExhYTaE621XjMWpWeH7i4miU4sjjyMGSzU757mz+j/OzcO1G2+erbAya58cTsa8N4A2ozPw1go6TFoDXHHdYAH5ekGWkBky+lv8RgvHvFux7kxxa9oJBSPoxPoF7rZwz+lrU5eiv2sEnV2u3v9SabzvLHJ8RX2qV1wRD1lgw0+LrmxmHR4UrtrvN0pfjTh8R1tdJdkyjZz2apVYXz+ag0UPVFIKvfKLJ/DPyNNaEgIJrb68RP33zZYN7+KXVH/epw8t/ksY98bEakI03ig5qph9LKQ8M2dvI4UExySo5nP0LgZ8uj/jBLkdoIAFRhYcyVyDrbcL0= MIME-Version: 1.0 X-OriginatorOrg: wdc.com X-MS-Exchange-CrossTenant-Network-Message-Id: fb090c41-6fec-4b4e-7bec-08d747bfbe3b X-MS-Exchange-CrossTenant-originalarrivaltime: 03 Oct 2019 05:08:35.5847 (UTC) X-MS-Exchange-CrossTenant-fromentityheader: Hosted X-MS-Exchange-CrossTenant-id: b61c8803-16f3-4c35-9b17-6f65f441df86 X-MS-Exchange-CrossTenant-mailboxtype: HOSTED X-MS-Exchange-CrossTenant-userprincipalname: Who5KASXGs/UHa6SDj6drdHPcRLgszkzdWsk0Hk/jIdkL0UNF9fLkfiJGT6df6IbFf5WAb5ni4usb1zAofW/tA== X-MS-Exchange-Transport-CrossTenantHeadersStamped: MN2PR04MB6272 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20191002_220838_612847_392D9212 X-CRM114-Status: GOOD ( 19.81 ) X-Spam-Score: -2.5 (--) X-Spam-Report: SpamAssassin version 3.4.2 on bombadil.infradead.org summary: Content analysis details: (-2.5 points) pts rule name description ---- ---------------------- -------------------------------------------------- -2.3 RCVD_IN_DNSWL_MED RBL: Sender listed at https://www.dnswl.org/, medium trust [68.232.143.124 listed in list.dnswl.org] -0.0 SPF_PASS SPF: sender matches SPF record 0.0 SPF_HELO_NONE SPF: HELO does not publish an SPF Record -0.1 DKIM_VALID_EF Message has a valid DKIM or DK signature from envelope-from domain 0.1 DKIM_SIGNED Message has a DKIM or DK signature, not necessarily valid -0.1 DKIM_VALID_AU Message has a valid DKIM or DK signature from author's domain -0.1 DKIM_VALID Message has at least one valid DKIM or DK signature X-BeenThere: linux-riscv@lists.infradead.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Damien Le Moal , Anup Patel , "kvm@vger.kernel.org" , Anup Patel , Daniel Lezcano , "linux-kernel@vger.kernel.org" , Christoph Hellwig , Atish Patra , Alexander Graf , Alistair Francis , Thomas Gleixner , "linux-riscv@lists.infradead.org" Sender: "linux-riscv" Errors-To: linux-riscv-bounces+patchwork-linux-riscv=patchwork.kernel.org@lists.infradead.org Instead of returning error to Guest for unhandled SBI calls, we should forward such SBI calls to KVM user-space tool (QEMU/KVMTOOL). This way KVM userspace tool can do something about unhandled SBI calls: 1. Print unhandled SBI call details and kill the Guest 2. Emulate unhandled SBI call and resume the Guest To achieve this, we end-up having a RISC-V specific SBI exit reason and riscv_sbi member under "struct kvm_run". The riscv_sbi member of "struct kvm_run" added by this patch is compatible with both SBI v0.1 and SBI v0.2 specs. Currently, we implement SBI v0.1 for Guest where CONSOLE_GETCHAR and CONSOLE_PUTCHART SBI calls are unhandled in KVM RISC-V kernel module so we forward these calls to userspace. In future when we implement SBI v0.2 for Guest, we will forward SBI v0.2 experimental and vendor extension calls to userspace. Signed-off-by: Anup Patel --- arch/riscv/include/asm/kvm_host.h | 8 ++++ arch/riscv/kvm/vcpu.c | 9 ++++ arch/riscv/kvm/vcpu_sbi.c | 69 +++++++++++++++++++++++++------ include/uapi/linux/kvm.h | 8 ++++ 4 files changed, 81 insertions(+), 13 deletions(-) diff --git a/arch/riscv/include/asm/kvm_host.h b/arch/riscv/include/asm/kvm_host.h index 74ccd8d00ec5..6f44eefc1641 100644 --- a/arch/riscv/include/asm/kvm_host.h +++ b/arch/riscv/include/asm/kvm_host.h @@ -74,6 +74,10 @@ struct kvm_mmio_decode { int return_handled; }; +struct kvm_sbi_context { + int return_handled; +}; + #define KVM_MMU_PAGE_CACHE_NR_OBJS 32 struct kvm_mmu_page_cache { @@ -176,6 +180,9 @@ struct kvm_vcpu_arch { /* MMIO instruction details */ struct kvm_mmio_decode mmio_decode; + /* SBI context */ + struct kvm_sbi_context sbi_context; + /* Cache pages needed to program page tables with spinlock held */ struct kvm_mmu_page_cache mmu_page_cache; @@ -250,6 +257,7 @@ bool kvm_riscv_vcpu_has_interrupt(struct kvm_vcpu *vcpu); void kvm_riscv_vcpu_power_off(struct kvm_vcpu *vcpu); void kvm_riscv_vcpu_power_on(struct kvm_vcpu *vcpu); +int kvm_riscv_vcpu_sbi_return(struct kvm_vcpu *vcpu, struct kvm_run *run); int kvm_riscv_vcpu_sbi_ecall(struct kvm_vcpu *vcpu, struct kvm_run *run); #endif /* __RISCV_KVM_HOST_H__ */ diff --git a/arch/riscv/kvm/vcpu.c b/arch/riscv/kvm/vcpu.c index 8f2b058a4714..27174e2ec8a0 100644 --- a/arch/riscv/kvm/vcpu.c +++ b/arch/riscv/kvm/vcpu.c @@ -885,6 +885,15 @@ int kvm_arch_vcpu_ioctl_run(struct kvm_vcpu *vcpu, struct kvm_run *run) } } + /* Process SBI value returned from user-space */ + if (run->exit_reason == KVM_EXIT_RISCV_SBI) { + ret = kvm_riscv_vcpu_sbi_return(vcpu, vcpu->run); + if (ret) { + srcu_read_unlock(&vcpu->kvm->srcu, vcpu->arch.srcu_idx); + return ret; + } + } + if (run->immediate_exit) { srcu_read_unlock(&vcpu->kvm->srcu, vcpu->arch.srcu_idx); return -EINTR; diff --git a/arch/riscv/kvm/vcpu_sbi.c b/arch/riscv/kvm/vcpu_sbi.c index 88fa0faa3545..983ccaf2a54e 100644 --- a/arch/riscv/kvm/vcpu_sbi.c +++ b/arch/riscv/kvm/vcpu_sbi.c @@ -31,6 +31,44 @@ static void kvm_sbi_system_shutdown(struct kvm_vcpu *vcpu, run->exit_reason = KVM_EXIT_SYSTEM_EVENT; } +static void kvm_riscv_vcpu_sbi_forward(struct kvm_vcpu *vcpu, + struct kvm_run *run) +{ + struct kvm_cpu_context *cp = &vcpu->arch.guest_context; + + vcpu->arch.sbi_context.return_handled = 0; + run->exit_reason = KVM_EXIT_RISCV_SBI; + run->riscv_sbi.extension_id = cp->a7; + run->riscv_sbi.function_id = cp->a6; + run->riscv_sbi.args[0] = cp->a0; + run->riscv_sbi.args[1] = cp->a1; + run->riscv_sbi.args[2] = cp->a2; + run->riscv_sbi.args[3] = cp->a3; + run->riscv_sbi.args[4] = cp->a4; + run->riscv_sbi.args[5] = cp->a5; + run->riscv_sbi.ret[0] = cp->a0; + run->riscv_sbi.ret[1] = cp->a1; +} + +int kvm_riscv_vcpu_sbi_return(struct kvm_vcpu *vcpu, struct kvm_run *run) +{ + struct kvm_cpu_context *cp = &vcpu->arch.guest_context; + + /* Handle SBI return only once */ + if (vcpu->arch.sbi_context.return_handled) + return 0; + vcpu->arch.sbi_context.return_handled = 1; + + /* Update return values */ + cp->a0 = run->riscv_sbi.ret[0]; + cp->a1 = run->riscv_sbi.ret[1]; + + /* Move to next instruction */ + vcpu->arch.guest_context.sepc += 4; + + return 0; +} + int kvm_riscv_vcpu_sbi_ecall(struct kvm_vcpu *vcpu, struct kvm_run *run) { int i, ret = 1; @@ -44,7 +82,16 @@ int kvm_riscv_vcpu_sbi_ecall(struct kvm_vcpu *vcpu, struct kvm_run *run) return -EINVAL; switch (cp->a7) { - case SBI_SET_TIMER: + case SBI_EXT_0_1_CONSOLE_GETCHAR: + case SBI_EXT_0_1_CONSOLE_PUTCHAR: + /* + * The CONSOLE_GETCHAR/CONSOLE_PUTCHAR SBI calls cannot be + * handled in kernel so we forward these to user-space + */ + kvm_riscv_vcpu_sbi_forward(vcpu, run); + ret = 0; + break; + case SBI_EXT_0_1_SET_TIMER: #if __riscv_xlen == 32 next_cycle = ((u64)cp->a1 << 32) | (u64)cp->a0; #else @@ -52,10 +99,10 @@ int kvm_riscv_vcpu_sbi_ecall(struct kvm_vcpu *vcpu, struct kvm_run *run) #endif kvm_riscv_vcpu_timer_next_event(vcpu, next_cycle); break; - case SBI_CLEAR_IPI: + case SBI_EXT_0_1_CLEAR_IPI: kvm_riscv_vcpu_unset_interrupt(vcpu, IRQ_S_SOFT); break; - case SBI_SEND_IPI: + case SBI_EXT_0_1_SEND_IPI: hmask = kvm_riscv_vcpu_unpriv_read(vcpu, false, cp->a0, &ut_scause); if (ut_scause) { @@ -69,11 +116,11 @@ int kvm_riscv_vcpu_sbi_ecall(struct kvm_vcpu *vcpu, struct kvm_run *run) } } break; - case SBI_SHUTDOWN: + case SBI_EXT_0_1_SHUTDOWN: kvm_sbi_system_shutdown(vcpu, run, KVM_SYSTEM_EVENT_SHUTDOWN); ret = 0; break; - case SBI_REMOTE_FENCE_I: + case SBI_EXT_0_1_REMOTE_FENCE_I: sbi_remote_fence_i(NULL); break; /* @@ -81,21 +128,17 @@ int kvm_riscv_vcpu_sbi_ecall(struct kvm_vcpu *vcpu, struct kvm_run *run) * Preferred method is now a SBI call. Until then, just flush * all tlbs. */ - case SBI_REMOTE_SFENCE_VMA: + case SBI_EXT_0_1_REMOTE_SFENCE_VMA: /* TODO: Parse vma range. */ sbi_remote_sfence_vma(NULL, 0, 0); break; - case SBI_REMOTE_SFENCE_VMA_ASID: + case SBI_EXT_0_1_REMOTE_SFENCE_VMA_ASID: /* TODO: Parse vma range for given ASID */ sbi_remote_sfence_vma(NULL, 0, 0); break; default: - /* - * For now, just return error to Guest. - * TODO: In-future, we will route unsupported SBI calls - * to user-space. - */ - cp->a0 = -ENOTSUPP; + /* Return error for unsupported SBI calls */ + cp->a0 = SBI_ERR_NOT_SUPPORTED; break; }; diff --git a/include/uapi/linux/kvm.h b/include/uapi/linux/kvm.h index 52641d8ca9e8..441fd81312a4 100644 --- a/include/uapi/linux/kvm.h +++ b/include/uapi/linux/kvm.h @@ -235,6 +235,7 @@ struct kvm_hyperv_exit { #define KVM_EXIT_S390_STSI 25 #define KVM_EXIT_IOAPIC_EOI 26 #define KVM_EXIT_HYPERV 27 +#define KVM_EXIT_RISCV_SBI 28 /* For KVM_EXIT_INTERNAL_ERROR */ /* Emulate instruction failed. */ @@ -394,6 +395,13 @@ struct kvm_run { } eoi; /* KVM_EXIT_HYPERV */ struct kvm_hyperv_exit hyperv; + /* KVM_EXIT_RISCV_SBI */ + struct { + unsigned long extension_id; + unsigned long function_id; + unsigned long args[6]; + unsigned long ret[2]; + } riscv_sbi; /* Fix the size of the union. */ char padding[256]; }; From patchwork Thu Oct 3 05:08:42 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Anup Patel X-Patchwork-Id: 11172155 Return-Path: Received: from mail.kernel.org (pdx-korg-mail-1.web.codeaurora.org [172.30.200.123]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id 839101902 for ; Thu, 3 Oct 2019 05:08:59 +0000 (UTC) Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id 5E0D221D81 for ; Thu, 3 Oct 2019 05:08:59 +0000 (UTC) Authentication-Results: mail.kernel.org; dkim=pass (2048-bit key) header.d=lists.infradead.org header.i=@lists.infradead.org header.b="DRRGlFOA"; dkim=fail reason="signature verification failed" (2048-bit key) header.d=wdc.com header.i=@wdc.com header.b="bPTxVIUH"; dkim=fail reason="signature verification failed" (1024-bit key) header.d=sharedspace.onmicrosoft.com header.i=@sharedspace.onmicrosoft.com header.b="e6Xq4JsA" DMARC-Filter: OpenDMARC Filter v1.3.2 mail.kernel.org 5E0D221D81 Authentication-Results: mail.kernel.org; dmarc=fail (p=none dis=none) header.from=wdc.com Authentication-Results: mail.kernel.org; spf=none smtp.mailfrom=linux-riscv-bounces+patchwork-linux-riscv=patchwork.kernel.org@lists.infradead.org DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=bombadil.20170209; h=Sender: Content-Transfer-Encoding:Content-Type:Cc:List-Subscribe:List-Help:List-Post: List-Archive:List-Unsubscribe:List-Id:MIME-Version:In-Reply-To:References: Message-ID:Date:Subject:To:From:Reply-To:Content-ID:Content-Description: Resent-Date:Resent-From:Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID: List-Owner; bh=HsIxoXvyyl4xJjTS9uzcDi9k982k6FsOHm+9pLRc3ds=; b=DRRGlFOAKowRHD Sh9zmby58I2RUP42Swk78HadNiNilC4fUOS55RxNDdJGrl5YdonN4x2OGpDb3pRPAtkvRKO9xmO6X OxjyVElWRlCi6E67DgYBbB/rABraukX6CZj4ohOgdJCSf6F7v/w7nIkJtoyezYsYgn1mbKC+TMm3K 3FhAjbR1oYWDLS13SrvbIQ25qbyDIdgRFRJVUMPKUefQdy3DMxnp5IdjNIbF5yC+LTVGQ6iOy++TX eCkWQ0g1YBsi6O69N8ZfIVNS819RqiWVdRyXr7h+KZajWD9jLGRoru2AnXuqOfuL9NIEe2DBMSOy0 EEvE9LDRhkAmVQkSg3tw==; Received: from localhost ([127.0.0.1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.92.2 #3 (Red Hat Linux)) id 1iFtMA-0004i2-C3; Thu, 03 Oct 2019 05:08:50 +0000 Received: from esa2.hgst.iphmx.com ([68.232.143.124]) by bombadil.infradead.org with esmtps (Exim 4.92.2 #3 (Red Hat Linux)) id 1iFtM6-0004hO-VS for linux-riscv@lists.infradead.org; Thu, 03 Oct 2019 05:08:49 +0000 DKIM-Signature: v=1; a=rsa-sha256; c=simple/simple; d=wdc.com; i=@wdc.com; q=dns/txt; s=dkim.wdc.com; t=1570079338; x=1601615338; h=from:to:cc:subject:date:message-id:references: in-reply-to:content-transfer-encoding:mime-version; bh=I5TOrsqtVvuRTKqrh7Cq4V4sM1VGWVgxcVHmmBk8H8M=; b=bPTxVIUHnEo4C6qoj+ku4CMd3jn5OVO8Qbli5hRm3bmVvpNb2hVcDn34 8qxO9jXi9k3vyPymgTvSbyxohxDAZZSSiRcpGxoRQIo+1oyCSc2h4bn6a 4uhWPmNoMMirbrCTc4jrQf35Z3jOtQKs6XgiFo9P8Af3odAEjx1bLT3up fMCzP7/Dq4FURWaIwCYcCH5lY7GtCVIyNOCVF4fTfL8SJ+0V+T0vXiIr9 RU6iMiqG7Ql0VuXZU3KfUphfSXc8RNGHhaOSrGpVeD47Jb0mWAmDq24cg OYb3fM/m47t0bJb4V8xyVul+ZiUfUL1fuj2B1dHUFC3l9DwZCUISH3doZ A==; IronPort-SDR: jiv3WoKbv8iYq77tYJ5kIAwvFdbHl5RhhdEeDR+U9sxkw5f7zsKxwb7yRPjPoXy2+nUiSJNc7z 7WdFukT0/isOfkZkNGVRzung2x8xcM6QOQDiZihmTwbrWv79euetz3uvIBjgiV/Z7DbON6stTk Jb7tIqulShDVKu2221AzadtZDaaqVd5I4O+lnDZIbwXlsPGnCXsWKFGMqlq4N/lbfq6IEMyVeq hB/KrM/kHzyGa99F4y8v8mzY+x5xM/D8oQXZCTXoWh/e8bqd+nbUqde/wZ2BVGGMQ1PoHOul9f ipM= X-IronPort-AV: E=Sophos;i="5.67,251,1566835200"; d="scan'208";a="220620964" Received: from mail-co1nam05lp2056.outbound.protection.outlook.com (HELO NAM05-CO1-obe.outbound.protection.outlook.com) ([104.47.48.56]) by ob1.hgst.iphmx.com with ESMTP; 03 Oct 2019 13:08:53 +0800 ARC-Seal: i=1; a=rsa-sha256; s=arcselector9901; d=microsoft.com; cv=none; b=as4x0Wu/1N5P9dSMpGr8OsSfdwwZEK/00bpPcvarbBddc/gMAPKm+WQ7oa0R3ZVcOxck1NbVUsLp8nhLPq5kwBjHOLvfwVnuaOLIHixzo6saU27wnC7B9tG+ILYj3OOkWor5hU1ywnW311GkaV6sxUh6j8JiHWB/G33+yUwE5/Ig8B09d073TrqkdjHY5hQE82v0tR9gPNFi53DtKzQxDPYFqO73hzvJ49/giuMwccPWH93Ikg216zbwIMxd3p67ZDRFjvL3on3QoFHvMYaIUtPxc20+ASDmqLQAk29FEQMGxh6rdiiyGV/Z0bIPWLWh62KcTqJU2oQx8XUq6h2I0Q== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=microsoft.com; s=arcselector9901; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-SenderADCheck; bh=PoJ8pfpI5dTJHPPel0IttbvqQeo9z28YxuHukEFvOiM=; b=E3H525FE6czA0tfJBwSg5fyax8N4nL4WDmZHHpJfze2sI1zzEXddunSfDne585kNKmrwRE1flv1W0y4ZpsRq8/6eO7mD0cMni01W4Rc1kRYOJhWEu49HquzXGBHwM6L2o5Ty8AGpGfuD7WPaSLGgXXoTgXamZxkDTRQlZpz+Y7jPHeiVb/BbZmC/dhfWjI843/zgEPi72uSWLoylNIhdT1ARs+xTD7Nk5H3Gq8P6ZttJVBUTKphvSX+uxRT8ZbQyWXHUDgajca6YIel15AJnrvJY1dwle6UPqWSeMcTnhwZPJNn94dL6anOVukS25zzNe2ENCEZ7xKbgAkRzgRjzrw== ARC-Authentication-Results: i=1; mx.microsoft.com 1; spf=pass smtp.mailfrom=wdc.com; dmarc=pass action=none header.from=wdc.com; dkim=pass header.d=wdc.com; arc=none DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=sharedspace.onmicrosoft.com; s=selector2-sharedspace-onmicrosoft-com; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-SenderADCheck; bh=PoJ8pfpI5dTJHPPel0IttbvqQeo9z28YxuHukEFvOiM=; b=e6Xq4JsApYjjJk03rs1h87wCo9/ezRwZiU/7Q/UWc63bIMpbY04wujg8Y6Lwe3mtMwNoTTp6CEhceQb6tdtQ6tadNnnjE0FYP143PKDXdvyRfVEyl5GXZNMSCxq0TDONzy7pxEAwz/bCHQ2tVNi9m1bAYXFlkVsBwsP0YOJDg9Q= Received: from MN2PR04MB6061.namprd04.prod.outlook.com (20.178.246.15) by MN2PR04MB6272.namprd04.prod.outlook.com (20.178.248.27) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.2305.17; Thu, 3 Oct 2019 05:08:42 +0000 Received: from MN2PR04MB6061.namprd04.prod.outlook.com ([fe80::1454:87a:13b0:d3a]) by MN2PR04MB6061.namprd04.prod.outlook.com ([fe80::1454:87a:13b0:d3a%7]) with mapi id 15.20.2305.023; Thu, 3 Oct 2019 05:08:42 +0000 From: Anup Patel To: Palmer Dabbelt , Paul Walmsley , Paolo Bonzini , Radim K Subject: [PATCH v8 18/19] RISC-V: KVM: Document RISC-V specific parts of KVM API. Thread-Topic: [PATCH v8 18/19] RISC-V: KVM: Document RISC-V specific parts of KVM API. Thread-Index: AQHVeaigvJ4hGft79EmXR9Xkj/55rw== Date: Thu, 3 Oct 2019 05:08:42 +0000 Message-ID: <20191003050558.9031-19-anup.patel@wdc.com> References: <20191003050558.9031-1-anup.patel@wdc.com> In-Reply-To: <20191003050558.9031-1-anup.patel@wdc.com> Accept-Language: en-US Content-Language: en-US X-MS-Has-Attach: X-MS-TNEF-Correlator: x-clientproxiedby: BMXPR01CA0030.INDPRD01.PROD.OUTLOOK.COM (2603:1096:b00:c::16) To MN2PR04MB6061.namprd04.prod.outlook.com (2603:10b6:208:d8::15) authentication-results: spf=none (sender IP is ) smtp.mailfrom=Anup.Patel@wdc.com; x-ms-exchange-messagesentrepresentingtype: 1 x-mailer: git-send-email 2.17.1 x-originating-ip: [111.235.74.37] x-ms-publictraffictype: Email x-ms-office365-filtering-correlation-id: 75489bb8-eb09-47da-35f0-08d747bfc268 x-ms-office365-filtering-ht: Tenant x-ms-traffictypediagnostic: MN2PR04MB6272: x-ms-exchange-purlcount: 1 x-ms-exchange-transport-forked: True x-microsoft-antispam-prvs: wdcipoutbound: EOP-TRUE x-ms-oob-tlc-oobclassifiers: OLM:9508; x-forefront-prvs: 01792087B6 x-forefront-antispam-report: SFV:NSPM; SFS:(10019020)(4636009)(136003)(376002)(346002)(366004)(396003)(39860400002)(189003)(199004)(6512007)(6306002)(6486002)(81166006)(81156014)(8936002)(6116002)(3846002)(8676002)(50226002)(2906002)(110136005)(66066001)(6436002)(316002)(66476007)(66556008)(7416002)(66446008)(36756003)(1076003)(5660300002)(54906003)(7736002)(305945005)(76176011)(25786009)(52116002)(256004)(14444005)(71190400001)(86362001)(99286004)(71200400001)(2616005)(446003)(14454004)(476003)(102836004)(186003)(26005)(11346002)(966005)(44832011)(6506007)(486006)(478600001)(4326008)(66946007)(386003)(64756008); DIR:OUT; SFP:1102; SCL:1; SRVR:MN2PR04MB6272; H:MN2PR04MB6061.namprd04.prod.outlook.com; FPR:; SPF:None; LANG:en; PTR:InfoNoRecords; MX:1; A:1; x-ms-exchange-senderadcheck: 1 x-microsoft-antispam: BCL:0; x-microsoft-antispam-message-info: bxecYzqNI/JDh/5OzHevz/dP8sHY5ipCl9xXjsw1F7XlASdF0QhuSrygp5CRsmbVqthpicGDkHeAFm6g74yzFMTU4xzp/8yuctSEny82rk+H65Pb9DjSGmbihtfRaTrEt7fWvec0lp2r5z0KdsYN5Y9fobIB4hRW8v6WyQs6MbZp+nc5PERu/SCIh3HSlLcu7RbhBRtRmYvDFVv/CzoE+/H7qgwxG0NVVfCMtIfqtiEqQ4qPUt+w3leQy0kSxBj1B6inV39wYQffINQ8dW8uzf+xyLiVx8cchTvk9AWi4Ffd8oY1RN846jjyVdLQNa3BLjKY5SjDu9WJNeyB5hiyu1/0RR8e5IJ6j6G/rS2lyaRQwyXPemej/kG7QFu2tzs11JuC/jBi89R4p74fTYBgDQwh1k7yKTAtde/dOki+6Y5Qn3ujd9pPb9hejvZJqEU49GV1Dldw0WXD2OFfNb3atQ== MIME-Version: 1.0 X-OriginatorOrg: wdc.com X-MS-Exchange-CrossTenant-Network-Message-Id: 75489bb8-eb09-47da-35f0-08d747bfc268 X-MS-Exchange-CrossTenant-originalarrivaltime: 03 Oct 2019 05:08:42.5937 (UTC) X-MS-Exchange-CrossTenant-fromentityheader: Hosted X-MS-Exchange-CrossTenant-id: b61c8803-16f3-4c35-9b17-6f65f441df86 X-MS-Exchange-CrossTenant-mailboxtype: HOSTED X-MS-Exchange-CrossTenant-userprincipalname: SF5TOdRsWLEdulv5IcDtziMRIdaSelRxUBkkuNFgvEt9UMnGOvW5w88OQOv1S5rRpEVil5EVsuRlPwfjL9bPWw== X-MS-Exchange-Transport-CrossTenantHeadersStamped: MN2PR04MB6272 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20191002_220847_065694_937C5508 X-CRM114-Status: GOOD ( 16.38 ) X-Spam-Score: -2.5 (--) X-Spam-Report: SpamAssassin version 3.4.2 on bombadil.infradead.org summary: Content analysis details: (-2.5 points) pts rule name description ---- ---------------------- -------------------------------------------------- -2.3 RCVD_IN_DNSWL_MED RBL: Sender listed at https://www.dnswl.org/, medium trust [68.232.143.124 listed in list.dnswl.org] -0.0 SPF_PASS SPF: sender matches SPF record 0.0 SPF_HELO_NONE SPF: HELO does not publish an SPF Record -0.1 DKIM_VALID_EF Message has a valid DKIM or DK signature from envelope-from domain 0.1 DKIM_SIGNED Message has a DKIM or DK signature, not necessarily valid -0.1 DKIM_VALID_AU Message has a valid DKIM or DK signature from author's domain -0.1 DKIM_VALID Message has at least one valid DKIM or DK signature X-BeenThere: linux-riscv@lists.infradead.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Damien Le Moal , Anup Patel , "kvm@vger.kernel.org" , Anup Patel , Daniel Lezcano , "linux-kernel@vger.kernel.org" , Christoph Hellwig , Atish Patra , Alexander Graf , Alistair Francis , Thomas Gleixner , "linux-riscv@lists.infradead.org" Sender: "linux-riscv" Errors-To: linux-riscv-bounces+patchwork-linux-riscv=patchwork.kernel.org@lists.infradead.org Document RISC-V specific parts of the KVM API, such as: - The interrupt numbers passed to the KVM_INTERRUPT ioctl. - The states supported by the KVM_{GET,SET}_MP_STATE ioctls. - The registers supported by the KVM_{GET,SET}_ONE_REG interface and the encoding of those register ids. - The exit reason KVM_EXIT_RISCV_SBI for SBI calls forwarded to userspace tool. Signed-off-by: Anup Patel --- Documentation/virt/kvm/api.txt | 158 +++++++++++++++++++++++++++++++-- 1 file changed, 151 insertions(+), 7 deletions(-) diff --git a/Documentation/virt/kvm/api.txt b/Documentation/virt/kvm/api.txt index 4833904d32a5..f9ea81fe1143 100644 --- a/Documentation/virt/kvm/api.txt +++ b/Documentation/virt/kvm/api.txt @@ -471,7 +471,7 @@ struct kvm_translation { 4.16 KVM_INTERRUPT Capability: basic -Architectures: x86, ppc, mips +Architectures: x86, ppc, mips, riscv Type: vcpu ioctl Parameters: struct kvm_interrupt (in) Returns: 0 on success, negative on failure. @@ -531,6 +531,22 @@ interrupt number dequeues the interrupt. This is an asynchronous vcpu ioctl and can be invoked from any thread. +RISC-V: + +Queues an external interrupt to be injected into the virutal CPU. This ioctl +is overloaded with 2 different irq values: + +a) KVM_INTERRUPT_SET + + This sets external interrupt for a virtual CPU and it will receive + once it is ready. + +b) KVM_INTERRUPT_UNSET + + This clears pending external interrupt for a virtual CPU. + +This is an asynchronous vcpu ioctl and can be invoked from any thread. + 4.17 KVM_DEBUG_GUEST @@ -1219,7 +1235,7 @@ for vm-wide capabilities. 4.38 KVM_GET_MP_STATE Capability: KVM_CAP_MP_STATE -Architectures: x86, s390, arm, arm64 +Architectures: x86, s390, arm, arm64, riscv Type: vcpu ioctl Parameters: struct kvm_mp_state (out) Returns: 0 on success; -1 on error @@ -1233,7 +1249,8 @@ uniprocessor guests). Possible values are: - - KVM_MP_STATE_RUNNABLE: the vcpu is currently running [x86,arm/arm64] + - KVM_MP_STATE_RUNNABLE: the vcpu is currently running + [x86,arm/arm64,riscv] - KVM_MP_STATE_UNINITIALIZED: the vcpu is an application processor (AP) which has not yet received an INIT signal [x86] - KVM_MP_STATE_INIT_RECEIVED: the vcpu has received an INIT signal, and is @@ -1242,7 +1259,7 @@ Possible values are: is waiting for an interrupt [x86] - KVM_MP_STATE_SIPI_RECEIVED: the vcpu has just received a SIPI (vector accessible via KVM_GET_VCPU_EVENTS) [x86] - - KVM_MP_STATE_STOPPED: the vcpu is stopped [s390,arm/arm64] + - KVM_MP_STATE_STOPPED: the vcpu is stopped [s390,arm/arm64,riscv] - KVM_MP_STATE_CHECK_STOP: the vcpu is in a special error state [s390] - KVM_MP_STATE_OPERATING: the vcpu is operating (running or halted) [s390] @@ -1253,7 +1270,7 @@ On x86, this ioctl is only useful after KVM_CREATE_IRQCHIP. Without an in-kernel irqchip, the multiprocessing state must be maintained by userspace on these architectures. -For arm/arm64: +For arm/arm64/riscv: The only states that are valid are KVM_MP_STATE_STOPPED and KVM_MP_STATE_RUNNABLE which reflect if the vcpu is paused or not. @@ -1261,7 +1278,7 @@ KVM_MP_STATE_RUNNABLE which reflect if the vcpu is paused or not. 4.39 KVM_SET_MP_STATE Capability: KVM_CAP_MP_STATE -Architectures: x86, s390, arm, arm64 +Architectures: x86, s390, arm, arm64, riscv Type: vcpu ioctl Parameters: struct kvm_mp_state (in) Returns: 0 on success; -1 on error @@ -1273,7 +1290,7 @@ On x86, this ioctl is only useful after KVM_CREATE_IRQCHIP. Without an in-kernel irqchip, the multiprocessing state must be maintained by userspace on these architectures. -For arm/arm64: +For arm/arm64/riscv: The only states that are valid are KVM_MP_STATE_STOPPED and KVM_MP_STATE_RUNNABLE which reflect if the vcpu should be paused or not. @@ -2282,6 +2299,116 @@ following id bit patterns: 0x7020 0000 0003 02 <0:3> +RISC-V registers are mapped using the lower 32 bits. The upper 8 bits of +that is the register group type. + +RISC-V config registers are meant for configuring a Guest VCPU and it has +the following id bit patterns: + 0x8020 0000 01 (32bit Host) + 0x8030 0000 01 (64bit Host) + +Following are the RISC-V config registers: + + Encoding Register Description +------------------------------------------------------------------ + 0x80x0 0000 0100 0000 isa ISA feature bitmap of Guest VCPU + 0x80x0 0000 0100 0001 tbfreq Time base frequency + +The isa config register can be read anytime but can only be written before +a Guest VCPU runs. It will have ISA feature bits matching underlying host +set by default. The tbfreq config register is a read-only register and it +will return host timebase frequenc. + +RISC-V core registers represent the general excution state of a Guest VCPU +and it has the following id bit patterns: + 0x8020 0000 02 (32bit Host) + 0x8030 0000 02 (64bit Host) + +Following are the RISC-V core registers: + + Encoding Register Description +------------------------------------------------------------------ + 0x80x0 0000 0200 0000 regs.pc Program counter + 0x80x0 0000 0200 0001 regs.ra Return address + 0x80x0 0000 0200 0002 regs.sp Stack pointer + 0x80x0 0000 0200 0003 regs.gp Global pointer + 0x80x0 0000 0200 0004 regs.tp Task pointer + 0x80x0 0000 0200 0005 regs.t0 Caller saved register 0 + 0x80x0 0000 0200 0006 regs.t1 Caller saved register 1 + 0x80x0 0000 0200 0007 regs.t2 Caller saved register 2 + 0x80x0 0000 0200 0008 regs.s0 Callee saved register 0 + 0x80x0 0000 0200 0009 regs.s1 Callee saved register 1 + 0x80x0 0000 0200 000a regs.a0 Function argument (or return value) 0 + 0x80x0 0000 0200 000b regs.a1 Function argument (or return value) 1 + 0x80x0 0000 0200 000c regs.a2 Function argument 2 + 0x80x0 0000 0200 000d regs.a3 Function argument 3 + 0x80x0 0000 0200 000e regs.a4 Function argument 4 + 0x80x0 0000 0200 000f regs.a5 Function argument 5 + 0x80x0 0000 0200 0010 regs.a6 Function argument 6 + 0x80x0 0000 0200 0011 regs.a7 Function argument 7 + 0x80x0 0000 0200 0012 regs.s2 Callee saved register 2 + 0x80x0 0000 0200 0013 regs.s3 Callee saved register 3 + 0x80x0 0000 0200 0014 regs.s4 Callee saved register 4 + 0x80x0 0000 0200 0015 regs.s5 Callee saved register 5 + 0x80x0 0000 0200 0016 regs.s6 Callee saved register 6 + 0x80x0 0000 0200 0017 regs.s7 Callee saved register 7 + 0x80x0 0000 0200 0018 regs.s8 Callee saved register 8 + 0x80x0 0000 0200 0019 regs.s9 Callee saved register 9 + 0x80x0 0000 0200 001a regs.s10 Callee saved register 10 + 0x80x0 0000 0200 001b regs.s11 Callee saved register 11 + 0x80x0 0000 0200 001c regs.t3 Caller saved register 3 + 0x80x0 0000 0200 001d regs.t4 Caller saved register 4 + 0x80x0 0000 0200 001e regs.t5 Caller saved register 5 + 0x80x0 0000 0200 001f regs.t6 Caller saved register 6 + 0x80x0 0000 0200 0020 mode Privilege mode (1 = S-mode or 0 = U-mode) + +RISC-V csr registers represent the supervisor mode control/status registers +of a Guest VCPU and it has the following id bit patterns: + 0x8020 0000 03 (32bit Host) + 0x8030 0000 03 (64bit Host) + +Following are the RISC-V csr registers: + + Encoding Register Description +------------------------------------------------------------------ + 0x80x0 0000 0300 0000 sstatus Supervisor status + 0x80x0 0000 0300 0001 sie Supervisor interrupt enable + 0x80x0 0000 0300 0002 stvec Supervisor trap vector base + 0x80x0 0000 0300 0003 sscratch Supervisor scratch register + 0x80x0 0000 0300 0004 sepc Supervisor exception program counter + 0x80x0 0000 0300 0005 scause Supervisor trap cause + 0x80x0 0000 0300 0006 stval Supervisor bad address or instruction + 0x80x0 0000 0300 0007 sip Supervisor interrupt pending + 0x80x0 0000 0300 0008 satp Supervisor address translation and protection + +RISC-V F extension registers represent the single precision floating point +state of a Guest VCPU and it has the following id bit patterns: + 0x8020 0000 04 + +Following are the RISC-V F extension registers: + + Encoding Register Description +------------------------------------------------------------------ + 0x8020 0000 0400 0000 f[0] Floating point register 0 + ... + 0x8020 0000 0400 001f f[31] Floating point register 31 + 0x8020 0000 0400 0020 fcsr Floating point control and status register + +RISC-V D extension registers represent the double precision floating point +state of a Guest VCPU and it has the following id bit patterns: + 0x8020 0000 05 (fcsr) + 0x8030 0000 05 (non-fcsr) + +Following are the RISC-V D extension registers: + + Encoding Register Description +------------------------------------------------------------------ + 0x8030 0000 0500 0000 f[0] Floating point register 0 + ... + 0x8030 0000 0500 001f f[31] Floating point register 31 + 0x8020 0000 0500 0020 fcsr Floating point control and status register + + 4.69 KVM_GET_ONE_REG Capability: KVM_CAP_ONE_REG @@ -4468,6 +4595,23 @@ Hyper-V SynIC state change. Notification is used to remap SynIC event/message pages and to enable/disable SynIC messages/events processing in userspace. + /* KVM_EXIT_RISCV_SBI */ + struct { + unsigned long extension_id; + unsigned long function_id; + unsigned long args[6]; + unsigned long ret[2]; + } riscv_sbi; +If exit reason is KVM_EXIT_RISCV_SBI then it indicates that the VCPU has +done a SBI call which is not handled by KVM RISC-V kernel module. The details +of the SBI call are available in 'riscv_sbi' member of kvm_run stucture. The +'extension_id' field of 'riscv_sbi' represents SBI extension ID whereas the +'function_id' field represents function ID of given SBI extension. The 'args' +array field of 'riscv_sbi' represents parameters for the SBI call and 'ret' +array field represents return values. The userspace should update the return +values of SBI call before resuming the VCPU. For more details on RISC-V SBI +spec refer, https://github.com/riscv/riscv-sbi-doc. + /* Fix the size of the union. */ char padding[256]; }; From patchwork Thu Oct 3 05:08:49 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Anup Patel X-Patchwork-Id: 11172159 Return-Path: Received: from mail.kernel.org (pdx-korg-mail-1.web.codeaurora.org [172.30.200.123]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id 7DFE814DB for ; Thu, 3 Oct 2019 05:09:07 +0000 (UTC) Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id 5B15321D81 for ; Thu, 3 Oct 2019 05:09:07 +0000 (UTC) Authentication-Results: mail.kernel.org; dkim=pass (2048-bit key) header.d=lists.infradead.org header.i=@lists.infradead.org header.b="fsmgI3xa"; dkim=fail reason="signature verification failed" (2048-bit key) header.d=wdc.com header.i=@wdc.com header.b="LVqu0gQw"; dkim=fail reason="signature verification failed" (1024-bit key) header.d=sharedspace.onmicrosoft.com header.i=@sharedspace.onmicrosoft.com header.b="ZVsrMi0x" DMARC-Filter: OpenDMARC Filter v1.3.2 mail.kernel.org 5B15321D81 Authentication-Results: mail.kernel.org; dmarc=fail (p=none dis=none) header.from=wdc.com Authentication-Results: mail.kernel.org; spf=none smtp.mailfrom=linux-riscv-bounces+patchwork-linux-riscv=patchwork.kernel.org@lists.infradead.org DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=bombadil.20170209; h=Sender: Content-Transfer-Encoding:Content-Type:Cc:List-Subscribe:List-Help:List-Post: List-Archive:List-Unsubscribe:List-Id:MIME-Version:In-Reply-To:References: Message-ID:Date:Subject:To:From:Reply-To:Content-ID:Content-Description: Resent-Date:Resent-From:Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID: List-Owner; bh=rCEtbwaI5eL+erYhqBF7ywXquD6P6rVRS2rZktuGh18=; b=fsmgI3xaV9v1Xd sUqWqNbCc1dNLeO4BuAUhECVTKvu9Eh71AHojPYlqUKw6rWo6DmoU9PraGghM/paDbnM7U0JelICa e/uly5w//G3b1VkNkiTAlP6VDvJ2J1UsFsmX/cGCzeKVV4IqZz9kM8bKTQhbnXo2FesMcWm3ctGjU YSoghwMnp3effG+8pCrhH2aOEsXN6ykF7CFxTtqEMylzEIOTe0zBUM1UjQX3hwhL/bdaszvxTeNWa RdMA09Mj5b//sZXPt1JPC5c7gtpEmnMa11DAESvhqGiJh4F3zijCr2lmUtQyBP+kwHdqhK/G+PcKW YzLz8j+hF+6YtuU7NqmQ==; Received: from localhost ([127.0.0.1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.92.2 #3 (Red Hat Linux)) id 1iFtMJ-0004mp-4Y; Thu, 03 Oct 2019 05:08:59 +0000 Received: from esa2.hgst.iphmx.com ([68.232.143.124]) by bombadil.infradead.org with esmtps (Exim 4.92.2 #3 (Red Hat Linux)) id 1iFtMG-0004mM-CA for linux-riscv@lists.infradead.org; Thu, 03 Oct 2019 05:08:57 +0000 DKIM-Signature: v=1; a=rsa-sha256; c=simple/simple; d=wdc.com; i=@wdc.com; q=dns/txt; s=dkim.wdc.com; t=1570079352; x=1601615352; h=from:to:cc:subject:date:message-id:references: in-reply-to:content-transfer-encoding:mime-version; bh=e4IeyBIoCbMLkmvC4pIlXMoWK9e6hQZ7UT/EejEs+y4=; b=LVqu0gQwO3Fg+uDHtXcqbcVXJFDvC1h1AI6NOztexJmckgr7qFn8BFvu 7AfIzrJPMainKVMGOQ24+FejBOvPEXcevgvWbQivTh8bcVwQDXaZw1Dp2 Y9GvEpO5xfkfet4B/43CWvLqs4n2YW3WNEaRppNaI8I6Eh27yTieXiTXf 8NJNM9K1BlxMysisv3AEvDWiZBaJRuIXjcwBiZDQp90sscE4+DSNmnC73 oax7ExWvRMqQWwAK1YPOrW47HdfTSF4uGA1XRArxzWfuEYNaCVMqCKAs5 SxskLCPs/8BNLvKPU43x20ArfP0H33MnU5XUvhputGFCK9loHeuu4U6Zp Q==; IronPort-SDR: 4tlD4bsmYFAIQDjrP7WdWT/aiT2Y3SvvifAWDOe51bibDY/YvB7tL//LFA4xqEKDyLWc2Umk9G V6GvOaz+n3DFJR9fnNngjvG+wbbHCJpDULfJzVC1EZ/Iy86hVD1md/k1gPNzuNVPwydTAK1FqH 3m95RTidSsHLCsrlRejDa0p6i3Q3DDmoMYzYQ2vgbrnRYG/xBoJDs8f9LgLWCOLYknKu8Y72Nf c5PMYmWgd03mILleiRAk8wfF5TTxK+eN4ybzDhGDkGotBTDwFe+uKZuBk1y2gsSqIMDB+0zAck NdY= X-IronPort-AV: E=Sophos;i="5.67,251,1566835200"; d="scan'208";a="220620976" Received: from mail-by2nam05lp2051.outbound.protection.outlook.com (HELO NAM05-BY2-obe.outbound.protection.outlook.com) ([104.47.50.51]) by ob1.hgst.iphmx.com with ESMTP; 03 Oct 2019 13:09:04 +0800 ARC-Seal: i=1; a=rsa-sha256; s=arcselector9901; d=microsoft.com; cv=none; b=j7yLgKv6ZNBygPrwWV7Pfr3306SfWS39Eq5zvfnGposN4zxQMnzplqYP0Sl4cs7FZ8QxNLF9RcxUe7HOxT9pkFNV7vNYrtBckppEHl8W9HIVn2iq3JGq8+Uci6apADA0OW145DS/GSzerqPExE9iU1hi/PgkBowIHzDzBMQIu1Q2VS0NFTeVMCBgaCTVcKfrmOTbOac9/sI0dYjmYHow6Xu4EdpatGuOkYt++PTi16vIdu7iHwKO/Qx61Aj4ARyNWNuODeSnj8/hx7nEBFvh1rfaxRoDDZarmj9V2bpD9zM04EgtxDLUKRg4ERxYjF1nddd4Jx+GPv928eQexYFIUw== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=microsoft.com; s=arcselector9901; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-SenderADCheck; bh=eyJioRD2MCDWcOnHG5aafsm4TsMtXV13r+iC9EJ4k0s=; b=HA0MQT2KKf4+7KVzVhHMc+O55yiZfJnsFD6IdMwBJCssBXNRXCMv+Ywy45xstq4WIGAbhx1kBVLcMDwyoLrmslWY0VKNKjopYEysXP0oZ1iqE38FvCrB/+zBaXc3L0+d9BsRQzwO8kFl4Zcolch8nLvAXtvM1X8ByYOUFTavnFVD3EIdyYABT4T3XaoWJ0cAWGUX7lNJectQQR32VUYnSRqwUiew+vDyb42orpTW98RQ3Sj58mZUcy/pu6ILJ+5IVCm1y9G+2O0RHtfXPEbHSsvMxHRSzUC2Skx0xTqAfSWVw7C6X16PeEm9z7nCtfVt+N2/FdwkEu65uB1k0sfddQ== ARC-Authentication-Results: i=1; mx.microsoft.com 1; spf=pass smtp.mailfrom=wdc.com; dmarc=pass action=none header.from=wdc.com; dkim=pass header.d=wdc.com; arc=none DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=sharedspace.onmicrosoft.com; s=selector2-sharedspace-onmicrosoft-com; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-SenderADCheck; bh=eyJioRD2MCDWcOnHG5aafsm4TsMtXV13r+iC9EJ4k0s=; b=ZVsrMi0x0byPiwe0ezRmyel0UF1z1Ac3M4M9pek1sHa+4pqjLtQ1fP92L1DOzm+nNS0m+Pgc/fDBEtTw8HtJA8HT9s4iBekOyEDqPhH5jYy14J/1OcxWFlBdpH1VUnJHgO+AM5vRaxe8WzTxUyV09K9Ts/bMVn1YgAnYjcQ38NI= Received: from MN2PR04MB6061.namprd04.prod.outlook.com (20.178.246.15) by MN2PR04MB6272.namprd04.prod.outlook.com (20.178.248.27) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.2305.17; Thu, 3 Oct 2019 05:08:49 +0000 Received: from MN2PR04MB6061.namprd04.prod.outlook.com ([fe80::1454:87a:13b0:d3a]) by MN2PR04MB6061.namprd04.prod.outlook.com ([fe80::1454:87a:13b0:d3a%7]) with mapi id 15.20.2305.023; Thu, 3 Oct 2019 05:08:49 +0000 From: Anup Patel To: Palmer Dabbelt , Paul Walmsley , Paolo Bonzini , Radim K Subject: [PATCH v8 19/19] RISC-V: KVM: Add MAINTAINERS entry Thread-Topic: [PATCH v8 19/19] RISC-V: KVM: Add MAINTAINERS entry Thread-Index: AQHVeaikWtIEjYUkWUCF0M+05pNo4g== Date: Thu, 3 Oct 2019 05:08:49 +0000 Message-ID: <20191003050558.9031-20-anup.patel@wdc.com> References: <20191003050558.9031-1-anup.patel@wdc.com> In-Reply-To: <20191003050558.9031-1-anup.patel@wdc.com> Accept-Language: en-US Content-Language: en-US X-MS-Has-Attach: X-MS-TNEF-Correlator: x-clientproxiedby: BMXPR01CA0030.INDPRD01.PROD.OUTLOOK.COM (2603:1096:b00:c::16) To MN2PR04MB6061.namprd04.prod.outlook.com (2603:10b6:208:d8::15) authentication-results: spf=none (sender IP is ) smtp.mailfrom=Anup.Patel@wdc.com; x-ms-exchange-messagesentrepresentingtype: 1 x-mailer: git-send-email 2.17.1 x-originating-ip: [111.235.74.37] x-ms-publictraffictype: Email x-ms-office365-filtering-correlation-id: 898c908d-4b2f-44b8-e093-08d747bfc678 x-ms-office365-filtering-ht: Tenant x-ms-traffictypediagnostic: MN2PR04MB6272: x-ms-exchange-transport-forked: True x-microsoft-antispam-prvs: wdcipoutbound: EOP-TRUE x-ms-oob-tlc-oobclassifiers: OLM:1303; x-forefront-prvs: 01792087B6 x-forefront-antispam-report: SFV:NSPM; SFS:(10019020)(4636009)(136003)(376002)(346002)(366004)(396003)(39860400002)(189003)(199004)(6512007)(6486002)(81166006)(81156014)(8936002)(6116002)(3846002)(8676002)(50226002)(2906002)(110136005)(66066001)(6436002)(316002)(66476007)(66556008)(7416002)(66446008)(36756003)(1076003)(5660300002)(54906003)(4744005)(7736002)(305945005)(76176011)(25786009)(52116002)(256004)(71190400001)(86362001)(99286004)(71200400001)(2616005)(446003)(14454004)(476003)(102836004)(186003)(26005)(11346002)(44832011)(6506007)(486006)(478600001)(4326008)(66946007)(386003)(64756008); DIR:OUT; SFP:1102; SCL:1; SRVR:MN2PR04MB6272; H:MN2PR04MB6061.namprd04.prod.outlook.com; FPR:; SPF:None; LANG:en; PTR:InfoNoRecords; MX:1; A:1; x-ms-exchange-senderadcheck: 1 x-microsoft-antispam: BCL:0; x-microsoft-antispam-message-info: lHMapwfuiL/3qCE0E+2DdpqR3s0pJhIuJW/gX3ZU2zKiYROh/Ei9ubZX8q4c3uNffNCXUcf7r4VTGXy7Hdb/1ahTbcwV6bW9lFgbR/zmQVaylTLPuFc7jlJWYVfOe2o/izux1mUEDV+v0Irtlqglwm0y+Ov14YNUV+50YjcpKYso3UGJIjDEXw5IUuIOJpHeLKm5VJwcymmC6g3JY+FPD5vl398bTogfJeELdMNgLiRmCrYheIyWavNds7xHL0btftons95lFyC+LgunTyW0UNZCVy7MqanrKTpisPUxEdUKje24pNK2P/l2KTB9yS9kK8Vd1fMX3ZWDAsJTIYjqiPS9hH2SRLSddfydlZDRiSCb9CKcl4nVQHDGa9w24h9VU2cTDC4B8tEBuRPjdJzJpS1HybOd1YjEcfu7w/JlPeE= MIME-Version: 1.0 X-OriginatorOrg: wdc.com X-MS-Exchange-CrossTenant-Network-Message-Id: 898c908d-4b2f-44b8-e093-08d747bfc678 X-MS-Exchange-CrossTenant-originalarrivaltime: 03 Oct 2019 05:08:49.6027 (UTC) X-MS-Exchange-CrossTenant-fromentityheader: Hosted X-MS-Exchange-CrossTenant-id: b61c8803-16f3-4c35-9b17-6f65f441df86 X-MS-Exchange-CrossTenant-mailboxtype: HOSTED X-MS-Exchange-CrossTenant-userprincipalname: Iz9D3tn/CVFBPzlqU3vMOwTAynoCvpiHEOFsptDPoeuwR4Pb3ak2We3T2AHqbCNku+4ksOCfGexBcqVBHtCNvA== X-MS-Exchange-Transport-CrossTenantHeadersStamped: MN2PR04MB6272 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20191002_220856_452970_58F2ADB9 X-CRM114-Status: GOOD ( 11.45 ) X-Spam-Score: -2.5 (--) X-Spam-Report: SpamAssassin version 3.4.2 on bombadil.infradead.org summary: Content analysis details: (-2.5 points) pts rule name description ---- ---------------------- -------------------------------------------------- -2.3 RCVD_IN_DNSWL_MED RBL: Sender listed at https://www.dnswl.org/, medium trust [68.232.143.124 listed in list.dnswl.org] -0.0 SPF_PASS SPF: sender matches SPF record 0.0 SPF_HELO_NONE SPF: HELO does not publish an SPF Record -0.1 DKIM_VALID_EF Message has a valid DKIM or DK signature from envelope-from domain 0.1 DKIM_SIGNED Message has a DKIM or DK signature, not necessarily valid -0.1 DKIM_VALID_AU Message has a valid DKIM or DK signature from author's domain -0.1 DKIM_VALID Message has at least one valid DKIM or DK signature X-BeenThere: linux-riscv@lists.infradead.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Damien Le Moal , Anup Patel , "kvm@vger.kernel.org" , Anup Patel , Daniel Lezcano , "linux-kernel@vger.kernel.org" , Christoph Hellwig , Atish Patra , Alexander Graf , Alistair Francis , Thomas Gleixner , "linux-riscv@lists.infradead.org" Sender: "linux-riscv" Errors-To: linux-riscv-bounces+patchwork-linux-riscv=patchwork.kernel.org@lists.infradead.org Add myself as maintainer for KVM RISC-V and Atish as designated reviewer. Signed-off-by: Atish Patra Signed-off-by: Anup Patel Acked-by: Paolo Bonzini Reviewed-by: Paolo Bonzini Reviewed-by: Alexander Graf --- MAINTAINERS | 10 ++++++++++ 1 file changed, 10 insertions(+) diff --git a/MAINTAINERS b/MAINTAINERS index 296de2b51c83..67f6cb317866 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -8980,6 +8980,16 @@ F: arch/powerpc/include/asm/kvm* F: arch/powerpc/kvm/ F: arch/powerpc/kernel/kvm* +KERNEL VIRTUAL MACHINE FOR RISC-V (KVM/riscv) +M: Anup Patel +R: Atish Patra +L: kvm@vger.kernel.org +T: git git://github.com/kvm-riscv/linux.git +S: Maintained +F: arch/riscv/include/uapi/asm/kvm* +F: arch/riscv/include/asm/kvm* +F: arch/riscv/kvm/ + KERNEL VIRTUAL MACHINE for s390 (KVM/s390) M: Christian Borntraeger M: Janosch Frank