From patchwork Wed Sep 12 16:07:17 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Jonathan Cameron X-Patchwork-Id: 10597979 X-Patchwork-Delegate: herbert@gondor.apana.org.au Return-Path: Received: from mail.wl.linuxfoundation.org (pdx-wl-mail.web.codeaurora.org [172.30.200.125]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id 4818D14BD for ; Wed, 12 Sep 2018 16:08:00 +0000 (UTC) Received: from mail.wl.linuxfoundation.org (localhost [127.0.0.1]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id 39AA32621B for ; Wed, 12 Sep 2018 16:08:00 +0000 (UTC) Received: by mail.wl.linuxfoundation.org (Postfix, from userid 486) id 2E2192A6D4; Wed, 12 Sep 2018 16:08:00 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on pdx-wl-mail.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-7.9 required=2.0 tests=BAYES_00,MAILING_LIST_MULTI, RCVD_IN_DNSWL_HI autolearn=ham version=3.3.1 Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id CEED32A6CF for ; Wed, 12 Sep 2018 16:07:59 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1726839AbeILVNJ (ORCPT ); Wed, 12 Sep 2018 17:13:09 -0400 Received: from szxga05-in.huawei.com ([45.249.212.191]:11694 "EHLO huawei.com" rhost-flags-OK-OK-OK-FAIL) by vger.kernel.org with ESMTP id S1726673AbeILVNJ (ORCPT ); Wed, 12 Sep 2018 17:13:09 -0400 Received: from DGGEMS405-HUB.china.huawei.com (unknown [172.30.72.60]) by Forcepoint Email with ESMTP id 89EB0DFD06D0A; Thu, 13 Sep 2018 00:07:54 +0800 (CST) Received: from j00421895-HPW10.china.huawei.com (10.202.226.46) by DGGEMS405-HUB.china.huawei.com (10.3.19.205) with Microsoft SMTP Server id 14.3.399.0; Thu, 13 Sep 2018 00:07:49 +0800 From: Jonathan Cameron To: , Rob Herring CC: , xuwei , , Jonathan Cameron Subject: [PATCH 1/2] dt-bindings: crypto: hip07-sec, drop incorrect commas Date: Wed, 12 Sep 2018 17:07:17 +0100 Message-ID: <20180912160718.3324-2-Jonathan.Cameron@huawei.com> X-Mailer: git-send-email 2.17.0.windows.1 MIME-Version: 1.0 X-Originating-IP: [10.202.226.46] X-CFilter-Loop: Reflected Sender: linux-crypto-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-crypto@vger.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP There should not be a comma in the address used for the instance so drop them. This is a left over from a review of the final version before Herbert Xu picked the series up. Reported-by: Rob Herring Signed-off-by: Jonathan Cameron Fixes: 8f026dc887fe ("dt-bindings: Add bidnings for Hisilicon SEC crypto accelerators") --- .../devicetree/bindings/crypto/hisilicon,hip07-sec.txt | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/Documentation/devicetree/bindings/crypto/hisilicon,hip07-sec.txt b/Documentation/devicetree/bindings/crypto/hisilicon,hip07-sec.txt index 78d2db9d4de5..d28fd1af01b4 100644 --- a/Documentation/devicetree/bindings/crypto/hisilicon,hip07-sec.txt +++ b/Documentation/devicetree/bindings/crypto/hisilicon,hip07-sec.txt @@ -24,7 +24,7 @@ Optional properties: Example: -p1_sec_a: crypto@400,d2000000 { +p1_sec_a: crypto@400d2000000 { compatible = "hisilicon,hip07-sec"; reg = <0x400 0xd0000000 0x0 0x10000 0x400 0xd2000000 0x0 0x10000 From patchwork Wed Sep 12 16:07:18 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Jonathan Cameron X-Patchwork-Id: 10597981 X-Patchwork-Delegate: herbert@gondor.apana.org.au Return-Path: Received: from mail.wl.linuxfoundation.org (pdx-wl-mail.web.codeaurora.org [172.30.200.125]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id C55FC921 for ; Wed, 12 Sep 2018 16:08:11 +0000 (UTC) Received: from mail.wl.linuxfoundation.org (localhost [127.0.0.1]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id B69F62A6DB for ; Wed, 12 Sep 2018 16:08:11 +0000 (UTC) Received: by mail.wl.linuxfoundation.org (Postfix, from userid 486) id AB01C2A6ED; Wed, 12 Sep 2018 16:08:11 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on pdx-wl-mail.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-7.9 required=2.0 tests=BAYES_00,MAILING_LIST_MULTI, RCVD_IN_DNSWL_HI autolearn=ham version=3.3.1 Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id 429E52A6DB for ; Wed, 12 Sep 2018 16:08:11 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1727772AbeILVNP (ORCPT ); Wed, 12 Sep 2018 17:13:15 -0400 Received: from szxga07-in.huawei.com ([45.249.212.35]:46216 "EHLO huawei.com" rhost-flags-OK-OK-OK-FAIL) by vger.kernel.org with ESMTP id S1726800AbeILVNO (ORCPT ); Wed, 12 Sep 2018 17:13:14 -0400 Received: from DGGEMS405-HUB.china.huawei.com (unknown [172.30.72.58]) by Forcepoint Email with ESMTP id DA376B9D01F3C; Thu, 13 Sep 2018 00:07:59 +0800 (CST) Received: from j00421895-HPW10.china.huawei.com (10.202.226.46) by DGGEMS405-HUB.china.huawei.com (10.3.19.205) with Microsoft SMTP Server id 14.3.399.0; Thu, 13 Sep 2018 00:07:51 +0800 From: Jonathan Cameron To: , Rob Herring CC: , xuwei , , Jonathan Cameron Subject: [PATCH 2/2] arm64: dts: hisilicon hip07: drop commas from @address node names Date: Wed, 12 Sep 2018 17:07:18 +0100 Message-ID: <20180912160718.3324-3-Jonathan.Cameron@huawei.com> X-Mailer: git-send-email 2.17.0.windows.1 In-Reply-To: <20180912160718.3324-2-Jonathan.Cameron@huawei.com> References: <20180912160718.3324-2-Jonathan.Cameron@huawei.com> MIME-Version: 1.0 X-Originating-IP: [10.202.226.46] X-CFilter-Loop: Reflected Sender: linux-crypto-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-crypto@vger.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP Reported-by: Rob Herring Signed-off-by: Jonathan Cameron Fixes: e4a1f7858ab8 ("arm64: dts: hisi: add SEC crypto accelerator nodes for hip07 SoC") --- arch/arm64/boot/dts/hisilicon/hip07.dtsi | 28 ++++++++++++------------ 1 file changed, 14 insertions(+), 14 deletions(-) diff --git a/arch/arm64/boot/dts/hisilicon/hip07.dtsi b/arch/arm64/boot/dts/hisilicon/hip07.dtsi index c33adefc3061..bc0113445655 100644 --- a/arch/arm64/boot/dts/hisilicon/hip07.dtsi +++ b/arch/arm64/boot/dts/hisilicon/hip07.dtsi @@ -949,35 +949,35 @@ reg = <0x0 0xc6000000 0x0 0x40000>; }; - p0_its_dsa_b: interrupt-controller@8,c6000000 { + p0_its_dsa_b: interrupt-controller@8c6000000 { compatible = "arm,gic-v3-its"; msi-controller; #msi-cells = <1>; reg = <0x8 0xc6000000 0x0 0x40000>; }; - p1_its_peri_a: interrupt-controller@400,4c000000 { + p1_its_peri_a: interrupt-controller@4004c000000 { compatible = "arm,gic-v3-its"; msi-controller; #msi-cells = <1>; reg = <0x400 0x4c000000 0x0 0x40000>; }; - p1_its_peri_b: interrupt-controller@400,6c000000 { + p1_its_peri_b: interrupt-controller@4006c000000 { compatible = "arm,gic-v3-its"; msi-controller; #msi-cells = <1>; reg = <0x400 0x6c000000 0x0 0x40000>; }; - p1_its_dsa_a: interrupt-controller@400,c6000000 { + p1_its_dsa_a: interrupt-controller@400c6000000 { compatible = "arm,gic-v3-its"; msi-controller; #msi-cells = <1>; reg = <0x400 0xc6000000 0x0 0x40000>; }; - p1_its_dsa_b: interrupt-controller@408,c6000000 { + p1_its_dsa_b: interrupt-controller@408c6000000 { compatible = "arm,gic-v3-its"; msi-controller; #msi-cells = <1>; @@ -1066,7 +1066,7 @@ num-pins = <3>; }; }; - p0_mbigen_alg_b:interrupt-controller@8,d0080000 { + p0_mbigen_alg_b:interrupt-controller@8d0080000 { compatible = "hisilicon,mbigen-v2"; reg = <0x8 0xd0080000 0x0 0x10000>; @@ -1083,7 +1083,7 @@ num-pins = <3>; }; }; - p1_mbigen_alg_a:interrupt-controller@400,d0080000 { + p1_mbigen_alg_a:interrupt-controller@400d0080000 { compatible = "hisilicon,mbigen-v2"; reg = <0x400 0xd0080000 0x0 0x10000>; @@ -1100,7 +1100,7 @@ num-pins = <3>; }; }; - p1_mbigen_alg_b:interrupt-controller@408,d0080000 { + p1_mbigen_alg_b:interrupt-controller@408d0080000 { compatible = "hisilicon,mbigen-v2"; reg = <0x408 0xd0080000 0x0 0x10000>; @@ -1187,7 +1187,7 @@ hisilicon,broken-prefetch-cmd; /* smmu-cb-memtype = <0x0 0x1>;*/ }; - p0_smmu_alg_b: smmu_alg@8,d0040000 { + p0_smmu_alg_b: smmu_alg@8d0040000 { compatible = "arm,smmu-v3"; reg = <0x8 0xd0040000 0x0 0x20000>; interrupt-parent = <&p0_mbigen_smmu_alg_b>; @@ -1200,7 +1200,7 @@ hisilicon,broken-prefetch-cmd; /* smmu-cb-memtype = <0x0 0x1>;*/ }; - p1_smmu_alg_a: smmu_alg@400,d0040000 { + p1_smmu_alg_a: smmu_alg@400d0040000 { compatible = "arm,smmu-v3"; reg = <0x400 0xd0040000 0x0 0x20000>; interrupt-parent = <&p1_mbigen_smmu_alg_a>; @@ -1213,7 +1213,7 @@ hisilicon,broken-prefetch-cmd; /* smmu-cb-memtype = <0x0 0x1>;*/ }; - p1_smmu_alg_b: smmu_alg@408,d0040000 { + p1_smmu_alg_b: smmu_alg@408d0040000 { compatible = "arm,smmu-v3"; reg = <0x408 0xd0040000 0x0 0x20000>; interrupt-parent = <&p1_mbigen_smmu_alg_b>; @@ -1763,7 +1763,7 @@ <605 1>, <606 4>, <607 1>, <608 4>; }; - p0_sec_b: crypto@8,d2000000 { + p0_sec_b: crypto@8d2000000 { compatible = "hisilicon,hip07-sec"; reg = <0x8 0xd0000000 0x0 0x10000 0x8 0xd2000000 0x0 0x10000 @@ -1804,7 +1804,7 @@ <605 1>, <606 4>, <607 1>, <608 4>; }; - p1_sec_a: crypto@400,d2000000 { + p1_sec_a: crypto@400d2000000 { compatible = "hisilicon,hip07-sec"; reg = <0x400 0xd0000000 0x0 0x10000 0x400 0xd2000000 0x0 0x10000 @@ -1845,7 +1845,7 @@ <605 1>, <606 4>, <607 1>, <608 4>; }; - p1_sec_b: crypto@408,d2000000 { + p1_sec_b: crypto@408d2000000 { compatible = "hisilicon,hip07-sec"; reg = <0x408 0xd0000000 0x0 0x10000 0x408 0xd2000000 0x0 0x10000