From patchwork Wed Sep 12 16:11:16 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Alexandre Belloni X-Patchwork-Id: 10598051 Return-Path: Received: from mail.wl.linuxfoundation.org (pdx-wl-mail.web.codeaurora.org [172.30.200.125]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id C90211575 for ; Wed, 12 Sep 2018 16:32:09 +0000 (UTC) Received: from mail.wl.linuxfoundation.org (localhost [127.0.0.1]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id B7E452A7C1 for ; Wed, 12 Sep 2018 16:32:09 +0000 (UTC) Received: by mail.wl.linuxfoundation.org (Postfix, from userid 486) id ABB872A7D5; Wed, 12 Sep 2018 16:32:09 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on pdx-wl-mail.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-2.9 required=2.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,MAILING_LIST_MULTI,RCVD_IN_DNSWL_NONE,UPPERCASE_50_75 autolearn=ham version=3.3.1 Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.wl.linuxfoundation.org (Postfix) with ESMTPS id 170CB2A7C1 for ; Wed, 12 Sep 2018 16:32:08 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=bombadil.20170209; h=Sender: Content-Transfer-Encoding:Content-Type:Cc:List-Subscribe:List-Help:List-Post: List-Archive:List-Unsubscribe:List-Id:MIME-Version:References:In-Reply-To: Message-Id:Date:Subject:To:From:Reply-To:Content-ID:Content-Description: Resent-Date:Resent-From:Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID: List-Owner; bh=KmpxaIwMPqzH7axIa1MDRsnpKnxmAVNUDUbN7lf//bQ=; b=Iu0/qQPtDc1Ybl TbQwRDSWAb4TPK77WstwCNeyiZ/i8Ht3/XLX8jbWEGo2QJEpJDgtIEsMWCzwdyg2q0zfJVQ0dGEHK 0m2AEfupgmb8jkAaQ8O09WiBuqNPcJp2v/i8YqEclyMxxN1k9fb0IMEIavyt6DWZgORGrfGTQ2AsD rJJv97Th8O1iuB7xFDe+eI60rzjShCLXZ5l5J4p7YAgmZtpfZSoKLlEKwW6wzQHjPiS2fhdxE49On tCqHSZ90OHoNi3DYkHyISKEFGUB2ntMpN1zCYszA2LYZurjUJNkBbaYVeroLeEY7nsJMW7zF0ORQw ttSKI8o4FjxFXV7u9uAQ==; Received: from localhost ([127.0.0.1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.90_1 #2 (Red Hat Linux)) id 1g083a-0007TP-WD; Wed, 12 Sep 2018 16:31:59 +0000 Received: from casper.infradead.org ([2001:8b0:10b:1236::1]) by bombadil.infradead.org with esmtps (Exim 4.90_1 #2 (Red Hat Linux)) id 1g07yS-0003Xt-Ue for linux-arm-kernel@bombadil.infradead.org; Wed, 12 Sep 2018 16:26:41 +0000 DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=infradead.org; s=casper.20170209; h=Content-Transfer-Encoding:MIME-Version: References:In-Reply-To:Message-Id:Date:Subject:Cc:To:From:Sender:Reply-To: Content-Type:Content-ID:Content-Description:Resent-Date:Resent-From: Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID:List-Id:List-Help: List-Unsubscribe:List-Subscribe:List-Post:List-Owner:List-Archive; bh=ek6bqP4zAm3O8cS6ntkmkSY1s1puVbhZ8b1oIfdwOSU=; b=S925PL5wchUyrQi6WoEHb/Yqp3 qJYpYkmWXazgo2Suh5EI1IJDgsA+1RNYEyRvTYMlvm3a7DKKc5oWOSojR2QSN+hK+y8u+7bI7WhtD wozOEPCtx1dmkbxSv7THga8f0+LObjZktP/zSP6Yl+J0sKOk77nCC2Ik6KxlZQSEHuuTFmaxTGJGS tIsdzR6bU79U+fSBoFnK0nmLnKgNrFSSq46lI/rZhWahv18DToZGAnp/+i/9uRjxS6yzQWrmr0WhR XKbuKLhotxBL0pRn5lyzOhrzi3FBwADyuFh+lCheGA5UbA0PhdRYPGe40Yr0goTD5UmiZEPQtxihq +n9gY5JA==; Received: from mail.bootlin.com ([62.4.15.54]) by casper.infradead.org with esmtp (Exim 4.90_1 #2 (Red Hat Linux)) id 1g07jr-00080T-Nn for linux-arm-kernel@lists.infradead.org; Wed, 12 Sep 2018 16:11:39 +0000 Received: by mail.bootlin.com (Postfix, from userid 110) id F019820799; Wed, 12 Sep 2018 18:11:24 +0200 (CEST) Received: from localhost (242.171.71.37.rev.sfr.net [37.71.171.242]) by mail.bootlin.com (Postfix) with ESMTPSA id C05EC2071D; Wed, 12 Sep 2018 18:11:24 +0200 (CEST) From: Alexandre Belloni To: Daniel Lezcano Subject: [PATCH v6 1/7] ARM: at91: add TCB registers definitions Date: Wed, 12 Sep 2018 18:11:16 +0200 Message-Id: <20180912161122.7717-2-alexandre.belloni@bootlin.com> X-Mailer: git-send-email 2.19.0.rc2 In-Reply-To: <20180912161122.7717-1-alexandre.belloni@bootlin.com> References: <20180912161122.7717-1-alexandre.belloni@bootlin.com> MIME-Version: 1.0 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20180912_171135_999184_81FA1ED5 X-CRM114-Status: GOOD ( 15.37 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Alexandre Belloni , Alexander Dahl , Sebastian Andrzej Siewior , linux-kernel@vger.kernel.org, Thomas Gleixner , linux-arm-kernel@lists.infradead.org Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+patchwork-linux-arm=patchwork.kernel.org@lists.infradead.org X-Virus-Scanned: ClamAV using ClamSMTP Add registers and bits definitions for the timer counter blocks found on Atmel ARM SoCs. Tested-by: Alexander Dahl Tested-by: Andras Szemzo Signed-off-by: Alexandre Belloni --- include/soc/at91/atmel_tcb.h | 183 +++++++++++++++++++++++++++++++++++ 1 file changed, 183 insertions(+) create mode 100644 include/soc/at91/atmel_tcb.h diff --git a/include/soc/at91/atmel_tcb.h b/include/soc/at91/atmel_tcb.h new file mode 100644 index 000000000000..657e234b1483 --- /dev/null +++ b/include/soc/at91/atmel_tcb.h @@ -0,0 +1,183 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +/* Copyright (C) 2018 Microchip */ + +#ifndef __SOC_ATMEL_TCB_H +#define __SOC_ATMEL_TCB_H + +/* Channel registers */ +#define ATMEL_TC_COFFS(c) ((c) * 0x40) +#define ATMEL_TC_CCR(c) ATMEL_TC_COFFS(c) +#define ATMEL_TC_CMR(c) (ATMEL_TC_COFFS(c) + 0x4) +#define ATMEL_TC_SMMR(c) (ATMEL_TC_COFFS(c) + 0x8) +#define ATMEL_TC_RAB(c) (ATMEL_TC_COFFS(c) + 0xc) +#define ATMEL_TC_CV(c) (ATMEL_TC_COFFS(c) + 0x10) +#define ATMEL_TC_RA(c) (ATMEL_TC_COFFS(c) + 0x14) +#define ATMEL_TC_RB(c) (ATMEL_TC_COFFS(c) + 0x18) +#define ATMEL_TC_RC(c) (ATMEL_TC_COFFS(c) + 0x1c) +#define ATMEL_TC_SR(c) (ATMEL_TC_COFFS(c) + 0x20) +#define ATMEL_TC_IER(c) (ATMEL_TC_COFFS(c) + 0x24) +#define ATMEL_TC_IDR(c) (ATMEL_TC_COFFS(c) + 0x28) +#define ATMEL_TC_IMR(c) (ATMEL_TC_COFFS(c) + 0x2c) +#define ATMEL_TC_EMR(c) (ATMEL_TC_COFFS(c) + 0x30) + +/* Block registers */ +#define ATMEL_TC_BCR 0xc0 +#define ATMEL_TC_BMR 0xc4 +#define ATMEL_TC_QIER 0xc8 +#define ATMEL_TC_QIDR 0xcc +#define ATMEL_TC_QIMR 0xd0 +#define ATMEL_TC_QISR 0xd4 +#define ATMEL_TC_FMR 0xd8 +#define ATMEL_TC_WPMR 0xe4 + +/* CCR fields */ +#define ATMEL_TC_CCR_CLKEN BIT(0) +#define ATMEL_TC_CCR_CLKDIS BIT(1) +#define ATMEL_TC_CCR_SWTRG BIT(2) + +/* Common CMR fields */ +#define ATMEL_TC_CMR_TCLKS_MSK GENMASK(2, 0) +#define ATMEL_TC_CMR_TCLK(x) (x) +#define ATMEL_TC_CMR_XC(x) ((x) + 5) +#define ATMEL_TC_CMR_CLKI BIT(3) +#define ATMEL_TC_CMR_BURST_MSK GENMASK(5, 4) +#define ATMEL_TC_CMR_BURST_XC(x) (((x) + 1) << 4) +#define ATMEL_TC_CMR_WAVE BIT(15) + +/* Capture mode CMR fields */ +#define ATMEL_TC_CMR_LDBSTOP BIT(6) +#define ATMEL_TC_CMR_LDBDIS BIT(7) +#define ATMEL_TC_CMR_ETRGEDG_MSK GENMASK(9, 8) +#define ATMEL_TC_CMR_ETRGEDG_NONE (0 << 8) +#define ATMEL_TC_CMR_ETRGEDG_RISING (1 << 8) +#define ATMEL_TC_CMR_ETRGEDG_FALLING (2 << 8) +#define ATMEL_TC_CMR_ETRGEDG_BOTH (3 << 8) +#define ATMEL_TC_CMR_ABETRG BIT(10) +#define ATMEL_TC_CMR_CPCTRG BIT(14) +#define ATMEL_TC_CMR_LDRA_MSK GENMASK(17, 16) +#define ATMEL_TC_CMR_LDRA_NONE (0 << 16) +#define ATMEL_TC_CMR_LDRA_RISING (1 << 16) +#define ATMEL_TC_CMR_LDRA_FALLING (2 << 16) +#define ATMEL_TC_CMR_LDRA_BOTH (3 << 16) +#define ATMEL_TC_CMR_LDRB_MSK GENMASK(19, 18) +#define ATMEL_TC_CMR_LDRB_NONE (0 << 18) +#define ATMEL_TC_CMR_LDRB_RISING (1 << 18) +#define ATMEL_TC_CMR_LDRB_FALLING (2 << 18) +#define ATMEL_TC_CMR_LDRB_BOTH (3 << 18) +#define ATMEL_TC_CMR_SBSMPLR_MSK GENMASK(22, 20) +#define ATMEL_TC_CMR_SBSMPLR(x) ((x) << 20) + +/* Waveform mode CMR fields */ +#define ATMEL_TC_CMR_CPCSTOP BIT(6) +#define ATMEL_TC_CMR_CPCDIS BIT(7) +#define ATMEL_TC_CMR_EEVTEDG_MSK GENMASK(9, 8) +#define ATMEL_TC_CMR_EEVTEDG_NONE (0 << 8) +#define ATMEL_TC_CMR_EEVTEDG_RISING (1 << 8) +#define ATMEL_TC_CMR_EEVTEDG_FALLING (2 << 8) +#define ATMEL_TC_CMR_EEVTEDG_BOTH (3 << 8) +#define ATMEL_TC_CMR_EEVT_MSK GENMASK(11, 10) +#define ATMEL_TC_CMR_EEVT_XC(x) (((x) + 1) << 10) +#define ATMEL_TC_CMR_ENETRG BIT(12) +#define ATMEL_TC_CMR_WAVESEL_MSK GENMASK(14, 13) +#define ATMEL_TC_CMR_WAVESEL_UP (0 << 13) +#define ATMEL_TC_CMR_WAVESEL_UPDOWN (1 << 13) +#define ATMEL_TC_CMR_WAVESEL_UPRC (2 << 13) +#define ATMEL_TC_CMR_WAVESEL_UPDOWNRC (3 << 13) +#define ATMEL_TC_CMR_ACPA_MSK GENMASK(17, 16) +#define ATMEL_TC_CMR_ACPA(a) (ATMEL_TC_CMR_ACTION_##a << 16) +#define ATMEL_TC_CMR_ACPC_MSK GENMASK(19, 18) +#define ATMEL_TC_CMR_ACPC(a) (ATMEL_TC_CMR_ACTION_##a << 18) +#define ATMEL_TC_CMR_AEEVT_MSK GENMASK(21, 20) +#define ATMEL_TC_CMR_AEEVT(a) (ATMEL_TC_CMR_ACTION_##a << 20) +#define ATMEL_TC_CMR_ASWTRG_MSK GENMASK(23, 22) +#define ATMEL_TC_CMR_ASWTRG(a) (ATMEL_TC_CMR_ACTION_##a << 22) +#define ATMEL_TC_CMR_BCPB_MSK GENMASK(25, 24) +#define ATMEL_TC_CMR_BCPB(a) (ATMEL_TC_CMR_ACTION_##a << 24) +#define ATMEL_TC_CMR_BCPC_MSK GENMASK(27, 26) +#define ATMEL_TC_CMR_BCPC(a) (ATMEL_TC_CMR_ACTION_##a << 26) +#define ATMEL_TC_CMR_BEEVT_MSK GENMASK(29, 28) +#define ATMEL_TC_CMR_BEEVT(a) (ATMEL_TC_CMR_ACTION_##a << 28) +#define ATMEL_TC_CMR_BSWTRG_MSK GENMASK(31, 30) +#define ATMEL_TC_CMR_BSWTRG(a) (ATMEL_TC_CMR_ACTION_##a << 30) +#define ATMEL_TC_CMR_ACTION_NONE 0 +#define ATMEL_TC_CMR_ACTION_SET 1 +#define ATMEL_TC_CMR_ACTION_CLEAR 2 +#define ATMEL_TC_CMR_ACTION_TOGGLE 3 + +/* SMMR fields */ +#define ATMEL_TC_SMMR_GCEN BIT(0) +#define ATMEL_TC_SMMR_DOWN BIT(1) + +/* SR/IER/IDR/IMR fields */ +#define ATMEL_TC_COVFS BIT(0) +#define ATMEL_TC_LOVRS BIT(1) +#define ATMEL_TC_CPAS BIT(2) +#define ATMEL_TC_CPBS BIT(3) +#define ATMEL_TC_CPCS BIT(4) +#define ATMEL_TC_LDRAS BIT(5) +#define ATMEL_TC_LDRBS BIT(6) +#define ATMEL_TC_ETRGS BIT(7) +#define ATMEL_TC_CLKSTA BIT(16) +#define ATMEL_TC_MTIOA BIT(17) +#define ATMEL_TC_MTIOB BIT(18) + +/* EMR fields */ +#define ATMEL_TC_EMR_TRIGSRCA_MSK GENMASK(1, 0) +#define ATMEL_TC_EMR_TRIGSRCA_TIOA 0 +#define ATMEL_TC_EMR_TRIGSRCA_PWMX 1 +#define ATMEL_TC_EMR_TRIGSRCB_MSK GENMASK(5, 4) +#define ATMEL_TC_EMR_TRIGSRCB_TIOB (0 << 4) +#define ATMEL_TC_EMR_TRIGSRCB_PWM (1 << 4) +#define ATMEL_TC_EMR_NOCLKDIV BIT(8) + +/* BCR fields */ +#define ATMEL_TC_BCR_SYNC BIT(0) + +/* BMR fields */ +#define ATMEL_TC_BMR_TCXC_MSK(c) GENMASK(((c) * 2) + 1, (c) * 2) +#define ATMEL_TC_BMR_TCXC(x, c) ((x) << (2 * (c))) +#define ATMEL_TC_BMR_QDEN BIT(8) +#define ATMEL_TC_BMR_POSEN BIT(9) +#define ATMEL_TC_BMR_SPEEDEN BIT(10) +#define ATMEL_TC_BMR_QDTRANS BIT(11) +#define ATMEL_TC_BMR_EDGPHA BIT(12) +#define ATMEL_TC_BMR_INVA BIT(13) +#define ATMEL_TC_BMR_INVB BIT(14) +#define ATMEL_TC_BMR_INVIDX BIT(15) +#define ATMEL_TC_BMR_SWAP BIT(16) +#define ATMEL_TC_BMR_IDXPHB BIT(17) +#define ATMEL_TC_BMR_AUTOC BIT(18) +#define ATMEL_TC_MAXFILT_MSK GENMASK(25, 20) +#define ATMEL_TC_MAXFILT(x) (((x) - 1) << 20) +#define ATMEL_TC_MAXCMP_MSK GENMASK(29, 26) +#define ATMEL_TC_MAXCMP(x) ((x) << 26) + +/* QEDC fields */ +#define ATMEL_TC_QEDC_IDX BIT(0) +#define ATMEL_TC_QEDC_DIRCHG BIT(1) +#define ATMEL_TC_QEDC_QERR BIT(2) +#define ATMEL_TC_QEDC_MPE BIT(3) +#define ATMEL_TC_QEDC_DIR BIT(8) + +/* FMR fields */ +#define ATMEL_TC_FMR_ENCF(x) BIT(x) + +/* WPMR fields */ +#define ATMEL_TC_WPMR_WPKEY (0x54494d << 8) +#define ATMEL_TC_WPMR_WPEN BIT(0) + +static const u8 atmel_tc_divisors[5] = { 2, 8, 32, 128, 0, }; + +static const struct of_device_id atmel_tcb_dt_ids[] = { + { + .compatible = "atmel,at91rm9200-tcb", + .data = (void *)16, + }, { + .compatible = "atmel,at91sam9x5-tcb", + .data = (void *)32, + }, { + /* sentinel */ + } +}; + +#endif /* __SOC_ATMEL_TCB_H */ From patchwork Wed Sep 12 16:11:17 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 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2.19.0.rc2 In-Reply-To: <20180912161122.7717-1-alexandre.belloni@bootlin.com> References: <20180912161122.7717-1-alexandre.belloni@bootlin.com> MIME-Version: 1.0 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20180912_121137_958597_7A2EA5C4 X-CRM114-Status: GOOD ( 33.33 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Alexandre Belloni , Alexander Dahl , Sebastian Andrzej Siewior , linux-kernel@vger.kernel.org, Thomas Gleixner , linux-arm-kernel@lists.infradead.org Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+patchwork-linux-arm=patchwork.kernel.org@lists.infradead.org X-Virus-Scanned: ClamAV using ClamSMTP Add a driver for the Atmel Timer Counter Blocks. This driver provides a clocksource and two clockevent devices. One of the clockevent device is linked to the clocksource counter and so it will run at the same frequency. This will be used when there is only on TCB channel available for timers. The other clockevent device runs on a separate TCB channel when available. This driver uses regmap and syscon to be able to probe early in the boot and avoid having to switch on the TCB clocksource later. Using regmap also means that unused TCB channels may be used by other drivers (PWM for example). read/writel are still used to access channel specific registers to avoid the performance impact of regmap (mainly locking). Tested-by: Alexander Dahl Tested-by: Andras Szemzo Signed-off-by: Alexandre Belloni --- drivers/clocksource/Kconfig | 8 + drivers/clocksource/Makefile | 3 +- drivers/clocksource/timer-atmel-tcb.c | 409 ++++++++++++++++++++++++++ 3 files changed, 419 insertions(+), 1 deletion(-) create mode 100644 drivers/clocksource/timer-atmel-tcb.c diff --git a/drivers/clocksource/Kconfig b/drivers/clocksource/Kconfig index a11f4ba98b05..8c7324e409f6 100644 --- a/drivers/clocksource/Kconfig +++ b/drivers/clocksource/Kconfig @@ -403,6 +403,14 @@ config ATMEL_ST help Support for the Atmel ST timer. +config ATMEL_ARM_TCB_CLKSRC + bool "Microchip ARM TC Block" if COMPILE_TEST + select REGMAP_MMIO + depends on GENERIC_CLOCKEVENTS + help + This enables build of clocksource and clockevent driver for + the integrated Timer Counter Blocks in Microchip ARM SoCs. + config CLKSRC_EXYNOS_MCT bool "Exynos multi core timer driver" if COMPILE_TEST depends on ARM || ARM64 diff --git a/drivers/clocksource/Makefile b/drivers/clocksource/Makefile index db51b2427e8a..0df9384a1230 100644 --- a/drivers/clocksource/Makefile +++ b/drivers/clocksource/Makefile @@ -3,7 +3,8 @@ obj-$(CONFIG_TIMER_OF) += timer-of.o obj-$(CONFIG_TIMER_PROBE) += timer-probe.o obj-$(CONFIG_ATMEL_PIT) += timer-atmel-pit.o obj-$(CONFIG_ATMEL_ST) += timer-atmel-st.o -obj-$(CONFIG_ATMEL_TCB_CLKSRC) += tcb_clksrc.o +obj-$(CONFIG_ATMEL_TCB_CLKSRC) += tcb_clksrc.o +obj-$(CONFIG_ATMEL_ARM_TCB_CLKSRC) += timer-atmel-tcb.o obj-$(CONFIG_X86_PM_TIMER) += acpi_pm.o obj-$(CONFIG_SCx200HR_TIMER) += scx200_hrt.o obj-$(CONFIG_CS5535_CLOCK_EVENT_SRC) += cs5535-clockevt.o diff --git a/drivers/clocksource/timer-atmel-tcb.c b/drivers/clocksource/timer-atmel-tcb.c new file mode 100644 index 000000000000..3064881af963 --- /dev/null +++ b/drivers/clocksource/timer-atmel-tcb.c @@ -0,0 +1,409 @@ +// SPDX-License-Identifier: GPL-2.0 +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +struct atmel_tcb_clksrc { + struct clocksource clksrc; + struct clock_event_device clkevt; + struct regmap *regmap; + void __iomem *base; + struct clk *clk[2]; + char name[20]; + int channels[2]; + int bits; + int irq; + struct { + u32 cmr; + u32 imr; + u32 rc; + bool clken; + } cache[2]; + u32 bmr_cache; + bool registered; + bool clk_enabled; +}; + +static struct atmel_tcb_clksrc tc; + +static struct clk *tcb_clk_get(struct device_node *node, int channel) +{ + struct clk *clk; + char clk_name[] = "t0_clk"; + + clk_name[1] += channel; + clk = of_clk_get_by_name(node->parent, clk_name); + if (!IS_ERR(clk)) + return clk; + + return of_clk_get_by_name(node->parent, "t0_clk"); +} + +/* + * Clocksource and clockevent using the same channel(s) + */ +static u64 tc_get_cycles(struct clocksource *cs) +{ + u32 lower, upper; + + do { + upper = readl_relaxed(tc.base + ATMEL_TC_CV(tc.channels[1])); + lower = readl_relaxed(tc.base + ATMEL_TC_CV(tc.channels[0])); + } while (upper != readl_relaxed(tc.base + ATMEL_TC_CV(tc.channels[1]))); + + return (upper << 16) | lower; +} + +static u64 tc_get_cycles32(struct clocksource *cs) +{ + return readl_relaxed(tc.base + ATMEL_TC_CV(tc.channels[0])); +} + +static u64 notrace tc_sched_clock_read(void) +{ + return tc_get_cycles(&tc.clksrc); +} + +static u64 notrace tc_sched_clock_read32(void) +{ + return tc_get_cycles32(&tc.clksrc); +} + +static int tcb_clkevt_next_event(unsigned long delta, + struct clock_event_device *d) +{ + u32 old, next, cur; + + old = readl(tc.base + ATMEL_TC_CV(tc.channels[0])); + next = old + delta; + writel(next, tc.base + ATMEL_TC_RC(tc.channels[0])); + cur = readl(tc.base + ATMEL_TC_CV(tc.channels[0])); + + /* check whether the delta elapsed while setting the register */ + if ((next < old && cur < old && cur > next) || + (next > old && (cur < old || cur > next))) { + /* + * Clear the CPCS bit in the status register to avoid + * generating a spurious interrupt next time a valid + * timer event is configured. + */ + old = readl(tc.base + ATMEL_TC_SR(tc.channels[0])); + return -ETIME; + } + + writel(ATMEL_TC_CPCS, tc.base + ATMEL_TC_IER(tc.channels[0])); + + return 0; +} + +static irqreturn_t tc_clkevt_irq(int irq, void *handle) +{ + unsigned int sr; + + sr = readl(tc.base + ATMEL_TC_SR(tc.channels[0])); + if (sr & ATMEL_TC_CPCS) { + tc.clkevt.event_handler(&tc.clkevt); + return IRQ_HANDLED; + } + + return IRQ_NONE; +} + +static int tcb_clkevt_oneshot(struct clock_event_device *dev) +{ + if (clockevent_state_oneshot(dev)) + return 0; + + /* + * Because both clockevent devices may share the same IRQ, we don't want + * the less likely one to stay requested + */ + return request_irq(tc.irq, tc_clkevt_irq, IRQF_TIMER | IRQF_SHARED, + tc.name, &tc); +} + +static int tcb_clkevt_shutdown(struct clock_event_device *dev) +{ + writel(0xff, tc.base + ATMEL_TC_IDR(tc.channels[0])); + if (tc.bits == 16) + writel(0xff, tc.base + ATMEL_TC_IDR(tc.channels[1])); + + if (!clockevent_state_detached(dev)) + free_irq(tc.irq, &tc); + + return 0; +} + +static void __init tcb_setup_dual_chan(struct atmel_tcb_clksrc *tc, + int mck_divisor_idx) +{ + /* first channel: waveform mode, input mclk/8, clock TIOA on overflow */ + writel(mck_divisor_idx /* likely divide-by-8 */ + | ATMEL_TC_CMR_WAVE + | ATMEL_TC_CMR_WAVESEL_UP /* free-run */ + | ATMEL_TC_CMR_ACPA(SET) /* TIOA rises at 0 */ + | ATMEL_TC_CMR_ACPC(CLEAR), /* (duty cycle 50%) */ + tc->base + ATMEL_TC_CMR(tc->channels[0])); + writel(0x0000, tc->base + ATMEL_TC_RA(tc->channels[0])); + writel(0x8000, tc->base + ATMEL_TC_RC(tc->channels[0])); + writel(0xff, tc->base + ATMEL_TC_IDR(tc->channels[0])); /* no irqs */ + writel(ATMEL_TC_CCR_CLKEN, tc->base + ATMEL_TC_CCR(tc->channels[0])); + + /* second channel: waveform mode, input TIOA */ + writel(ATMEL_TC_CMR_XC(tc->channels[1]) /* input: TIOA */ + | ATMEL_TC_CMR_WAVE + | ATMEL_TC_CMR_WAVESEL_UP, /* free-run */ + tc->base + ATMEL_TC_CMR(tc->channels[1])); + writel(0xff, tc->base + ATMEL_TC_IDR(tc->channels[1])); /* no irqs */ + writel(ATMEL_TC_CCR_CLKEN, tc->base + ATMEL_TC_CCR(tc->channels[1])); + + /* chain both channel, we assume the previous channel */ + regmap_write(tc->regmap, ATMEL_TC_BMR, + ATMEL_TC_BMR_TCXC(1 + tc->channels[1], tc->channels[1])); + /* then reset all the timers */ + regmap_write(tc->regmap, ATMEL_TC_BCR, ATMEL_TC_BCR_SYNC); +} + +static void __init tcb_setup_single_chan(struct atmel_tcb_clksrc *tc, + int mck_divisor_idx) +{ + /* channel 0: waveform mode, input mclk/8 */ + writel(mck_divisor_idx /* likely divide-by-8 */ + | ATMEL_TC_CMR_WAVE + | ATMEL_TC_CMR_WAVESEL_UP, /* free-run */ + tc->base + ATMEL_TC_CMR(tc->channels[0])); + writel(0xff, tc->base + ATMEL_TC_IDR(tc->channels[0])); /* no irqs */ + writel(ATMEL_TC_CCR_CLKEN, tc->base + ATMEL_TC_CCR(tc->channels[0])); + + /* then reset all the timers */ + regmap_write(tc->regmap, ATMEL_TC_BCR, ATMEL_TC_BCR_SYNC); +} + +static void tc_clksrc_suspend(struct clocksource *cs) +{ + int i; + + for (i = 0; i < 1 + (tc.bits == 16); i++) { + tc.cache[i].cmr = readl(tc.base + ATMEL_TC_CMR(tc.channels[i])); + tc.cache[i].imr = readl(tc.base + ATMEL_TC_IMR(tc.channels[i])); + tc.cache[i].rc = readl(tc.base + ATMEL_TC_RC(tc.channels[i])); + tc.cache[i].clken = !!(readl(tc.base + + ATMEL_TC_SR(tc.channels[i])) & + ATMEL_TC_CLKSTA); + } + + if (tc.bits == 16) + regmap_read(tc.regmap, ATMEL_TC_BMR, &tc.bmr_cache); +} + +static void tc_clksrc_resume(struct clocksource *cs) +{ + int i; + + for (i = 0; i < 1 + (tc.bits == 16); i++) { + /* Restore registers for the channel, RA and RB are not used */ + writel(tc.cache[i].cmr, tc.base + ATMEL_TC_CMR(tc.channels[i])); + writel(tc.cache[i].rc, tc.base + ATMEL_TC_RC(tc.channels[i])); + writel(0, tc.base + ATMEL_TC_RA(tc.channels[i])); + writel(0, tc.base + ATMEL_TC_RB(tc.channels[i])); + /* Disable all the interrupts */ + writel(0xff, tc.base + ATMEL_TC_IDR(tc.channels[i])); + /* Reenable interrupts that were enabled before suspending */ + writel(tc.cache[i].imr, tc.base + ATMEL_TC_IER(tc.channels[i])); + + /* Start the clock if it was used */ + if (tc.cache[i].clken) + writel(ATMEL_TC_CCR_CLKEN, tc.base + + ATMEL_TC_CCR(tc.channels[i])); + } + + /* in case of dual channel, chain channels */ + if (tc.bits == 16) + regmap_write(tc.regmap, ATMEL_TC_BMR, tc.bmr_cache); + /* Finally, trigger all the channels*/ + regmap_write(tc.regmap, ATMEL_TC_BCR, ATMEL_TC_BCR_SYNC); +} + +static int __init tcb_clksrc_register(struct device_node *node, + struct regmap *regmap, void __iomem *base, + int channel, int channel1, int irq, + int bits) +{ + u32 rate, divided_rate = 0; + int best_divisor_idx = -1; + int i, err = -1; + u64 (*tc_sched_clock)(void); + + tc.regmap = regmap; + tc.base = base; + tc.channels[0] = channel; + tc.channels[1] = channel1; + tc.irq = irq; + tc.bits = bits; + + tc.clk[0] = tcb_clk_get(node, tc.channels[0]); + if (IS_ERR(tc.clk[0])) + return PTR_ERR(tc.clk[0]); + err = clk_prepare_enable(tc.clk[0]); + if (err) { + pr_debug("can't enable T0 clk\n"); + goto err_clk; + } + + /* How fast will we be counting? Pick something over 5 MHz. */ + rate = (u32)clk_get_rate(tc.clk[0]); + for (i = 0; i < 5; i++) { + unsigned int divisor = atmel_tc_divisors[i]; + unsigned int tmp; + + if (!divisor) + continue; + + tmp = rate / divisor; + pr_debug("TC: %u / %-3u [%d] --> %u\n", rate, divisor, i, tmp); + if (best_divisor_idx > 0) { + if (tmp < 5 * 1000 * 1000) + continue; + } + divided_rate = tmp; + best_divisor_idx = i; + } + + if (tc.bits == 32) { + tc.clksrc.read = tc_get_cycles32; + tcb_setup_single_chan(&tc, best_divisor_idx); + tc_sched_clock = tc_sched_clock_read32; + snprintf(tc.name, sizeof(tc.name), "%s:%d", + kbasename(node->parent->full_name), tc.channels[0]); + } else { + tc.clk[1] = tcb_clk_get(node, tc.channels[1]); + if (IS_ERR(tc.clk[1])) + goto err_disable_t0; + + err = clk_prepare_enable(tc.clk[1]); + if (err) { + pr_debug("can't enable T1 clk\n"); + goto err_clk1; + } + tc.clksrc.read = tc_get_cycles, + tcb_setup_dual_chan(&tc, best_divisor_idx); + tc_sched_clock = tc_sched_clock_read; + snprintf(tc.name, sizeof(tc.name), "%s:%d,%d", + kbasename(node->parent->full_name), tc.channels[0], + tc.channels[1]); + } + + pr_debug("%s at %d.%03d MHz\n", tc.name, + divided_rate / 1000000, + ((divided_rate + 500000) % 1000000) / 1000); + + tc.clksrc.name = tc.name; + tc.clksrc.suspend = tc_clksrc_suspend; + tc.clksrc.resume = tc_clksrc_resume; + tc.clksrc.rating = 200; + tc.clksrc.mask = CLOCKSOURCE_MASK(32); + tc.clksrc.flags = CLOCK_SOURCE_IS_CONTINUOUS; + + err = clocksource_register_hz(&tc.clksrc, divided_rate); + if (err) + goto err_disable_t1; + + sched_clock_register(tc_sched_clock, 32, divided_rate); + + tc.registered = true; + + /* Set up and register clockevents */ + tc.clkevt.name = tc.name; + tc.clkevt.cpumask = cpumask_of(0); + tc.clkevt.set_next_event = tcb_clkevt_next_event; + tc.clkevt.set_state_oneshot = tcb_clkevt_oneshot; + tc.clkevt.set_state_shutdown = tcb_clkevt_shutdown; + tc.clkevt.features = CLOCK_EVT_FEAT_ONESHOT; + tc.clkevt.rating = 125; + + clockevents_config_and_register(&tc.clkevt, divided_rate, 1, + BIT(tc.bits) - 1); + + return 0; + +err_disable_t1: + if (tc.bits == 16) + clk_disable_unprepare(tc.clk[1]); + +err_clk1: + if (tc.bits == 16) + clk_put(tc.clk[1]); + +err_disable_t0: + clk_disable_unprepare(tc.clk[0]); + +err_clk: + clk_put(tc.clk[0]); + + pr_err("%s: unable to register clocksource/clockevent\n", + tc.clksrc.name); + + return err; +} + +static int __init tcb_clksrc_init(struct device_node *node) +{ + const struct of_device_id *match; + struct regmap *regmap; + void __iomem *tcb_base; + u32 channel; + int bits, irq, err, chan1 = -1; + + if (tc.registered) + return -ENODEV; + + /* + * The regmap has to be used to access registers that are shared + * between channels on the same TCB but we keep direct IO access for + * the counters to avoid the impact on performance + */ + regmap = syscon_node_to_regmap(node->parent); + if (IS_ERR(regmap)) + return PTR_ERR(regmap); + + tcb_base = of_iomap(node->parent, 0); + if (!tcb_base) { + pr_err("%s +%d %s\n", __FILE__, __LINE__, __func__); + return -ENXIO; + } + + match = of_match_node(atmel_tcb_dt_ids, node->parent); + bits = (int)match->data; + + err = of_property_read_u32_index(node, "reg", 0, &channel); + if (err) + return err; + + irq = of_irq_get(node->parent, channel); + if (irq < 0) { + irq = of_irq_get(node->parent, 0); + if (irq < 0) + return irq; + } + + if (bits == 16) { + of_property_read_u32_index(node, "reg", 1, &chan1); + if (chan1 == -1) { + pr_err("%s: clocksource needs two channels\n", + node->parent->full_name); + return -EINVAL; + } + } + + return tcb_clksrc_register(node, regmap, tcb_base, channel, chan1, irq, + bits); +} +TIMER_OF_DECLARE(atmel_tcb_clksrc, "atmel,tcb-timer", tcb_clksrc_init); From patchwork Wed Sep 12 16:11:18 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Alexandre Belloni X-Patchwork-Id: 10598057 Return-Path: Received: from mail.wl.linuxfoundation.org (pdx-wl-mail.web.codeaurora.org [172.30.200.125]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id 60B661575 for ; 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bh=W9dfFI0N9alr2XmUqJw6jLE8Ix8HlFgQwmA87Nt3D9A=; b=iLRrhINtVHzTZLOj1oMEt+xjXu yFhxH0iH43UijIL81Mspu9MvHP6UeQ3umzMzZhylMv+GQDJ2iUWsu900u/YPfMAsC2hgxSrFkfgJi 9QHemem3jTm2Ul5hCPGN3yr7TiW7SiSLvb9ZfFSdsqjl3XzOFc5Oe3yrTZqhoMIBdgrZHq2tb0pKr 2vWecWPFpisDu2OxIjAsxedbfxpG5qzxMe1SFL/KIqjBxK8w49sSjcDCvOTFjT71CabwUfuZ9S8ln GviYvQFmM0Rv2vAMKXZtkNaPIMXwYpwg2tmmw+kH3G8eTSutBc7obKnFnXVH1Fgn/VumDEQeYaDb2 V+5ffGgg==; Received: from mail.bootlin.com ([62.4.15.54]) by casper.infradead.org with esmtp (Exim 4.90_1 #2 (Red Hat Linux)) id 1g07jr-00080Y-M7 for linux-arm-kernel@lists.infradead.org; Wed, 12 Sep 2018 16:11:37 +0000 Received: by mail.bootlin.com (Postfix, from userid 110) id 986152080A; Wed, 12 Sep 2018 18:11:25 +0200 (CEST) Received: from localhost (242.171.71.37.rev.sfr.net [37.71.171.242]) by mail.bootlin.com (Postfix) with ESMTPSA id 629082071D; Wed, 12 Sep 2018 18:11:25 +0200 (CEST) From: Alexandre Belloni To: Daniel Lezcano Subject: [PATCH v6 3/7] clocksource/drivers: timer-atmel-tcb: add clockevent device on separate channel Date: Wed, 12 Sep 2018 18:11:18 +0200 Message-Id: <20180912161122.7717-4-alexandre.belloni@bootlin.com> X-Mailer: git-send-email 2.19.0.rc2 In-Reply-To: <20180912161122.7717-1-alexandre.belloni@bootlin.com> References: <20180912161122.7717-1-alexandre.belloni@bootlin.com> MIME-Version: 1.0 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20180912_171135_828369_0099265C X-CRM114-Status: GOOD ( 22.34 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Alexandre Belloni , Alexander Dahl , Sebastian Andrzej Siewior , linux-kernel@vger.kernel.org, Thomas Gleixner , linux-arm-kernel@lists.infradead.org Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+patchwork-linux-arm=patchwork.kernel.org@lists.infradead.org X-Virus-Scanned: ClamAV using ClamSMTP Add an other clockevent device that uses a separate TCB channel when available. Signed-off-by: Alexandre Belloni --- drivers/clocksource/timer-atmel-tcb.c | 217 +++++++++++++++++++++++++- 1 file changed, 212 insertions(+), 5 deletions(-) diff --git a/drivers/clocksource/timer-atmel-tcb.c b/drivers/clocksource/timer-atmel-tcb.c index 3064881af963..2dd032d30fac 100644 --- a/drivers/clocksource/timer-atmel-tcb.c +++ b/drivers/clocksource/timer-atmel-tcb.c @@ -32,7 +32,7 @@ struct atmel_tcb_clksrc { bool clk_enabled; }; -static struct atmel_tcb_clksrc tc; +static struct atmel_tcb_clksrc tc, tce; static struct clk *tcb_clk_get(struct device_node *node, int channel) { @@ -47,6 +47,203 @@ static struct clk *tcb_clk_get(struct device_node *node, int channel) return of_clk_get_by_name(node->parent, "t0_clk"); } +/* + * Clockevent device using its own channel + */ + +static void tc_clkevt2_clk_disable(struct clock_event_device *d) +{ + clk_disable(tce.clk[0]); + tce.clk_enabled = false; +} + +static void tc_clkevt2_clk_enable(struct clock_event_device *d) +{ + if (tce.clk_enabled) + return; + clk_enable(tce.clk[0]); + tce.clk_enabled = true; +} + +static int tc_clkevt2_stop(struct clock_event_device *d) +{ + writel(0xff, tce.base + ATMEL_TC_IDR(tce.channels[0])); + writel(ATMEL_TC_CCR_CLKDIS, tce.base + ATMEL_TC_CCR(tce.channels[0])); + + return 0; +} + +static int tc_clkevt2_shutdown(struct clock_event_device *d) +{ + tc_clkevt2_stop(d); + if (!clockevent_state_detached(d)) + tc_clkevt2_clk_disable(d); + + return 0; +} + +/* For now, we always use the 32K clock ... this optimizes for NO_HZ, + * because using one of the divided clocks would usually mean the + * tick rate can never be less than several dozen Hz (vs 0.5 Hz). + * + * A divided clock could be good for high resolution timers, since + * 30.5 usec resolution can seem "low". + */ +static int tc_clkevt2_set_oneshot(struct clock_event_device *d) +{ + if (clockevent_state_oneshot(d) || clockevent_state_periodic(d)) + tc_clkevt2_stop(d); + + tc_clkevt2_clk_enable(d); + + /* slow clock, count up to RC, then irq and stop */ + writel(ATMEL_TC_CMR_TCLK(4) | ATMEL_TC_CMR_CPCSTOP | + ATMEL_TC_CMR_WAVE | ATMEL_TC_CMR_WAVESEL_UPRC, + tce.base + ATMEL_TC_CMR(tce.channels[0])); + writel(ATMEL_TC_CPCS, tce.base + ATMEL_TC_IER(tce.channels[0])); + + return 0; +} + +static int tc_clkevt2_set_periodic(struct clock_event_device *d) +{ + if (clockevent_state_oneshot(d) || clockevent_state_periodic(d)) + tc_clkevt2_stop(d); + + /* By not making the gentime core emulate periodic mode on top + * of oneshot, we get lower overhead and improved accuracy. + */ + tc_clkevt2_clk_enable(d); + + /* slow clock, count up to RC, then irq and restart */ + writel(ATMEL_TC_CMR_TCLK(4) | ATMEL_TC_CMR_WAVE | + ATMEL_TC_CMR_WAVESEL_UPRC, + tce.base + ATMEL_TC_CMR(tce.channels[0])); + writel((32768 + HZ / 2) / HZ, tce.base + ATMEL_TC_RC(tce.channels[0])); + + /* Enable clock and interrupts on RC compare */ + writel(ATMEL_TC_CPCS, tce.base + ATMEL_TC_IER(tce.channels[0])); + writel(ATMEL_TC_CCR_CLKEN | ATMEL_TC_CCR_SWTRG, + tce.base + ATMEL_TC_CCR(tce.channels[0])); + + return 0; +} + +static int tc_clkevt2_next_event(unsigned long delta, + struct clock_event_device *d) +{ + writel(delta, tce.base + ATMEL_TC_RC(tce.channels[0])); + writel(ATMEL_TC_CCR_CLKEN | ATMEL_TC_CCR_SWTRG, + tce.base + ATMEL_TC_CCR(tce.channels[0])); + + return 0; +} + +static irqreturn_t tc_clkevt2_irq(int irq, void *handle) +{ + unsigned int sr; + + sr = readl(tce.base + ATMEL_TC_SR(tce.channels[0])); + if (sr & ATMEL_TC_CPCS) { + tce.clkevt.event_handler(&tce.clkevt); + return IRQ_HANDLED; + } + + return IRQ_NONE; +} + +static void tc_clkevt2_suspend(struct clock_event_device *d) +{ + tce.cache[0].cmr = readl(tce.base + ATMEL_TC_CMR(tce.channels[0])); + tce.cache[0].imr = readl(tce.base + ATMEL_TC_IMR(tce.channels[0])); + tce.cache[0].rc = readl(tce.base + ATMEL_TC_RC(tce.channels[0])); + tce.cache[0].clken = !!(readl(tce.base + ATMEL_TC_SR(tce.channels[0])) & + ATMEL_TC_CLKSTA); +} + +static void tc_clkevt2_resume(struct clock_event_device *d) +{ + /* Restore registers for the channel, RA and RB are not used */ + writel(tce.cache[0].cmr, tc.base + ATMEL_TC_CMR(tce.channels[0])); + writel(tce.cache[0].rc, tc.base + ATMEL_TC_RC(tce.channels[0])); + writel(0, tc.base + ATMEL_TC_RA(tce.channels[0])); + writel(0, tc.base + ATMEL_TC_RB(tce.channels[0])); + /* Disable all the interrupts */ + writel(0xff, tc.base + ATMEL_TC_IDR(tce.channels[0])); + /* Reenable interrupts that were enabled before suspending */ + writel(tce.cache[0].imr, tc.base + ATMEL_TC_IER(tce.channels[0])); + + /* Start the clock if it was used */ + if (tce.cache[0].clken) + writel(ATMEL_TC_CCR_CLKEN | ATMEL_TC_CCR_SWTRG, + tc.base + ATMEL_TC_CCR(tce.channels[0])); +} + +static int __init tc_clkevt_register(struct device_node *node, + struct regmap *regmap, void __iomem *base, + int channel, int irq, int bits) +{ + int ret; + struct clk *slow_clk; + + tce.regmap = regmap; + tce.base = base; + tce.channels[0] = channel; + tce.irq = irq; + + slow_clk = of_clk_get_by_name(node->parent, "slow_clk"); + if (IS_ERR(slow_clk)) + return PTR_ERR(slow_clk); + + ret = clk_prepare_enable(slow_clk); + if (ret) + return ret; + + tce.clk[0] = tcb_clk_get(node, tce.channels[0]); + if (IS_ERR(tce.clk[0])) { + ret = PTR_ERR(tce.clk[0]); + goto err_slow; + } + + snprintf(tce.name, sizeof(tce.name), "%s:%d", + kbasename(node->parent->full_name), channel); + tce.clkevt.cpumask = cpumask_of(0); + tce.clkevt.name = tce.name; + tce.clkevt.set_next_event = tc_clkevt2_next_event, + tce.clkevt.set_state_shutdown = tc_clkevt2_shutdown, + tce.clkevt.set_state_periodic = tc_clkevt2_set_periodic, + tce.clkevt.set_state_oneshot = tc_clkevt2_set_oneshot, + tce.clkevt.suspend = tc_clkevt2_suspend, + tce.clkevt.resume = tc_clkevt2_resume, + tce.clkevt.features = CLOCK_EVT_FEAT_PERIODIC | CLOCK_EVT_FEAT_ONESHOT; + tce.clkevt.rating = 140; + + /* try to enable clk to avoid future errors in mode change */ + ret = clk_prepare_enable(tce.clk[0]); + if (ret) + goto err_slow; + clk_disable(tce.clk[0]); + + clockevents_config_and_register(&tce.clkevt, 32768, 1, + CLOCKSOURCE_MASK(bits)); + + ret = request_irq(tce.irq, tc_clkevt2_irq, IRQF_TIMER | IRQF_SHARED, + tce.clkevt.name, &tce); + if (ret) + goto err_clk; + + tce.registered = true; + + return 0; + +err_clk: + clk_unprepare(tce.clk[0]); +err_slow: + clk_disable_unprepare(slow_clk); + + return ret; +} + /* * Clocksource and clockevent using the same channel(s) */ @@ -362,7 +559,7 @@ static int __init tcb_clksrc_init(struct device_node *node) u32 channel; int bits, irq, err, chan1 = -1; - if (tc.registered) + if (tc.registered && tce.registered) return -ENODEV; /* @@ -394,12 +591,22 @@ static int __init tcb_clksrc_init(struct device_node *node) return irq; } + if (tc.registered) + return tc_clkevt_register(node, regmap, tcb_base, channel, irq, + bits); + if (bits == 16) { of_property_read_u32_index(node, "reg", 1, &chan1); if (chan1 == -1) { - pr_err("%s: clocksource needs two channels\n", - node->parent->full_name); - return -EINVAL; + if (tce.registered) { + pr_err("%s: clocksource needs two channels\n", + node->parent->full_name); + return -EINVAL; + } else { + return tc_clkevt_register(node, regmap, + tcb_base, channel, + irq, bits); + } } } From patchwork Wed Sep 12 16:11:19 2018 Content-Type: text/plain; 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Received: from mail.bootlin.com ([62.4.15.54]) by casper.infradead.org with esmtp (Exim 4.90_1 #2 (Red Hat Linux)) id 1g07jr-00080Z-M8 for linux-arm-kernel@lists.infradead.org; Wed, 12 Sep 2018 16:11:37 +0000 Received: by mail.bootlin.com (Postfix, from userid 110) id DE34A207F0; Wed, 12 Sep 2018 18:11:25 +0200 (CEST) Received: from localhost (242.171.71.37.rev.sfr.net [37.71.171.242]) by mail.bootlin.com (Postfix) with ESMTPSA id AF4FD2071D; Wed, 12 Sep 2018 18:11:25 +0200 (CEST) From: Alexandre Belloni To: Daniel Lezcano Subject: [PATCH v6 4/7] clocksource/drivers: atmel-pit: make option silent Date: Wed, 12 Sep 2018 18:11:19 +0200 Message-Id: <20180912161122.7717-5-alexandre.belloni@bootlin.com> X-Mailer: git-send-email 2.19.0.rc2 In-Reply-To: <20180912161122.7717-1-alexandre.belloni@bootlin.com> References: <20180912161122.7717-1-alexandre.belloni@bootlin.com> MIME-Version: 1.0 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20180912_171135_824706_BEE3215E X-CRM114-Status: GOOD ( 13.19 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Alexandre Belloni , Alexander Dahl , Sebastian Andrzej Siewior , linux-kernel@vger.kernel.org, Thomas Gleixner , linux-arm-kernel@lists.infradead.org Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+patchwork-linux-arm=patchwork.kernel.org@lists.infradead.org X-Virus-Scanned: ClamAV using ClamSMTP To conform with the other option, make the ATMEL_PIT option silent so it can be selected from the platform Tested-by: Alexander Dahl Signed-off-by: Alexandre Belloni --- drivers/clocksource/Kconfig | 5 ++++- 1 file changed, 4 insertions(+), 1 deletion(-) diff --git a/drivers/clocksource/Kconfig b/drivers/clocksource/Kconfig index 8c7324e409f6..2388fee46e99 100644 --- a/drivers/clocksource/Kconfig +++ b/drivers/clocksource/Kconfig @@ -392,8 +392,11 @@ config ARMV7M_SYSTICK This options enables support for the ARMv7M system timer unit config ATMEL_PIT + bool "Microchip ARM Periodic Interval Timer (PIT)" if COMPILE_TEST select TIMER_OF if OF - def_bool SOC_AT91SAM9 || SOC_SAMA5 + help + This enables build of clocksource and clockevent driver for + the integrated PIT in Microchip ARM SoCs. config ATMEL_ST bool "Atmel ST timer support" if COMPILE_TEST From patchwork Wed Sep 12 16:11:20 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Alexandre Belloni X-Patchwork-Id: 10598043 Return-Path: Received: from mail.wl.linuxfoundation.org (pdx-wl-mail.web.codeaurora.org [172.30.200.125]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id 9DA2214E5 for ; Wed, 12 Sep 2018 16:28:06 +0000 (UTC) Received: from mail.wl.linuxfoundation.org (localhost [127.0.0.1]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id 8C1DD2A790 for ; Wed, 12 Sep 2018 16:28:06 +0000 (UTC) Received: by mail.wl.linuxfoundation.org (Postfix, from userid 486) id 7F2C82A793; Wed, 12 Sep 2018 16:28:06 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on pdx-wl-mail.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-2.9 required=2.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,MAILING_LIST_MULTI,RCVD_IN_DNSWL_NONE autolearn=ham version=3.3.1 Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.wl.linuxfoundation.org (Postfix) with ESMTPS id A4AEE2A790 for ; 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Wed, 12 Sep 2018 16:27:54 +0000 Received: from mail.bootlin.com ([62.4.15.54]) by bombadil.infradead.org with esmtp (Exim 4.90_1 #2 (Red Hat Linux)) id 1g07k4-0002D0-AB for linux-arm-kernel@lists.infradead.org; Wed, 12 Sep 2018 16:12:13 +0000 Received: by mail.bootlin.com (Postfix, from userid 110) id 33E84208AC; Wed, 12 Sep 2018 18:11:26 +0200 (CEST) Received: from localhost (242.171.71.37.rev.sfr.net [37.71.171.242]) by mail.bootlin.com (Postfix) with ESMTPSA id 023F52071D; Wed, 12 Sep 2018 18:11:25 +0200 (CEST) From: Alexandre Belloni To: Daniel Lezcano Subject: [PATCH v6 5/7] ARM: at91: Implement clocksource selection Date: Wed, 12 Sep 2018 18:11:20 +0200 Message-Id: <20180912161122.7717-6-alexandre.belloni@bootlin.com> X-Mailer: git-send-email 2.19.0.rc2 In-Reply-To: <20180912161122.7717-1-alexandre.belloni@bootlin.com> References: <20180912161122.7717-1-alexandre.belloni@bootlin.com> MIME-Version: 1.0 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20180912_091148_540185_9A880D3F X-CRM114-Status: GOOD ( 10.67 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Alexandre Belloni , Alexander Dahl , Sebastian Andrzej Siewior , linux-kernel@vger.kernel.org, Thomas Gleixner , linux-arm-kernel@lists.infradead.org Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+patchwork-linux-arm=patchwork.kernel.org@lists.infradead.org X-Virus-Scanned: ClamAV using ClamSMTP Allow selecting and unselecting the PIT clocksource driver so it doesn't have to be compile when unused. Tested-by: Alexander Dahl Signed-off-by: Alexandre Belloni --- arch/arm/mach-at91/Kconfig | 25 +++++++++++++++++++++++++ 1 file changed, 25 insertions(+) diff --git a/arch/arm/mach-at91/Kconfig b/arch/arm/mach-at91/Kconfig index 903f23c309df..fa493a86e2bb 100644 --- a/arch/arm/mach-at91/Kconfig +++ b/arch/arm/mach-at91/Kconfig @@ -107,6 +107,31 @@ config SOC_AT91SAM9 AT91SAM9X35 AT91SAM9XE +comment "Clocksource driver selection" + +config ATMEL_CLOCKSOURCE_PIT + bool "Periodic Interval Timer (PIT) support" + depends on SOC_AT91SAM9 || SOC_SAMA5 + default SOC_AT91SAM9 || SOC_SAMA5 + select ATMEL_PIT + help + Select this to get a clocksource based on the Atmel Periodic Interval + Timer. It has a relatively low resolution and the TC Block clocksource + should be preferred. + +config ATMEL_CLOCKSOURCE_TCB + bool "Timer Counter Blocks (TCB) support" + depends on SOC_AT91RM9200 || SOC_AT91SAM9 || SOC_SAMA5 || COMPILE_TEST + default SOC_AT91RM9200 || SOC_AT91SAM9 || SOC_SAMA5 + depends on !ATMEL_TCLIB + select ATMEL_ARM_TCB_CLKSRC + help + Select this to get a high precision clocksource based on a + TC block with a 5+ MHz base clock rate. + On platforms with 16-bit counters, two timer channels are combined + to make a single 32-bit timer. + It can also be used as a clock event device supporting oneshot mode. + config HAVE_AT91_UTMI bool From patchwork Wed Sep 12 16:11:21 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Alexandre Belloni X-Patchwork-Id: 10598039 Return-Path: Received: from mail.wl.linuxfoundation.org (pdx-wl-mail.web.codeaurora.org [172.30.200.125]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id 33C1C1575 for ; Wed, 12 Sep 2018 16:26:18 +0000 (UTC) Received: from mail.wl.linuxfoundation.org (localhost [127.0.0.1]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id 2123B28A97 for ; Wed, 12 Sep 2018 16:26:18 +0000 (UTC) Received: by mail.wl.linuxfoundation.org (Postfix, from userid 486) id 123C0296E1; Wed, 12 Sep 2018 16:26:18 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on pdx-wl-mail.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-2.9 required=2.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,MAILING_LIST_MULTI,RCVD_IN_DNSWL_NONE autolearn=ham version=3.3.1 Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.wl.linuxfoundation.org (Postfix) with ESMTPS id 814D628A97 for ; Wed, 12 Sep 2018 16:26:17 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=bombadil.20170209; h=Sender: Content-Transfer-Encoding:Content-Type:Cc:List-Subscribe:List-Help:List-Post: List-Archive:List-Unsubscribe:List-Id:MIME-Version:References:In-Reply-To: Message-Id:Date:Subject:To:From:Reply-To:Content-ID:Content-Description: Resent-Date:Resent-From:Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID: List-Owner; bh=NBQSYwmLIQzbcY5w5d/QfrbU+K/6fMBi9BEGdLlgzM8=; b=TMrTt+UQqWc1V3 tk7AVAvV+e2CFhKp+mnJXSjiVjE531C3VFqWXx6h9bMyco3KiPvZCExpXEvNiexgXXIeuOdnwt2G1 yoGGDtVp2+FBpemCYq73Wf6jXcXWf74rYoYtH3uLCYsxbUj+fmoyAFnlqXG6uM0ZhwlXZzY1Et4wY a2TggVtTZl3kt5IFDSmEVCMmZ5YG0UodAvffUpts2SLKl51RORwDqXeyVhQWjpTcdXqT86SKq/yir WoVPZESDHXzY4qwFXCzjmLf3+lc+KJXA7AAvMzkBJq5c4EHn31CeWTPWLcrb7/z/DdZAlt2IctIiU 3pl0Y+MNOT3hoxAMrMCw==; Received: from localhost ([127.0.0.1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.90_1 #2 (Red Hat Linux)) id 1g07xq-0003Tr-58; Wed, 12 Sep 2018 16:26:02 +0000 Received: from mail.bootlin.com ([62.4.15.54]) by bombadil.infradead.org with esmtp (Exim 4.90_1 #2 (Red Hat Linux)) id 1g07k4-0002Cz-Ab for linux-arm-kernel@lists.infradead.org; Wed, 12 Sep 2018 16:12:10 +0000 Received: by mail.bootlin.com (Postfix, from userid 110) id AEE75208DC; Wed, 12 Sep 2018 18:11:26 +0200 (CEST) Received: from localhost (242.171.71.37.rev.sfr.net [37.71.171.242]) by mail.bootlin.com (Postfix) with ESMTPSA id 3DF4C2071D; Wed, 12 Sep 2018 18:11:26 +0200 (CEST) From: Alexandre Belloni To: Daniel Lezcano Subject: [PATCH v6 6/7] ARM: configs: at91: use new TCB timer driver Date: Wed, 12 Sep 2018 18:11:21 +0200 Message-Id: <20180912161122.7717-7-alexandre.belloni@bootlin.com> X-Mailer: git-send-email 2.19.0.rc2 In-Reply-To: <20180912161122.7717-1-alexandre.belloni@bootlin.com> References: <20180912161122.7717-1-alexandre.belloni@bootlin.com> MIME-Version: 1.0 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20180912_091148_522034_69C2B347 X-CRM114-Status: GOOD ( 10.33 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Alexandre Belloni , Alexander Dahl , Sebastian Andrzej Siewior , linux-kernel@vger.kernel.org, Thomas Gleixner , linux-arm-kernel@lists.infradead.org Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+patchwork-linux-arm=patchwork.kernel.org@lists.infradead.org X-Virus-Scanned: ClamAV using ClamSMTP Unselecting ATMEL_TCLIB switches the TCB timer driver from tcb_clksrc to timer-atmel-tcb. Signed-off-by: Alexandre Belloni --- arch/arm/configs/at91_dt_defconfig | 1 - arch/arm/configs/sama5_defconfig | 1 - 2 files changed, 2 deletions(-) diff --git a/arch/arm/configs/at91_dt_defconfig b/arch/arm/configs/at91_dt_defconfig index e4b1be66b3f5..09f262e59fef 100644 --- a/arch/arm/configs/at91_dt_defconfig +++ b/arch/arm/configs/at91_dt_defconfig @@ -64,7 +64,6 @@ CONFIG_BLK_DEV_LOOP=y CONFIG_BLK_DEV_RAM=y CONFIG_BLK_DEV_RAM_COUNT=4 CONFIG_BLK_DEV_RAM_SIZE=8192 -CONFIG_ATMEL_TCLIB=y CONFIG_ATMEL_SSC=y CONFIG_SCSI=y CONFIG_BLK_DEV_SD=y diff --git a/arch/arm/configs/sama5_defconfig b/arch/arm/configs/sama5_defconfig index 2080025556b5..f2bbc6339ca6 100644 --- a/arch/arm/configs/sama5_defconfig +++ b/arch/arm/configs/sama5_defconfig @@ -75,7 +75,6 @@ CONFIG_BLK_DEV_LOOP=y CONFIG_BLK_DEV_RAM=y CONFIG_BLK_DEV_RAM_COUNT=4 CONFIG_BLK_DEV_RAM_SIZE=8192 -CONFIG_ATMEL_TCLIB=y CONFIG_ATMEL_SSC=y CONFIG_EEPROM_AT24=y CONFIG_SCSI=y From patchwork Wed Sep 12 16:11:22 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Alexandre Belloni X-Patchwork-Id: 10598041 Return-Path: Received: from mail.wl.linuxfoundation.org (pdx-wl-mail.web.codeaurora.org [172.30.200.125]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id C21181575 for ; Wed, 12 Sep 2018 16:27:22 +0000 (UTC) Received: from mail.wl.linuxfoundation.org (localhost [127.0.0.1]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id B11552A738 for ; Wed, 12 Sep 2018 16:27:22 +0000 (UTC) Received: by mail.wl.linuxfoundation.org (Postfix, from userid 486) id A4A202A7B0; Wed, 12 Sep 2018 16:27:22 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on pdx-wl-mail.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-2.9 required=2.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,MAILING_LIST_MULTI,RCVD_IN_DNSWL_NONE autolearn=ham version=3.3.1 Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.wl.linuxfoundation.org (Postfix) with ESMTPS id 250492A738 for ; Wed, 12 Sep 2018 16:27:22 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=bombadil.20170209; h=Sender: Content-Transfer-Encoding:Content-Type:Cc:List-Subscribe:List-Help:List-Post: List-Archive:List-Unsubscribe:List-Id:MIME-Version:References:In-Reply-To: Message-Id:Date:Subject:To:From:Reply-To:Content-ID:Content-Description: Resent-Date:Resent-From:Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID: List-Owner; bh=xpk5lRoY1mGrP57yCId4oc9xrJFQ2E/WHSWfxOZwrRs=; b=tJ05h1PZxsd3pv GKPvBclN7aJGN/nnEaWgdw3xvk7m6oW9eHgmdkmAoxXVQFq5CKi4jA6jywc6gRUJlwu8fFNnnBHu+ AoYEqb0DiXpmbDXYQDx+BiCMnYtgFFzlaYqyc9Xv3HSiS05Ooqt65gI6Vtvl4bDD8pD5Mm3DWCXHi XMyT97HDd8BnANaW8ZdZi6yvjNPPG+F3H3NT2OZmOUXIiUn+fCoW85XePuRPcaYEUhf+m9rW0Rqjd XygXUDjBjbhmeOJIw+2sAom9Iz1tzTMfQixXxyBhOm29RL5R+xgaWAk7CAezuQEhQZ/hBSjTH1doB mvTl2hVn9idDN5gDHfIA==; Received: from localhost ([127.0.0.1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.90_1 #2 (Red Hat Linux)) id 1g07yt-00043d-Lw; Wed, 12 Sep 2018 16:27:07 +0000 Received: from mail.bootlin.com ([62.4.15.54]) by bombadil.infradead.org with esmtp (Exim 4.90_1 #2 (Red Hat Linux)) id 1g07k4-0002D4-A9 for linux-arm-kernel@lists.infradead.org; Wed, 12 Sep 2018 16:12:12 +0000 Received: by mail.bootlin.com (Postfix, from userid 110) id E9DE4208F0; Wed, 12 Sep 2018 18:11:26 +0200 (CEST) Received: from localhost (242.171.71.37.rev.sfr.net [37.71.171.242]) by mail.bootlin.com (Postfix) with ESMTPSA id C0E0E208D9; Wed, 12 Sep 2018 18:11:26 +0200 (CEST) From: Alexandre Belloni To: Daniel Lezcano Subject: [PATCH v6 7/7] ARM: configs: at91: unselect PIT Date: Wed, 12 Sep 2018 18:11:22 +0200 Message-Id: <20180912161122.7717-8-alexandre.belloni@bootlin.com> X-Mailer: git-send-email 2.19.0.rc2 In-Reply-To: <20180912161122.7717-1-alexandre.belloni@bootlin.com> References: <20180912161122.7717-1-alexandre.belloni@bootlin.com> MIME-Version: 1.0 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20180912_091148_536622_0895D4F0 X-CRM114-Status: GOOD ( 11.36 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Alexandre Belloni , Alexander Dahl , Sebastian Andrzej Siewior , linux-kernel@vger.kernel.org, Thomas Gleixner , linux-arm-kernel@lists.infradead.org Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+patchwork-linux-arm=patchwork.kernel.org@lists.infradead.org X-Virus-Scanned: ClamAV using ClamSMTP The PIT is not required anymore to successfully boot and may actually harm in case preempt-rt is used because the PIT interrupt is shared. Disable it so the TCB clocksource is used. Signed-off-by: Alexandre Belloni --- arch/arm/configs/at91_dt_defconfig | 1 + arch/arm/configs/sama5_defconfig | 1 + 2 files changed, 2 insertions(+) diff --git a/arch/arm/configs/at91_dt_defconfig b/arch/arm/configs/at91_dt_defconfig index 09f262e59fef..f4b253bd05ed 100644 --- a/arch/arm/configs/at91_dt_defconfig +++ b/arch/arm/configs/at91_dt_defconfig @@ -19,6 +19,7 @@ CONFIG_ARCH_MULTI_V5=y CONFIG_ARCH_AT91=y CONFIG_SOC_AT91RM9200=y CONFIG_SOC_AT91SAM9=y +# CONFIG_ATMEL_CLOCKSOURCE_PIT is not set CONFIG_AEABI=y CONFIG_UACCESS_WITH_MEMCPY=y CONFIG_ZBOOT_ROM_TEXT=0x0 diff --git a/arch/arm/configs/sama5_defconfig b/arch/arm/configs/sama5_defconfig index f2bbc6339ca6..be92871ab155 100644 --- a/arch/arm/configs/sama5_defconfig +++ b/arch/arm/configs/sama5_defconfig @@ -20,6 +20,7 @@ CONFIG_ARCH_AT91=y CONFIG_SOC_SAMA5D2=y CONFIG_SOC_SAMA5D3=y CONFIG_SOC_SAMA5D4=y +# CONFIG_ATMEL_CLOCKSOURCE_PIT is not set CONFIG_AEABI=y CONFIG_UACCESS_WITH_MEMCPY=y CONFIG_ZBOOT_ROM_TEXT=0x0