From patchwork Sat Oct 5 10:41:31 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: AngeloGioacchino Del Regno X-Patchwork-Id: 11175593 Return-Path: Received: from mail.kernel.org (pdx-korg-mail-1.web.codeaurora.org [172.30.200.123]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id B638714DB for ; Sat, 5 Oct 2019 10:41:55 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.kernel.org (Postfix) with ESMTP id 8B664222C7 for ; Sat, 5 Oct 2019 10:41:55 +0000 (UTC) Authentication-Results: mail.kernel.org; dkim=pass (2048-bit key) header.d=gmail.com header.i=@gmail.com header.b="Z1jISMRN" Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1727033AbfJEKlz (ORCPT ); Sat, 5 Oct 2019 06:41:55 -0400 Received: from mail-wr1-f48.google.com ([209.85.221.48]:40837 "EHLO mail-wr1-f48.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1727461AbfJEKly (ORCPT ); Sat, 5 Oct 2019 06:41:54 -0400 Received: by mail-wr1-f48.google.com with SMTP id h4so1210554wrv.7 for ; Sat, 05 Oct 2019 03:41:50 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=ywRq1h6IIUyQKu7cF5HFDA/Nwr2p+JBmdtBK4X8+0r4=; b=Z1jISMRN/h963o7kgiY1FEj65TjFDYh78HGAye2mF/HtZ66mah3FPRJ9A94N0SGDHc e7tkMo9w115Y1eTb0kPr5lmVfoh50a6ZYPYCh4vbBcAhDsNxgTLvL08+6WYN8lfWXdVc 21Od0UBAe0x4DCg0JXKXWRAbc3SPrh/XGAYcVxV+F0G7F6YyMY2PxVpszRP6Ddym7qCe rtRXoKQ2wpw/9bgBgQjEcAP97qeIU4nKWUNYTbV4cyxf3+9kPGeglrhOinK0jb/q9Q0h 9bvIqTJMelHYbFJJb1x1wwuTBABwCmi6vr2kELP6Pp5bHlTfciQISRBbQOQFgUHBLGkH 6nYg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=ywRq1h6IIUyQKu7cF5HFDA/Nwr2p+JBmdtBK4X8+0r4=; b=tyzh3I0c/I6Sm/P3S9OZraNqcw2oBBepkMd9J3vWYLTVWkluVav0jjOa7iIQyJnwjC dw5queYGeBJiC5v4z+2wz7S0vx7t52tv3ZR3RWKDz1V6g2BI65cs6QFBC6kayYe/4Eyq OHXb9+Qe1I6dzJtupB0NxC6PVPxUoXKuQiQ+awLvVV3DarhDXttgFLJF6c/QZJnqFbGC OWyqj8UuUKyh9HqXsrcHb+4CItFohW+AyYYoGSMuoEMlzsi7pBVjSlXi9qYTBBerS/Al oESNYXuD5xm+ydg+8IRclVxFIvIkU/4nzxq7z78mPCC6/JLT0UvWlURkHspsbz5RAbmz UWdA== X-Gm-Message-State: APjAAAVxElMHDwrosLQjlQ3e6mNJxqZ0RyN7FR35nbe5i8jJzdnbu3qW FV7le8+KDS+wDSFYQ62hxb4Ovv2zBDxwMw== X-Google-Smtp-Source: APXvYqyn6z52sIp5o+6pu1UsM/6doXhue+ACw9caqK9S/dCOFoyCncyrm+8/7B6MqEMfffLYg8eWSw== X-Received: by 2002:adf:f14f:: with SMTP id y15mr11764450wro.344.1570272109800; Sat, 05 Oct 2019 03:41:49 -0700 (PDT) Received: from IcarusMOD.eternityproject.eu ([93.51.16.173]) by smtp.gmail.com with ESMTPSA id u4sm16471674wmg.41.2019.10.05.03.41.48 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Sat, 05 Oct 2019 03:41:48 -0700 (PDT) From: kholk11@gmail.com To: linux-arm-msm@vger.kernel.org Cc: kholk11@gmail.com, marijns95@gmail.com, agross@kernel.org, daniel.lezcano@linaro.org, robh+dt@kernel.org, mark.rutland@arm.com, amit.kucheria@linaro.org Subject: [PATCH v3 1/3] thermal: qcom: tsens-v1: Add support for MSM8956 and MSM8976 Date: Sat, 5 Oct 2019 12:41:31 +0200 Message-Id: <20191005104133.30297-2-kholk11@gmail.com> X-Mailer: git-send-email 2.21.0 In-Reply-To: <20191005104133.30297-1-kholk11@gmail.com> References: <20191005104133.30297-1-kholk11@gmail.com> MIME-Version: 1.0 Sender: linux-arm-msm-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-arm-msm@vger.kernel.org From: AngeloGioacchino Del Regno Add support for reading calibrated value from thermistors in MSM8956, MSM8976 and their APQ variants. Signed-off-by: AngeloGioacchino Del Regno Reviewed-by: Amit Kucheria --- drivers/thermal/qcom/tsens-v1.c | 171 +++++++++++++++++++++++++++++++- drivers/thermal/qcom/tsens.c | 3 + drivers/thermal/qcom/tsens.h | 2 +- 3 files changed, 174 insertions(+), 2 deletions(-) diff --git a/drivers/thermal/qcom/tsens-v1.c b/drivers/thermal/qcom/tsens-v1.c index 10b595d4f619..3c85a698123a 100644 --- a/drivers/thermal/qcom/tsens-v1.c +++ b/drivers/thermal/qcom/tsens-v1.c @@ -6,6 +6,7 @@ #include #include #include +#include #include "tsens.h" /* ----- SROT ------ */ @@ -18,6 +19,68 @@ #define TM_Sn_STATUS_OFF 0x0044 #define TM_TRDY_OFF 0x0084 +/* eeprom layout data for msm8956/76 (v1) */ +#define MSM8976_BASE0_MASK 0xff +#define MSM8976_BASE1_MASK 0xff +#define MSM8976_BASE1_SHIFT 8 + +#define MSM8976_S0_P1_MASK 0x3f00 +#define MSM8976_S1_P1_MASK 0x3f00000 +#define MSM8976_S2_P1_MASK 0x3f +#define MSM8976_S3_P1_MASK 0x3f000 +#define MSM8976_S4_P1_MASK 0x3f00 +#define MSM8976_S5_P1_MASK 0x3f00000 +#define MSM8976_S6_P1_MASK 0x3f +#define MSM8976_S7_P1_MASK 0x3f000 +#define MSM8976_S8_P1_MASK 0x1f8 +#define MSM8976_S9_P1_MASK 0x1f8000 +#define MSM8976_S10_P1_MASK 0xf8000000 +#define MSM8976_S10_P1_MASK_1 0x1 + +#define MSM8976_S0_P2_MASK 0xfc000 +#define MSM8976_S1_P2_MASK 0xfc000000 +#define MSM8976_S2_P2_MASK 0xfc0 +#define MSM8976_S3_P2_MASK 0xfc0000 +#define MSM8976_S4_P2_MASK 0xfc000 +#define MSM8976_S5_P2_MASK 0xfc000000 +#define MSM8976_S6_P2_MASK 0xfc0 +#define MSM8976_S7_P2_MASK 0xfc0000 +#define MSM8976_S8_P2_MASK 0x7e00 +#define MSM8976_S9_P2_MASK 0x7e00000 +#define MSM8976_S10_P2_MASK 0x7e + +#define MSM8976_S0_P1_SHIFT 8 +#define MSM8976_S1_P1_SHIFT 20 +#define MSM8976_S2_P1_SHIFT 0 +#define MSM8976_S3_P1_SHIFT 12 +#define MSM8976_S4_P1_SHIFT 8 +#define MSM8976_S5_P1_SHIFT 20 +#define MSM8976_S6_P1_SHIFT 0 +#define MSM8976_S7_P1_SHIFT 12 +#define MSM8976_S8_P1_SHIFT 3 +#define MSM8976_S9_P1_SHIFT 15 +#define MSM8976_S10_P1_SHIFT 27 +#define MSM8976_S10_P1_SHIFT_1 0 + +#define MSM8976_S0_P2_SHIFT 14 +#define MSM8976_S1_P2_SHIFT 26 +#define MSM8976_S2_P2_SHIFT 6 +#define MSM8976_S3_P2_SHIFT 18 +#define MSM8976_S4_P2_SHIFT 14 +#define MSM8976_S5_P2_SHIFT 26 +#define MSM8976_S6_P2_SHIFT 6 +#define MSM8976_S7_P2_SHIFT 18 +#define MSM8976_S8_P2_SHIFT 9 +#define MSM8976_S9_P2_SHIFT 21 +#define MSM8976_S10_P2_SHIFT 1 + +#define MSM8976_CAL_SEL_MASK 0x3 + +#define MSM8976_CAL_DEGC_PT1 30 +#define MSM8976_CAL_DEGC_PT2 120 +#define MSM8976_SLOPE_FACTOR 1000 +#define MSM8976_SLOPE_DEFAULT 3200 + /* eeprom layout data for qcs404/405 (v1) */ #define BASE0_MASK 0x000007f8 #define BASE1_MASK 0x0007f800 @@ -77,6 +140,30 @@ #define CAL_SEL_MASK 7 #define CAL_SEL_SHIFT 0 +static void compute_intercept_slope_8976(struct tsens_priv *priv, + u32 *p1, u32 *p2, u32 mode) +{ + int i; + + priv->sensor[0].slope = 3313; + priv->sensor[1].slope = 3275; + priv->sensor[2].slope = 3320; + priv->sensor[3].slope = 3246; + priv->sensor[4].slope = 3279; + priv->sensor[5].slope = 3257; + priv->sensor[6].slope = 3234; + priv->sensor[7].slope = 3269; + priv->sensor[8].slope = 3255; + priv->sensor[9].slope = 3239; + priv->sensor[10].slope = 3286; + + for (i = 0; i < priv->num_sensors; i++) { + priv->sensor[i].offset = (p1[i] * MSM8976_SLOPE_FACTOR) - + (MSM8976_CAL_DEGC_PT1 * + priv->sensor[i].slope); + } +} + static int calibrate_v1(struct tsens_priv *priv) { u32 base0 = 0, base1 = 0; @@ -142,7 +229,74 @@ static int calibrate_v1(struct tsens_priv *priv) return 0; } -/* v1.x: qcs404,405 */ +static int calibrate_8976(struct tsens_priv *priv) +{ + int base0 = 0, base1 = 0, i; + u32 p1[11], p2[11]; + int mode = 0, tmp = 0; + u32 *qfprom_cdata; + + qfprom_cdata = (u32 *)qfprom_read(priv->dev, "calib"); + if (IS_ERR(qfprom_cdata)) { + kfree(qfprom_cdata); + return PTR_ERR(qfprom_cdata); + } + + mode = (qfprom_cdata[4] & MSM8976_CAL_SEL_MASK); + dev_dbg(priv->dev, "calibration mode is %d\n", mode); + + switch (mode) { + case TWO_PT_CALIB: + base1 = (qfprom_cdata[2] & MSM8976_BASE1_MASK) >> MSM8976_BASE1_SHIFT; + p2[0] = (qfprom_cdata[0] & MSM8976_S0_P2_MASK) >> MSM8976_S0_P2_SHIFT; + p2[1] = (qfprom_cdata[0] & MSM8976_S1_P2_MASK) >> MSM8976_S1_P2_SHIFT; + p2[2] = (qfprom_cdata[1] & MSM8976_S2_P2_MASK) >> MSM8976_S2_P2_SHIFT; + p2[3] = (qfprom_cdata[1] & MSM8976_S3_P2_MASK) >> MSM8976_S3_P2_SHIFT; + p2[4] = (qfprom_cdata[2] & MSM8976_S4_P2_MASK) >> MSM8976_S4_P2_SHIFT; + p2[5] = (qfprom_cdata[2] & MSM8976_S5_P2_MASK) >> MSM8976_S5_P2_SHIFT; + p2[6] = (qfprom_cdata[3] & MSM8976_S6_P2_MASK) >> MSM8976_S6_P2_SHIFT; + p2[7] = (qfprom_cdata[3] & MSM8976_S7_P2_MASK) >> MSM8976_S7_P2_SHIFT; + p2[8] = (qfprom_cdata[4] & MSM8976_S8_P2_MASK) >> MSM8976_S8_P2_SHIFT; + p2[9] = (qfprom_cdata[4] & MSM8976_S9_P2_MASK) >> MSM8976_S9_P2_SHIFT; + p2[10] = (qfprom_cdata[5] & MSM8976_S10_P2_MASK) >> MSM8976_S10_P2_SHIFT; + + for (i = 0; i < priv->num_sensors; i++) + p2[i] = ((base1 + p2[i]) << 2); + /* Fall through */ + case ONE_PT_CALIB2: + base0 = qfprom_cdata[0] & MSM8976_BASE0_MASK; + p1[0] = (qfprom_cdata[0] & MSM8976_S0_P1_MASK) >> MSM8976_S0_P1_SHIFT; + p1[1] = (qfprom_cdata[0] & MSM8976_S1_P1_MASK) >> MSM8976_S1_P1_SHIFT; + p1[2] = (qfprom_cdata[1] & MSM8976_S2_P1_MASK) >> MSM8976_S2_P1_SHIFT; + p1[3] = (qfprom_cdata[1] & MSM8976_S3_P1_MASK) >> MSM8976_S3_P1_SHIFT; + p1[4] = (qfprom_cdata[2] & MSM8976_S4_P1_MASK) >> MSM8976_S4_P1_SHIFT; + p1[5] = (qfprom_cdata[2] & MSM8976_S5_P1_MASK) >> MSM8976_S5_P1_SHIFT; + p1[6] = (qfprom_cdata[3] & MSM8976_S6_P1_MASK) >> MSM8976_S6_P1_SHIFT; + p1[7] = (qfprom_cdata[3] & MSM8976_S7_P1_MASK) >> MSM8976_S7_P1_SHIFT; + p1[8] = (qfprom_cdata[4] & MSM8976_S8_P1_MASK) >> MSM8976_S8_P1_SHIFT; + p1[9] = (qfprom_cdata[4] & MSM8976_S9_P1_MASK) >> MSM8976_S9_P1_SHIFT; + p1[10] = (qfprom_cdata[4] & MSM8976_S10_P1_MASK) >> MSM8976_S10_P1_SHIFT; + tmp = (qfprom_cdata[5] & MSM8976_S10_P1_MASK_1) << MSM8976_S10_P1_SHIFT_1; + p1[10] |= tmp; + + for (i = 0; i < priv->num_sensors; i++) + p1[i] = (((base0) + p1[i]) << 2); + break; + default: + for (i = 0; i < priv->num_sensors; i++) { + p1[i] = 500; + p2[i] = 780; + } + break; + } + + compute_intercept_slope_8976(priv, p1, p2, mode); + kfree(qfprom_cdata); + + return 0; +} + +/* v1.x: msm8956,8976,qcs404,405 */ static const struct tsens_features tsens_v1_feat = { .ver_major = VER_1_X, @@ -191,3 +345,18 @@ const struct tsens_plat_data data_tsens_v1 = { .feat = &tsens_v1_feat, .fields = tsens_v1_regfields, }; + +static const struct tsens_ops ops_8976 = { + .init = init_common, + .calibrate = calibrate_8976, + .get_temp = get_temp_tsens_valid, +}; + +/* Valid for both MSM8956 and MSM8976. Sensor ID 3 is unused. */ +const struct tsens_plat_data data_8976 = { + .num_sensors = 11, + .ops = &ops_8976, + .hw_ids = (unsigned int[]){0, 1, 2, 4, 5, 6, 7, 8, 9, 10}, + .feat = &tsens_v1_feat, + .fields = tsens_v1_regfields, +}; diff --git a/drivers/thermal/qcom/tsens.c b/drivers/thermal/qcom/tsens.c index 0627d8615c30..24bb05e0eaf8 100644 --- a/drivers/thermal/qcom/tsens.c +++ b/drivers/thermal/qcom/tsens.c @@ -60,6 +60,9 @@ static const struct of_device_id tsens_table[] = { }, { .compatible = "qcom,msm8974-tsens", .data = &data_8974, + }, { + .compatible = "qcom,msm8976-tsens", + .data = &data_8976, }, { .compatible = "qcom,msm8996-tsens", .data = &data_8996, diff --git a/drivers/thermal/qcom/tsens.h b/drivers/thermal/qcom/tsens.h index 2fd94997245b..8efec747bfcb 100644 --- a/drivers/thermal/qcom/tsens.h +++ b/drivers/thermal/qcom/tsens.h @@ -323,7 +323,7 @@ extern const struct tsens_plat_data data_8960; extern const struct tsens_plat_data data_8916, data_8974; /* TSENS v1 targets */ -extern const struct tsens_plat_data data_tsens_v1; +extern const struct tsens_plat_data data_tsens_v1, data_8976; /* TSENS v2 targets */ extern const struct tsens_plat_data data_8996, data_tsens_v2; From patchwork Sat Oct 5 10:41:32 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: AngeloGioacchino Del Regno X-Patchwork-Id: 11175589 Return-Path: Received: from mail.kernel.org (pdx-korg-mail-1.web.codeaurora.org [172.30.200.123]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id B96F316B1 for ; Sat, 5 Oct 2019 10:41:53 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.kernel.org (Postfix) with ESMTP id 996FB222C5 for ; Sat, 5 Oct 2019 10:41:53 +0000 (UTC) Authentication-Results: mail.kernel.org; dkim=pass (2048-bit key) header.d=gmail.com header.i=@gmail.com header.b="lqy7bkGb" Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1727478AbfJEKlx (ORCPT ); Sat, 5 Oct 2019 06:41:53 -0400 Received: from mail-wm1-f67.google.com ([209.85.128.67]:50413 "EHLO mail-wm1-f67.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1726283AbfJEKlw (ORCPT ); Sat, 5 Oct 2019 06:41:52 -0400 Received: by mail-wm1-f67.google.com with SMTP id 5so8097865wmg.0 for ; Sat, 05 Oct 2019 03:41:51 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=PdQqnIRetGhmX5t5KUNz0D/PW18I35dBAgGn5+TVGHo=; b=lqy7bkGbpgpXOiYREGcRT60+tz1bKA5j8IVaJXkOgrZYFH+W0NhYnqVxxlFO0y5/Id 5iIyK03+r26SR2/cfDZgNN94sjrlBPQBOd1ljUvtCrN8RrBVgXLuuqK9U20Edv3dUg4u Oc4QQAeTDanrlzBqcGgYbseynZvPIYagVCj9XYDiYD7CNVOgkzvBXBeHHI8Qsk0pr3NS lvdfcZ/ES9itFh2UuQxHZw6c+tNGYSh4gKVxYZZs6jcjPvdiFQ978NMxnIvvW4xU8Oqc l2AehHMsFcnlDZdr4ihBmOuBwFGM1Xh+0rtfrRkAYlFJiMKG3rd8r2bzNbLWho57bKWK ANUA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=PdQqnIRetGhmX5t5KUNz0D/PW18I35dBAgGn5+TVGHo=; b=frAlRWnGthCfg1u9Ze3jH8l7JqZeSgI+47AyMnybMXpWQLa0g/oEM9JpZyatUY+zS/ +mCQEiEaNVm9TXFKQunYOdb5gGNQgfjF6spsah6+GEY0HdijHqr6ggM81lHxmzvQmms/ V0MkL2UAgY2AHP4IDBkOScIS6CjG6K3xVZuZuy/zlJnMZK89TKfItVsXQRUui+0u5Ys9 2ASsU0pWmJ8Kd1xcwtqAPZV76I/LREdQ+rSxfpqgShFw1ciNqAu1fUFOiCTiKIHtp3aP hAAuqBjcmQdX82lCp5MNwiOklpWPYV8iQKeQ4R4ryBmZmpxmEtsUDW3GlZieRIUrWYID iimg== X-Gm-Message-State: APjAAAVYCMUREvPVyq1dU7yhhNvbvT1a6y1VRkABHRyRIhqzCqs+plVw 22mpF3eh8a4WxJumsdGTLMVCYJoXhHfrdA== X-Google-Smtp-Source: APXvYqxMyNKDlIzjIsYxZ+OkpiZLnf4oHCgI8kV4JmcHIQaAIqVo1YFU90qOYYXtdQ64xrKrlzBNyw== X-Received: by 2002:a05:600c:118a:: with SMTP id i10mr13894681wmf.80.1570272110488; Sat, 05 Oct 2019 03:41:50 -0700 (PDT) Received: from IcarusMOD.eternityproject.eu ([93.51.16.173]) by smtp.gmail.com with ESMTPSA id u4sm16471674wmg.41.2019.10.05.03.41.49 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Sat, 05 Oct 2019 03:41:50 -0700 (PDT) From: kholk11@gmail.com To: linux-arm-msm@vger.kernel.org Cc: kholk11@gmail.com, marijns95@gmail.com, agross@kernel.org, daniel.lezcano@linaro.org, robh+dt@kernel.org, mark.rutland@arm.com, amit.kucheria@linaro.org Subject: [PATCH v3 2/3] dt: thermal: tsens: Document compatible for MSM8976/56 Date: Sat, 5 Oct 2019 12:41:32 +0200 Message-Id: <20191005104133.30297-3-kholk11@gmail.com> X-Mailer: git-send-email 2.21.0 In-Reply-To: <20191005104133.30297-1-kholk11@gmail.com> References: <20191005104133.30297-1-kholk11@gmail.com> MIME-Version: 1.0 Sender: linux-arm-msm-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-arm-msm@vger.kernel.org From: AngeloGioacchino Del Regno Support for MSM8976 and MSM8956 (having tsens ip version 1) has been added to the qcom tsens driver: document the addition here. Signed-off-by: AngeloGioacchino Del Regno Reviewed-by: Amit Kucheria --- Documentation/devicetree/bindings/thermal/qcom-tsens.yaml | 2 ++ 1 file changed, 2 insertions(+) diff --git a/Documentation/devicetree/bindings/thermal/qcom-tsens.yaml b/Documentation/devicetree/bindings/thermal/qcom-tsens.yaml index 23afc7bf5a44..eef13b9446a8 100644 --- a/Documentation/devicetree/bindings/thermal/qcom-tsens.yaml +++ b/Documentation/devicetree/bindings/thermal/qcom-tsens.yaml @@ -29,6 +29,7 @@ properties: - description: v1 of TSENS items: - enum: + - qcom,msm8976-tsens - qcom,qcs404-tsens - const: qcom,tsens-v1 @@ -82,6 +83,7 @@ allOf: enum: - qcom,msm8916-tsens - qcom,msm8974-tsens + - qcom,msm8976-tsens - qcom,qcs404-tsens - qcom,tsens-v0_1 - qcom,tsens-v1 From patchwork Sat Oct 5 10:41:33 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: AngeloGioacchino Del Regno X-Patchwork-Id: 11175591 Return-Path: Received: from mail.kernel.org (pdx-korg-mail-1.web.codeaurora.org [172.30.200.123]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id 6518C1902 for ; Sat, 5 Oct 2019 10:41:54 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.kernel.org (Postfix) with ESMTP id 44A86222C7 for ; Sat, 5 Oct 2019 10:41:54 +0000 (UTC) Authentication-Results: mail.kernel.org; dkim=pass (2048-bit key) header.d=gmail.com header.i=@gmail.com header.b="s4Y8/h+v" Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1726283AbfJEKlx (ORCPT ); Sat, 5 Oct 2019 06:41:53 -0400 Received: from mail-wr1-f66.google.com ([209.85.221.66]:36868 "EHLO mail-wr1-f66.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1727033AbfJEKlx (ORCPT ); Sat, 5 Oct 2019 06:41:53 -0400 Received: by mail-wr1-f66.google.com with SMTP id p14so9010761wro.4 for ; Sat, 05 Oct 2019 03:41:52 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=3/PXG2bkbg7x3ohBOF3GXLjn8xoQKFLCILOx5cPdBhg=; b=s4Y8/h+v34BXkR18MHBaEc78C+YEAbKa6Bit3VVsxiqe2NwI1/Wdhlmzfw6GnTL8nZ +Lwj4Y7sg4ilBhwJUUYuTd0kOVPuPKheQfb+/sqdzBeOaGB7aU+anN0S5xVMHbBPkeXa 1ZwRIT+Ier2sZWXXpzywa7Szx/xUvZV7rWWBIxqCRnYU4xG5xQNCtiw9OyHBF+15vUn6 wf8l2pjrndgwx8R6WlabCf121ePSV8/41FWVNA90YhadzAodN9r/a9hzth2nlQRWFe8V qR2L7CGxTOWY7u/jwtFEj/iUBxTZf4jD5ZvkiGR6XIybiF7JLNZENiq2Y8GMk4B94jgO FtpQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=3/PXG2bkbg7x3ohBOF3GXLjn8xoQKFLCILOx5cPdBhg=; b=MpBq+cUojISQoSM7TI1f0GfdNT9Ny9cJn+j5sVXB46w9wLPQb/BFsKMuRM9N5/nvGk IdaRucymvIXpb8HtcH0tzjmNWY4NxIXuZGwTst/Oas9xkj2QeWmMdU6UlVNla2BR6m98 LOgFOqe+9ZYSdgH6GCT9A42A1VzLSSH1wGjMieF+XCyjnzDe4KVU3D5LirYFN9oFXFbO /nndI4vtjYxzsisWVhe+XInCSMDywhnvORCkZ2sB59XLjX2GtUyjzpxAblm60uQN8Q1y GtgpO1z4x/PkE5a8OySrhL0uLA7PHkvw3KKrlTw9OhXgqZDyjQWzk/UAGsReLQVEcb/t zpkw== X-Gm-Message-State: APjAAAVDeiC1vM9QYc2Iinwo6IWc6XKGi1ZryaXNQ72Hjxxgv0aQVJsh CSlKMtq6wfLgu0WGp9fTxuGEsf99pVDbBw== X-Google-Smtp-Source: APXvYqzNO+osc1lR2iTyKLFwGRE+3t32pfYIWGrq/FaJaScmnE0RAVuOmr5AYys29RgUhHqbw/Gepg== X-Received: by 2002:adf:ed04:: with SMTP id a4mr15240394wro.77.1570272111357; Sat, 05 Oct 2019 03:41:51 -0700 (PDT) Received: from IcarusMOD.eternityproject.eu ([93.51.16.173]) by smtp.gmail.com with ESMTPSA id u4sm16471674wmg.41.2019.10.05.03.41.50 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Sat, 05 Oct 2019 03:41:50 -0700 (PDT) From: kholk11@gmail.com To: linux-arm-msm@vger.kernel.org Cc: kholk11@gmail.com, marijns95@gmail.com, agross@kernel.org, daniel.lezcano@linaro.org, robh+dt@kernel.org, mark.rutland@arm.com, amit.kucheria@linaro.org Subject: [PATCH v3 3/3] thermal: qcom: tsens-v1: Free memory in calibrate_v1 where required Date: Sat, 5 Oct 2019 12:41:33 +0200 Message-Id: <20191005104133.30297-4-kholk11@gmail.com> X-Mailer: git-send-email 2.21.0 In-Reply-To: <20191005104133.30297-1-kholk11@gmail.com> References: <20191005104133.30297-1-kholk11@gmail.com> MIME-Version: 1.0 Sender: linux-arm-msm-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-arm-msm@vger.kernel.org From: AngeloGioacchino Del Regno The calibrate_v1 function allocates the qfprom_cdata variable during qfprom_read, but it never gets freed: properly kfree it. Signed-off-by: AngeloGioacchino Del Regno --- drivers/thermal/qcom/tsens-v1.c | 5 ++++- 1 file changed, 4 insertions(+), 1 deletion(-) diff --git a/drivers/thermal/qcom/tsens-v1.c b/drivers/thermal/qcom/tsens-v1.c index 3c85a698123a..017501f37a41 100644 --- a/drivers/thermal/qcom/tsens-v1.c +++ b/drivers/thermal/qcom/tsens-v1.c @@ -173,8 +173,10 @@ static int calibrate_v1(struct tsens_priv *priv) int i; qfprom_cdata = (u32 *)qfprom_read(priv->dev, "calib"); - if (IS_ERR(qfprom_cdata)) + if (IS_ERR(qfprom_cdata)) { + kfree(qfprom_cdata); return PTR_ERR(qfprom_cdata); + } mode = (qfprom_cdata[4] & CAL_SEL_MASK) >> CAL_SEL_SHIFT; dev_dbg(priv->dev, "calibration mode is %d\n", mode); @@ -225,6 +227,7 @@ static int calibrate_v1(struct tsens_priv *priv) } compute_intercept_slope(priv, p1, p2, mode); + kfree(qfprom_cdata); return 0; }