From patchwork Mon Oct 7 12:29:29 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Tero Kristo X-Patchwork-Id: 11177369 Return-Path: Received: from mail.kernel.org (pdx-korg-mail-1.web.codeaurora.org [172.30.200.123]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id B7D391747 for ; Mon, 7 Oct 2019 12:29:47 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.kernel.org (Postfix) with ESMTP id 965142070B for ; Mon, 7 Oct 2019 12:29:47 +0000 (UTC) Authentication-Results: mail.kernel.org; dkim=pass (1024-bit key) header.d=ti.com header.i=@ti.com header.b="OK4Dc0eU" Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1727554AbfJGM3r (ORCPT ); Mon, 7 Oct 2019 08:29:47 -0400 Received: from lelv0142.ext.ti.com ([198.47.23.249]:47976 "EHLO lelv0142.ext.ti.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1727798AbfJGM3q (ORCPT ); Mon, 7 Oct 2019 08:29:46 -0400 Received: from lelv0265.itg.ti.com ([10.180.67.224]) by lelv0142.ext.ti.com (8.15.2/8.15.2) with ESMTP id x97CTbKe092218; Mon, 7 Oct 2019 07:29:37 -0500 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=ti.com; s=ti-com-17Q1; t=1570451377; bh=CrweeoqDBqIdn3s+o5LCr5A3MF6tfykZWffRhUe50/g=; h=From:To:CC:Subject:Date:In-Reply-To:References; b=OK4Dc0eUBmyvrqDlw7uFj8IcMEebY8TMr9dWBEwXLAz/CfxdX+7CF7NTtX4x8eZTN SW/lijT6g6/ZKkqDqPsuSXum08+EOKNrgMK5Ugy+D8MOxMsJ8NSuyuxzFOubAt/KxU PVrFemc+rF3lSc9S90B4royxzaVlRsNNddO37U9U= Received: from DLEE109.ent.ti.com (dlee109.ent.ti.com [157.170.170.41]) by lelv0265.itg.ti.com (8.15.2/8.15.2) with ESMTPS id x97CTbDL085408 (version=TLSv1.2 cipher=AES256-GCM-SHA384 bits=256 verify=FAIL); Mon, 7 Oct 2019 07:29:37 -0500 Received: from DLEE101.ent.ti.com (157.170.170.31) by DLEE109.ent.ti.com (157.170.170.41) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.1713.5; Mon, 7 Oct 2019 07:29:34 -0500 Received: from lelv0327.itg.ti.com (10.180.67.183) by DLEE101.ent.ti.com (157.170.170.31) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.1713.5 via Frontend Transport; Mon, 7 Oct 2019 07:29:34 -0500 Received: from sokoban.bb.dnainternet.fi (ileax41-snat.itg.ti.com [10.172.224.153]) by lelv0327.itg.ti.com (8.15.2/8.15.2) with ESMTP id x97CTYe6066760; Mon, 7 Oct 2019 07:29:36 -0500 From: Tero Kristo To: , CC: Subject: [PATCH 1/3] bus: ti-sysc: re-order reset and main clock controls Date: Mon, 7 Oct 2019 15:29:29 +0300 Message-ID: <20191007122931.18668-2-t-kristo@ti.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20191007122931.18668-1-t-kristo@ti.com> References: <20191007122931.18668-1-t-kristo@ti.com> MIME-Version: 1.0 X-EXCLAIMER-MD-CONFIG: e1e8a2fd-e40a-4ac6-ac9b-f7e9cc9ee180 Sender: linux-omap-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-omap@vger.kernel.org The main clocks and reset controls have a hardware level dependency, where one can't transition state without the other one transitioning. Because we don't have the dependency implemented in software, we must ensure the ordering of these two is done properly; they way this is handled is that clocks transition on software level without delay, and the status is only polled on reset side. Because of this, we must re-order the main clock and reset handling on the ti-sysc driver. Signed-off-by: Tero Kristo --- drivers/bus/ti-sysc.c | 8 ++++---- 1 file changed, 4 insertions(+), 4 deletions(-) diff --git a/drivers/bus/ti-sysc.c b/drivers/bus/ti-sysc.c index 193d8b23d54d..c9d01e2d3a64 100644 --- a/drivers/bus/ti-sysc.c +++ b/drivers/bus/ti-sysc.c @@ -1032,8 +1032,6 @@ static int __maybe_unused sysc_runtime_resume_legacy(struct device *dev, struct ti_sysc_platform_data *pdata; int error; - reset_control_deassert(ddata->rsts); - pdata = dev_get_platdata(ddata->dev); if (!pdata) return 0; @@ -1046,6 +1044,8 @@ static int __maybe_unused sysc_runtime_resume_legacy(struct device *dev, dev_err(dev, "%s: could not enable: %i\n", __func__, error); + reset_control_deassert(ddata->rsts); + return 0; } @@ -1099,8 +1099,6 @@ static int __maybe_unused sysc_runtime_resume(struct device *dev) sysc_clkdm_deny_idle(ddata); - reset_control_deassert(ddata->rsts); - if (sysc_opt_clks_needed(ddata)) { error = sysc_enable_opt_clocks(ddata); if (error) @@ -1111,6 +1109,8 @@ static int __maybe_unused sysc_runtime_resume(struct device *dev) if (error) goto err_opt_clocks; + reset_control_deassert(ddata->rsts); + if (ddata->legacy_mode) { error = sysc_runtime_resume_legacy(dev, ddata); if (error) From patchwork Mon Oct 7 12:29:30 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Tero Kristo X-Patchwork-Id: 11177365 Return-Path: Received: from mail.kernel.org (pdx-korg-mail-1.web.codeaurora.org [172.30.200.123]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id A96E817D4 for ; Mon, 7 Oct 2019 12:29:46 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.kernel.org (Postfix) with ESMTP id 88B2121655 for ; Mon, 7 Oct 2019 12:29:46 +0000 (UTC) Authentication-Results: mail.kernel.org; dkim=pass (1024-bit key) header.d=ti.com header.i=@ti.com header.b="IxuYlVjB" Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1727589AbfJGM3q (ORCPT ); Mon, 7 Oct 2019 08:29:46 -0400 Received: from lelv0142.ext.ti.com ([198.47.23.249]:47974 "EHLO lelv0142.ext.ti.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1727939AbfJGM3p (ORCPT ); Mon, 7 Oct 2019 08:29:45 -0400 Received: from fllv0034.itg.ti.com ([10.64.40.246]) by lelv0142.ext.ti.com (8.15.2/8.15.2) with ESMTP id x97CTd5A092228; Mon, 7 Oct 2019 07:29:39 -0500 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=ti.com; s=ti-com-17Q1; t=1570451379; bh=KWT9j+QacvjVEBtE+hjvy3qdfIygfB4NgnQaBBRf21w=; h=From:To:CC:Subject:Date:In-Reply-To:References; b=IxuYlVjB1sRkwp3e9rNKfqASkNDHvJ0VbKo6k4PD55oB0XcESmqcddvSbzseiKXY/ EI7Pn+eVGc06tR88RZ2xkvhWnFcGuAGigXi8hWYberH1ahf181/fjKA20ZV3cf7XYX FJpvBOwHVNoEAs5GnmauXmPrc5EGYLtX2mmh+87I= Received: from DLEE100.ent.ti.com (dlee100.ent.ti.com [157.170.170.30]) by fllv0034.itg.ti.com (8.15.2/8.15.2) with ESMTPS id x97CTdFd069561 (version=TLSv1.2 cipher=AES256-GCM-SHA384 bits=256 verify=FAIL); Mon, 7 Oct 2019 07:29:39 -0500 Received: from DLEE113.ent.ti.com (157.170.170.24) by DLEE100.ent.ti.com (157.170.170.30) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.1713.5; Mon, 7 Oct 2019 07:29:38 -0500 Received: from lelv0327.itg.ti.com (10.180.67.183) by DLEE113.ent.ti.com (157.170.170.24) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.1713.5 via Frontend Transport; Mon, 7 Oct 2019 07:29:36 -0500 Received: from sokoban.bb.dnainternet.fi (ileax41-snat.itg.ti.com [10.172.224.153]) by lelv0327.itg.ti.com (8.15.2/8.15.2) with ESMTP id x97CTYe7066760; Mon, 7 Oct 2019 07:29:37 -0500 From: Tero Kristo To: , CC: Subject: [PATCH 2/3] bus: ti-sysc: drop the extra hardreset during init Date: Mon, 7 Oct 2019 15:29:30 +0300 Message-ID: <20191007122931.18668-3-t-kristo@ti.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20191007122931.18668-1-t-kristo@ti.com> References: <20191007122931.18668-1-t-kristo@ti.com> MIME-Version: 1.0 X-EXCLAIMER-MD-CONFIG: e1e8a2fd-e40a-4ac6-ac9b-f7e9cc9ee180 Sender: linux-omap-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-omap@vger.kernel.org There seems to be unnecessary extra hardreset line toggling applied during module init. This is unnecessary, as the reset lines are already asserted during boot, and it can cause certain modules to hang (iommus, remoteprocs.) Remove the extra hardreset toggle, and remove the now redundant function to handle this also. Signed-off-by: Tero Kristo --- drivers/bus/ti-sysc.c | 37 +------------------------------------ 1 file changed, 1 insertion(+), 36 deletions(-) diff --git a/drivers/bus/ti-sysc.c b/drivers/bus/ti-sysc.c index c9d01e2d3a64..6f392469d5b0 100644 --- a/drivers/bus/ti-sysc.c +++ b/drivers/bus/ti-sysc.c @@ -1518,37 +1518,6 @@ static int sysc_legacy_init(struct sysc *ddata) return error; } -/** - * sysc_rstctrl_reset_deassert - deassert rstctrl reset - * @ddata: device driver data - * @reset: reset before deassert - * - * A module can have both OCP softreset control and external rstctrl. - * If more complicated rstctrl resets are needed, please handle these - * directly from the child device driver and map only the module reset - * for the parent interconnect target module device. - * - * Automatic reset of the module on init can be skipped with the - * "ti,no-reset-on-init" device tree property. - */ -static int sysc_rstctrl_reset_deassert(struct sysc *ddata, bool reset) -{ - int error; - - if (!ddata->rsts) - return 0; - - if (reset) { - error = reset_control_assert(ddata->rsts); - if (error) - return error; - } - - reset_control_deassert(ddata->rsts); - - return 0; -} - /* * Note that the caller must ensure the interconnect target module is enabled * before calling reset. Otherwise reset will not complete. @@ -1613,10 +1582,6 @@ static int sysc_init_module(struct sysc *ddata) int error = 0; bool manage_clocks = true; - error = sysc_rstctrl_reset_deassert(ddata, false); - if (error) - return error; - if (ddata->cfg.quirks & (SYSC_QUIRK_NO_IDLE | SYSC_QUIRK_NO_IDLE_ON_INIT)) manage_clocks = false; @@ -1640,7 +1605,7 @@ static int sysc_init_module(struct sysc *ddata) goto err_opt_clocks; if (!(ddata->cfg.quirks & SYSC_QUIRK_NO_RESET_ON_INIT)) { - error = sysc_rstctrl_reset_deassert(ddata, true); + error = reset_control_deassert(ddata->rsts); if (error) goto err_main_clocks; } From patchwork Mon Oct 7 12:29:31 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Tero Kristo X-Patchwork-Id: 11177363 Return-Path: Received: from mail.kernel.org (pdx-korg-mail-1.web.codeaurora.org [172.30.200.123]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id 216901599 for ; Mon, 7 Oct 2019 12:29:46 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.kernel.org (Postfix) with ESMTP id F389A2070B for ; Mon, 7 Oct 2019 12:29:45 +0000 (UTC) Authentication-Results: mail.kernel.org; dkim=pass (1024-bit key) header.d=ti.com header.i=@ti.com header.b="MixkhmX4" Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1727566AbfJGM3p (ORCPT ); Mon, 7 Oct 2019 08:29:45 -0400 Received: from lelv0143.ext.ti.com ([198.47.23.248]:44694 "EHLO lelv0143.ext.ti.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1727589AbfJGM3p (ORCPT ); Mon, 7 Oct 2019 08:29:45 -0400 Received: from fllv0034.itg.ti.com ([10.64.40.246]) by lelv0143.ext.ti.com (8.15.2/8.15.2) with ESMTP id x97CTeXE023818; Mon, 7 Oct 2019 07:29:40 -0500 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=ti.com; s=ti-com-17Q1; t=1570451380; bh=Fw2h1o3Q27rAtV1ZBgNrh1rdPKvZXkA0SznxBk2nGYI=; h=From:To:CC:Subject:Date:In-Reply-To:References; b=MixkhmX43tUUry6e993e/Yco947fJbi1rMC19OF9pm5/zSujPfcpwYBOoHGq2mrHX 6dOraZqOcNC6kfF8l+Dlg8/rT9RB/puZgb+vd9qAp9uU6Pk5QLGXIYoJ9qYo75QZTE sGwGGDT5Vd1tth1czc4GIM36ceSFNRl67fBHkI30= Received: from DFLE115.ent.ti.com (dfle115.ent.ti.com [10.64.6.36]) by fllv0034.itg.ti.com (8.15.2/8.15.2) with ESMTPS id x97CTdwq069570 (version=TLSv1.2 cipher=AES256-GCM-SHA384 bits=256 verify=FAIL); Mon, 7 Oct 2019 07:29:40 -0500 Received: from DFLE103.ent.ti.com (10.64.6.24) by DFLE115.ent.ti.com (10.64.6.36) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.1713.5; Mon, 7 Oct 2019 07:29:37 -0500 Received: from lelv0327.itg.ti.com (10.180.67.183) by DFLE103.ent.ti.com (10.64.6.24) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.1713.5 via Frontend Transport; Mon, 7 Oct 2019 07:29:39 -0500 Received: from sokoban.bb.dnainternet.fi (ileax41-snat.itg.ti.com [10.172.224.153]) by lelv0327.itg.ti.com (8.15.2/8.15.2) with ESMTP id x97CTYe8066760; Mon, 7 Oct 2019 07:29:38 -0500 From: Tero Kristo To: , CC: Subject: [PATCH 3/3] bus: ti-sysc: avoid toggling power state of module during probe Date: Mon, 7 Oct 2019 15:29:31 +0300 Message-ID: <20191007122931.18668-4-t-kristo@ti.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20191007122931.18668-1-t-kristo@ti.com> References: <20191007122931.18668-1-t-kristo@ti.com> MIME-Version: 1.0 X-EXCLAIMER-MD-CONFIG: e1e8a2fd-e40a-4ac6-ac9b-f7e9cc9ee180 Sender: linux-omap-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-omap@vger.kernel.org Current implementation for ti-sysc powers down the module once module init is complete. However, right after power is disabled, it is enabled via runtime PM. This is unnecessary so avoid it by re-ordering the events a bit; move powering down of the module post runtime PM enable which makes sure the use counts are maintained properly and there is no extra power down/up sequence for the module. Signed-off-by: Tero Kristo --- drivers/bus/ti-sysc.c | 32 +++++++++++++++++++------------- 1 file changed, 19 insertions(+), 13 deletions(-) diff --git a/drivers/bus/ti-sysc.c b/drivers/bus/ti-sysc.c index 6f392469d5b0..5b69457fa857 100644 --- a/drivers/bus/ti-sysc.c +++ b/drivers/bus/ti-sysc.c @@ -1580,11 +1580,6 @@ static int sysc_reset(struct sysc *ddata) static int sysc_init_module(struct sysc *ddata) { int error = 0; - bool manage_clocks = true; - - if (ddata->cfg.quirks & - (SYSC_QUIRK_NO_IDLE | SYSC_QUIRK_NO_IDLE_ON_INIT)) - manage_clocks = false; error = sysc_clockdomain_init(ddata); if (error) @@ -1617,28 +1612,32 @@ static int sysc_init_module(struct sysc *ddata) if (ddata->legacy_mode) { error = sysc_legacy_init(ddata); if (error) - goto err_main_clocks; + goto err_reset; } if (!ddata->legacy_mode) { error = sysc_enable_module(ddata->dev); if (error) - goto err_main_clocks; + goto err_reset; } error = sysc_reset(ddata); if (error) dev_err(ddata->dev, "Reset failed with %d\n", error); - if (!ddata->legacy_mode && manage_clocks) + if (error && !ddata->legacy_mode) sysc_disable_module(ddata->dev); +err_reset: + if (error && !(ddata->cfg.quirks & SYSC_QUIRK_NO_RESET_ON_INIT)) + reset_control_assert(ddata->rsts); + err_main_clocks: - if (manage_clocks) + if (error) sysc_disable_main_clocks(ddata); err_opt_clocks: /* No re-enable of clockdomain autoidle to prevent module autoidle */ - if (manage_clocks) { + if (error) { sysc_disable_opt_clocks(ddata); sysc_clkdm_allow_idle(ddata); } @@ -2411,9 +2410,16 @@ static int sysc_probe(struct platform_device *pdev) goto unprepare; } - /* Balance reset counts */ - if (ddata->rsts) - reset_control_assert(ddata->rsts); + /* Balance use counts as PM runtime should have enabled these all */ + if (!(ddata->cfg.quirks & SYSC_QUIRK_NO_RESET_ON_INIT)) + reset_control_assert(ddata->rsts); + + if (!(ddata->cfg.quirks & + (SYSC_QUIRK_NO_IDLE | SYSC_QUIRK_NO_IDLE_ON_INIT))) { + sysc_disable_main_clocks(ddata); + sysc_disable_opt_clocks(ddata); + sysc_clkdm_allow_idle(ddata); + } sysc_show_registers(ddata);