From patchwork Tue Oct 8 00:13:16 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Jonathan Behrens X-Patchwork-Id: 11178643 Return-Path: Received: from mail.kernel.org (pdx-korg-mail-1.web.codeaurora.org [172.30.200.123]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id 32CFD139A for ; Tue, 8 Oct 2019 00:17:21 +0000 (UTC) Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id 05D9820867 for ; Tue, 8 Oct 2019 00:17:21 +0000 (UTC) Authentication-Results: mail.kernel.org; dkim=fail reason="signature verification failed" (2048-bit key) header.d=fintelia.io header.i=@fintelia.io header.b="Lh8WarIs" DMARC-Filter: OpenDMARC Filter v1.3.2 mail.kernel.org 05D9820867 Authentication-Results: mail.kernel.org; dmarc=none (p=none dis=none) header.from=fintelia.io Authentication-Results: mail.kernel.org; spf=pass smtp.mailfrom=qemu-devel-bounces+patchwork-qemu-devel=patchwork.kernel.org@nongnu.org Received: from localhost ([::1]:50240 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1iHdBo-0004Mv-22 for patchwork-qemu-devel@patchwork.kernel.org; Mon, 07 Oct 2019 20:17:20 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:37151) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1iHd92-0002Uv-5u for qemu-devel@nongnu.org; Mon, 07 Oct 2019 20:14:29 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1iHd91-0005LL-1N for qemu-devel@nongnu.org; Mon, 07 Oct 2019 20:14:28 -0400 Received: from rs224.mailgun.us ([209.61.151.224]:46215) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1iHd90-0005Jn-Ge for qemu-devel@nongnu.org; Mon, 07 Oct 2019 20:14:26 -0400 DKIM-Signature: a=rsa-sha256; v=1; c=relaxed/relaxed; d=fintelia.io; q=dns/txt; s=pic; t=1570493666; h=Content-Transfer-Encoding: MIME-Version: References: In-Reply-To: Message-Id: Date: Subject: Cc: To: From: Sender; bh=gUUopECUHc7cg4bXJNiFx5+MQFSc9HWlEgYorCg8juM=; b=Lh8WarIsK7LNDa0ABiFNj9TPgclGttGYh1CiEJRaBTDkQo9RK6N4ESpudydvq1+TR/o/cHaR ZNVM8oWQ/docunS9N3ESvBFm7OUuPZmvOa1zHuM2u30tQ4gnf5eUHnVizruqj6mtRFAfJQc+ 5DYZMczNFfy3eQj/cDwVg2b/zhsY4MCL25HKSUCKldvcEdi3xCW0Erka5XoHsoNmD9kdD+OF NA6YmYV2YTm6jXimjcF3qHbUj4ZshfL8D7AgQTP9hqfmpG5iDOPW0d8AaOjs8+kmJ9PivwPH wSu8jWh38D+CWEl1laPNW3t/AILtSiO6QiFIRyiBMSqPBe0AR9Xc8w== X-Mailgun-Sending-Ip: 209.61.151.224 X-Mailgun-Sid: WyJlMGM5NSIsICJxZW11LWRldmVsQG5vbmdudS5vcmciLCAiOWI0ZTc2Il0= Received: from jonathan-ThinkPad-X1-Carbon.pdos.lcs.mit.edu (26-5-211.dynamic.csail.mit.edu [18.26.5.211]) by mxa.mailgun.org with ESMTP id 5d9bd4de.7f51c380ba28-smtp-out-n01; Tue, 08 Oct 2019 00:14:22 -0000 (UTC) From: Jonathan Behrens To: qemu-devel@nongnu.org, qemu-riscv@nongnu.org Subject: [PATCH v3 1/3] target/riscv: Tell gdbstub the correct number of CSRs Date: Mon, 7 Oct 2019 20:13:16 -0400 Message-Id: <20191008001318.219367-2-jonathan@fintelia.io> X-Mailer: git-send-email 2.23.0 In-Reply-To: <20191008001318.219367-1-jonathan@fintelia.io> References: <20191008001318.219367-1-jonathan@fintelia.io> MIME-Version: 1.0 X-detected-operating-system: by eggs.gnu.org: GNU/Linux 2.2.x-3.x [generic] [fuzzy] X-Received-From: 209.61.151.224 X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Jonathan Behrens , Palmer Dabbelt , Alistair Francis , Sagar Karandikar , Bastian Koppelmann Errors-To: qemu-devel-bounces+patchwork-qemu-devel=patchwork.kernel.org@nongnu.org Sender: "Qemu-devel" If the number of registers reported to the gdbstub code does not match the number in the associated XML file, then the register numbers used by the stub may get out of sync with a remote GDB instance. Signed-off-by: Jonathan Behrens Reviewed-by: Bin Meng Reviewed-by: Alistair Francis --- target/riscv/gdbstub.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/target/riscv/gdbstub.c b/target/riscv/gdbstub.c index ded140e8d8..cb5bfd3d50 100644 --- a/target/riscv/gdbstub.c +++ b/target/riscv/gdbstub.c @@ -384,7 +384,7 @@ void riscv_cpu_register_gdb_regs_for_features(CPUState *cs) } gdb_register_coprocessor(cs, riscv_gdb_get_csr, riscv_gdb_set_csr, - 4096, "riscv-32bit-csr.xml", 0); + 240, "riscv-32bit-csr.xml", 0); #elif defined(TARGET_RISCV64) if (env->misa & RVF) { gdb_register_coprocessor(cs, riscv_gdb_get_fpu, riscv_gdb_set_fpu, @@ -392,6 +392,6 @@ void riscv_cpu_register_gdb_regs_for_features(CPUState *cs) } gdb_register_coprocessor(cs, riscv_gdb_get_csr, riscv_gdb_set_csr, - 4096, "riscv-64bit-csr.xml", 0); + 240, "riscv-64bit-csr.xml", 0); #endif } From patchwork Tue Oct 8 00:13:17 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Jonathan Behrens X-Patchwork-Id: 11178645 Return-Path: Received: from mail.kernel.org (pdx-korg-mail-1.web.codeaurora.org [172.30.200.123]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id CB566139A for ; Tue, 8 Oct 2019 00:19:41 +0000 (UTC) Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id A165820867 for ; Tue, 8 Oct 2019 00:19:41 +0000 (UTC) Authentication-Results: mail.kernel.org; dkim=fail reason="signature verification failed" (2048-bit key) header.d=fintelia.io header.i=@fintelia.io header.b="VAANlhLX" DMARC-Filter: OpenDMARC Filter v1.3.2 mail.kernel.org A165820867 Authentication-Results: mail.kernel.org; dmarc=none (p=none dis=none) header.from=fintelia.io Authentication-Results: mail.kernel.org; spf=pass smtp.mailfrom=qemu-devel-bounces+patchwork-qemu-devel=patchwork.kernel.org@nongnu.org Received: from localhost ([::1]:50274 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1iHdE4-0006i7-Hk for patchwork-qemu-devel@patchwork.kernel.org; Mon, 07 Oct 2019 20:19:40 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:37167) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1iHd92-0002Vb-Ri for qemu-devel@nongnu.org; Mon, 07 Oct 2019 20:14:30 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1iHd91-0005MD-J7 for qemu-devel@nongnu.org; Mon, 07 Oct 2019 20:14:28 -0400 Received: from rs224.mailgun.us ([209.61.151.224]:15755) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1iHd91-0005K8-7B for qemu-devel@nongnu.org; Mon, 07 Oct 2019 20:14:27 -0400 DKIM-Signature: a=rsa-sha256; v=1; c=relaxed/relaxed; d=fintelia.io; q=dns/txt; s=pic; t=1570493667; h=Content-Transfer-Encoding: MIME-Version: References: In-Reply-To: Message-Id: Date: Subject: Cc: To: From: Sender; bh=oBPZgEFOLKTVX1RbYFPu/Z2W49S8279uUe0qDuElOXM=; b=VAANlhLXCgdh92g/nuTRgMYD4I3Dhh+8JxrZY7+CEbSJizqhAFn4pH5Dz9xrpJg/8MgoMydS FRMhKRErgs7px4FRrrq+d0JwNojd7DwjbKBwHVpPKz/wkO5iby5EFGYoULoXH+QdmruIKgQC OlCJj9Rgo4L02wOY2MPazYpQuxifyr3uhujIIynsWGrHRev9iiFDPeksugK0ZWgtCi+OK+eI 1NYVa1eOQ7erANcYd5VLP6QNWjaxyJdfyhM0rIUGRnlQxkooOLUIMYwPMKiJA9JjkrUxt1N4 O3qPAqaUXtEqTmuATYH1Kvoi+S+EaWm0lzDEqEeA0o8+fPXRubnghQ== X-Mailgun-Sending-Ip: 209.61.151.224 X-Mailgun-Sid: WyJlMGM5NSIsICJxZW11LWRldmVsQG5vbmdudS5vcmciLCAiOWI0ZTc2Il0= Received: from jonathan-ThinkPad-X1-Carbon.pdos.lcs.mit.edu (26-5-211.dynamic.csail.mit.edu [18.26.5.211]) by mxa.mailgun.org with ESMTP id 5d9bd4e1.7f51c380ba28-smtp-out-n01; Tue, 08 Oct 2019 00:14:25 -0000 (UTC) From: Jonathan Behrens To: qemu-devel@nongnu.org, qemu-riscv@nongnu.org Subject: [PATCH v3 2/3] target/riscv: Expose priv register for GDB for reads Date: Mon, 7 Oct 2019 20:13:17 -0400 Message-Id: <20191008001318.219367-3-jonathan@fintelia.io> X-Mailer: git-send-email 2.23.0 In-Reply-To: <20191008001318.219367-1-jonathan@fintelia.io> References: <20191008001318.219367-1-jonathan@fintelia.io> MIME-Version: 1.0 X-detected-operating-system: by eggs.gnu.org: GNU/Linux 2.2.x-3.x [generic] [fuzzy] X-Received-From: 209.61.151.224 X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Sagar Karandikar , Jonathan Behrens , Palmer Dabbelt , =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= , Alistair Francis , Bastian Koppelmann , =?utf-8?q?Alex_Benn?= =?utf-8?q?=C3=A9e?= Errors-To: qemu-devel-bounces+patchwork-qemu-devel=patchwork.kernel.org@nongnu.org Sender: "Qemu-devel" This patch enables a debugger to read the current privilege level via a virtual "priv" register. When compiled with CONFIG_USER_ONLY the register is still visible but always reports the value zero. Signed-off-by: Jonathan Behrens --- configure | 4 ++-- gdb-xml/riscv-32bit-virtual.xml | 11 +++++++++++ gdb-xml/riscv-64bit-virtual.xml | 11 +++++++++++ target/riscv/gdbstub.c | 23 +++++++++++++++++++++++ 4 files changed, 47 insertions(+), 2 deletions(-) create mode 100644 gdb-xml/riscv-32bit-virtual.xml create mode 100644 gdb-xml/riscv-64bit-virtual.xml diff --git a/configure b/configure index 30544f52e6..6118a6a045 100755 --- a/configure +++ b/configure @@ -7520,13 +7520,13 @@ case "$target_name" in TARGET_BASE_ARCH=riscv TARGET_ABI_DIR=riscv mttcg=yes - gdb_xml_files="riscv-32bit-cpu.xml riscv-32bit-fpu.xml riscv-32bit-csr.xml" + gdb_xml_files="riscv-32bit-cpu.xml riscv-32bit-fpu.xml riscv-32bit-csr.xml riscv-32bit-virtual.xml" ;; riscv64) TARGET_BASE_ARCH=riscv TARGET_ABI_DIR=riscv mttcg=yes - gdb_xml_files="riscv-64bit-cpu.xml riscv-64bit-fpu.xml riscv-64bit-csr.xml" + gdb_xml_files="riscv-64bit-cpu.xml riscv-64bit-fpu.xml riscv-64bit-csr.xml riscv-64bit-virtual.xml" ;; sh4|sh4eb) TARGET_ARCH=sh4 diff --git a/gdb-xml/riscv-32bit-virtual.xml b/gdb-xml/riscv-32bit-virtual.xml new file mode 100644 index 0000000000..905f1c555d --- /dev/null +++ b/gdb-xml/riscv-32bit-virtual.xml @@ -0,0 +1,11 @@ + + + + + + + diff --git a/gdb-xml/riscv-64bit-virtual.xml b/gdb-xml/riscv-64bit-virtual.xml new file mode 100644 index 0000000000..62d86c237b --- /dev/null +++ b/gdb-xml/riscv-64bit-virtual.xml @@ -0,0 +1,11 @@ + + + + + + + diff --git a/target/riscv/gdbstub.c b/target/riscv/gdbstub.c index cb5bfd3d50..33cf7c4c7d 100644 --- a/target/riscv/gdbstub.c +++ b/target/riscv/gdbstub.c @@ -373,6 +373,23 @@ static int riscv_gdb_set_csr(CPURISCVState *env, uint8_t *mem_buf, int n) return 0; } +static int riscv_gdb_get_virtual(CPURISCVState *cs, uint8_t *mem_buf, int n) +{ + if (n == 0) { +#ifdef CONFIG_USER_ONLY + return gdb_get_regl(mem_buf, 0); +#else + return gdb_get_regl(mem_buf, cs->priv); +#endif + } + return 0; +} + +static int riscv_gdb_set_virtual(CPURISCVState *cs, uint8_t *mem_buf, int n) +{ + return 0; +} + void riscv_cpu_register_gdb_regs_for_features(CPUState *cs) { RISCVCPU *cpu = RISCV_CPU(cs); @@ -385,6 +402,9 @@ void riscv_cpu_register_gdb_regs_for_features(CPUState *cs) gdb_register_coprocessor(cs, riscv_gdb_get_csr, riscv_gdb_set_csr, 240, "riscv-32bit-csr.xml", 0); + + gdb_register_coprocessor(cs, riscv_gdb_get_virtual, riscv_gdb_set_virtual, + 1, "riscv-32bit-csr.xml", 0); #elif defined(TARGET_RISCV64) if (env->misa & RVF) { gdb_register_coprocessor(cs, riscv_gdb_get_fpu, riscv_gdb_set_fpu, @@ -393,5 +413,8 @@ void riscv_cpu_register_gdb_regs_for_features(CPUState *cs) gdb_register_coprocessor(cs, riscv_gdb_get_csr, riscv_gdb_set_csr, 240, "riscv-64bit-csr.xml", 0); + + gdb_register_coprocessor(cs, riscv_gdb_get_virtual, riscv_gdb_set_virtual, + 1, "riscv-64bit-virtual.xml", 0); #endif } From patchwork Tue Oct 8 00:13:18 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Jonathan Behrens X-Patchwork-Id: 11178647 Return-Path: Received: from mail.kernel.org (pdx-korg-mail-1.web.codeaurora.org [172.30.200.123]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id B79EE139A for ; Tue, 8 Oct 2019 00:21:36 +0000 (UTC) Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id 8E57820867 for ; Tue, 8 Oct 2019 00:21:36 +0000 (UTC) Authentication-Results: mail.kernel.org; dkim=fail reason="signature verification failed" (2048-bit key) header.d=fintelia.io header.i=@fintelia.io header.b="zQL2uxkI" DMARC-Filter: OpenDMARC Filter v1.3.2 mail.kernel.org 8E57820867 Authentication-Results: mail.kernel.org; dmarc=none (p=none dis=none) header.from=fintelia.io Authentication-Results: mail.kernel.org; spf=pass smtp.mailfrom=qemu-devel-bounces+patchwork-qemu-devel=patchwork.kernel.org@nongnu.org Received: from localhost ([::1]:50322 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1iHdFv-00013y-QP for patchwork-qemu-devel@patchwork.kernel.org; Mon, 07 Oct 2019 20:21:35 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:37188) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1iHd96-0002Yq-Kr for qemu-devel@nongnu.org; Mon, 07 Oct 2019 20:14:33 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1iHd94-0005NQ-L2 for qemu-devel@nongnu.org; Mon, 07 Oct 2019 20:14:32 -0400 Received: from rs224.mailgun.us ([209.61.151.224]:21472) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1iHd94-0005Gw-4n for qemu-devel@nongnu.org; Mon, 07 Oct 2019 20:14:30 -0400 DKIM-Signature: a=rsa-sha256; v=1; c=relaxed/relaxed; d=fintelia.io; q=dns/txt; s=pic; t=1570493670; h=Content-Transfer-Encoding: MIME-Version: References: In-Reply-To: Message-Id: Date: Subject: Cc: To: From: Sender; bh=0AYrTLQGGVMjJAwteX2M1fMUA+ZMU7mBXK8haObkZGg=; b=zQL2uxkIZj4Do4cfKzu5FyTAK1PIDVYRZuZ/MDR4m1nkX5P8EB9T4e/LVaPxsYI5PwMXiL+o M2BnU8wr+HjSoZsEx9CGwfq6Zuo7Ncyrp9ZgL0CtaJxvlKK005wBkhKkz0IvP/iJDGxX9Jkc 5EfNIx03AC8578FjBDiEA5PLg5/+mYszPG6g0MLGHJyGHOEQgrUlHV/l5cv5MiLkIMxJ8xEY BZwxl7/1mNcX++BCIvYAygLLAdEkSkGDneb2hTejpp2EXR741sdEVawJnYXphcu1WcCfW8nu AQrXsNfxJ57W98p2z3IaM3g0BdBAKTV3jr96UimF4DPBPM42P0l91Q== X-Mailgun-Sending-Ip: 209.61.151.224 X-Mailgun-Sid: WyJlMGM5NSIsICJxZW11LWRldmVsQG5vbmdudS5vcmciLCAiOWI0ZTc2Il0= Received: from jonathan-ThinkPad-X1-Carbon.pdos.lcs.mit.edu (26-5-211.dynamic.csail.mit.edu [18.26.5.211]) by mxa.mailgun.org with ESMTP id 5d9bd4e5.7f51c380ba28-smtp-out-n01; Tue, 08 Oct 2019 00:14:29 -0000 (UTC) From: Jonathan Behrens To: qemu-devel@nongnu.org, qemu-riscv@nongnu.org Subject: [PATCH v3 3/3] target/riscv: Make the priv register writable by GDB Date: Mon, 7 Oct 2019 20:13:18 -0400 Message-Id: <20191008001318.219367-4-jonathan@fintelia.io> X-Mailer: git-send-email 2.23.0 In-Reply-To: <20191008001318.219367-1-jonathan@fintelia.io> References: <20191008001318.219367-1-jonathan@fintelia.io> MIME-Version: 1.0 X-detected-operating-system: by eggs.gnu.org: GNU/Linux 2.2.x-3.x [generic] [fuzzy] X-Received-From: 209.61.151.224 X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Jonathan Behrens , Palmer Dabbelt , Alistair Francis , Sagar Karandikar , Bastian Koppelmann Errors-To: qemu-devel-bounces+patchwork-qemu-devel=patchwork.kernel.org@nongnu.org Sender: "Qemu-devel" Currently only PRV_U, PRV_S and PRV_M are supported, so this patch ensures that the privilege mode is set to one of them. Once support for the H-extension is added, this code will also need to properly update the virtualization status when switching between VU/VS-modes and M-mode. Signed-off-by: Jonathan Behrens Reviewed-by: Bin Meng Tested-by: Bin Meng Reviewed-by: Alistair Francis --- target/riscv/gdbstub.c | 9 +++++++++ 1 file changed, 9 insertions(+) diff --git a/target/riscv/gdbstub.c b/target/riscv/gdbstub.c index 33cf7c4c7d..bc84b599c2 100644 --- a/target/riscv/gdbstub.c +++ b/target/riscv/gdbstub.c @@ -387,6 +387,15 @@ static int riscv_gdb_get_virtual(CPURISCVState *cs, uint8_t *mem_buf, int n) static int riscv_gdb_set_virtual(CPURISCVState *cs, uint8_t *mem_buf, int n) { + if (n == 0) { +#ifndef CONFIG_USER_ONLY + cs->priv = ldtul_p(mem_buf) & 0x3; + if (cs->priv == PRV_H) { + cs->priv = PRV_S; + } +#endif + return sizeof(target_ulong); + } return 0; }