From patchwork Tue Oct 8 11:35:22 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Andrew Jeffery X-Patchwork-Id: 11179437 Return-Path: Received: from mail.kernel.org (pdx-korg-mail-1.web.codeaurora.org [172.30.200.123]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id 8BB991862 for ; Tue, 8 Oct 2019 11:34:32 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.kernel.org (Postfix) with ESMTP id 6BAD520673 for ; Tue, 8 Oct 2019 11:34:32 +0000 (UTC) Authentication-Results: mail.kernel.org; dkim=pass (2048-bit key) header.d=aj.id.au header.i=@aj.id.au header.b="J2bgWrEK"; dkim=pass (2048-bit key) header.d=messagingengine.com header.i=@messagingengine.com header.b="iVEeZKv+" Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1730738AbfJHLe2 (ORCPT ); Tue, 8 Oct 2019 07:34:28 -0400 Received: from out4-smtp.messagingengine.com ([66.111.4.28]:34529 "EHLO out4-smtp.messagingengine.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1730156AbfJHLe2 (ORCPT ); Tue, 8 Oct 2019 07:34:28 -0400 Received: from compute4.internal (compute4.nyi.internal [10.202.2.44]) by mailout.nyi.internal (Postfix) with ESMTP id 795A521947; Tue, 8 Oct 2019 07:34:27 -0400 (EDT) Received: from mailfrontend2 ([10.202.2.163]) by compute4.internal (MEProxy); Tue, 08 Oct 2019 07:34:27 -0400 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=aj.id.au; h=from :to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; s=fm3; bh=FwWI9/MDx5th9 3BPylor5pCFZ4biSV3bwPlyQ31srtU=; b=J2bgWrEKdLiSxVKsQHfspdwIW4M/o nP89ghxsFqU8xdG1vHZvtuDlte3JCnWb2Vs6ztb44LMJdzqWJ9OUs/PZSKNSZKGn EtxlL0cvPj0KCBCaETT5kd+2Fjw89yfLKbPqqwFENYlhJWFZMrSSABZRLO9noHNu vyxfeG+cbMrukkywZvd4u18ZXx31HGQcVL9eLA0B8d7u7MjJSP4hcF/vSwjU4FAF jRLE2oWUPbrZsRf4rvFw6GcPa5Rjip4M1PjgyOu0UfYjjzVceTZBSKxBcn283SmR hz6/6teBWTkmKnIYU59AiV7YHzrkZI2QSEcLhGCgRbW2q5Ufq2gob21sQ== DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d= messagingengine.com; h=cc:content-transfer-encoding:date:from :in-reply-to:message-id:mime-version:references:subject:to :x-me-proxy:x-me-proxy:x-me-sender:x-me-sender:x-sasl-enc; s= fm1; bh=FwWI9/MDx5th93BPylor5pCFZ4biSV3bwPlyQ31srtU=; b=iVEeZKv+ eF+dvDxO9NHd0GbE1lc+WBUkCjWbVlpHWX7Sx8e/ufcDhLOfwuvF21zC9vf4nfo8 HKykZntvU+MAGbRy+dhkOI+Yi6DTAf+hV1egvYfBrfT8EcvjbSgjnqxXw+7dVI32 DwAKZgFYIxxtw4chJegrZX0yNxMCDnJmJ8Kpvo1a8FjQAYV/ojlMmLCbv39nSxI1 uvfa8iyD1UXD2aaQZIz0VIO71Stv5GIwMAobCzaKKDhXqpoqldmQzY9GvAKBuB1T Qhkk1Pu1xfLW7xGKrsJEjAAWJ8/J1wDzascmWgyHwzUWj6sOrTVh4X/eao9kPHm9 2yHVekz4ZXhaXw== X-ME-Sender: X-ME-Proxy-Cause: gggruggvucftvghtrhhoucdtuddrgedufedrheelgdegfecutefuodetggdotefrodftvf curfhrohhfihhlvgemucfhrghsthforghilhdpqfgfvfdpuffrtefokffrpgfnqfghnecu uegrihhlohhuthemuceftddtnecunecujfgurhephffvufffkffojghfggfgsedtkeertd ertddtnecuhfhrohhmpeetnhgurhgvficulfgvfhhfvghrhicuoegrnhgurhgvfiesrghj rdhiugdrrghuqeenucfkphepvddtfedrheejrddvudehrddujeeknecurfgrrhgrmhepmh grihhlfhhrohhmpegrnhgurhgvfiesrghjrdhiugdrrghunecuvehluhhsthgvrhfuihii vgeptd X-ME-Proxy: Received: from mistburn.lan (203-57-215-178.dyn.iinet.net.au [203.57.215.178]) by mail.messagingengine.com (Postfix) with ESMTPA id 8C2EDD6005B; Tue, 8 Oct 2019 07:34:23 -0400 (EDT) From: Andrew Jeffery To: linux-clk@vger.kernel.org Cc: mturquette@baylibre.com, sboyd@kernel.org, joel@jms.id.au, robh+dt@kernel.org, mark.rutland@arm.com, linux-arm-kernel@lists.infradead.org, linux-aspeed@lists.ozlabs.org, linux-kernel@vger.kernel.org, devicetree@vger.kernel.org Subject: [PATCH 1/2] dt-bindings: clock: Add AST2500 RMII RCLK definitions Date: Tue, 8 Oct 2019 22:05:22 +1030 Message-Id: <20191008113523.13601-2-andrew@aj.id.au> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20191008113523.13601-1-andrew@aj.id.au> References: <20191008113523.13601-1-andrew@aj.id.au> MIME-Version: 1.0 Sender: linux-clk-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-clk@vger.kernel.org The AST2500 has an explicit gate for the RMII RCLK for each of the two MACs. Signed-off-by: Andrew Jeffery --- include/dt-bindings/clock/aspeed-clock.h | 2 ++ 1 file changed, 2 insertions(+) diff --git a/include/dt-bindings/clock/aspeed-clock.h b/include/dt-bindings/clock/aspeed-clock.h index f43738607d77..64e245fb113f 100644 --- a/include/dt-bindings/clock/aspeed-clock.h +++ b/include/dt-bindings/clock/aspeed-clock.h @@ -39,6 +39,8 @@ #define ASPEED_CLK_BCLK 33 #define ASPEED_CLK_MPLL 34 #define ASPEED_CLK_24M 35 +#define ASPEED_CLK_GATE_MAC1RCLK 36 +#define ASPEED_CLK_GATE_MAC2RCLK 37 #define ASPEED_RESET_XDMA 0 #define ASPEED_RESET_MCTP 1 From patchwork Tue Oct 8 11:35:23 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Andrew Jeffery X-Patchwork-Id: 11179439 Return-Path: Received: from mail.kernel.org (pdx-korg-mail-1.web.codeaurora.org [172.30.200.123]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id 7E58917D4 for ; Tue, 8 Oct 2019 11:34:38 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.kernel.org (Postfix) with ESMTP id 5EBC92173B for ; Tue, 8 Oct 2019 11:34:38 +0000 (UTC) Authentication-Results: mail.kernel.org; dkim=pass (2048-bit key) header.d=aj.id.au header.i=@aj.id.au header.b="dIgBzduc"; dkim=pass (2048-bit key) header.d=messagingengine.com header.i=@messagingengine.com header.b="Mvlrt3Tc" Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1730317AbfJHLeh (ORCPT ); Tue, 8 Oct 2019 07:34:37 -0400 Received: from out4-smtp.messagingengine.com ([66.111.4.28]:35657 "EHLO out4-smtp.messagingengine.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1730683AbfJHLed (ORCPT ); Tue, 8 Oct 2019 07:34:33 -0400 Received: from compute4.internal (compute4.nyi.internal [10.202.2.44]) by mailout.nyi.internal (Postfix) with ESMTP id C46B221AF1; Tue, 8 Oct 2019 07:34:31 -0400 (EDT) Received: from mailfrontend2 ([10.202.2.163]) by compute4.internal (MEProxy); Tue, 08 Oct 2019 07:34:31 -0400 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=aj.id.au; h=from :to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; s=fm3; bh=IomXpyVOXZ8Uv 1dPMisUUdf86QeS1crpf/LOXGB55i0=; b=dIgBzducLtm3bjO9Leg5vJzPwNDZA tD3kxhrpI+XDTH4bNxgAYJb23dsHyzJQAp39K5TEMP5ilJjObK5wkBZSHea6mEwh 7sHbTuw0IAUCD1bwZ1sJpvgpa0qYvcuWrdhkEFw6/NMXuDHmLuiaCtGj+JwZtTrq +RLvW1+ampAFaghMuHzTuFTVAxdzW7XBGTLGT2AAAEmzZSa9zuMdsXpXlZr2Ntfh Fd/iPM+vS2aE2HyFSvVmAggOcYYcrK9hoZ/Xf6VEsgvyyWJEA7uAIX0NenHQ65Gr xr/AvWCpg/ayCkerE0ULc8NwwIU9Ri774XG4V8zsF+g53MJ1HkQUy3lFA== DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d= messagingengine.com; h=cc:content-transfer-encoding:date:from :in-reply-to:message-id:mime-version:references:subject:to :x-me-proxy:x-me-proxy:x-me-sender:x-me-sender:x-sasl-enc; s= fm1; bh=IomXpyVOXZ8Uv1dPMisUUdf86QeS1crpf/LOXGB55i0=; b=Mvlrt3Tc WpZePURq8P27c6YFdUo8xibi6zt7wN4rHEOGaZEThpmYXOiSpyrQa234C8KBcsf5 DgzLwtorIZykfr+ZrPFz6vOrwuY6+8nMBdvZErHf19D5eYt6vq7kebUz6QVq1Rv5 0gFDl6jekAXvkUMRc1DuqVe36k1q8LKQeo1k3Su0xPRz/AccWukw4wgYqtee9C+U tG7Uy+v6Rex3bJeqGLLF1IBIQzSxIpZvq8ruFLUvHfM/1CK1BwdLF4ywOA8d6kJv Xv0LYoF+3sdy+OwQjj77YBj975e8TwaH6DsW1GOovL0EVm+Atm1ecshlX16GHqga SKKp4f1l0lEA8w== X-ME-Sender: X-ME-Proxy-Cause: gggruggvucftvghtrhhoucdtuddrgedufedrheelgdegfecutefuodetggdotefrodftvf curfhrohhfihhlvgemucfhrghsthforghilhdpqfgfvfdpuffrtefokffrpgfnqfghnecu uegrihhlohhuthemuceftddtnecunecujfgurhephffvufffkffojghfggfgsedtkeertd ertddtnecuhfhrohhmpeetnhgurhgvficulfgvfhhfvghrhicuoegrnhgurhgvfiesrghj rdhiugdrrghuqeenucfkphepvddtfedrheejrddvudehrddujeeknecurfgrrhgrmhepmh grihhlfhhrohhmpegrnhgurhgvfiesrghjrdhiugdrrghunecuvehluhhsthgvrhfuihii vgepud X-ME-Proxy: Received: from mistburn.lan (203-57-215-178.dyn.iinet.net.au [203.57.215.178]) by mail.messagingengine.com (Postfix) with ESMTPA id E1EBCD6005B; Tue, 8 Oct 2019 07:34:27 -0400 (EDT) From: Andrew Jeffery To: linux-clk@vger.kernel.org Cc: mturquette@baylibre.com, sboyd@kernel.org, joel@jms.id.au, robh+dt@kernel.org, mark.rutland@arm.com, linux-arm-kernel@lists.infradead.org, linux-aspeed@lists.ozlabs.org, linux-kernel@vger.kernel.org, devicetree@vger.kernel.org Subject: [PATCH 2/2] clk: aspeed: Add RMII RCLK gates for both AST2500 MACs Date: Tue, 8 Oct 2019 22:05:23 +1030 Message-Id: <20191008113523.13601-3-andrew@aj.id.au> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20191008113523.13601-1-andrew@aj.id.au> References: <20191008113523.13601-1-andrew@aj.id.au> MIME-Version: 1.0 Sender: linux-clk-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-clk@vger.kernel.org RCLK is a fixed 50MHz clock derived from HPLL that is described by a single gate for each MAC. Signed-off-by: Andrew Jeffery --- drivers/clk/clk-aspeed.c | 27 ++++++++++++++++++++++++++- 1 file changed, 26 insertions(+), 1 deletion(-) diff --git a/drivers/clk/clk-aspeed.c b/drivers/clk/clk-aspeed.c index abf06fb6453e..867d8771bb1e 100644 --- a/drivers/clk/clk-aspeed.c +++ b/drivers/clk/clk-aspeed.c @@ -14,7 +14,7 @@ #include "clk-aspeed.h" -#define ASPEED_NUM_CLKS 36 +#define ASPEED_NUM_CLKS 38 #define ASPEED_RESET2_OFFSET 32 @@ -28,6 +28,7 @@ #define AST2400_HPLL_BYPASS_EN BIT(17) #define ASPEED_MISC_CTRL 0x2c #define UART_DIV13_EN BIT(12) +#define ASPEED_MAC_CLK_DLY 0x48 #define ASPEED_STRAP 0x70 #define CLKIN_25MHZ_EN BIT(23) #define AST2400_CLK_SOURCE_SEL BIT(18) @@ -462,6 +463,30 @@ static int aspeed_clk_probe(struct platform_device *pdev) return PTR_ERR(hw); aspeed_clk_data->hws[ASPEED_CLK_MAC] = hw; + if (of_device_is_compatible(pdev->dev.of_node, "aspeed,ast2500-scu")) { + /* RMII 50MHz RCLK */ + hw = clk_hw_register_fixed_rate(dev, "mac12rclk", "hpll", 0, + 50000000); + if (IS_ERR(hw)) + return PTR_ERR(hw); + + /* RMII1 50MHz (RCLK) output enable */ + hw = clk_hw_register_gate(dev, "mac1rclk-gate", "mac12rclk", 0, + scu_base + ASPEED_MAC_CLK_DLY, 29, 0, + &aspeed_clk_lock); + if (IS_ERR(hw)) + return PTR_ERR(hw); + aspeed_clk_data->hws[ASPEED_CLK_GATE_MAC1RCLK] = hw; + + /* RMII2 50MHz (RCLK) output enable */ + hw = clk_hw_register_gate(dev, "mac2rclk-gate", "mac12rclk", 0, + scu_base + ASPEED_MAC_CLK_DLY, 30, 0, + &aspeed_clk_lock); + if (IS_ERR(hw)) + return PTR_ERR(hw); + aspeed_clk_data->hws[ASPEED_CLK_GATE_MAC2RCLK] = hw; + } + /* LPC Host (LHCLK) clock divider */ hw = clk_hw_register_divider_table(dev, "lhclk", "hpll", 0, scu_base + ASPEED_CLK_SELECTION, 20, 3, 0,