From patchwork Fri Oct 11 20:09:42 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?b?VmlsbGUgU3lyasOkbMOk?= X-Patchwork-Id: 11186325 Return-Path: Received: from mail.kernel.org (pdx-korg-mail-1.web.codeaurora.org [172.30.200.123]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id B4B8115AB for ; Fri, 11 Oct 2019 20:09:57 +0000 (UTC) Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id 9CCEF214E0 for ; Fri, 11 Oct 2019 20:09:57 +0000 (UTC) DMARC-Filter: OpenDMARC Filter v1.3.2 mail.kernel.org 9CCEF214E0 Authentication-Results: mail.kernel.org; dmarc=fail (p=none dis=none) header.from=linux.intel.com Authentication-Results: mail.kernel.org; spf=none smtp.mailfrom=intel-gfx-bounces@lists.freedesktop.org Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id CF5726EC8E; Fri, 11 Oct 2019 20:09:56 +0000 (UTC) X-Original-To: intel-gfx@lists.freedesktop.org Delivered-To: intel-gfx@lists.freedesktop.org Received: from mga01.intel.com (mga01.intel.com [192.55.52.88]) by gabe.freedesktop.org (Postfix) with ESMTPS id C83556EC8E for ; Fri, 11 Oct 2019 20:09:55 +0000 (UTC) X-Amp-Result: SKIPPED(no attachment in message) X-Amp-File-Uploaded: False Received: from fmsmga001.fm.intel.com ([10.253.24.23]) by fmsmga101.fm.intel.com with ESMTP/TLS/DHE-RSA-AES256-GCM-SHA384; 11 Oct 2019 13:09:55 -0700 X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.67,285,1566889200"; d="scan'208";a="207501256" Received: from stinkbox.fi.intel.com (HELO stinkbox) ([10.237.72.174]) by fmsmga001.fm.intel.com with SMTP; 11 Oct 2019 13:09:53 -0700 Received: by stinkbox (sSMTP sendmail emulation); Fri, 11 Oct 2019 23:09:52 +0300 From: Ville Syrjala To: intel-gfx@lists.freedesktop.org Date: Fri, 11 Oct 2019 23:09:42 +0300 Message-Id: <20191011200949.7839-2-ville.syrjala@linux.intel.com> X-Mailer: git-send-email 2.21.0 In-Reply-To: <20191011200949.7839-1-ville.syrjala@linux.intel.com> References: <20191011200949.7839-1-ville.syrjala@linux.intel.com> MIME-Version: 1.0 Subject: [Intel-gfx] [PATCH 1/8] drm/i915: Nuke the useless changed param from skl_ddb_add_affected_pipes() X-BeenThere: intel-gfx@lists.freedesktop.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: Intel graphics driver community testing & development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: intel-gfx-bounces@lists.freedesktop.org Sender: "Intel-gfx" From: Ville Syrjälä changed==true just means we have some crtcs in the state. All the stuff following this only operates on crtcs in the state anyway so there is no point in having this bool. Signed-off-by: Ville Syrjälä Reviewed-by: Stanislav Lisovskiy --- drivers/gpu/drm/i915/intel_pm.c | 30 ++++-------------------------- 1 file changed, 4 insertions(+), 26 deletions(-) diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c index b306e2338f5a..49568270a89d 100644 --- a/drivers/gpu/drm/i915/intel_pm.c +++ b/drivers/gpu/drm/i915/intel_pm.c @@ -5424,35 +5424,14 @@ skl_print_wm_changes(struct intel_atomic_state *state) } static int -skl_ddb_add_affected_pipes(struct intel_atomic_state *state, bool *changed) +skl_ddb_add_affected_pipes(struct intel_atomic_state *state) { struct drm_device *dev = state->base.dev; const struct drm_i915_private *dev_priv = to_i915(dev); struct intel_crtc *crtc; struct intel_crtc_state *crtc_state; u32 realloc_pipes = pipes_modified(state); - int ret, i; - - /* - * When we distrust bios wm we always need to recompute to set the - * expected DDB allocations for each CRTC. - */ - if (dev_priv->wm.distrust_bios_wm) - (*changed) = true; - - /* - * If this transaction isn't actually touching any CRTC's, don't - * bother with watermark calculation. Note that if we pass this - * test, we're guaranteed to hold at least one CRTC state mutex, - * which means we can safely use values like dev_priv->active_pipes - * since any racing commits that want to update them would need to - * hold _all_ CRTC state mutexes. - */ - for_each_new_intel_crtc_in_state(state, crtc, crtc_state, i) - (*changed) = true; - - if (!*changed) - return 0; + int ret; /* * If this is our first atomic update following hardware readout, @@ -5576,14 +5555,13 @@ skl_compute_wm(struct intel_atomic_state *state) struct intel_crtc_state *new_crtc_state; struct intel_crtc_state *old_crtc_state; struct skl_ddb_values *results = &state->wm_results; - bool changed = false; int ret, i; /* Clear all dirty flags */ results->dirty_pipes = 0; - ret = skl_ddb_add_affected_pipes(state, &changed); - if (ret || !changed) + ret = skl_ddb_add_affected_pipes(state); + if (ret) return ret; /* From patchwork Fri Oct 11 20:09:43 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?b?VmlsbGUgU3lyasOkbMOk?= X-Patchwork-Id: 11186327 Return-Path: Received: from mail.kernel.org (pdx-korg-mail-1.web.codeaurora.org [172.30.200.123]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id DE30E139A for ; Fri, 11 Oct 2019 20:10:00 +0000 (UTC) Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id C6BF321835 for ; Fri, 11 Oct 2019 20:10:00 +0000 (UTC) DMARC-Filter: OpenDMARC Filter v1.3.2 mail.kernel.org C6BF321835 Authentication-Results: mail.kernel.org; dmarc=fail (p=none dis=none) header.from=linux.intel.com Authentication-Results: mail.kernel.org; spf=none smtp.mailfrom=intel-gfx-bounces@lists.freedesktop.org Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id 55DF46EC8F; Fri, 11 Oct 2019 20:10:00 +0000 (UTC) X-Original-To: intel-gfx@lists.freedesktop.org Delivered-To: intel-gfx@lists.freedesktop.org Received: from mga05.intel.com (mga05.intel.com [192.55.52.43]) by gabe.freedesktop.org (Postfix) with ESMTPS id C69436EC8F for ; Fri, 11 Oct 2019 20:09:59 +0000 (UTC) X-Amp-Result: SKIPPED(no attachment in message) X-Amp-File-Uploaded: False Received: from orsmga002.jf.intel.com ([10.7.209.21]) by fmsmga105.fm.intel.com with ESMTP/TLS/DHE-RSA-AES256-GCM-SHA384; 11 Oct 2019 13:09:59 -0700 X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.67,285,1566889200"; d="scan'208";a="206552258" Received: from stinkbox.fi.intel.com (HELO stinkbox) ([10.237.72.174]) by orsmga002.jf.intel.com with SMTP; 11 Oct 2019 13:09:56 -0700 Received: by stinkbox (sSMTP sendmail emulation); Fri, 11 Oct 2019 23:09:55 +0300 From: Ville Syrjala To: intel-gfx@lists.freedesktop.org Date: Fri, 11 Oct 2019 23:09:43 +0300 Message-Id: <20191011200949.7839-3-ville.syrjala@linux.intel.com> X-Mailer: git-send-email 2.21.0 In-Reply-To: <20191011200949.7839-1-ville.syrjala@linux.intel.com> References: <20191011200949.7839-1-ville.syrjala@linux.intel.com> MIME-Version: 1.0 Subject: [Intel-gfx] [PATCH 2/8] drm/i915: Nuke 'realloc_pipes' X-BeenThere: intel-gfx@lists.freedesktop.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: Intel graphics driver community testing & development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: intel-gfx-bounces@lists.freedesktop.org Sender: "Intel-gfx" From: Ville Syrjälä The 'realloc_pipes' bitmask is pointless. It is either: a) the set of pipes which are already part of the state, in which case adding them again is entirely redundant b) the set of all pipes which we then add to the state Also the fact that 'realloc_pipes' uses the crtc indexes is going to bite is at some point so best get rid of it quick. Signed-off-by: Ville Syrjälä Reviewed-by: Stanislav Lisovskiy --- drivers/gpu/drm/i915/intel_pm.c | 50 ++++++++++++++------------------- 1 file changed, 21 insertions(+), 29 deletions(-) diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c index 49568270a89d..3536c2e975e7 100644 --- a/drivers/gpu/drm/i915/intel_pm.c +++ b/drivers/gpu/drm/i915/intel_pm.c @@ -5235,19 +5235,6 @@ bool skl_ddb_allocation_overlaps(const struct skl_ddb_entry *ddb, return false; } -static u32 -pipes_modified(struct intel_atomic_state *state) -{ - struct intel_crtc *crtc; - struct intel_crtc_state *crtc_state; - u32 i, ret = 0; - - for_each_new_intel_crtc_in_state(state, crtc, crtc_state, i) - ret |= drm_crtc_mask(&crtc->base); - - return ret; -} - static int skl_ddb_add_affected_planes(const struct intel_crtc_state *old_crtc_state, struct intel_crtc_state *new_crtc_state) @@ -5423,14 +5410,26 @@ skl_print_wm_changes(struct intel_atomic_state *state) } } +static int intel_add_all_pipes(struct intel_atomic_state *state) +{ + struct drm_i915_private *dev_priv = to_i915(state->base.dev); + struct intel_crtc *crtc; + + for_each_intel_crtc(&dev_priv->drm, crtc) { + struct intel_crtc_state *crtc_state; + + crtc_state = intel_atomic_get_crtc_state(&state->base, crtc); + if (IS_ERR(crtc_state)) + return PTR_ERR(crtc_state); + } + + return 0; +} + static int skl_ddb_add_affected_pipes(struct intel_atomic_state *state) { - struct drm_device *dev = state->base.dev; - const struct drm_i915_private *dev_priv = to_i915(dev); - struct intel_crtc *crtc; - struct intel_crtc_state *crtc_state; - u32 realloc_pipes = pipes_modified(state); + struct drm_i915_private *dev_priv = to_i915(state->base.dev); int ret; /* @@ -5440,7 +5439,7 @@ skl_ddb_add_affected_pipes(struct intel_atomic_state *state) * ensure a full DDB recompute. */ if (dev_priv->wm.distrust_bios_wm) { - ret = drm_modeset_lock(&dev->mode_config.connection_mutex, + ret = drm_modeset_lock(&dev_priv->drm.mode_config.connection_mutex, state->base.acquire_ctx); if (ret) return ret; @@ -5471,18 +5470,11 @@ skl_ddb_add_affected_pipes(struct intel_atomic_state *state) * to grab the lock on *all* CRTC's. */ if (state->active_pipe_changes || state->modeset) { - realloc_pipes = ~0; state->wm_results.dirty_pipes = ~0; - } - /* - * We're not recomputing for the pipes not included in the commit, so - * make sure we start with the current state. - */ - for_each_intel_crtc_mask(dev, crtc, realloc_pipes) { - crtc_state = intel_atomic_get_crtc_state(&state->base, crtc); - if (IS_ERR(crtc_state)) - return PTR_ERR(crtc_state); + ret = intel_add_all_pipes(state); + if (ret) + return ret; } return 0; From patchwork Fri Oct 11 20:09:44 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?b?VmlsbGUgU3lyasOkbMOk?= X-Patchwork-Id: 11186329 Return-Path: Received: from mail.kernel.org (pdx-korg-mail-1.web.codeaurora.org [172.30.200.123]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id 7250915AB for ; Fri, 11 Oct 2019 20:10:05 +0000 (UTC) Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id 5A376214E0 for ; Fri, 11 Oct 2019 20:10:05 +0000 (UTC) DMARC-Filter: OpenDMARC Filter v1.3.2 mail.kernel.org 5A376214E0 Authentication-Results: mail.kernel.org; dmarc=fail (p=none dis=none) header.from=linux.intel.com Authentication-Results: mail.kernel.org; spf=none smtp.mailfrom=intel-gfx-bounces@lists.freedesktop.org Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id 886286EC91; Fri, 11 Oct 2019 20:10:04 +0000 (UTC) X-Original-To: intel-gfx@lists.freedesktop.org Delivered-To: intel-gfx@lists.freedesktop.org Received: from mga09.intel.com (mga09.intel.com [134.134.136.24]) by gabe.freedesktop.org (Postfix) with ESMTPS id 714C86EC91 for ; Fri, 11 Oct 2019 20:10:03 +0000 (UTC) X-Amp-Result: SKIPPED(no attachment in message) X-Amp-File-Uploaded: False Received: from fmsmga007.fm.intel.com ([10.253.24.52]) by orsmga102.jf.intel.com with ESMTP/TLS/DHE-RSA-AES256-GCM-SHA384; 11 Oct 2019 13:10:02 -0700 X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.67,285,1566889200"; d="scan'208";a="194433880" Received: from stinkbox.fi.intel.com (HELO stinkbox) ([10.237.72.174]) by fmsmga007.fm.intel.com with SMTP; 11 Oct 2019 13:10:00 -0700 Received: by stinkbox (sSMTP sendmail emulation); Fri, 11 Oct 2019 23:09:59 +0300 From: Ville Syrjala To: intel-gfx@lists.freedesktop.org Date: Fri, 11 Oct 2019 23:09:44 +0300 Message-Id: <20191011200949.7839-4-ville.syrjala@linux.intel.com> X-Mailer: git-send-email 2.21.0 In-Reply-To: <20191011200949.7839-1-ville.syrjala@linux.intel.com> References: <20191011200949.7839-1-ville.syrjala@linux.intel.com> MIME-Version: 1.0 Subject: [Intel-gfx] [PATCH 3/8] drm/i915: Make dirty_pipes refer to pipes X-BeenThere: intel-gfx@lists.freedesktop.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: Intel graphics driver community testing & development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: intel-gfx-bounces@lists.freedesktop.org Sender: "Intel-gfx" From: Ville Syrjälä Despite the its name dirty_pipes refers to crtc indexes. Let's change its behaviout to match the name. Signed-off-by: Ville Syrjälä Reviewed-by: Stanislav Lisovskiy --- drivers/gpu/drm/i915/display/intel_display.c | 9 +++------ drivers/gpu/drm/i915/intel_pm.c | 13 ++++++------- 2 files changed, 9 insertions(+), 13 deletions(-) diff --git a/drivers/gpu/drm/i915/display/intel_display.c b/drivers/gpu/drm/i915/display/intel_display.c index a146ec02a0c1..b9b51bd0c956 100644 --- a/drivers/gpu/drm/i915/display/intel_display.c +++ b/drivers/gpu/drm/i915/display/intel_display.c @@ -13883,7 +13883,6 @@ static void skl_commit_modeset_enables(struct intel_atomic_state *state) struct intel_crtc_state *old_crtc_state, *new_crtc_state; unsigned int updated = 0; bool progress; - enum pipe pipe; int i; u8 hw_enabled_slices = dev_priv->wm.skl_hw.ddb.enabled_slices; u8 required_slices = state->wm_results.ddb.enabled_slices; @@ -13908,12 +13907,10 @@ static void skl_commit_modeset_enables(struct intel_atomic_state *state) progress = false; for_each_oldnew_intel_crtc_in_state(state, crtc, old_crtc_state, new_crtc_state, i) { + enum pipe pipe = crtc->pipe; bool vbl_wait = false; - unsigned int cmask = drm_crtc_mask(&crtc->base); - - pipe = crtc->pipe; - if (updated & cmask || !new_crtc_state->base.active) + if (updated & BIT(crtc->pipe) || !new_crtc_state->base.active) continue; if (skl_ddb_allocation_overlaps(&new_crtc_state->wm.skl.ddb, @@ -13921,7 +13918,7 @@ static void skl_commit_modeset_enables(struct intel_atomic_state *state) INTEL_NUM_PIPES(dev_priv), i)) continue; - updated |= cmask; + updated |= BIT(pipe); entries[i] = new_crtc_state->wm.skl.ddb; /* diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c index 3536c2e975e7..2b71d52a4ede 100644 --- a/drivers/gpu/drm/i915/intel_pm.c +++ b/drivers/gpu/drm/i915/intel_pm.c @@ -5575,7 +5575,7 @@ skl_compute_wm(struct intel_atomic_state *state) if (!skl_pipe_wm_equals(crtc, &old_crtc_state->wm.skl.optimal, &new_crtc_state->wm.skl.optimal)) - results->dirty_pipes |= drm_crtc_mask(&crtc->base); + results->dirty_pipes |= BIT(crtc->pipe); } ret = skl_compute_ddb(state); @@ -5595,7 +5595,7 @@ static void skl_atomic_update_crtc_wm(struct intel_atomic_state *state, struct skl_pipe_wm *pipe_wm = &crtc_state->wm.skl.optimal; enum pipe pipe = crtc->pipe; - if (!(state->wm_results.dirty_pipes & drm_crtc_mask(&crtc->base))) + if ((state->wm_results.dirty_pipes & BIT(crtc->pipe)) == 0) return; I915_WRITE(PIPE_WM_LINETIME(pipe), pipe_wm->linetime); @@ -5604,12 +5604,11 @@ static void skl_atomic_update_crtc_wm(struct intel_atomic_state *state, static void skl_initial_wm(struct intel_atomic_state *state, struct intel_crtc_state *crtc_state) { - struct intel_crtc *intel_crtc = to_intel_crtc(crtc_state->base.crtc); - struct drm_device *dev = intel_crtc->base.dev; - struct drm_i915_private *dev_priv = to_i915(dev); + struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc); + struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); struct skl_ddb_values *results = &state->wm_results; - if ((results->dirty_pipes & drm_crtc_mask(&intel_crtc->base)) == 0) + if ((results->dirty_pipes & BIT(crtc->pipe)) == 0) return; mutex_lock(&dev_priv->wm.wm_mutex); @@ -5758,7 +5757,7 @@ void skl_wm_get_hw_state(struct drm_i915_private *dev_priv) skl_pipe_wm_get_hw_state(crtc, &crtc_state->wm.skl.optimal); if (crtc->active) - hw->dirty_pipes |= drm_crtc_mask(&crtc->base); + hw->dirty_pipes |= BIT(crtc->pipe); } if (dev_priv->active_pipes) { From patchwork Fri Oct 11 20:09:45 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?b?VmlsbGUgU3lyasOkbMOk?= X-Patchwork-Id: 11186331 Return-Path: Received: from mail.kernel.org (pdx-korg-mail-1.web.codeaurora.org [172.30.200.123]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id B6D5615AB for ; Fri, 11 Oct 2019 20:10:08 +0000 (UTC) Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id 9F65721835 for ; Fri, 11 Oct 2019 20:10:08 +0000 (UTC) DMARC-Filter: OpenDMARC Filter v1.3.2 mail.kernel.org 9F65721835 Authentication-Results: mail.kernel.org; dmarc=fail (p=none dis=none) header.from=linux.intel.com Authentication-Results: mail.kernel.org; spf=none smtp.mailfrom=intel-gfx-bounces@lists.freedesktop.org Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id 3D04D6EC95; Fri, 11 Oct 2019 20:10:08 +0000 (UTC) X-Original-To: intel-gfx@lists.freedesktop.org Delivered-To: intel-gfx@lists.freedesktop.org Received: from mga03.intel.com (mga03.intel.com [134.134.136.65]) by gabe.freedesktop.org (Postfix) with ESMTPS id 845CC6EC95 for ; Fri, 11 Oct 2019 20:10:06 +0000 (UTC) X-Amp-Result: SKIPPED(no attachment in message) X-Amp-File-Uploaded: False Received: from orsmga001.jf.intel.com ([10.7.209.18]) by orsmga103.jf.intel.com with ESMTP/TLS/DHE-RSA-AES256-GCM-SHA384; 11 Oct 2019 13:10:05 -0700 X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.67,285,1566889200"; d="scan'208";a="278232084" Received: from stinkbox.fi.intel.com (HELO stinkbox) ([10.237.72.174]) by orsmga001.jf.intel.com with SMTP; 11 Oct 2019 13:10:03 -0700 Received: by stinkbox (sSMTP sendmail emulation); Fri, 11 Oct 2019 23:10:03 +0300 From: Ville Syrjala To: intel-gfx@lists.freedesktop.org Date: Fri, 11 Oct 2019 23:09:45 +0300 Message-Id: <20191011200949.7839-5-ville.syrjala@linux.intel.com> X-Mailer: git-send-email 2.21.0 In-Reply-To: <20191011200949.7839-1-ville.syrjala@linux.intel.com> References: <20191011200949.7839-1-ville.syrjala@linux.intel.com> MIME-Version: 1.0 Subject: [Intel-gfx] [PATCH 4/8] drm/i915: Don't set undefined bits in dirty_pipes X-BeenThere: intel-gfx@lists.freedesktop.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: Intel graphics driver community testing & development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: intel-gfx-bounces@lists.freedesktop.org Sender: "Intel-gfx" From: Ville Syrjälä skl_commit_modeset_enables() straight up compares dirty_pipes with a bitmask of already committed pipes. If we set bits in dirty_pipes for non-existent pipes that comparison will never work right. So let's limit ourselves to bits that exist. And we'll do the same for the active_pipes_changed bitmask. Signed-off-by: Ville Syrjälä Reviewed-by: Stanislav Lisovskiy --- drivers/gpu/drm/i915/intel_pm.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c index 2b71d52a4ede..f21eb9250d23 100644 --- a/drivers/gpu/drm/i915/intel_pm.c +++ b/drivers/gpu/drm/i915/intel_pm.c @@ -5444,7 +5444,7 @@ skl_ddb_add_affected_pipes(struct intel_atomic_state *state) if (ret) return ret; - state->active_pipe_changes = ~0; + state->active_pipe_changes = INTEL_INFO(dev_priv)->pipe_mask; /* * We usually only initialize state->active_pipes if we @@ -5470,7 +5470,7 @@ skl_ddb_add_affected_pipes(struct intel_atomic_state *state) * to grab the lock on *all* CRTC's. */ if (state->active_pipe_changes || state->modeset) { - state->wm_results.dirty_pipes = ~0; + state->wm_results.dirty_pipes = INTEL_INFO(dev_priv)->pipe_mask; ret = intel_add_all_pipes(state); if (ret) From patchwork Fri Oct 11 20:09:46 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?b?VmlsbGUgU3lyasOkbMOk?= X-Patchwork-Id: 11186333 Return-Path: Received: from mail.kernel.org (pdx-korg-mail-1.web.codeaurora.org [172.30.200.123]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id EC286139A for ; Fri, 11 Oct 2019 20:10:11 +0000 (UTC) Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id D4C7F222C5 for ; Fri, 11 Oct 2019 20:10:11 +0000 (UTC) DMARC-Filter: OpenDMARC Filter v1.3.2 mail.kernel.org D4C7F222C5 Authentication-Results: mail.kernel.org; dmarc=fail (p=none dis=none) header.from=linux.intel.com Authentication-Results: mail.kernel.org; spf=none smtp.mailfrom=intel-gfx-bounces@lists.freedesktop.org Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id 6D6DF6EC9A; Fri, 11 Oct 2019 20:10:11 +0000 (UTC) X-Original-To: intel-gfx@lists.freedesktop.org Delivered-To: intel-gfx@lists.freedesktop.org Received: from mga02.intel.com (mga02.intel.com [134.134.136.20]) by gabe.freedesktop.org (Postfix) with ESMTPS id B1B326EC9A for ; Fri, 11 Oct 2019 20:10:09 +0000 (UTC) X-Amp-Result: SKIPPED(no attachment in message) X-Amp-File-Uploaded: False Received: from orsmga006.jf.intel.com ([10.7.209.51]) by orsmga101.jf.intel.com with ESMTP/TLS/DHE-RSA-AES256-GCM-SHA384; 11 Oct 2019 13:10:09 -0700 X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.67,285,1566889200"; d="scan'208";a="198802730" Received: from stinkbox.fi.intel.com (HELO stinkbox) ([10.237.72.174]) by orsmga006.jf.intel.com with SMTP; 11 Oct 2019 13:10:06 -0700 Received: by stinkbox (sSMTP sendmail emulation); Fri, 11 Oct 2019 23:10:06 +0300 From: Ville Syrjala To: intel-gfx@lists.freedesktop.org Date: Fri, 11 Oct 2019 23:09:46 +0300 Message-Id: <20191011200949.7839-6-ville.syrjala@linux.intel.com> X-Mailer: git-send-email 2.21.0 In-Reply-To: <20191011200949.7839-1-ville.syrjala@linux.intel.com> References: <20191011200949.7839-1-ville.syrjala@linux.intel.com> MIME-Version: 1.0 Subject: [Intel-gfx] [PATCH 5/8] drm/i915: Streamline skl_commit_modeset_enables() X-BeenThere: intel-gfx@lists.freedesktop.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: Intel graphics driver community testing & development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: intel-gfx-bounces@lists.freedesktop.org Sender: "Intel-gfx" From: Ville Syrjälä skl_commit_modeset_enables() is a bit of mess. Let's streamline it by simply tracking which pipes still need to be updated. As a bonus we get rid of the state->wm_results.dirty_pipes usage. Signed-off-by: Ville Syrjälä Reviewed-by: Stanislav Lisovskiy --- drivers/gpu/drm/i915/display/intel_display.c | 39 +++++++++----------- 1 file changed, 17 insertions(+), 22 deletions(-) diff --git a/drivers/gpu/drm/i915/display/intel_display.c b/drivers/gpu/drm/i915/display/intel_display.c index b9b51bd0c956..9eab67bbf61d 100644 --- a/drivers/gpu/drm/i915/display/intel_display.c +++ b/drivers/gpu/drm/i915/display/intel_display.c @@ -13881,17 +13881,19 @@ static void skl_commit_modeset_enables(struct intel_atomic_state *state) struct drm_i915_private *dev_priv = to_i915(state->base.dev); struct intel_crtc *crtc; struct intel_crtc_state *old_crtc_state, *new_crtc_state; - unsigned int updated = 0; - bool progress; - int i; u8 hw_enabled_slices = dev_priv->wm.skl_hw.ddb.enabled_slices; u8 required_slices = state->wm_results.ddb.enabled_slices; struct skl_ddb_entry entries[I915_MAX_PIPES] = {}; + u8 dirty_pipes = 0; + int i; - for_each_oldnew_intel_crtc_in_state(state, crtc, old_crtc_state, new_crtc_state, i) + for_each_oldnew_intel_crtc_in_state(state, crtc, old_crtc_state, new_crtc_state, i) { /* ignore allocations for crtc's that have been turned off. */ - if (new_crtc_state->base.active) + if (new_crtc_state->base.active) { entries[i] = old_crtc_state->wm.skl.ddb; + dirty_pipes |= BIT(crtc->pipe); + } + } /* If 2nd DBuf slice required, enable it here */ if (INTEL_GEN(dev_priv) >= 11 && required_slices > hw_enabled_slices) @@ -13903,14 +13905,12 @@ static void skl_commit_modeset_enables(struct intel_atomic_state *state) * never overlap with eachother inbetween CRTC updates. Otherwise we'll * cause pipe underruns and other bad stuff. */ - do { - progress = false; - - for_each_oldnew_intel_crtc_in_state(state, crtc, old_crtc_state, new_crtc_state, i) { + while (dirty_pipes) { + for_each_oldnew_intel_crtc_in_state(state, crtc, old_crtc_state, + new_crtc_state, i) { enum pipe pipe = crtc->pipe; - bool vbl_wait = false; - if (updated & BIT(crtc->pipe) || !new_crtc_state->base.active) + if ((dirty_pipes & BIT(pipe)) == 0) continue; if (skl_ddb_allocation_overlaps(&new_crtc_state->wm.skl.ddb, @@ -13918,8 +13918,11 @@ static void skl_commit_modeset_enables(struct intel_atomic_state *state) INTEL_NUM_PIPES(dev_priv), i)) continue; - updated |= BIT(pipe); entries[i] = new_crtc_state->wm.skl.ddb; + dirty_pipes &= ~BIT(pipe); + + intel_update_crtc(crtc, state, old_crtc_state, + new_crtc_state); /* * If this is an already active pipe, it's DDB changed, @@ -13930,18 +13933,10 @@ static void skl_commit_modeset_enables(struct intel_atomic_state *state) if (!skl_ddb_entry_equal(&new_crtc_state->wm.skl.ddb, &old_crtc_state->wm.skl.ddb) && !new_crtc_state->base.active_changed && - state->wm_results.dirty_pipes != updated) - vbl_wait = true; - - intel_update_crtc(crtc, state, old_crtc_state, - new_crtc_state); - - if (vbl_wait) + dirty_pipes) intel_wait_for_vblank(dev_priv, pipe); - - progress = true; } - } while (progress); + } /* If 2nd DBuf slice is no more required disable it */ if (INTEL_GEN(dev_priv) >= 11 && required_slices < hw_enabled_slices) From patchwork Fri Oct 11 20:09:47 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?b?VmlsbGUgU3lyasOkbMOk?= X-Patchwork-Id: 11186337 Return-Path: Received: from mail.kernel.org (pdx-korg-mail-1.web.codeaurora.org [172.30.200.123]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id 21DBB15AB for ; Fri, 11 Oct 2019 20:10:14 +0000 (UTC) Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id 0A99921835 for ; Fri, 11 Oct 2019 20:10:14 +0000 (UTC) DMARC-Filter: OpenDMARC Filter v1.3.2 mail.kernel.org 0A99921835 Authentication-Results: mail.kernel.org; dmarc=fail (p=none dis=none) header.from=linux.intel.com Authentication-Results: mail.kernel.org; spf=none smtp.mailfrom=intel-gfx-bounces@lists.freedesktop.org Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id 92D7C6ECA1; Fri, 11 Oct 2019 20:10:13 +0000 (UTC) X-Original-To: intel-gfx@lists.freedesktop.org Delivered-To: intel-gfx@lists.freedesktop.org Received: from mga06.intel.com (mga06.intel.com [134.134.136.31]) by gabe.freedesktop.org (Postfix) with ESMTPS id DA16F6EC9D for ; Fri, 11 Oct 2019 20:10:12 +0000 (UTC) X-Amp-Result: SKIPPED(no attachment in message) X-Amp-File-Uploaded: False Received: from fmsmga002.fm.intel.com ([10.253.24.26]) by orsmga104.jf.intel.com with ESMTP/TLS/DHE-RSA-AES256-GCM-SHA384; 11 Oct 2019 13:10:12 -0700 X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.67,285,1566889200"; d="scan'208";a="224443733" Received: from stinkbox.fi.intel.com (HELO stinkbox) ([10.237.72.174]) by fmsmga002.fm.intel.com with SMTP; 11 Oct 2019 13:10:10 -0700 Received: by stinkbox (sSMTP sendmail emulation); Fri, 11 Oct 2019 23:10:09 +0300 From: Ville Syrjala To: intel-gfx@lists.freedesktop.org Date: Fri, 11 Oct 2019 23:09:47 +0300 Message-Id: <20191011200949.7839-7-ville.syrjala@linux.intel.com> X-Mailer: git-send-email 2.21.0 In-Reply-To: <20191011200949.7839-1-ville.syrjala@linux.intel.com> References: <20191011200949.7839-1-ville.syrjala@linux.intel.com> MIME-Version: 1.0 Subject: [Intel-gfx] [PATCH 6/8] drm/i915: Polish WM_LINETIME register stuff X-BeenThere: intel-gfx@lists.freedesktop.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: Intel graphics driver community testing & development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: intel-gfx-bounces@lists.freedesktop.org Sender: "Intel-gfx" From: Ville Syrjälä Let's store the normal and IPS linetime watermarks individually, and while at it we'll pimp the register definitions as well. Signed-off-by: Ville Syrjälä --- .../drm/i915/display/intel_display_types.h | 3 +- drivers/gpu/drm/i915/i915_reg.h | 14 ++-- drivers/gpu/drm/i915/intel_pm.c | 72 ++++++++++--------- 3 files changed, 49 insertions(+), 40 deletions(-) diff --git a/drivers/gpu/drm/i915/display/intel_display_types.h b/drivers/gpu/drm/i915/display/intel_display_types.h index 40390d855815..841952332c7e 100644 --- a/drivers/gpu/drm/i915/display/intel_display_types.h +++ b/drivers/gpu/drm/i915/display/intel_display_types.h @@ -631,7 +631,8 @@ struct intel_crtc_scaler_state { struct intel_pipe_wm { struct intel_wm_level wm[5]; - u32 linetime; + u16 linetime; + u16 ips_linetime; bool fbc_wm_enabled; bool pipe_enabled; bool sprites_enabled; diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h index 0fb9030b89f1..e1db85768084 100644 --- a/drivers/gpu/drm/i915/i915_reg.h +++ b/drivers/gpu/drm/i915/i915_reg.h @@ -10394,13 +10394,13 @@ enum skl_power_gate { #define D_COMP_COMP_DISABLE (1 << 0) /* Pipe WM_LINETIME - watermark line time */ -#define _PIPE_WM_LINETIME_A 0x45270 -#define _PIPE_WM_LINETIME_B 0x45274 -#define PIPE_WM_LINETIME(pipe) _MMIO_PIPE(pipe, _PIPE_WM_LINETIME_A, _PIPE_WM_LINETIME_B) -#define PIPE_WM_LINETIME_MASK (0x1ff) -#define PIPE_WM_LINETIME_TIME(x) ((x)) -#define PIPE_WM_LINETIME_IPS_LINETIME_MASK (0x1ff << 16) -#define PIPE_WM_LINETIME_IPS_LINETIME(x) ((x) << 16) +#define _WM_LINETIME_A 0x45270 +#define _WM_LINETIME_B 0x45274 +#define WM_LINETIME(pipe) _MMIO_PIPE(pipe, _WM_LINETIME_A, _WM_LINETIME_B) +#define HSW_LINETIME_MASK REG_GENMASK(8, 0) +#define HSW_LINETIME(x) REG_FIELD_PREP(HSW_LINETIME_MASK, (x)) +#define HSW_IPS_LINETIME_MASK REG_GENMASK(24, 16) +#define HSW_IPS_LINETIME(x) REG_FIELD_PREP(HSW_IPS_LINETIME_MASK, (x)) /* SFUSE_STRAP */ #define SFUSE_STRAP _MMIO(0xc2014) diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c index f21eb9250d23..f6893b771078 100644 --- a/drivers/gpu/drm/i915/intel_pm.c +++ b/drivers/gpu/drm/i915/intel_pm.c @@ -2764,31 +2764,31 @@ static void ilk_compute_wm_level(const struct drm_i915_private *dev_priv, } static u32 -hsw_compute_linetime_wm(const struct intel_crtc_state *crtc_state) +hsw_linetime_wm(const struct intel_crtc_state *crtc_state) { - const struct intel_atomic_state *intel_state = - to_intel_atomic_state(crtc_state->base.state); const struct drm_display_mode *adjusted_mode = &crtc_state->base.adjusted_mode; - u32 linetime, ips_linetime; if (!crtc_state->base.active) return 0; - if (WARN_ON(adjusted_mode->crtc_clock == 0)) - return 0; - if (WARN_ON(intel_state->cdclk.logical.cdclk == 0)) - return 0; - /* The WM are computed with base on how long it takes to fill a single - * row at the given clock rate, multiplied by 8. - * */ - linetime = DIV_ROUND_CLOSEST(adjusted_mode->crtc_htotal * 1000 * 8, - adjusted_mode->crtc_clock); - ips_linetime = DIV_ROUND_CLOSEST(adjusted_mode->crtc_htotal * 1000 * 8, - intel_state->cdclk.logical.cdclk); + return DIV_ROUND_CLOSEST(adjusted_mode->crtc_htotal * 1000 * 8, + adjusted_mode->crtc_clock); +} + +static u32 +hsw_ips_linetime_wm(const struct intel_crtc_state *crtc_state) +{ + const struct intel_atomic_state *state = + to_intel_atomic_state(crtc_state->base.state); + const struct drm_display_mode *adjusted_mode = + &crtc_state->base.adjusted_mode; - return PIPE_WM_LINETIME_IPS_LINETIME(ips_linetime) | - PIPE_WM_LINETIME_TIME(linetime); + if (!crtc_state->base.active) + return 0; + + return DIV_ROUND_CLOSEST(adjusted_mode->crtc_htotal * 1000 * 8, + state->cdclk.logical.cdclk); } static void intel_read_wm_latency(struct drm_i915_private *dev_priv, @@ -3128,8 +3128,10 @@ static int ilk_compute_pipe_wm(struct intel_crtc_state *crtc_state) ilk_compute_wm_level(dev_priv, intel_crtc, 0, crtc_state, pristate, sprstate, curstate, &pipe_wm->wm[0]); - if (IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv)) - pipe_wm->linetime = hsw_compute_linetime_wm(crtc_state); + if (IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv)) { + pipe_wm->linetime = hsw_linetime_wm(crtc_state); + pipe_wm->ips_linetime = hsw_ips_linetime_wm(crtc_state); + } if (!ilk_validate_pipe_wm(dev_priv, pipe_wm)) return -EINVAL; @@ -3329,7 +3331,7 @@ static void ilk_compute_wm_results(struct drm_i915_private *dev_priv, enum intel_ddb_partitioning partitioning, struct ilk_wm_values *results) { - struct intel_crtc *intel_crtc; + struct intel_crtc *crtc; int level, wm_lp; results->enable_fbc_wm = merged->fbc_wm_enabled; @@ -3374,15 +3376,17 @@ static void ilk_compute_wm_results(struct drm_i915_private *dev_priv, } /* LP0 register values */ - for_each_intel_crtc(&dev_priv->drm, intel_crtc) { - enum pipe pipe = intel_crtc->pipe; - const struct intel_wm_level *r = - &intel_crtc->wm.active.ilk.wm[0]; + for_each_intel_crtc(&dev_priv->drm, crtc) { + enum pipe pipe = crtc->pipe; + const struct intel_pipe_wm *pipe_wm = &crtc->wm.active.ilk; + const struct intel_wm_level *r = &pipe_wm->wm[0]; if (WARN_ON(!r->enable)) continue; - results->wm_linetime[pipe] = intel_crtc->wm.active.ilk.linetime; + results->wm_linetime[pipe] = + HSW_LINETIME(pipe_wm->linetime) | + HSW_IPS_LINETIME(pipe_wm->ips_linetime); results->wm_pipe[pipe] = (r->pri_val << WM0_PIPE_PLANE_SHIFT) | @@ -3535,11 +3539,11 @@ static void ilk_write_wm_values(struct drm_i915_private *dev_priv, I915_WRITE(WM0_PIPEC_IVB, results->wm_pipe[2]); if (dirty & WM_DIRTY_LINETIME(PIPE_A)) - I915_WRITE(PIPE_WM_LINETIME(PIPE_A), results->wm_linetime[0]); + I915_WRITE(WM_LINETIME(PIPE_A), results->wm_linetime[0]); if (dirty & WM_DIRTY_LINETIME(PIPE_B)) - I915_WRITE(PIPE_WM_LINETIME(PIPE_B), results->wm_linetime[1]); + I915_WRITE(WM_LINETIME(PIPE_B), results->wm_linetime[1]); if (dirty & WM_DIRTY_LINETIME(PIPE_C)) - I915_WRITE(PIPE_WM_LINETIME(PIPE_C), results->wm_linetime[2]); + I915_WRITE(WM_LINETIME(PIPE_C), results->wm_linetime[2]); if (dirty & WM_DIRTY_DDB) { if (IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv)) { @@ -5598,7 +5602,7 @@ static void skl_atomic_update_crtc_wm(struct intel_atomic_state *state, if ((state->wm_results.dirty_pipes & BIT(crtc->pipe)) == 0) return; - I915_WRITE(PIPE_WM_LINETIME(pipe), pipe_wm->linetime); + I915_WRITE(WM_LINETIME(pipe), HSW_LINETIME(pipe_wm->linetime)); } static void skl_initial_wm(struct intel_atomic_state *state, @@ -5740,7 +5744,8 @@ void skl_pipe_wm_get_hw_state(struct intel_crtc *crtc, if (!crtc->active) return; - out->linetime = I915_READ(PIPE_WM_LINETIME(pipe)); + val = I915_READ(WM_LINETIME(pipe)); + out->linetime = REG_FIELD_GET(HSW_LINETIME_MASK, val); } void skl_wm_get_hw_state(struct drm_i915_private *dev_priv) @@ -5782,7 +5787,7 @@ static void ilk_pipe_wm_get_hw_state(struct intel_crtc *crtc) hw->wm_pipe[pipe] = I915_READ(wm0_pipe_reg[pipe]); if (IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv)) - hw->wm_linetime[pipe] = I915_READ(PIPE_WM_LINETIME(pipe)); + hw->wm_linetime[pipe] = I915_READ(WM_LINETIME(pipe)); memset(active, 0, sizeof(*active)); @@ -5801,7 +5806,10 @@ static void ilk_pipe_wm_get_hw_state(struct intel_crtc *crtc) active->wm[0].pri_val = (tmp & WM0_PIPE_PLANE_MASK) >> WM0_PIPE_PLANE_SHIFT; active->wm[0].spr_val = (tmp & WM0_PIPE_SPRITE_MASK) >> WM0_PIPE_SPRITE_SHIFT; active->wm[0].cur_val = tmp & WM0_PIPE_CURSOR_MASK; - active->linetime = hw->wm_linetime[pipe]; + active->linetime = REG_FIELD_GET(HSW_LINETIME_MASK, + hw->wm_linetime[pipe]); + active->ips_linetime = REG_FIELD_GET(HSW_IPS_LINETIME_MASK, + hw->wm_linetime[pipe]); } else { int level, max_level = ilk_wm_max_level(dev_priv); From patchwork Fri Oct 11 20:09:48 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?b?VmlsbGUgU3lyasOkbMOk?= X-Patchwork-Id: 11186341 Return-Path: Received: from mail.kernel.org (pdx-korg-mail-1.web.codeaurora.org [172.30.200.123]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id CB569139A for ; Fri, 11 Oct 2019 20:10:17 +0000 (UTC) Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id B068721D7F for ; Fri, 11 Oct 2019 20:10:17 +0000 (UTC) DMARC-Filter: OpenDMARC Filter v1.3.2 mail.kernel.org B068721D7F Authentication-Results: mail.kernel.org; dmarc=fail (p=none dis=none) header.from=linux.intel.com Authentication-Results: mail.kernel.org; spf=none smtp.mailfrom=intel-gfx-bounces@lists.freedesktop.org Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id 3730F6EC94; Fri, 11 Oct 2019 20:10:17 +0000 (UTC) X-Original-To: intel-gfx@lists.freedesktop.org Delivered-To: intel-gfx@lists.freedesktop.org Received: from mga05.intel.com (mga05.intel.com [192.55.52.43]) by gabe.freedesktop.org (Postfix) with ESMTPS id 04E5C6EC9D for ; Fri, 11 Oct 2019 20:10:15 +0000 (UTC) X-Amp-Result: SKIPPED(no attachment in message) X-Amp-File-Uploaded: False Received: from orsmga008.jf.intel.com ([10.7.209.65]) by fmsmga105.fm.intel.com with ESMTP/TLS/DHE-RSA-AES256-GCM-SHA384; 11 Oct 2019 13:10:15 -0700 X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.67,285,1566889200"; d="scan'208";a="188418340" Received: from stinkbox.fi.intel.com (HELO stinkbox) ([10.237.72.174]) by orsmga008.jf.intel.com with SMTP; 11 Oct 2019 13:10:13 -0700 Received: by stinkbox (sSMTP sendmail emulation); Fri, 11 Oct 2019 23:10:12 +0300 From: Ville Syrjala To: intel-gfx@lists.freedesktop.org Date: Fri, 11 Oct 2019 23:09:48 +0300 Message-Id: <20191011200949.7839-8-ville.syrjala@linux.intel.com> X-Mailer: git-send-email 2.21.0 In-Reply-To: <20191011200949.7839-1-ville.syrjala@linux.intel.com> References: <20191011200949.7839-1-ville.syrjala@linux.intel.com> MIME-Version: 1.0 Subject: [Intel-gfx] [PATCH 7/8] drm/i915: Move linetime wms into the crtc state X-BeenThere: intel-gfx@lists.freedesktop.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: Intel graphics driver community testing & development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: intel-gfx-bounces@lists.freedesktop.org Sender: "Intel-gfx" From: Ville Syrjälä The linetime watermarks really have very little in common with the plane watermarks. It looks to be cleaner to simply track them in the crtc_state and program them from the normal modeset/fastset paths. The only dark cloud comes from the fact that the register is still supposedly single buffered. So in theory it might still need some form of two stage programming. Note that even though HSW/BDWhave two stage programming we never computed any special intermediate values for the linetime watermarks, and on SKL+ we don't even have the two stage stuff plugged in since everything else is double buffered. So let's assume it's all fine and continue doing what we've been doing. Actually on HSW/BDW the value should not even change without a full modeset since it doesn't account for pfit downscaling. Thus only fastboot might be affected. But on SKL+ the pfit scaling factor is take into consideration so the value may change during any fastset. As a bonus we'll plug this thing into the state checker/dump now. Signed-off-by: Ville Syrjälä --- drivers/gpu/drm/i915/display/intel_display.c | 94 +++++++++++++- .../drm/i915/display/intel_display_types.h | 7 +- drivers/gpu/drm/i915/i915_drv.h | 1 - drivers/gpu/drm/i915/intel_pm.c | 116 +----------------- 4 files changed, 97 insertions(+), 121 deletions(-) diff --git a/drivers/gpu/drm/i915/display/intel_display.c b/drivers/gpu/drm/i915/display/intel_display.c index 9eab67bbf61d..3eb6f337dff0 100644 --- a/drivers/gpu/drm/i915/display/intel_display.c +++ b/drivers/gpu/drm/i915/display/intel_display.c @@ -6397,6 +6397,16 @@ static void icl_pipe_mbus_enable(struct intel_crtc *crtc) I915_WRITE(PIPE_MBUS_DBOX_CTL(pipe), val); } +static void hsw_set_linetime_wm(const struct intel_crtc_state *crtc_state) +{ + struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc); + struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); + + I915_WRITE(WM_LINETIME(crtc->pipe), + HSW_LINETIME(crtc_state->linetime) | + HSW_IPS_LINETIME(crtc_state->linetime)); +} + static void haswell_crtc_enable(struct intel_crtc_state *pipe_config, struct intel_atomic_state *state) { @@ -6465,6 +6475,8 @@ static void haswell_crtc_enable(struct intel_crtc_state *pipe_config, if (INTEL_GEN(dev_priv) < 9) intel_disable_primary_plane(pipe_config); + hsw_set_linetime_wm(pipe_config); + if (INTEL_GEN(dev_priv) >= 11) icl_set_pipe_chicken(intel_crtc); @@ -10401,6 +10413,7 @@ static bool haswell_get_pipe_config(struct intel_crtc *crtc, enum intel_display_power_domain power_domain; u64 power_domain_mask; bool active; + u32 tmp; intel_crtc_init_scalers(crtc, pipe_config); @@ -10464,7 +10477,7 @@ static bool haswell_get_pipe_config(struct intel_crtc *crtc, pipe_config->csc_mode = I915_READ(PIPE_CSC_MODE(crtc->pipe)); if (INTEL_GEN(dev_priv) >= 9) { - u32 tmp = I915_READ(SKL_BOTTOM_COLOR(crtc->pipe)); + tmp = I915_READ(SKL_BOTTOM_COLOR(crtc->pipe)); if (tmp & SKL_BOTTOM_COLOR_GAMMA_ENABLE) pipe_config->gamma_enable = true; @@ -10477,6 +10490,12 @@ static bool haswell_get_pipe_config(struct intel_crtc *crtc, intel_color_get_config(pipe_config); + tmp = I915_READ(WM_LINETIME(crtc->pipe)); + pipe_config->linetime = REG_FIELD_GET(HSW_LINETIME_MASK, tmp); + if (IS_BROADWELL(dev_priv) || IS_HASWELL(dev_priv)) + pipe_config->ips_linetime = + REG_FIELD_GET(HSW_IPS_LINETIME_MASK, tmp); + power_domain = POWER_DOMAIN_PIPE_PANEL_FITTER(crtc->pipe); WARN_ON(power_domain_mask & BIT_ULL(power_domain)); @@ -11784,6 +11803,53 @@ static bool c8_planes_changed(const struct intel_crtc_state *new_crtc_state) return !old_crtc_state->c8_planes != !new_crtc_state->c8_planes; } +static u16 hsw_linetime_wm(const struct intel_crtc_state *crtc_state) +{ + const struct drm_display_mode *adjusted_mode = + &crtc_state->base.adjusted_mode; + + if (!crtc_state->base.enable) + return 0; + + return DIV_ROUND_CLOSEST(adjusted_mode->crtc_htotal * 1000 * 8, + adjusted_mode->crtc_clock); +} + +static u16 hsw_ips_linetime_wm(const struct intel_crtc_state *crtc_state) +{ + const struct intel_atomic_state *state = + to_intel_atomic_state(crtc_state->base.state); + const struct drm_display_mode *adjusted_mode = + &crtc_state->base.adjusted_mode; + + if (!crtc_state->base.enable) + return 0; + + return DIV_ROUND_CLOSEST(adjusted_mode->crtc_htotal * 1000 * 8, + state->cdclk.logical.cdclk); +} + +static u16 skl_linetime_wm(const struct intel_crtc_state *crtc_state) +{ + struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc); + struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); + const struct drm_display_mode *adjusted_mode = + &crtc_state->base.adjusted_mode; + u16 linetime_wm; + + if (!crtc_state->base.enable) + return 0; + + linetime_wm = DIV_ROUND_UP(adjusted_mode->crtc_htotal * 1000 * 8, + crtc_state->pixel_rate); + + /* Display WA #1135: BXT:ALL GLK:ALL */ + if (IS_GEN9_LP(dev_priv) && dev_priv->ipc_enabled) + linetime_wm /= 2; + + return linetime_wm; +} + static int intel_crtc_atomic_check(struct drm_crtc *_crtc, struct drm_crtc_state *_crtc_state) { @@ -11861,6 +11927,13 @@ static int intel_crtc_atomic_check(struct drm_crtc *_crtc, if (HAS_IPS(dev_priv)) crtc_state->ips_enabled = hsw_compute_ips_config(crtc_state); + if (INTEL_GEN(dev_priv) >= 9) { + crtc_state->linetime = skl_linetime_wm(crtc_state); + } else if (IS_BROADWELL(dev_priv) || IS_HASWELL(dev_priv)) { + crtc_state->linetime = hsw_linetime_wm(crtc_state); + crtc_state->ips_linetime = hsw_ips_linetime_wm(crtc_state); + } + return ret; } @@ -12154,6 +12227,9 @@ static void intel_dump_pipe_config(const struct intel_crtc_state *pipe_config, pipe_config->pipe_src_w, pipe_config->pipe_src_h, pipe_config->pixel_rate); + DRM_DEBUG_KMS("linetime: %d, ips linetime: %d\n", + pipe_config->linetime, pipe_config->ips_linetime); + if (INTEL_GEN(dev_priv) >= 9) DRM_DEBUG_KMS("num_scalers: %d, scaler_users: 0x%x, scaler_id: %d\n", crtc->num_scalers, @@ -12836,10 +12912,12 @@ intel_pipe_config_compare(const struct intel_crtc_state *current_config, PIPE_CONF_CHECK_BOOL(gamma_enable); PIPE_CONF_CHECK_BOOL(csc_enable); + PIPE_CONF_CHECK_I(linetime); + PIPE_CONF_CHECK_I(ips_linetime); + bp_gamma = intel_color_get_gamma_bit_precision(pipe_config); if (bp_gamma) PIPE_CONF_CHECK_COLOR_LUT(gamma_mode, base.gamma_lut, bp_gamma); - } PIPE_CONF_CHECK_BOOL(double_wide); @@ -13711,6 +13789,18 @@ static void intel_pipe_fastset(const struct intel_crtc_state *old_crtc_state, ironlake_pfit_disable(old_crtc_state); } + /* + * The register is supposedly single buffered so perhaps + * not 100% correct to do this here. But SKL+ calculate + * this based on the adjust pixel rate so pfit changes do + * affect it and so it must be updated for fastsets. + * HSW/BDW only really need this here for fastboot, after + * that the value should not change without a full modeset. + */ + if (INTEL_GEN(dev_priv) >= 9 || + IS_BROADWELL(dev_priv) || IS_HASWELL(dev_priv)) + hsw_set_linetime_wm(new_crtc_state); + if (INTEL_GEN(dev_priv) >= 11) icl_set_pipe_chicken(crtc); } diff --git a/drivers/gpu/drm/i915/display/intel_display_types.h b/drivers/gpu/drm/i915/display/intel_display_types.h index 841952332c7e..9b606e507778 100644 --- a/drivers/gpu/drm/i915/display/intel_display_types.h +++ b/drivers/gpu/drm/i915/display/intel_display_types.h @@ -631,8 +631,6 @@ struct intel_crtc_scaler_state { struct intel_pipe_wm { struct intel_wm_level wm[5]; - u16 linetime; - u16 ips_linetime; bool fbc_wm_enabled; bool pipe_enabled; bool sprites_enabled; @@ -648,7 +646,6 @@ struct skl_plane_wm { struct skl_pipe_wm { struct skl_plane_wm planes[I915_MAX_PLANES]; - u32 linetime; }; enum vlv_wm_level { @@ -990,6 +987,10 @@ struct intel_crtc_state { } dsc_params; struct drm_dsc_config dp_dsc_cfg; + /* HSW+ linetime watermarks */ + u16 linetime; + u16 ips_linetime; + /* Forward Error correction State */ bool fec_enable; }; diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h index c46b339064c0..eba9055c4405 100644 --- a/drivers/gpu/drm/i915/i915_drv.h +++ b/drivers/gpu/drm/i915/i915_drv.h @@ -842,7 +842,6 @@ struct ilk_wm_values { u32 wm_pipe[3]; u32 wm_lp[3]; u32 wm_lp_spr[3]; - u32 wm_linetime[3]; bool enable_fbc_wm; enum intel_ddb_partitioning partitioning; }; diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c index f6893b771078..390d1f8d45ba 100644 --- a/drivers/gpu/drm/i915/intel_pm.c +++ b/drivers/gpu/drm/i915/intel_pm.c @@ -2763,34 +2763,6 @@ static void ilk_compute_wm_level(const struct drm_i915_private *dev_priv, result->enable = true; } -static u32 -hsw_linetime_wm(const struct intel_crtc_state *crtc_state) -{ - const struct drm_display_mode *adjusted_mode = - &crtc_state->base.adjusted_mode; - - if (!crtc_state->base.active) - return 0; - - return DIV_ROUND_CLOSEST(adjusted_mode->crtc_htotal * 1000 * 8, - adjusted_mode->crtc_clock); -} - -static u32 -hsw_ips_linetime_wm(const struct intel_crtc_state *crtc_state) -{ - const struct intel_atomic_state *state = - to_intel_atomic_state(crtc_state->base.state); - const struct drm_display_mode *adjusted_mode = - &crtc_state->base.adjusted_mode; - - if (!crtc_state->base.active) - return 0; - - return DIV_ROUND_CLOSEST(adjusted_mode->crtc_htotal * 1000 * 8, - state->cdclk.logical.cdclk); -} - static void intel_read_wm_latency(struct drm_i915_private *dev_priv, u16 wm[8]) { @@ -3128,11 +3100,6 @@ static int ilk_compute_pipe_wm(struct intel_crtc_state *crtc_state) ilk_compute_wm_level(dev_priv, intel_crtc, 0, crtc_state, pristate, sprstate, curstate, &pipe_wm->wm[0]); - if (IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv)) { - pipe_wm->linetime = hsw_linetime_wm(crtc_state); - pipe_wm->ips_linetime = hsw_ips_linetime_wm(crtc_state); - } - if (!ilk_validate_pipe_wm(dev_priv, pipe_wm)) return -EINVAL; @@ -3384,10 +3351,6 @@ static void ilk_compute_wm_results(struct drm_i915_private *dev_priv, if (WARN_ON(!r->enable)) continue; - results->wm_linetime[pipe] = - HSW_LINETIME(pipe_wm->linetime) | - HSW_IPS_LINETIME(pipe_wm->ips_linetime); - results->wm_pipe[pipe] = (r->pri_val << WM0_PIPE_PLANE_SHIFT) | (r->spr_val << WM0_PIPE_SPRITE_SHIFT) | @@ -3426,7 +3389,6 @@ ilk_find_best_result(struct drm_i915_private *dev_priv, /* dirty bits used to track which watermarks need changes */ #define WM_DIRTY_PIPE(pipe) (1 << (pipe)) -#define WM_DIRTY_LINETIME(pipe) (1 << (8 + (pipe))) #define WM_DIRTY_LP(wm_lp) (1 << (15 + (wm_lp))) #define WM_DIRTY_LP_ALL (WM_DIRTY_LP(1) | WM_DIRTY_LP(2) | WM_DIRTY_LP(3)) #define WM_DIRTY_FBC (1 << 24) @@ -3441,12 +3403,6 @@ static unsigned int ilk_compute_wm_dirty(struct drm_i915_private *dev_priv, int wm_lp; for_each_pipe(dev_priv, pipe) { - if (old->wm_linetime[pipe] != new->wm_linetime[pipe]) { - dirty |= WM_DIRTY_LINETIME(pipe); - /* Must disable LP1+ watermarks too */ - dirty |= WM_DIRTY_LP_ALL; - } - if (old->wm_pipe[pipe] != new->wm_pipe[pipe]) { dirty |= WM_DIRTY_PIPE(pipe); /* Must disable LP1+ watermarks too */ @@ -3538,13 +3494,6 @@ static void ilk_write_wm_values(struct drm_i915_private *dev_priv, if (dirty & WM_DIRTY_PIPE(PIPE_C)) I915_WRITE(WM0_PIPEC_IVB, results->wm_pipe[2]); - if (dirty & WM_DIRTY_LINETIME(PIPE_A)) - I915_WRITE(WM_LINETIME(PIPE_A), results->wm_linetime[0]); - if (dirty & WM_DIRTY_LINETIME(PIPE_B)) - I915_WRITE(WM_LINETIME(PIPE_B), results->wm_linetime[1]); - if (dirty & WM_DIRTY_LINETIME(PIPE_C)) - I915_WRITE(WM_LINETIME(PIPE_C), results->wm_linetime[2]); - if (dirty & WM_DIRTY_DDB) { if (IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv)) { val = I915_READ(WM_MISC); @@ -4884,24 +4833,6 @@ skl_compute_wm_levels(const struct intel_crtc_state *crtc_state, } } -static u32 -skl_compute_linetime_wm(const struct intel_crtc_state *crtc_state) -{ - struct drm_atomic_state *state = crtc_state->base.state; - struct drm_i915_private *dev_priv = to_i915(state->dev); - uint_fixed_16_16_t linetime_us; - u32 linetime_wm; - - linetime_us = intel_get_linetime_us(crtc_state); - linetime_wm = fixed16_to_u32_round_up(mul_u32_fixed16(8, linetime_us)); - - /* Display WA #1135: BXT:ALL GLK:ALL */ - if (IS_GEN9_LP(dev_priv) && dev_priv->ipc_enabled) - linetime_wm /= 2; - - return linetime_wm; -} - static void skl_compute_transition_wm(const struct intel_crtc_state *crtc_state, const struct skl_wm_params *wp, struct skl_plane_wm *wm) @@ -5089,8 +5020,6 @@ static int skl_build_pipe_wm(struct intel_crtc_state *crtc_state) return ret; } - pipe_wm->linetime = skl_compute_linetime_wm(crtc_state); - return 0; } @@ -5215,7 +5144,7 @@ static bool skl_pipe_wm_equals(struct intel_crtc *crtc, return false; } - return wm1->linetime == wm2->linetime; + return true; } static inline bool skl_ddb_entries_overlap(const struct skl_ddb_entry *a, @@ -5591,38 +5520,6 @@ skl_compute_wm(struct intel_atomic_state *state) return 0; } -static void skl_atomic_update_crtc_wm(struct intel_atomic_state *state, - struct intel_crtc_state *crtc_state) -{ - struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc); - struct drm_i915_private *dev_priv = to_i915(state->base.dev); - struct skl_pipe_wm *pipe_wm = &crtc_state->wm.skl.optimal; - enum pipe pipe = crtc->pipe; - - if ((state->wm_results.dirty_pipes & BIT(crtc->pipe)) == 0) - return; - - I915_WRITE(WM_LINETIME(pipe), HSW_LINETIME(pipe_wm->linetime)); -} - -static void skl_initial_wm(struct intel_atomic_state *state, - struct intel_crtc_state *crtc_state) -{ - struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc); - struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); - struct skl_ddb_values *results = &state->wm_results; - - if ((results->dirty_pipes & BIT(crtc->pipe)) == 0) - return; - - mutex_lock(&dev_priv->wm.wm_mutex); - - if (crtc_state->base.active_changed) - skl_atomic_update_crtc_wm(state, crtc_state); - - mutex_unlock(&dev_priv->wm.wm_mutex); -} - static void ilk_compute_wm_config(struct drm_i915_private *dev_priv, struct intel_wm_config *config) { @@ -5743,9 +5640,6 @@ void skl_pipe_wm_get_hw_state(struct intel_crtc *crtc, if (!crtc->active) return; - - val = I915_READ(WM_LINETIME(pipe)); - out->linetime = REG_FIELD_GET(HSW_LINETIME_MASK, val); } void skl_wm_get_hw_state(struct drm_i915_private *dev_priv) @@ -5786,8 +5680,6 @@ static void ilk_pipe_wm_get_hw_state(struct intel_crtc *crtc) }; hw->wm_pipe[pipe] = I915_READ(wm0_pipe_reg[pipe]); - if (IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv)) - hw->wm_linetime[pipe] = I915_READ(WM_LINETIME(pipe)); memset(active, 0, sizeof(*active)); @@ -5806,10 +5698,6 @@ static void ilk_pipe_wm_get_hw_state(struct intel_crtc *crtc) active->wm[0].pri_val = (tmp & WM0_PIPE_PLANE_MASK) >> WM0_PIPE_PLANE_SHIFT; active->wm[0].spr_val = (tmp & WM0_PIPE_SPRITE_MASK) >> WM0_PIPE_SPRITE_SHIFT; active->wm[0].cur_val = tmp & WM0_PIPE_CURSOR_MASK; - active->linetime = REG_FIELD_GET(HSW_LINETIME_MASK, - hw->wm_linetime[pipe]); - active->ips_linetime = REG_FIELD_GET(HSW_IPS_LINETIME_MASK, - hw->wm_linetime[pipe]); } else { int level, max_level = ilk_wm_max_level(dev_priv); @@ -8993,8 +8881,6 @@ void intel_init_pm(struct drm_i915_private *dev_priv) /* For FIFO watermark updates */ if (INTEL_GEN(dev_priv) >= 9) { skl_setup_wm_latency(dev_priv); - dev_priv->display.initial_watermarks = skl_initial_wm; - dev_priv->display.atomic_update_watermarks = skl_atomic_update_crtc_wm; dev_priv->display.compute_global_watermarks = skl_compute_wm; } else if (HAS_PCH_SPLIT(dev_priv)) { ilk_setup_wm_latency(dev_priv); From patchwork Fri Oct 11 20:09:49 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?b?VmlsbGUgU3lyasOkbMOk?= X-Patchwork-Id: 11186343 Return-Path: Received: from mail.kernel.org (pdx-korg-mail-1.web.codeaurora.org [172.30.200.123]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id EFD8E15AB for ; Fri, 11 Oct 2019 20:10:20 +0000 (UTC) Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id D825D2190F for ; Fri, 11 Oct 2019 20:10:20 +0000 (UTC) DMARC-Filter: OpenDMARC Filter v1.3.2 mail.kernel.org D825D2190F Authentication-Results: mail.kernel.org; dmarc=fail (p=none dis=none) header.from=linux.intel.com Authentication-Results: mail.kernel.org; spf=none smtp.mailfrom=intel-gfx-bounces@lists.freedesktop.org Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id 63C38892A8; Fri, 11 Oct 2019 20:10:20 +0000 (UTC) X-Original-To: intel-gfx@lists.freedesktop.org Delivered-To: intel-gfx@lists.freedesktop.org Received: from mga04.intel.com (mga04.intel.com [192.55.52.120]) by gabe.freedesktop.org (Postfix) with ESMTPS id 600CE89143 for ; Fri, 11 Oct 2019 20:10:19 +0000 (UTC) X-Amp-Result: SKIPPED(no attachment in message) X-Amp-File-Uploaded: False Received: from orsmga007.jf.intel.com ([10.7.209.58]) by fmsmga104.fm.intel.com with ESMTP/TLS/DHE-RSA-AES256-GCM-SHA384; 11 Oct 2019 13:10:18 -0700 X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.67,285,1566889200"; d="scan'208";a="184862446" Received: from stinkbox.fi.intel.com (HELO stinkbox) ([10.237.72.174]) by orsmga007.jf.intel.com with SMTP; 11 Oct 2019 13:10:16 -0700 Received: by stinkbox (sSMTP sendmail emulation); Fri, 11 Oct 2019 23:10:15 +0300 From: Ville Syrjala To: intel-gfx@lists.freedesktop.org Date: Fri, 11 Oct 2019 23:09:49 +0300 Message-Id: <20191011200949.7839-9-ville.syrjala@linux.intel.com> X-Mailer: git-send-email 2.21.0 In-Reply-To: <20191011200949.7839-1-ville.syrjala@linux.intel.com> References: <20191011200949.7839-1-ville.syrjala@linux.intel.com> MIME-Version: 1.0 Subject: [Intel-gfx] [PATCH 8/8] drm/i915: Nuke skl wm.dirty_pipes bitmask X-BeenThere: intel-gfx@lists.freedesktop.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: Intel graphics driver community testing & development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: intel-gfx-bounces@lists.freedesktop.org Sender: "Intel-gfx" From: Ville Syrjälä The dirty_pipes bitmask is now unused. Get rid of it. Signed-off-by: Ville Syrjälä --- drivers/gpu/drm/i915/i915_drv.h | 1 - drivers/gpu/drm/i915/intel_pm.c | 35 +-------------------------------- 2 files changed, 1 insertion(+), 35 deletions(-) diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h index eba9055c4405..c16ba85e2ec8 100644 --- a/drivers/gpu/drm/i915/i915_drv.h +++ b/drivers/gpu/drm/i915/i915_drv.h @@ -901,7 +901,6 @@ struct skl_ddb_allocation { }; struct skl_ddb_values { - unsigned dirty_pipes; struct skl_ddb_allocation ddb; }; diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c index 390d1f8d45ba..ccbb732cff44 100644 --- a/drivers/gpu/drm/i915/intel_pm.c +++ b/drivers/gpu/drm/i915/intel_pm.c @@ -5130,23 +5130,6 @@ static bool skl_plane_wm_equals(struct drm_i915_private *dev_priv, return skl_wm_level_equals(&wm1->trans_wm, &wm2->trans_wm); } -static bool skl_pipe_wm_equals(struct intel_crtc *crtc, - const struct skl_pipe_wm *wm1, - const struct skl_pipe_wm *wm2) -{ - struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); - enum plane_id plane_id; - - for_each_plane_id_on_crtc(crtc, plane_id) { - if (!skl_plane_wm_equals(dev_priv, - &wm1->planes[plane_id], - &wm2->planes[plane_id])) - return false; - } - - return true; -} - static inline bool skl_ddb_entries_overlap(const struct skl_ddb_entry *a, const struct skl_ddb_entry *b) { @@ -5403,8 +5386,6 @@ skl_ddb_add_affected_pipes(struct intel_atomic_state *state) * to grab the lock on *all* CRTC's. */ if (state->active_pipe_changes || state->modeset) { - state->wm_results.dirty_pipes = INTEL_INFO(dev_priv)->pipe_mask; - ret = intel_add_all_pipes(state); if (ret) return ret; @@ -5479,12 +5460,8 @@ skl_compute_wm(struct intel_atomic_state *state) struct intel_crtc *crtc; struct intel_crtc_state *new_crtc_state; struct intel_crtc_state *old_crtc_state; - struct skl_ddb_values *results = &state->wm_results; int ret, i; - /* Clear all dirty flags */ - results->dirty_pipes = 0; - ret = skl_ddb_add_affected_pipes(state); if (ret) return ret; @@ -5492,8 +5469,7 @@ skl_compute_wm(struct intel_atomic_state *state) /* * Calculate WM's for all pipes that are part of this transaction. * Note that skl_ddb_add_affected_pipes may have added more CRTC's that - * weren't otherwise being modified (and set bits in dirty_pipes) if - * pipe allocations had to change. + * weren't otherwise being modified if pipe allocations had to change. */ for_each_oldnew_intel_crtc_in_state(state, crtc, old_crtc_state, new_crtc_state, i) { @@ -5504,11 +5480,6 @@ skl_compute_wm(struct intel_atomic_state *state) ret = skl_wm_add_affected_planes(state, crtc); if (ret) return ret; - - if (!skl_pipe_wm_equals(crtc, - &old_crtc_state->wm.skl.optimal, - &new_crtc_state->wm.skl.optimal)) - results->dirty_pipes |= BIT(crtc->pipe); } ret = skl_compute_ddb(state); @@ -5644,7 +5615,6 @@ void skl_pipe_wm_get_hw_state(struct intel_crtc *crtc, void skl_wm_get_hw_state(struct drm_i915_private *dev_priv) { - struct skl_ddb_values *hw = &dev_priv->wm.skl_hw; struct skl_ddb_allocation *ddb = &dev_priv->wm.skl_hw.ddb; struct intel_crtc *crtc; struct intel_crtc_state *crtc_state; @@ -5654,9 +5624,6 @@ void skl_wm_get_hw_state(struct drm_i915_private *dev_priv) crtc_state = to_intel_crtc_state(crtc->base.state); skl_pipe_wm_get_hw_state(crtc, &crtc_state->wm.skl.optimal); - - if (crtc->active) - hw->dirty_pipes |= BIT(crtc->pipe); } if (dev_priv->active_pipes) {