From patchwork Tue Oct 15 16:59:58 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Dmitry Osipenko X-Patchwork-Id: 11191275 Return-Path: Received: from mail.kernel.org (pdx-korg-mail-1.web.codeaurora.org [172.30.200.123]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id E946A912 for ; Tue, 15 Oct 2019 17:02:55 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.kernel.org (Postfix) with ESMTP id C8EDC2168B for ; Tue, 15 Oct 2019 17:02:55 +0000 (UTC) Authentication-Results: mail.kernel.org; dkim=pass (2048-bit key) header.d=gmail.com header.i=@gmail.com header.b="FY5C708+" Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S2388415AbfJORBo (ORCPT ); Tue, 15 Oct 2019 13:01:44 -0400 Received: from mail-lj1-f194.google.com ([209.85.208.194]:40699 "EHLO mail-lj1-f194.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1726379AbfJORBm (ORCPT ); Tue, 15 Oct 2019 13:01:42 -0400 Received: by mail-lj1-f194.google.com with SMTP id 7so21029917ljw.7; Tue, 15 Oct 2019 10:01:40 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=AJsM8Od2cQbwnjMd2WWbJxd1SHRmM5N6fXuOeZ21tBs=; b=FY5C708+7R3R+T2+2UOKodWusasv7UcODH3feQg6EaDVYSPJItMgxs28+Euriicg2p DqH9dihcTkCskwC1ydhMiqccrDXHiSeWXlPMNbfCh/4WrgsVrv20bigOsKuMsxe9Z+l6 L/xcAmGzH8irwMxlSjkZFpZuC6AiqiVDgamhs/L5ZYs0wpIBFOdG+LL6roPkDUMMyo9K 93N2d/zAXlAk3NIw3VwXdYxKu768n3ijPPIU+1qfRojes3YVddknpTY/46h2D07iBarT KJSLn6qaVWTUIIR+JuXkbB2kS4T5/GsapEKcdAW9ZN7L5oimMeautX+uftwmzrI4d5BK qzrw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=AJsM8Od2cQbwnjMd2WWbJxd1SHRmM5N6fXuOeZ21tBs=; b=T/DX/FOEH3TxCRBC9/dUgYRzewTFgt0D92ea/8gsjAwwSUZE9J+SASAYYSPFdbxvHd uJgmOs087T7iao/Z6bzgp4tyeAgQh4X8r8Mz5ZraRRlksKobYBr7JEKhIxf3JCkmJ79Z qmesppyWCjYpMOavWJfjTk6NrxLjXh/2sCDJjX2wwl5MIHG1YjCwKsKVEoFmJsbZotRv oI9wWcy/Is7smgjq2efIshTE17Zaw++wzVGySyPToWyoegX53urTt9zVR6iIbRG1JBsl /RPaf3LhWNjuDsqlnHCxr0KUGcX8Qw04SsnEYGQxxSj3OrEkUNsX73tnW6BgdR7V+yx4 7m0A== X-Gm-Message-State: APjAAAXTbJw/Bu8Mj6cvhByLr/gh/LJEpG4u6LEIWAP5tzEyAMzP0RLa TdPzrpxkzfyVpMm1d2DWFiM= X-Google-Smtp-Source: APXvYqxpvul+nMVqpIug+XdB+meqQlQVFNMFw50vLLX2A3w8eaBdAb3LZ0LiyxBd6shpR4An30N4dA== X-Received: by 2002:a2e:8204:: with SMTP id w4mr23138163ljg.3.1571158900054; Tue, 15 Oct 2019 10:01:40 -0700 (PDT) Received: from localhost.localdomain ([94.29.10.250]) by smtp.gmail.com with ESMTPSA id t6sm5144992ljd.102.2019.10.15.10.01.39 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 15 Oct 2019 10:01:39 -0700 (PDT) From: Dmitry Osipenko To: Thierry Reding , Jonathan Hunter , Peter De Schrijver , "Rafael J. Wysocki" , Daniel Lezcano Cc: linux-pm@vger.kernel.org, linux-tegra@vger.kernel.org, linux-kernel@vger.kernel.org Subject: [PATCH v6 01/18] ARM: tegra: Compile sleep-tegra20/30.S unconditionally Date: Tue, 15 Oct 2019 19:59:58 +0300 Message-Id: <20191015170015.1135-2-digetx@gmail.com> X-Mailer: git-send-email 2.23.0 In-Reply-To: <20191015170015.1135-1-digetx@gmail.com> References: <20191015170015.1135-1-digetx@gmail.com> MIME-Version: 1.0 Sender: linux-pm-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-pm@vger.kernel.org The sleep-tegra*.S provides functionality required for suspend/resume and CPU hotplugging. The new unified CPUIDLE driver will support multiple hardware generations starting from Terga20 and ending with Tegra124, the driver will utilize functions that are provided by the assembly and thus it is cleaner to compile that code without any build-dependencies in order to avoid churning with #ifdef's. Signed-off-by: Dmitry Osipenko --- arch/arm/mach-tegra/Makefile | 6 ++---- arch/arm/mach-tegra/sleep.h | 2 -- 2 files changed, 2 insertions(+), 6 deletions(-) diff --git a/arch/arm/mach-tegra/Makefile b/arch/arm/mach-tegra/Makefile index 6c1dff2eccc2..965862608ff6 100644 --- a/arch/arm/mach-tegra/Makefile +++ b/arch/arm/mach-tegra/Makefile @@ -8,13 +8,13 @@ obj-y += reset.o obj-y += reset-handler.o obj-y += sleep.o obj-y += tegra.o +obj-y += sleep-tegra20.o +obj-y += sleep-tegra30.o obj-$(CONFIG_CPU_IDLE) += cpuidle.o -obj-$(CONFIG_ARCH_TEGRA_2x_SOC) += sleep-tegra20.o obj-$(CONFIG_ARCH_TEGRA_2x_SOC) += pm-tegra20.o ifeq ($(CONFIG_CPU_IDLE),y) obj-$(CONFIG_ARCH_TEGRA_2x_SOC) += cpuidle-tegra20.o endif -obj-$(CONFIG_ARCH_TEGRA_3x_SOC) += sleep-tegra30.o obj-$(CONFIG_ARCH_TEGRA_3x_SOC) += pm-tegra30.o ifeq ($(CONFIG_CPU_IDLE),y) obj-$(CONFIG_ARCH_TEGRA_3x_SOC) += cpuidle-tegra30.o @@ -22,12 +22,10 @@ endif obj-$(CONFIG_SMP) += platsmp.o obj-$(CONFIG_HOTPLUG_CPU) += hotplug.o -obj-$(CONFIG_ARCH_TEGRA_114_SOC) += sleep-tegra30.o obj-$(CONFIG_ARCH_TEGRA_114_SOC) += pm-tegra30.o ifeq ($(CONFIG_CPU_IDLE),y) obj-$(CONFIG_ARCH_TEGRA_114_SOC) += cpuidle-tegra114.o endif -obj-$(CONFIG_ARCH_TEGRA_124_SOC) += sleep-tegra30.o obj-$(CONFIG_ARCH_TEGRA_124_SOC) += pm-tegra30.o ifeq ($(CONFIG_CPU_IDLE),y) obj-$(CONFIG_ARCH_TEGRA_124_SOC) += cpuidle-tegra114.o diff --git a/arch/arm/mach-tegra/sleep.h b/arch/arm/mach-tegra/sleep.h index 78ef32a907c8..63e2205cbc82 100644 --- a/arch/arm/mach-tegra/sleep.h +++ b/arch/arm/mach-tegra/sleep.h @@ -120,10 +120,8 @@ void tegra_resume(void); int tegra_sleep_cpu_finish(unsigned long); void tegra_disable_clean_inv_dcache(u32 flag); -#ifdef CONFIG_HOTPLUG_CPU void tegra20_hotplug_shutdown(void); void tegra30_hotplug_shutdown(void); -#endif void tegra20_cpu_shutdown(int cpu); int tegra20_cpu_is_resettable_soon(void); From patchwork Tue Oct 15 16:59:59 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Dmitry Osipenko X-Patchwork-Id: 11191271 Return-Path: Received: from mail.kernel.org (pdx-korg-mail-1.web.codeaurora.org [172.30.200.123]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id EF9CB1390 for ; Tue, 15 Oct 2019 17:02:53 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.kernel.org (Postfix) with ESMTP id CDF0E2168B for ; Tue, 15 Oct 2019 17:02:53 +0000 (UTC) Authentication-Results: mail.kernel.org; dkim=pass (2048-bit key) header.d=gmail.com header.i=@gmail.com header.b="hhHXoeGk" Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S2388445AbfJORBr (ORCPT ); Tue, 15 Oct 2019 13:01:47 -0400 Received: from mail-lj1-f193.google.com ([209.85.208.193]:42354 "EHLO mail-lj1-f193.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1729897AbfJORBo (ORCPT ); Tue, 15 Oct 2019 13:01:44 -0400 Received: by mail-lj1-f193.google.com with SMTP id y23so21001583lje.9; Tue, 15 Oct 2019 10:01:42 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=PAYNs/o0oQ+5oMrw2AY1UO1+THnKmjTd9tnbcB8Y4M0=; b=hhHXoeGkeFH0aG2jGZZZ5SdqCD7w4e45J1BVWduxeXXVD4TeDF5TpJraTJ8N72qawA 49pAISszbYizOd2peiIVDpJoiFjO0qOJvev0OcvMPM+VE++6BxSlvPPc5JGpQn+ucBKM b28olFBRKPBb4cRw1u4OeEFkkH5fWybbbEPQFmWnD8XoQgdW4iA6ocWapMhxZta0buAk viiRVkSBtnZuGfo4vALCOhmjpiPxpKqz/WAoJEsClyf4Er/WuZY4MA9zCvXAuvGJkYyf jfqkYcLZVppSJNmgk0uM+4zkHPLRRK0hkLanIjftmD/0/1FeT6xLfHQqnNwzTX9yv4AQ h7Gw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=PAYNs/o0oQ+5oMrw2AY1UO1+THnKmjTd9tnbcB8Y4M0=; b=pyXyjV1PzEZcJWVTP/E3yq8dYj7PosS3UHK0pXVjdaiD7be2lPcJa7m0a5gji+wU7E id2r1NgtrqpX8UZaHnIkOCiK4IkkSrUZlSa4eYLAVcCBcxSyVQIrPz0ytldgmcbU1LSc pGyhS2o7y9NtcgPMCoIYTUJLwEX9ZOLen+b3QIQeyG0jt9TT9KiQuv6Ze1EUULbqcSNn UYv6Vxsk6qxMlf5jN/sT/H39hq1HREK24oODPqRNdb+oJl8gxezljOLapObbq6GeHM0m uS7n/FxpJZ6jU1kvvBdfvADfEYxeDElRrJr3aEp58X5wX9c2iyqmF22ia64YWdeDregW Yaqg== X-Gm-Message-State: APjAAAWO6Xq2F4ME17QMXQH6DRepFKcqbB6Cm/hpjTBm4Tl7x1TGmrJb WSdFjgjWkU5DtiDdQFof0So= X-Google-Smtp-Source: APXvYqxl7Tz9wEfgAkrvBVOg4eZ9ADEiRSRldWhV7QHOFUUVf8eYWuB4B5BDfnRtXrgCghrxi8WyRQ== X-Received: by 2002:a2e:858f:: with SMTP id b15mr23110599lji.68.1571158900984; Tue, 15 Oct 2019 10:01:40 -0700 (PDT) Received: from localhost.localdomain ([94.29.10.250]) by smtp.gmail.com with ESMTPSA id t6sm5144992ljd.102.2019.10.15.10.01.40 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 15 Oct 2019 10:01:40 -0700 (PDT) From: Dmitry Osipenko To: Thierry Reding , Jonathan Hunter , Peter De Schrijver , "Rafael J. Wysocki" , Daniel Lezcano Cc: linux-pm@vger.kernel.org, linux-tegra@vger.kernel.org, linux-kernel@vger.kernel.org Subject: [PATCH v6 02/18] ARM: tegra: Add tegra_pm_park_secondary_cpu() Date: Tue, 15 Oct 2019 19:59:59 +0300 Message-Id: <20191015170015.1135-3-digetx@gmail.com> X-Mailer: git-send-email 2.23.0 In-Reply-To: <20191015170015.1135-1-digetx@gmail.com> References: <20191015170015.1135-1-digetx@gmail.com> MIME-Version: 1.0 Sender: linux-pm-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-pm@vger.kernel.org This function resembles tegra_cpu_die() of the hotplug code, but this variant is more suitable to be used for CPU PM because it's made specifically to be used by cpu_suspend(). In short this function puts secondary CPU offline, it will be used by the new CPUIDLE driver. Signed-off-by: Dmitry Osipenko --- arch/arm/mach-tegra/pm.c | 14 ++++++++++++++ arch/arm/mach-tegra/pm.h | 5 +++++ 2 files changed, 19 insertions(+) diff --git a/arch/arm/mach-tegra/pm.c b/arch/arm/mach-tegra/pm.c index 3cab81b82866..f5ff3dd1dd81 100644 --- a/arch/arm/mach-tegra/pm.c +++ b/arch/arm/mach-tegra/pm.c @@ -436,4 +436,18 @@ void __init tegra_init_suspend(void) suspend_set_ops(&tegra_suspend_ops); } + +int tegra_pm_park_secondary_cpu(unsigned long cpu) +{ + if (cpu > 0) { + tegra_disable_clean_inv_dcache(TEGRA_FLUSH_CACHE_LOUIS); + + if (tegra_get_chip_id() == TEGRA20) + tegra20_hotplug_shutdown(); + else + tegra30_hotplug_shutdown(); + } + + return -EINVAL; +} #endif diff --git a/arch/arm/mach-tegra/pm.h b/arch/arm/mach-tegra/pm.h index 569151b3edc0..9a790f00237f 100644 --- a/arch/arm/mach-tegra/pm.h +++ b/arch/arm/mach-tegra/pm.h @@ -31,8 +31,13 @@ extern void (*tegra_tear_down_cpu)(void); #ifdef CONFIG_PM_SLEEP void tegra_init_suspend(void); +int tegra_pm_park_secondary_cpu(unsigned long cpu); #else static inline void tegra_init_suspend(void) {} +static inline int tegra_pm_park_secondary_cpu(unsigned long cpu) +{ + return -ENOTSUPP; +} #endif #endif /* _MACH_TEGRA_PM_H_ */ From patchwork Tue Oct 15 17:00:00 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Dmitry Osipenko X-Patchwork-Id: 11191241 Return-Path: Received: from mail.kernel.org (pdx-korg-mail-1.web.codeaurora.org [172.30.200.123]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id AB6B01390 for ; Tue, 15 Oct 2019 17:01:48 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.kernel.org (Postfix) with ESMTP id 7679E20873 for ; Tue, 15 Oct 2019 17:01:48 +0000 (UTC) Authentication-Results: mail.kernel.org; dkim=pass (2048-bit key) header.d=gmail.com header.i=@gmail.com header.b="ft2qNuMS" Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S2388437AbfJORBq (ORCPT ); Tue, 15 Oct 2019 13:01:46 -0400 Received: from mail-lj1-f193.google.com ([209.85.208.193]:39637 "EHLO mail-lj1-f193.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1729853AbfJORBp (ORCPT ); Tue, 15 Oct 2019 13:01:45 -0400 Received: by mail-lj1-f193.google.com with SMTP id y3so21046925ljj.6; Tue, 15 Oct 2019 10:01:43 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=rD51BVoFsaxSqaiMnnWA3suIhZ9MxObJJ+UlRiM36bw=; b=ft2qNuMSmSt/nGApSPb78ai+8013/Oxrf+HyQMC0UGKilRFr/UF1sVAKnLwpxlpwaQ 96j3SlZMA4SQpugqQWdwzxpLT7QhxC+RhMHBIyIWTRqruE3dtgu1bpKwhZ4jmiMpKVqT 11KzXCGRuiQpmCNQDIOE0AL06Eb+E4CpPFy6QsWogEEnFno7jPxijKVfq4+seC8MB8OP s1PequCwrD0N8ulaeQcJGAe2t/Fxi3OC7KiVV2nooW+fA3rr1uRPKDjy43fDaB1FVbCQ mW06/S04STgVHa2fukIGZYHYg8FtrRNgOxXH6m5yqQ6j8hm1HBaMIh4s7LO1VIqIm4Vw OHfw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=rD51BVoFsaxSqaiMnnWA3suIhZ9MxObJJ+UlRiM36bw=; b=gyC+p3gfJktGc/7fROHXOO0lzL7pon+ucXwx0l79RrU8yFVGJg5uxNf1XnK3kOJ3+l WUwm6I7vlsGBQTZcnL71mCN8ArMrN6XHfJJLT663Nd5B2NfndCw3+hcHqOU/yqzsYABY Kkb1R+sHAluaRrwTc0GzLe1XtIosv/yanQvi/GzLTnq0qJcwEe1HbBZFPizE4xknVkrW XHW1TZzS8RJ3/UH5QuVmo9Xe/9ybe4qGCtWXlRxoJm/XdcU+UHqn1v7nqmjgIpCxXnOr DNgbxS8YcC5Volf3FCIewn+VTRUshsX1MuL9mSm1L16PGbVGbX/UgU1vCUHPleSZT7/l aJ8g== X-Gm-Message-State: APjAAAVEbjo7OT/+2NXNoxx15QXwz2wlgDE4gbErlqgVNeguWIHveKME luQzJJHagSBvxrY1+KO104M= X-Google-Smtp-Source: APXvYqwrdbWvBVlnZHW2dTZTN16yfuY1FRibutqiG5DdBT7fusYBxAyQjkLK2yVDKoaIAJMUFlNqGg== X-Received: by 2002:a2e:8893:: with SMTP id k19mr13225162lji.5.1571158902058; Tue, 15 Oct 2019 10:01:42 -0700 (PDT) Received: from localhost.localdomain ([94.29.10.250]) by smtp.gmail.com with ESMTPSA id t6sm5144992ljd.102.2019.10.15.10.01.41 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 15 Oct 2019 10:01:41 -0700 (PDT) From: Dmitry Osipenko To: Thierry Reding , Jonathan Hunter , Peter De Schrijver , "Rafael J. Wysocki" , Daniel Lezcano Cc: linux-pm@vger.kernel.org, linux-tegra@vger.kernel.org, linux-kernel@vger.kernel.org Subject: [PATCH v6 03/18] ARM: tegra: Remove pen-locking from cpuidle-tegra20 Date: Tue, 15 Oct 2019 20:00:00 +0300 Message-Id: <20191015170015.1135-4-digetx@gmail.com> X-Mailer: git-send-email 2.23.0 In-Reply-To: <20191015170015.1135-1-digetx@gmail.com> References: <20191015170015.1135-1-digetx@gmail.com> MIME-Version: 1.0 Sender: linux-pm-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-pm@vger.kernel.org Pen-locking is meant to block CPU0 if CPU1 wakes up during of entering into LP2 because of some interrupt firing up, preventing unnecessary LP2 enter that will be resumed immediately. Apparently this case doesn't happen often in practice, I checked how often it takes place and found that after ~20 hours of browsing web, managing email, watching videos and idling (15+ hours) there is only a dozen of early LP2 entering abortions and they all happened while device was idling. Thus let's remove the pen-locking and make LP2 entering uninterruptible, simplifying code quite a lot. This will also become very handy for the upcoming unified cpuidle driver, allowing to have a common LP2 code-path across of different hardware generations. Signed-off-by: Dmitry Osipenko --- arch/arm/mach-tegra/cpuidle-tegra20.c | 46 +------ arch/arm/mach-tegra/pm.c | 7 -- arch/arm/mach-tegra/pm.h | 1 - arch/arm/mach-tegra/reset-handler.S | 11 -- arch/arm/mach-tegra/reset.h | 9 +- arch/arm/mach-tegra/sleep-tegra20.S | 170 -------------------------- arch/arm/mach-tegra/sleep.h | 12 -- 7 files changed, 5 insertions(+), 251 deletions(-) diff --git a/arch/arm/mach-tegra/cpuidle-tegra20.c b/arch/arm/mach-tegra/cpuidle-tegra20.c index 2447427cb4a8..4da5d72ae030 100644 --- a/arch/arm/mach-tegra/cpuidle-tegra20.c +++ b/arch/arm/mach-tegra/cpuidle-tegra20.c @@ -15,6 +15,7 @@ #include #include #include +#include #include #include @@ -65,28 +66,8 @@ static struct cpuidle_driver tegra_idle_driver = { #ifdef CONFIG_PM_SLEEP #ifdef CONFIG_SMP -static int tegra20_reset_sleeping_cpu_1(void) -{ - int ret = 0; - - tegra_pen_lock(); - - if (readb(tegra20_cpu1_resettable_status) == CPU_RESETTABLE) - tegra20_cpu_shutdown(1); - else - ret = -EINVAL; - - tegra_pen_unlock(); - - return ret; -} - static void tegra20_wake_cpu1_from_reset(void) { - tegra_pen_lock(); - - tegra20_cpu_clear_resettable(); - /* enable cpu clock on cpu */ tegra_enable_cpu_clock(1); @@ -95,39 +76,20 @@ static void tegra20_wake_cpu1_from_reset(void) /* unhalt the cpu */ flowctrl_write_cpu_halt(1, 0); - - tegra_pen_unlock(); -} - -static int tegra20_reset_cpu_1(void) -{ - if (!cpu_online(1) || !tegra20_reset_sleeping_cpu_1()) - return 0; - - tegra20_wake_cpu1_from_reset(); - return -EBUSY; } #else static inline void tegra20_wake_cpu1_from_reset(void) { } - -static inline int tegra20_reset_cpu_1(void) -{ - return 0; -} #endif static bool tegra20_cpu_cluster_power_down(struct cpuidle_device *dev, struct cpuidle_driver *drv, int index) { - while (tegra20_cpu_is_resettable_soon()) + while (!tegra_cpu_rail_off_ready()) cpu_relax(); - if (tegra20_reset_cpu_1() || !tegra_cpu_rail_off_ready()) - return false; - tegra_idle_lp2_last(); if (cpu_online(1)) @@ -141,9 +103,7 @@ static bool tegra20_idle_enter_lp2_cpu_1(struct cpuidle_device *dev, struct cpuidle_driver *drv, int index) { - cpu_suspend(0, tegra20_sleep_cpu_secondary_finish); - - tegra20_cpu_clear_resettable(); + cpu_suspend(dev->cpu, tegra_pm_park_secondary_cpu); return true; } diff --git a/arch/arm/mach-tegra/pm.c b/arch/arm/mach-tegra/pm.c index f5ff3dd1dd81..1ff499068bb1 100644 --- a/arch/arm/mach-tegra/pm.c +++ b/arch/arm/mach-tegra/pm.c @@ -137,18 +137,11 @@ bool tegra_set_cpu_in_lp2(void) if ((phy_cpu_id == 0) && cpumask_equal(cpu_lp2_mask, cpu_online_mask)) last_cpu = true; - else if (tegra_get_chip_id() == TEGRA20 && phy_cpu_id == 1) - tegra20_cpu_set_resettable_soon(); spin_unlock(&tegra_lp2_lock); return last_cpu; } -int tegra_cpu_do_idle(void) -{ - return cpu_do_idle(); -} - static int tegra_sleep_cpu(unsigned long v2p) { /* diff --git a/arch/arm/mach-tegra/pm.h b/arch/arm/mach-tegra/pm.h index 9a790f00237f..b9cc12222bb1 100644 --- a/arch/arm/mach-tegra/pm.h +++ b/arch/arm/mach-tegra/pm.h @@ -25,7 +25,6 @@ void tegra30_sleep_core_init(void); void tegra_clear_cpu_in_lp2(void); bool tegra_set_cpu_in_lp2(void); -int tegra_cpu_do_idle(void); void tegra_idle_lp2_last(void); extern void (*tegra_tear_down_cpu)(void); diff --git a/arch/arm/mach-tegra/reset-handler.S b/arch/arm/mach-tegra/reset-handler.S index 67b763fea005..df44828a34d3 100644 --- a/arch/arm/mach-tegra/reset-handler.S +++ b/arch/arm/mach-tegra/reset-handler.S @@ -183,17 +183,6 @@ after_errata: bleq __die @ CPU not present (to OS) #endif -#ifdef CONFIG_ARCH_TEGRA_2x_SOC - /* Are we on Tegra20? */ - cmp r6, #TEGRA20 - bne 1f - /* If not CPU0, don't let CPU0 reset CPU1 now that CPU1 is coming up. */ - mov r0, #CPU_NOT_RESETTABLE - cmp r10, #0 - strbne r0, [r12, #RESET_DATA(RESETTABLE_STATUS)] -1: -#endif - /* Waking up from LP1? */ ldr r8, [r12, #RESET_DATA(MASK_LP1)] tst r8, r11 @ if in_lp1 diff --git a/arch/arm/mach-tegra/reset.h b/arch/arm/mach-tegra/reset.h index a4cfc08159f6..51265592cb1a 100644 --- a/arch/arm/mach-tegra/reset.h +++ b/arch/arm/mach-tegra/reset.h @@ -16,9 +16,8 @@ #define TEGRA_RESET_STARTUP_SECONDARY 3 #define TEGRA_RESET_STARTUP_LP2 4 #define TEGRA_RESET_STARTUP_LP1 5 -#define TEGRA_RESET_RESETTABLE_STATUS 6 -#define TEGRA_RESET_TF_PRESENT 7 -#define TEGRA_RESET_DATA_SIZE 8 +#define TEGRA_RESET_TF_PRESENT 6 +#define TEGRA_RESET_DATA_SIZE 7 #define RESET_DATA(x) ((TEGRA_RESET_##x)*4) @@ -42,10 +41,6 @@ void __tegra_cpu_reset_handler_end(void); (IO_ADDRESS(TEGRA_IRAM_BASE + TEGRA_IRAM_RESET_HANDLER_OFFSET + \ ((u32)&__tegra_cpu_reset_handler_data[TEGRA_RESET_MASK_LP2] - \ (u32)__tegra_cpu_reset_handler_start))) -#define tegra20_cpu1_resettable_status \ - (IO_ADDRESS(TEGRA_IRAM_BASE + TEGRA_IRAM_RESET_HANDLER_OFFSET + \ - ((u32)&__tegra_cpu_reset_handler_data[TEGRA_RESET_RESETTABLE_STATUS] - \ - (u32)__tegra_cpu_reset_handler_start))) #endif #define tegra_cpu_reset_handler_offset \ diff --git a/arch/arm/mach-tegra/sleep-tegra20.S b/arch/arm/mach-tegra/sleep-tegra20.S index 9a89f30d53ca..0e00ba8cf646 100644 --- a/arch/arm/mach-tegra/sleep-tegra20.S +++ b/arch/arm/mach-tegra/sleep-tegra20.S @@ -43,9 +43,6 @@ #define APB_MISC_XM2CFGCPADCTRL2 0x8e4 #define APB_MISC_XM2CFGDPADCTRL2 0x8e8 -#define __tegra20_cpu1_resettable_status_offset \ - (__tegra_cpu_reset_handler_data_offset + RESET_DATA(RESETTABLE_STATUS)) - .macro pll_enable, rd, r_car_base, pll_base ldr \rd, [\r_car_base, #\pll_base] tst \rd, #(1 << 30) @@ -90,10 +87,6 @@ ENDPROC(tegra20_hotplug_shutdown) ENTRY(tegra20_cpu_shutdown) cmp r0, #0 reteq lr @ must not be called for CPU 0 - mov32 r1, TEGRA_IRAM_RESET_BASE_VIRT - ldr r2, =__tegra20_cpu1_resettable_status_offset - mov r12, #CPU_RESETTABLE - strb r12, [r1, r2] cpu_to_halt_reg r1, r0 ldr r3, =TEGRA_FLOW_CTRL_VIRT @@ -116,107 +109,6 @@ ENDPROC(tegra20_cpu_shutdown) #endif #ifdef CONFIG_PM_SLEEP -/* - * tegra_pen_lock - * - * spinlock implementation with no atomic test-and-set and no coherence - * using Peterson's algorithm on strongly-ordered registers - * used to synchronize a cpu waking up from wfi with entering lp2 on idle - * - * The reference link of Peterson's algorithm: - * http://en.wikipedia.org/wiki/Peterson's_algorithm - * - * SCRATCH37 = r1 = !turn (inverted from Peterson's algorithm) - * on cpu 0: - * r2 = flag[0] (in SCRATCH38) - * r3 = flag[1] (in SCRATCH39) - * on cpu1: - * r2 = flag[1] (in SCRATCH39) - * r3 = flag[0] (in SCRATCH38) - * - * must be called with MMU on - * corrupts r0-r3, r12 - */ -ENTRY(tegra_pen_lock) - mov32 r3, TEGRA_PMC_VIRT - cpu_id r0 - add r1, r3, #PMC_SCRATCH37 - cmp r0, #0 - addeq r2, r3, #PMC_SCRATCH38 - addeq r3, r3, #PMC_SCRATCH39 - addne r2, r3, #PMC_SCRATCH39 - addne r3, r3, #PMC_SCRATCH38 - - mov r12, #1 - str r12, [r2] @ flag[cpu] = 1 - dsb - str r12, [r1] @ !turn = cpu -1: dsb - ldr r12, [r3] - cmp r12, #1 @ flag[!cpu] == 1? - ldreq r12, [r1] - cmpeq r12, r0 @ !turn == cpu? - beq 1b @ while !turn == cpu && flag[!cpu] == 1 - - ret lr @ locked -ENDPROC(tegra_pen_lock) - -ENTRY(tegra_pen_unlock) - dsb - mov32 r3, TEGRA_PMC_VIRT - cpu_id r0 - cmp r0, #0 - addeq r2, r3, #PMC_SCRATCH38 - addne r2, r3, #PMC_SCRATCH39 - mov r12, #0 - str r12, [r2] - ret lr -ENDPROC(tegra_pen_unlock) - -/* - * tegra20_cpu_clear_resettable(void) - * - * Called to clear the "resettable soon" flag in IRAM variable when - * it is expected that the secondary CPU will be idle soon. - */ -ENTRY(tegra20_cpu_clear_resettable) - mov32 r1, TEGRA_IRAM_RESET_BASE_VIRT - ldr r2, =__tegra20_cpu1_resettable_status_offset - mov r12, #CPU_NOT_RESETTABLE - strb r12, [r1, r2] - ret lr -ENDPROC(tegra20_cpu_clear_resettable) - -/* - * tegra20_cpu_set_resettable_soon(void) - * - * Called to set the "resettable soon" flag in IRAM variable when - * it is expected that the secondary CPU will be idle soon. - */ -ENTRY(tegra20_cpu_set_resettable_soon) - mov32 r1, TEGRA_IRAM_RESET_BASE_VIRT - ldr r2, =__tegra20_cpu1_resettable_status_offset - mov r12, #CPU_RESETTABLE_SOON - strb r12, [r1, r2] - ret lr -ENDPROC(tegra20_cpu_set_resettable_soon) - -/* - * tegra20_cpu_is_resettable_soon(void) - * - * Returns true if the "resettable soon" flag in IRAM variable has been - * set because it is expected that the secondary CPU will be idle soon. - */ -ENTRY(tegra20_cpu_is_resettable_soon) - mov32 r1, TEGRA_IRAM_RESET_BASE_VIRT - ldr r2, =__tegra20_cpu1_resettable_status_offset - ldrb r12, [r1, r2] - cmp r12, #CPU_RESETTABLE_SOON - moveq r0, #1 - movne r0, #0 - ret lr -ENDPROC(tegra20_cpu_is_resettable_soon) - /* * tegra20_sleep_core_finish(unsigned long v2p) * @@ -242,68 +134,6 @@ ENTRY(tegra20_sleep_core_finish) ret r3 ENDPROC(tegra20_sleep_core_finish) -/* - * tegra20_sleep_cpu_secondary_finish(unsigned long v2p) - * - * Enters WFI on secondary CPU by exiting coherency. - */ -ENTRY(tegra20_sleep_cpu_secondary_finish) - stmfd sp!, {r4-r11, lr} - - mrc p15, 0, r11, c1, c0, 1 @ save actlr before exiting coherency - - /* Flush and disable the L1 data cache */ - mov r0, #TEGRA_FLUSH_CACHE_LOUIS - bl tegra_disable_clean_inv_dcache - - mov32 r0, TEGRA_IRAM_RESET_BASE_VIRT - ldr r4, =__tegra20_cpu1_resettable_status_offset - mov r3, #CPU_RESETTABLE - strb r3, [r0, r4] - - bl tegra_cpu_do_idle - - /* - * cpu may be reset while in wfi, which will return through - * tegra_resume to cpu_resume - * or interrupt may wake wfi, which will return here - * cpu state is unchanged - MMU is on, cache is on, coherency - * is off, and the data cache is off - * - * r11 contains the original actlr - */ - - bl tegra_pen_lock - - mov32 r0, TEGRA_IRAM_RESET_BASE_VIRT - ldr r4, =__tegra20_cpu1_resettable_status_offset - mov r3, #CPU_NOT_RESETTABLE - strb r3, [r0, r4] - - bl tegra_pen_unlock - - /* Re-enable the data cache */ - mrc p15, 0, r10, c1, c0, 0 - orr r10, r10, #CR_C - mcr p15, 0, r10, c1, c0, 0 - isb - - mcr p15, 0, r11, c1, c0, 1 @ reenable coherency - - /* Invalidate the TLBs & BTAC */ - mov r1, #0 - mcr p15, 0, r1, c8, c3, 0 @ invalidate shared TLBs - mcr p15, 0, r1, c7, c1, 6 @ invalidate shared BTAC - dsb - isb - - /* the cpu was running with coherency disabled, - * caches may be out of date */ - bl v7_flush_kern_cache_louis - - ldmfd sp!, {r4 - r11, pc} -ENDPROC(tegra20_sleep_cpu_secondary_finish) - /* * tegra20_tear_down_cpu * diff --git a/arch/arm/mach-tegra/sleep.h b/arch/arm/mach-tegra/sleep.h index 63e2205cbc82..4978def9db46 100644 --- a/arch/arm/mach-tegra/sleep.h +++ b/arch/arm/mach-tegra/sleep.h @@ -114,8 +114,6 @@ .endm #else -void tegra_pen_lock(void); -void tegra_pen_unlock(void); void tegra_resume(void); int tegra_sleep_cpu_finish(unsigned long); void tegra_disable_clean_inv_dcache(u32 flag); @@ -123,16 +121,6 @@ void tegra_disable_clean_inv_dcache(u32 flag); void tegra20_hotplug_shutdown(void); void tegra30_hotplug_shutdown(void); -void tegra20_cpu_shutdown(int cpu); -int tegra20_cpu_is_resettable_soon(void); -void tegra20_cpu_clear_resettable(void); -#ifdef CONFIG_ARCH_TEGRA_2x_SOC -void tegra20_cpu_set_resettable_soon(void); -#else -static inline void tegra20_cpu_set_resettable_soon(void) {} -#endif - -int tegra20_sleep_cpu_secondary_finish(unsigned long); void tegra20_tear_down_cpu(void); int tegra30_sleep_cpu_secondary_finish(unsigned long); void tegra30_tear_down_cpu(void); From patchwork Tue Oct 15 17:00:01 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Dmitry Osipenko X-Patchwork-Id: 11191273 Return-Path: Received: from mail.kernel.org (pdx-korg-mail-1.web.codeaurora.org [172.30.200.123]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id 7DC281668 for ; Tue, 15 Oct 2019 17:02:54 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.kernel.org (Postfix) with ESMTP id 5DE962168B for ; Tue, 15 Oct 2019 17:02:54 +0000 (UTC) Authentication-Results: mail.kernel.org; dkim=pass (2048-bit key) header.d=gmail.com header.i=@gmail.com header.b="ql+EZ+qs" Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S2388392AbfJORBq (ORCPT ); Tue, 15 Oct 2019 13:01:46 -0400 Received: from mail-lf1-f68.google.com ([209.85.167.68]:42130 "EHLO mail-lf1-f68.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S2388377AbfJORBp (ORCPT ); Tue, 15 Oct 2019 13:01:45 -0400 Received: by mail-lf1-f68.google.com with SMTP id c195so15062017lfg.9; Tue, 15 Oct 2019 10:01:43 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=5moJgPZ2Xa4K5tgWm4Nx1p1i/obHq7JljyrRhB5JMRE=; b=ql+EZ+qsgNkTj1l6uuRBk+HDu7XEubMfue2+p4/Rh98xlRRW78lzDTEz2PPRzTMCQT Nr4TimyF7bV2AuR2ulo+H+XbXH2szOfq7qWu5geaJuWtgr4WlkCIjLe84Mthud+GF2B9 F7dyUkMR0DVPiVI4aB/rCYvsahJzCEtyMklv4eFddBS2RQHVpqqgyk9DsaRieTw7GqAw re/W1bEMuX1gfk0N73HiqMUmTBaIzaW85AvMTUzF2Wr9PXZ4Yjx8v5JsYuqJn3hahmHm BiRzQTwrYjR4MThNOBBm+vW03p/9jrZpL7RxACCuDFSVh9/kiyK3CpYPm5nrSFeQiqv9 cJAw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=5moJgPZ2Xa4K5tgWm4Nx1p1i/obHq7JljyrRhB5JMRE=; b=aDF9nMk9DNM4fpSgb4ycELOFnLpF2kZ5jFyQAryIE6oYT+SKyCxiVc5hOLHJ1s1Qwd kVJVTwC0vZjPOaeMsHnwgu4pMy2+xtmqw1h7+St+Gzz0oyg/HCzeKUYOQQjc84Msr3gw pckkc2rBlCz+F+lq2XGPIGtgHuzfCbkCt46q5EhRBG6+PNpq1fKDdl8fJOmLYUyTutio ftRe+gAInTeVDlobH13yXQUE8Q40L+zbSYnuCZfLStNckd8kGlf6Np5EEtyiX2XwYtK1 yrMVGaPThRP0PJvJxVdKqmpjnU22Hdrg9/AX4r4h9M/wlqm2piiSEHd9a7RmXWBLzNVJ ig1A== X-Gm-Message-State: APjAAAVlziFuKAn7KN/3mAFZyTM4wpjird9JD/CZvXRmZb92bAyz9mFt gVc+OHRmieKpQqHL9Da9K7Q= X-Google-Smtp-Source: APXvYqz0N13dp4HmI2iWqx0gr7F7VoN8nEQp2x/hUAylnur/3lhCKlEWxfmQYlsIE6m16rfoWjbfGw== X-Received: by 2002:ac2:44c3:: with SMTP id d3mr20793012lfm.109.1571158902982; Tue, 15 Oct 2019 10:01:42 -0700 (PDT) Received: from localhost.localdomain ([94.29.10.250]) by smtp.gmail.com with ESMTPSA id t6sm5144992ljd.102.2019.10.15.10.01.42 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 15 Oct 2019 10:01:42 -0700 (PDT) From: Dmitry Osipenko To: Thierry Reding , Jonathan Hunter , Peter De Schrijver , "Rafael J. Wysocki" , Daniel Lezcano Cc: linux-pm@vger.kernel.org, linux-tegra@vger.kernel.org, linux-kernel@vger.kernel.org Subject: [PATCH v6 04/18] ARM: tegra: Change tegra_set_cpu_in_lp2() type to void Date: Tue, 15 Oct 2019 20:00:01 +0300 Message-Id: <20191015170015.1135-5-digetx@gmail.com> X-Mailer: git-send-email 2.23.0 In-Reply-To: <20191015170015.1135-1-digetx@gmail.com> References: <20191015170015.1135-1-digetx@gmail.com> MIME-Version: 1.0 Sender: linux-pm-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-pm@vger.kernel.org The Tegra30 CPUIDLE driver has intention to check whether primary CPU was the last CPU that entered LP2 (CC6) idle-state, but that functionality never got utilized because driver never supported the CC6 state for the case where any secondary CPU is online. The new cpuidle driver will properly support CC6 on Tegra30, including the case where secondary CPUs are online, and that knowledge about what CPUs entered into CC6 won't be needed at all because new driver will use different approach by making use of the coupled idle-state and explicitly parking secondary CPUs before entering into CC6. Thus this patch is just a minor cleanup change. Signed-off-by: Dmitry Osipenko --- arch/arm/mach-tegra/cpuidle-tegra30.c | 14 ++++---------- arch/arm/mach-tegra/pm.c | 8 +------- arch/arm/mach-tegra/pm.h | 2 +- 3 files changed, 6 insertions(+), 18 deletions(-) diff --git a/arch/arm/mach-tegra/cpuidle-tegra30.c b/arch/arm/mach-tegra/cpuidle-tegra30.c index c6128526877d..a3ce8dabfe18 100644 --- a/arch/arm/mach-tegra/cpuidle-tegra30.c +++ b/arch/arm/mach-tegra/cpuidle-tegra30.c @@ -98,22 +98,16 @@ static int tegra30_idle_lp2(struct cpuidle_device *dev, int index) { bool entered_lp2 = false; - bool last_cpu; local_fiq_disable(); - last_cpu = tegra_set_cpu_in_lp2(); + tegra_set_cpu_in_lp2(); cpu_pm_enter(); - if (dev->cpu == 0) { - if (last_cpu) - entered_lp2 = tegra30_cpu_cluster_power_down(dev, drv, - index); - else - cpu_do_idle(); - } else { + if (dev->cpu == 0) + entered_lp2 = tegra30_cpu_cluster_power_down(dev, drv, index); + else entered_lp2 = tegra30_cpu_core_power_down(dev, drv, index); - } cpu_pm_exit(); tegra_clear_cpu_in_lp2(); diff --git a/arch/arm/mach-tegra/pm.c b/arch/arm/mach-tegra/pm.c index 1ff499068bb1..a72f9a2d3cb7 100644 --- a/arch/arm/mach-tegra/pm.c +++ b/arch/arm/mach-tegra/pm.c @@ -123,11 +123,9 @@ void tegra_clear_cpu_in_lp2(void) spin_unlock(&tegra_lp2_lock); } -bool tegra_set_cpu_in_lp2(void) +void tegra_set_cpu_in_lp2(void) { int phy_cpu_id = cpu_logical_map(smp_processor_id()); - bool last_cpu = false; - cpumask_t *cpu_lp2_mask = tegra_cpu_lp2_mask; u32 *cpu_in_lp2 = tegra_cpu_lp2_mask; spin_lock(&tegra_lp2_lock); @@ -135,11 +133,7 @@ bool tegra_set_cpu_in_lp2(void) BUG_ON((*cpu_in_lp2 & BIT(phy_cpu_id))); *cpu_in_lp2 |= BIT(phy_cpu_id); - if ((phy_cpu_id == 0) && cpumask_equal(cpu_lp2_mask, cpu_online_mask)) - last_cpu = true; - spin_unlock(&tegra_lp2_lock); - return last_cpu; } static int tegra_sleep_cpu(unsigned long v2p) diff --git a/arch/arm/mach-tegra/pm.h b/arch/arm/mach-tegra/pm.h index b9cc12222bb1..2c294f6365c0 100644 --- a/arch/arm/mach-tegra/pm.h +++ b/arch/arm/mach-tegra/pm.h @@ -24,7 +24,7 @@ void tegra30_lp1_iram_hook(void); void tegra30_sleep_core_init(void); void tegra_clear_cpu_in_lp2(void); -bool tegra_set_cpu_in_lp2(void); +void tegra_set_cpu_in_lp2(void); void tegra_idle_lp2_last(void); extern void (*tegra_tear_down_cpu)(void); From patchwork Tue Oct 15 17:00:02 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Dmitry Osipenko X-Patchwork-Id: 11191243 Return-Path: Received: from mail.kernel.org (pdx-korg-mail-1.web.codeaurora.org [172.30.200.123]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id E00581668 for ; Tue, 15 Oct 2019 17:01:48 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.kernel.org (Postfix) with ESMTP id B54D220873 for ; Tue, 15 Oct 2019 17:01:48 +0000 (UTC) Authentication-Results: mail.kernel.org; dkim=pass (2048-bit key) header.d=gmail.com header.i=@gmail.com header.b="kwZUSK2A" Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S2388453AbfJORBs (ORCPT ); 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Tue, 15 Oct 2019 10:01:43 -0700 (PDT) From: Dmitry Osipenko To: Thierry Reding , Jonathan Hunter , Peter De Schrijver , "Rafael J. Wysocki" , Daniel Lezcano Cc: linux-pm@vger.kernel.org, linux-tegra@vger.kernel.org, linux-kernel@vger.kernel.org Subject: [PATCH v6 05/18] ARM: tegra: Propagate error from tegra_idle_lp2_last() Date: Tue, 15 Oct 2019 20:00:02 +0300 Message-Id: <20191015170015.1135-6-digetx@gmail.com> X-Mailer: git-send-email 2.23.0 In-Reply-To: <20191015170015.1135-1-digetx@gmail.com> References: <20191015170015.1135-1-digetx@gmail.com> MIME-Version: 1.0 Sender: linux-pm-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-pm@vger.kernel.org Technically cpu_suspend() may fail and it's never good to lose information about failure. For example things like cpuidle core could correctly sample idling time in the case of failure. Signed-off-by: Dmitry Osipenko --- arch/arm/mach-tegra/cpuidle-tegra20.c | 6 ++++-- arch/arm/mach-tegra/cpuidle-tegra30.c | 4 +--- arch/arm/mach-tegra/pm.c | 8 ++++++-- arch/arm/mach-tegra/pm.h | 2 +- 4 files changed, 12 insertions(+), 8 deletions(-) diff --git a/arch/arm/mach-tegra/cpuidle-tegra20.c b/arch/arm/mach-tegra/cpuidle-tegra20.c index 4da5d72ae030..74ba37992259 100644 --- a/arch/arm/mach-tegra/cpuidle-tegra20.c +++ b/arch/arm/mach-tegra/cpuidle-tegra20.c @@ -87,15 +87,17 @@ static bool tegra20_cpu_cluster_power_down(struct cpuidle_device *dev, struct cpuidle_driver *drv, int index) { + bool ret; + while (!tegra_cpu_rail_off_ready()) cpu_relax(); - tegra_idle_lp2_last(); + ret = !tegra_idle_lp2_last(); if (cpu_online(1)) tegra20_wake_cpu1_from_reset(); - return true; + return ret; } #ifdef CONFIG_SMP diff --git a/arch/arm/mach-tegra/cpuidle-tegra30.c b/arch/arm/mach-tegra/cpuidle-tegra30.c index a3ce8dabfe18..17cbd118abee 100644 --- a/arch/arm/mach-tegra/cpuidle-tegra30.c +++ b/arch/arm/mach-tegra/cpuidle-tegra30.c @@ -68,9 +68,7 @@ static bool tegra30_cpu_cluster_power_down(struct cpuidle_device *dev, return false; } - tegra_idle_lp2_last(); - - return true; + return !tegra_idle_lp2_last(); } #ifdef CONFIG_SMP diff --git a/arch/arm/mach-tegra/pm.c b/arch/arm/mach-tegra/pm.c index a72f9a2d3cb7..a094acaca307 100644 --- a/arch/arm/mach-tegra/pm.c +++ b/arch/arm/mach-tegra/pm.c @@ -189,14 +189,16 @@ static void tegra_pm_set(enum tegra_suspend_mode mode) tegra_pmc_enter_suspend_mode(mode); } -void tegra_idle_lp2_last(void) +int tegra_idle_lp2_last(void) { + int err; + tegra_pm_set(TEGRA_SUSPEND_LP2); cpu_cluster_pm_enter(); suspend_cpu_complex(); - cpu_suspend(PHYS_OFFSET - PAGE_OFFSET, &tegra_sleep_cpu); + err = cpu_suspend(PHYS_OFFSET - PAGE_OFFSET, &tegra_sleep_cpu); /* * Resume L2 cache if it wasn't re-enabled early during resume, @@ -208,6 +210,8 @@ void tegra_idle_lp2_last(void) restore_cpu_complex(); cpu_cluster_pm_exit(); + + return err; } enum tegra_suspend_mode tegra_pm_validate_suspend_mode( diff --git a/arch/arm/mach-tegra/pm.h b/arch/arm/mach-tegra/pm.h index 2c294f6365c0..7d72f31dee77 100644 --- a/arch/arm/mach-tegra/pm.h +++ b/arch/arm/mach-tegra/pm.h @@ -25,7 +25,7 @@ void tegra30_sleep_core_init(void); void tegra_clear_cpu_in_lp2(void); void tegra_set_cpu_in_lp2(void); -void tegra_idle_lp2_last(void); +int tegra_idle_lp2_last(void); extern void (*tegra_tear_down_cpu)(void); #ifdef CONFIG_PM_SLEEP From patchwork Tue Oct 15 17:00:03 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Dmitry Osipenko X-Patchwork-Id: 11191269 Return-Path: Received: from mail.kernel.org (pdx-korg-mail-1.web.codeaurora.org [172.30.200.123]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id 02F5D912 for ; Tue, 15 Oct 2019 17:02:53 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.kernel.org (Postfix) with ESMTP id CB580214AE for ; Tue, 15 Oct 2019 17:02:52 +0000 (UTC) Authentication-Results: mail.kernel.org; dkim=pass (2048-bit key) header.d=gmail.com header.i=@gmail.com header.b="j9yuI6Y7" Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S2388447AbfJORBr (ORCPT ); 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Tue, 15 Oct 2019 10:01:44 -0700 (PDT) From: Dmitry Osipenko To: Thierry Reding , Jonathan Hunter , Peter De Schrijver , "Rafael J. Wysocki" , Daniel Lezcano Cc: linux-pm@vger.kernel.org, linux-tegra@vger.kernel.org, linux-kernel@vger.kernel.org Subject: [PATCH v6 06/18] ARM: tegra: Expose PM functions required for new cpuidle driver Date: Tue, 15 Oct 2019 20:00:03 +0300 Message-Id: <20191015170015.1135-7-digetx@gmail.com> X-Mailer: git-send-email 2.23.0 In-Reply-To: <20191015170015.1135-1-digetx@gmail.com> References: <20191015170015.1135-1-digetx@gmail.com> MIME-Version: 1.0 Sender: linux-pm-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-pm@vger.kernel.org The upcoming unified CPUIDLE driver will be added to the drivers/cpuidle/ directory and it will require all these exposed Tegra PM-core functions. Signed-off-by: Dmitry Osipenko --- arch/arm/mach-tegra/cpuidle-tegra114.c | 3 +- arch/arm/mach-tegra/cpuidle-tegra20.c | 2 +- arch/arm/mach-tegra/cpuidle-tegra30.c | 3 +- arch/arm/mach-tegra/irq.c | 3 +- arch/arm/mach-tegra/pm.h | 8 ----- arch/arm/mach-tegra/sleep.h | 1 - arch/arm/mach-tegra/tegra.c | 1 - .../mach-tegra => include/soc/tegra}/irq.h | 8 +++-- include/soc/tegra/pm.h | 31 +++++++++++++++++++ 9 files changed, 43 insertions(+), 17 deletions(-) rename {arch/arm/mach-tegra => include/soc/tegra}/irq.h (59%) diff --git a/arch/arm/mach-tegra/cpuidle-tegra114.c b/arch/arm/mach-tegra/cpuidle-tegra114.c index 5118f777fd66..2d8527837aeb 100644 --- a/arch/arm/mach-tegra/cpuidle-tegra114.c +++ b/arch/arm/mach-tegra/cpuidle-tegra114.c @@ -12,13 +12,14 @@ #include +#include + #include #include #include #include #include "cpuidle.h" -#include "pm.h" #include "sleep.h" #ifdef CONFIG_PM_SLEEP diff --git a/arch/arm/mach-tegra/cpuidle-tegra20.c b/arch/arm/mach-tegra/cpuidle-tegra20.c index 74ba37992259..7de2151a2e0c 100644 --- a/arch/arm/mach-tegra/cpuidle-tegra20.c +++ b/arch/arm/mach-tegra/cpuidle-tegra20.c @@ -19,6 +19,7 @@ #include #include +#include #include #include @@ -27,7 +28,6 @@ #include "cpuidle.h" #include "iomap.h" #include "irq.h" -#include "pm.h" #include "reset.h" #include "sleep.h" diff --git a/arch/arm/mach-tegra/cpuidle-tegra30.c b/arch/arm/mach-tegra/cpuidle-tegra30.c index 17cbd118abee..3e91c29891f7 100644 --- a/arch/arm/mach-tegra/cpuidle-tegra30.c +++ b/arch/arm/mach-tegra/cpuidle-tegra30.c @@ -17,12 +17,13 @@ #include #include +#include + #include #include #include #include "cpuidle.h" -#include "pm.h" #include "sleep.h" #ifdef CONFIG_PM_SLEEP diff --git a/arch/arm/mach-tegra/irq.c b/arch/arm/mach-tegra/irq.c index ace7a390b5fe..4e1ee70b2a3f 100644 --- a/arch/arm/mach-tegra/irq.c +++ b/arch/arm/mach-tegra/irq.c @@ -18,9 +18,10 @@ #include #include +#include + #include "board.h" #include "iomap.h" -#include "irq.h" #define SGI_MASK 0xFFFF diff --git a/arch/arm/mach-tegra/pm.h b/arch/arm/mach-tegra/pm.h index 7d72f31dee77..81525f5f4a44 100644 --- a/arch/arm/mach-tegra/pm.h +++ b/arch/arm/mach-tegra/pm.h @@ -23,20 +23,12 @@ void tegra20_sleep_core_init(void); void tegra30_lp1_iram_hook(void); void tegra30_sleep_core_init(void); -void tegra_clear_cpu_in_lp2(void); -void tegra_set_cpu_in_lp2(void); -int tegra_idle_lp2_last(void); extern void (*tegra_tear_down_cpu)(void); #ifdef CONFIG_PM_SLEEP void tegra_init_suspend(void); -int tegra_pm_park_secondary_cpu(unsigned long cpu); #else static inline void tegra_init_suspend(void) {} -static inline int tegra_pm_park_secondary_cpu(unsigned long cpu) -{ - return -ENOTSUPP; -} #endif #endif /* _MACH_TEGRA_PM_H_ */ diff --git a/arch/arm/mach-tegra/sleep.h b/arch/arm/mach-tegra/sleep.h index 4978def9db46..4718a3cb45a1 100644 --- a/arch/arm/mach-tegra/sleep.h +++ b/arch/arm/mach-tegra/sleep.h @@ -122,7 +122,6 @@ void tegra20_hotplug_shutdown(void); void tegra30_hotplug_shutdown(void); void tegra20_tear_down_cpu(void); -int tegra30_sleep_cpu_secondary_finish(unsigned long); void tegra30_tear_down_cpu(void); #endif diff --git a/arch/arm/mach-tegra/tegra.c b/arch/arm/mach-tegra/tegra.c index e512e606eabd..00aaf495bbf7 100644 --- a/arch/arm/mach-tegra/tegra.c +++ b/arch/arm/mach-tegra/tegra.c @@ -42,7 +42,6 @@ #include "common.h" #include "cpuidle.h" #include "iomap.h" -#include "irq.h" #include "pm.h" #include "reset.h" #include "sleep.h" diff --git a/arch/arm/mach-tegra/irq.h b/include/soc/tegra/irq.h similarity index 59% rename from arch/arm/mach-tegra/irq.h rename to include/soc/tegra/irq.h index 7a94cf121448..8eb11a7109e4 100644 --- a/arch/arm/mach-tegra/irq.h +++ b/include/soc/tegra/irq.h @@ -3,9 +3,11 @@ * Copyright (c) 2012, NVIDIA Corporation. All rights reserved. */ -#ifndef __TEGRA_IRQ_H -#define __TEGRA_IRQ_H +#ifndef __SOC_TEGRA_IRQ_H +#define __SOC_TEGRA_IRQ_H +#if defined(CONFIG_ARM) bool tegra_pending_sgi(void); - #endif + +#endif /* __SOC_TEGRA_IRQ_H */ diff --git a/include/soc/tegra/pm.h b/include/soc/tegra/pm.h index 951fcd738d55..1974e8405098 100644 --- a/include/soc/tegra/pm.h +++ b/include/soc/tegra/pm.h @@ -6,6 +6,8 @@ #ifndef __SOC_TEGRA_PM_H__ #define __SOC_TEGRA_PM_H__ +#include + enum tegra_suspend_mode { TEGRA_SUSPEND_NONE = 0, TEGRA_SUSPEND_LP2, /* CPU voltage off */ @@ -20,6 +22,12 @@ tegra_pm_validate_suspend_mode(enum tegra_suspend_mode mode); /* low-level resume entry point */ void tegra_resume(void); + +int tegra30_sleep_cpu_secondary_finish(unsigned long arg); +void tegra_clear_cpu_in_lp2(void); +void tegra_set_cpu_in_lp2(void); +int tegra_idle_lp2_last(void); +int tegra_pm_park_secondary_cpu(unsigned long cpu); #else static inline enum tegra_suspend_mode tegra_pm_validate_suspend_mode(enum tegra_suspend_mode mode) @@ -30,6 +38,29 @@ tegra_pm_validate_suspend_mode(enum tegra_suspend_mode mode) static inline void tegra_resume(void) { } + +static inline int tegra30_sleep_cpu_secondary_finish(unsigned long arg) +{ + return -ENOTSUPP; +} + +static inline void tegra_clear_cpu_in_lp2(void) +{ +} + +static inline void tegra_set_cpu_in_lp2(void) +{ +} + +static inline int tegra_idle_lp2_last(void) +{ + return -ENOTSUPP; +} + +static inline int tegra_pm_park_secondary_cpu(unsigned long cpu) +{ + return -ENOTSUPP; +} #endif /* CONFIG_PM_SLEEP */ #endif /* __SOC_TEGRA_PM_H__ */ From patchwork Tue Oct 15 17:00:04 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Dmitry Osipenko X-Patchwork-Id: 11191267 Return-Path: Received: from mail.kernel.org (pdx-korg-mail-1.web.codeaurora.org [172.30.200.123]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id 1C02B912 for ; Tue, 15 Oct 2019 17:02:42 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.kernel.org (Postfix) with ESMTP id EEBFA20872 for ; Tue, 15 Oct 2019 17:02:41 +0000 (UTC) Authentication-Results: mail.kernel.org; dkim=pass (2048-bit key) header.d=gmail.com header.i=@gmail.com header.b="lX1R27iI" Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S2388679AbfJORCl (ORCPT ); Tue, 15 Oct 2019 13:02:41 -0400 Received: from mail-lj1-f196.google.com ([209.85.208.196]:41978 "EHLO mail-lj1-f196.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S2388438AbfJORBu (ORCPT ); Tue, 15 Oct 2019 13:01:50 -0400 Received: by mail-lj1-f196.google.com with SMTP id f5so21033055ljg.8; Tue, 15 Oct 2019 10:01:46 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=QSMnw45JPFQtRfFe6wAse8MxCVbZQdqVqJYx4LBrtpo=; b=lX1R27iI8h1Xha+X+JPsKqrWp1OBUUp8VpNsRdYxQgZWUgcAyWhFmlSZZB+sY5H54h M/4vthZtVFrycGmug8T8gI8Md3bYcYzsOrmErYAtqXm66yQZquIodvFVryR6aIXK9r7c xtA28vA46eLHncWMvL2MQCwFg/YEzp2pJDIhSM60uj4gTcaL1wAUkcmqHow/njyxh2uI eHU+MR7B36gytdZ92XO2XW6QrcWZjr5zrY8YPM4wqdfsjLt0/g+Lf9GUqCXW0J/9MCyq gTWLPDWRMPymWb7RQRq1V+ivNeVmqO9yjUVgITF76qf5OxT+ORFleCZspS1ihHD5donR RtEA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=QSMnw45JPFQtRfFe6wAse8MxCVbZQdqVqJYx4LBrtpo=; b=Ruvv8ZHgxIKhRCGljlMXt8sZN3Mzg77lQdtaYOatHxizJz5uHp+YgUffAGcJbUJH+g J61+bc2N9OoHq/VyHAfYFnEevqneV2DAaSl0gNft5wXZ4b+Zf2t9YsWQ3wi1wTORw3hy 7xKFgAcsbzWSVwxYKbyE+7fmCTVX24tSx3F/yoph2tn5vuO0U7w9V571cFSCxTlE6K3O lgNba40/jp87A3BeS3zEnibGG7pgb23Af4tP/FgXGzieb1Zfhh4NZ77r1tekOQpaiWSm rwZZzGnmXs3T7f5gNHY5jxGz4Mkpw6WO5zPDo0PNVedsmJO047EC2kedXC7MN+QnjQjj 3z4w== X-Gm-Message-State: APjAAAVpga2U688Du8dNOjUXZ0BsdRbQHIFAcuUvfLEkkmHG0Rg1wnr6 GMykysTAZ7DZLqmb4/ILm0Y= X-Google-Smtp-Source: APXvYqy0QdWCXbt953sln1qOOBktgEsvLzCUyzUWIxFxHC0kjALb0zucjoYcbdDU8XCizHvLXAsexw== X-Received: by 2002:a05:651c:1213:: with SMTP id i19mr16538348lja.19.1571158906147; Tue, 15 Oct 2019 10:01:46 -0700 (PDT) Received: from localhost.localdomain ([94.29.10.250]) by smtp.gmail.com with ESMTPSA id t6sm5144992ljd.102.2019.10.15.10.01.45 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 15 Oct 2019 10:01:45 -0700 (PDT) From: Dmitry Osipenko To: Thierry Reding , Jonathan Hunter , Peter De Schrijver , "Rafael J. Wysocki" , Daniel Lezcano Cc: linux-pm@vger.kernel.org, linux-tegra@vger.kernel.org, linux-kernel@vger.kernel.org Subject: [PATCH v6 07/18] ARM: tegra: Rename some of the newly exposed PM functions Date: Tue, 15 Oct 2019 20:00:04 +0300 Message-Id: <20191015170015.1135-8-digetx@gmail.com> X-Mailer: git-send-email 2.23.0 In-Reply-To: <20191015170015.1135-1-digetx@gmail.com> References: <20191015170015.1135-1-digetx@gmail.com> MIME-Version: 1.0 Sender: linux-pm-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-pm@vger.kernel.org Rename some of the recently exposed PM functions, prefixing them with "tegra_pm_" in order to make the naming of the PM functions consistent. Signed-off-by: Dmitry Osipenko --- arch/arm/mach-tegra/cpuidle-tegra114.c | 6 +++--- arch/arm/mach-tegra/cpuidle-tegra20.c | 6 +++--- arch/arm/mach-tegra/cpuidle-tegra30.c | 8 ++++---- arch/arm/mach-tegra/pm.c | 10 +++++----- arch/arm/mach-tegra/sleep-tegra30.S | 6 +++--- include/soc/tegra/pm.h | 16 ++++++++-------- 6 files changed, 26 insertions(+), 26 deletions(-) diff --git a/arch/arm/mach-tegra/cpuidle-tegra114.c b/arch/arm/mach-tegra/cpuidle-tegra114.c index 2d8527837aeb..858c30cc5dc7 100644 --- a/arch/arm/mach-tegra/cpuidle-tegra114.c +++ b/arch/arm/mach-tegra/cpuidle-tegra114.c @@ -35,17 +35,17 @@ static int tegra114_idle_power_down(struct cpuidle_device *dev, { local_fiq_disable(); - tegra_set_cpu_in_lp2(); + tegra_pm_set_cpu_in_lp2(); cpu_pm_enter(); call_firmware_op(prepare_idle, TF_PM_MODE_LP2_NOFLUSH_L2); /* Do suspend by ourselves if the firmware does not implement it */ if (call_firmware_op(do_idle, 0) == -ENOSYS) - cpu_suspend(0, tegra30_sleep_cpu_secondary_finish); + cpu_suspend(0, tegra30_pm_secondary_cpu_suspend); cpu_pm_exit(); - tegra_clear_cpu_in_lp2(); + tegra_pm_clear_cpu_in_lp2(); local_fiq_enable(); diff --git a/arch/arm/mach-tegra/cpuidle-tegra20.c b/arch/arm/mach-tegra/cpuidle-tegra20.c index 7de2151a2e0c..77702dd42479 100644 --- a/arch/arm/mach-tegra/cpuidle-tegra20.c +++ b/arch/arm/mach-tegra/cpuidle-tegra20.c @@ -92,7 +92,7 @@ static bool tegra20_cpu_cluster_power_down(struct cpuidle_device *dev, while (!tegra_cpu_rail_off_ready()) cpu_relax(); - ret = !tegra_idle_lp2_last(); + ret = !tegra_pm_enter_lp2(); if (cpu_online(1)) tegra20_wake_cpu1_from_reset(); @@ -137,7 +137,7 @@ static int tegra20_idle_lp2_coupled(struct cpuidle_device *dev, local_fiq_disable(); - tegra_set_cpu_in_lp2(); + tegra_pm_set_cpu_in_lp2(); cpu_pm_enter(); if (dev->cpu == 0) @@ -146,7 +146,7 @@ static int tegra20_idle_lp2_coupled(struct cpuidle_device *dev, entered_lp2 = tegra20_idle_enter_lp2_cpu_1(dev, drv, index); cpu_pm_exit(); - tegra_clear_cpu_in_lp2(); + tegra_pm_clear_cpu_in_lp2(); local_fiq_enable(); diff --git a/arch/arm/mach-tegra/cpuidle-tegra30.c b/arch/arm/mach-tegra/cpuidle-tegra30.c index 3e91c29891f7..a4f0add46a27 100644 --- a/arch/arm/mach-tegra/cpuidle-tegra30.c +++ b/arch/arm/mach-tegra/cpuidle-tegra30.c @@ -69,7 +69,7 @@ static bool tegra30_cpu_cluster_power_down(struct cpuidle_device *dev, return false; } - return !tegra_idle_lp2_last(); + return !tegra_pm_enter_lp2(); } #ifdef CONFIG_SMP @@ -79,7 +79,7 @@ static bool tegra30_cpu_core_power_down(struct cpuidle_device *dev, { smp_wmb(); - cpu_suspend(0, tegra30_sleep_cpu_secondary_finish); + cpu_suspend(0, tegra30_pm_secondary_cpu_suspend); return true; } @@ -100,7 +100,7 @@ static int tegra30_idle_lp2(struct cpuidle_device *dev, local_fiq_disable(); - tegra_set_cpu_in_lp2(); + tegra_pm_set_cpu_in_lp2(); cpu_pm_enter(); if (dev->cpu == 0) @@ -109,7 +109,7 @@ static int tegra30_idle_lp2(struct cpuidle_device *dev, entered_lp2 = tegra30_cpu_core_power_down(dev, drv, index); cpu_pm_exit(); - tegra_clear_cpu_in_lp2(); + tegra_pm_clear_cpu_in_lp2(); local_fiq_enable(); diff --git a/arch/arm/mach-tegra/pm.c b/arch/arm/mach-tegra/pm.c index a094acaca307..7d9ef26e52a7 100644 --- a/arch/arm/mach-tegra/pm.c +++ b/arch/arm/mach-tegra/pm.c @@ -110,7 +110,7 @@ static void suspend_cpu_complex(void) flowctrl_cpu_suspend_enter(cpu); } -void tegra_clear_cpu_in_lp2(void) +void tegra_pm_clear_cpu_in_lp2(void) { int phy_cpu_id = cpu_logical_map(smp_processor_id()); u32 *cpu_in_lp2 = tegra_cpu_lp2_mask; @@ -123,7 +123,7 @@ void tegra_clear_cpu_in_lp2(void) spin_unlock(&tegra_lp2_lock); } -void tegra_set_cpu_in_lp2(void) +void tegra_pm_set_cpu_in_lp2(void) { int phy_cpu_id = cpu_logical_map(smp_processor_id()); u32 *cpu_in_lp2 = tegra_cpu_lp2_mask; @@ -189,7 +189,7 @@ static void tegra_pm_set(enum tegra_suspend_mode mode) tegra_pmc_enter_suspend_mode(mode); } -int tegra_idle_lp2_last(void) +int tegra_pm_enter_lp2(void) { int err; @@ -356,7 +356,7 @@ static int tegra_suspend_enter(suspend_state_t state) tegra_suspend_enter_lp1(); break; case TEGRA_SUSPEND_LP2: - tegra_set_cpu_in_lp2(); + tegra_pm_set_cpu_in_lp2(); break; default: break; @@ -377,7 +377,7 @@ static int tegra_suspend_enter(suspend_state_t state) tegra_suspend_exit_lp1(); break; case TEGRA_SUSPEND_LP2: - tegra_clear_cpu_in_lp2(); + tegra_pm_clear_cpu_in_lp2(); break; default: break; diff --git a/arch/arm/mach-tegra/sleep-tegra30.S b/arch/arm/mach-tegra/sleep-tegra30.S index b408fa56eb89..386319a3d2d2 100644 --- a/arch/arm/mach-tegra/sleep-tegra30.S +++ b/arch/arm/mach-tegra/sleep-tegra30.S @@ -262,11 +262,11 @@ ENTRY(tegra30_sleep_core_finish) ENDPROC(tegra30_sleep_core_finish) /* - * tegra30_sleep_cpu_secondary_finish(unsigned long v2p) + * tegra30_pm_secondary_cpu_suspend(unsigned long unused_arg) * * Enters LP2 on secondary CPU by exiting coherency and powergating the CPU. */ -ENTRY(tegra30_sleep_cpu_secondary_finish) +ENTRY(tegra30_pm_secondary_cpu_suspend) mov r7, lr /* Flush and disable the L1 data cache */ @@ -278,7 +278,7 @@ ENTRY(tegra30_sleep_cpu_secondary_finish) bl tegra30_cpu_shutdown mov r0, #1 @ never return here ret r7 -ENDPROC(tegra30_sleep_cpu_secondary_finish) +ENDPROC(tegra30_pm_secondary_cpu_suspend) /* * tegra30_tear_down_cpu diff --git a/include/soc/tegra/pm.h b/include/soc/tegra/pm.h index 1974e8405098..08477d7bfab9 100644 --- a/include/soc/tegra/pm.h +++ b/include/soc/tegra/pm.h @@ -23,10 +23,10 @@ tegra_pm_validate_suspend_mode(enum tegra_suspend_mode mode); /* low-level resume entry point */ void tegra_resume(void); -int tegra30_sleep_cpu_secondary_finish(unsigned long arg); -void tegra_clear_cpu_in_lp2(void); -void tegra_set_cpu_in_lp2(void); -int tegra_idle_lp2_last(void); +int tegra30_pm_secondary_cpu_suspend(unsigned long arg); +void tegra_pm_clear_cpu_in_lp2(void); +void tegra_pm_set_cpu_in_lp2(void); +int tegra_pm_enter_lp2(void); int tegra_pm_park_secondary_cpu(unsigned long cpu); #else static inline enum tegra_suspend_mode @@ -39,20 +39,20 @@ static inline void tegra_resume(void) { } -static inline int tegra30_sleep_cpu_secondary_finish(unsigned long arg) +static inline int tegra30_pm_secondary_cpu_suspend(unsigned long arg) { return -ENOTSUPP; } -static inline void tegra_clear_cpu_in_lp2(void) +static inline void tegra_pm_clear_cpu_in_lp2(void) { } -static inline void tegra_set_cpu_in_lp2(void) +static inline void tegra_pm_set_cpu_in_lp2(void) { } -static inline int tegra_idle_lp2_last(void) +static inline int tegra_pm_enter_lp2(void) { return -ENOTSUPP; } From patchwork Tue Oct 15 17:00:05 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Dmitry Osipenko X-Patchwork-Id: 11191245 Return-Path: Received: from mail.kernel.org (pdx-korg-mail-1.web.codeaurora.org [172.30.200.123]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id 42AFB912 for ; Tue, 15 Oct 2019 17:01:51 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.kernel.org (Postfix) with ESMTP id 21B462084B for ; Tue, 15 Oct 2019 17:01:51 +0000 (UTC) Authentication-Results: mail.kernel.org; dkim=pass (2048-bit key) header.d=gmail.com header.i=@gmail.com header.b="R5BzyqQO" Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S2388491AbfJORBu (ORCPT ); Tue, 15 Oct 2019 13:01:50 -0400 Received: from mail-lf1-f65.google.com ([209.85.167.65]:41128 "EHLO mail-lf1-f65.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S2388448AbfJORBt (ORCPT ); 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Tue, 15 Oct 2019 10:01:47 -0700 (PDT) Received: from localhost.localdomain ([94.29.10.250]) by smtp.gmail.com with ESMTPSA id t6sm5144992ljd.102.2019.10.15.10.01.46 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 15 Oct 2019 10:01:46 -0700 (PDT) From: Dmitry Osipenko To: Thierry Reding , Jonathan Hunter , Peter De Schrijver , "Rafael J. Wysocki" , Daniel Lezcano Cc: linux-pm@vger.kernel.org, linux-tegra@vger.kernel.org, linux-kernel@vger.kernel.org Subject: [PATCH v6 08/18] ARM: tegra: Make outer_disable() open-coded Date: Tue, 15 Oct 2019 20:00:05 +0300 Message-Id: <20191015170015.1135-9-digetx@gmail.com> X-Mailer: git-send-email 2.23.0 In-Reply-To: <20191015170015.1135-1-digetx@gmail.com> References: <20191015170015.1135-1-digetx@gmail.com> MIME-Version: 1.0 Sender: linux-pm-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-pm@vger.kernel.org The outer_disable() of Tegra's suspend code is open-coded now since that helper produces spurious warning message about secondary CPUs being online when CPU enters into LP2 from cpuidle. The secondaries are actually halted by the cpuidle driver on entering into LP2 idle-state, but the online status is not touched by the cpuidle. This fixes a storm of warnings once LP2 idling state is enabled on Tegra30. The outer_disable() helper has sanity checks for interrupts and secondary CPUs being disabled and we are pretty confident about the interrupts state during of CPU idling / system suspend. The rail-off status check is added in this patch as equivalent for the "num_online_cpus() > 1". Signed-off-by: Dmitry Osipenko --- arch/arm/mach-tegra/pm.c | 11 ++++++++--- 1 file changed, 8 insertions(+), 3 deletions(-) diff --git a/arch/arm/mach-tegra/pm.c b/arch/arm/mach-tegra/pm.c index 7d9ef26e52a7..d1e1a61b12cf 100644 --- a/arch/arm/mach-tegra/pm.c +++ b/arch/arm/mach-tegra/pm.c @@ -138,6 +138,10 @@ void tegra_pm_set_cpu_in_lp2(void) static int tegra_sleep_cpu(unsigned long v2p) { + if (tegra_cpu_car_ops->rail_off_ready && + WARN_ON(!tegra_cpu_rail_off_ready())) + return -EBUSY; + /* * L2 cache disabling using kernel API only allowed when all * secondary CPU's are offline. Cache have to be disabled with @@ -146,9 +150,10 @@ static int tegra_sleep_cpu(unsigned long v2p) * if any of secondary CPU's is online and this is the LP2-idle * code-path only for Tegra20/30. */ - if (trusted_foundations_registered()) - outer_disable(); - +#ifdef CONFIG_OUTER_CACHE + if (trusted_foundations_registered() && outer_cache.disable) + outer_cache.disable(); +#endif /* * Note that besides of setting up CPU reset vector this firmware * call may also do the following, depending on the FW version: From patchwork Tue Oct 15 17:00:06 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Dmitry Osipenko X-Patchwork-Id: 11191265 Return-Path: Received: from mail.kernel.org (pdx-korg-mail-1.web.codeaurora.org [172.30.200.123]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id E4DED1390 for ; Tue, 15 Oct 2019 17:02:41 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.kernel.org (Postfix) with ESMTP id C3BF12168B for ; Tue, 15 Oct 2019 17:02:40 +0000 (UTC) Authentication-Results: mail.kernel.org; dkim=pass (2048-bit key) header.d=gmail.com header.i=@gmail.com header.b="g9AuvPk1" Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1727130AbfJORCg (ORCPT ); Tue, 15 Oct 2019 13:02:36 -0400 Received: from mail-lf1-f66.google.com ([209.85.167.66]:42135 "EHLO mail-lf1-f66.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S2388477AbfJORBu (ORCPT ); Tue, 15 Oct 2019 13:01:50 -0400 Received: by mail-lf1-f66.google.com with SMTP id c195so15062261lfg.9; Tue, 15 Oct 2019 10:01:49 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=KGjmb/MNUm+G9U/DTi2/uDEoahkabTTfxcEHeZSx3QE=; b=g9AuvPk1TIOd9q5Gk7ZwrjT8qZf2kcjsPpk0T4MRH4FC9nDA/8nrAWV5+uOVX4n/Oh U2ayMVOBteVql7xCAFrw4t8lwrt5m9E6RI+I7/2chcxaLmP9URYSuadme0BFDAhVMlhj ca8Ub2KgsiV47AVlEEYv//cWxobBoJZKieKHJPUfiA1cjt8JfEtAhdYUUcKe6tK/z5hD EDSX4AMGnkrdbbKfM+oqGjIrnn9E/hsxKevKqx8Ylbt0bBAv9i2ekQ617uSaA9Y9U/iD CNLJmWGCvz3LgloPUeJ23FWYQe3c0ej5mahQhUz1EiR2mBr2Z596DzlNbnNYJnviJX3e s+OQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=KGjmb/MNUm+G9U/DTi2/uDEoahkabTTfxcEHeZSx3QE=; b=rYL9Yf6LxA8VfLU0pu5ld2kAEo4QXmE6FaHra+CMIFQ6FjN0yqYk0iHQP1i2jyBstl RNWGRVjXzuWUvnKLr8NicEgcOGDaBLSKI6x+zjdwQc8xhn2M02azuM323mjZjN5vyuCH CGZeArdA2h1rIvuM3S7IY3cFKC2QAnAjEIf7fV4At2PnsaS3dftATQ4Gsj0Hkrot4EWk 7G8Xfce7d/wamA22MfJ3lqHwiWPj5+PYtBXyGZzotcror0Rr87yQaTX9dc2tBnUsXFVS xzAjrlu31ztcun0A3NcuHy4SEl7vFg0or4n3n26sNDTuO4beogOKpZVw8q1w5vYhpArt V8Jg== X-Gm-Message-State: APjAAAWZL8v3L41b3SE3V7RpNxoeUy+ogw7HELYwKgrFbkYxiOPCduT1 Zcld1bo49Rgcbh3U93Vf/MM= X-Google-Smtp-Source: APXvYqzJLD+MPyOOk8yuZBxjglv6s8ujesc90gedmP7eEFf8v3gSUyESdgpGETsqe6EhKvS3AbHlrg== X-Received: by 2002:ac2:44ae:: with SMTP id c14mr21275270lfm.116.1571158908279; Tue, 15 Oct 2019 10:01:48 -0700 (PDT) Received: from localhost.localdomain ([94.29.10.250]) by smtp.gmail.com with ESMTPSA id t6sm5144992ljd.102.2019.10.15.10.01.47 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 15 Oct 2019 10:01:47 -0700 (PDT) From: Dmitry Osipenko To: Thierry Reding , Jonathan Hunter , Peter De Schrijver , "Rafael J. Wysocki" , Daniel Lezcano Cc: linux-pm@vger.kernel.org, linux-tegra@vger.kernel.org, linux-kernel@vger.kernel.org Subject: [PATCH v6 09/18] clk: tegra: Add missing stubs for the case of !CONFIG_PM_SLEEP Date: Tue, 15 Oct 2019 20:00:06 +0300 Message-Id: <20191015170015.1135-10-digetx@gmail.com> X-Mailer: git-send-email 2.23.0 In-Reply-To: <20191015170015.1135-1-digetx@gmail.com> References: <20191015170015.1135-1-digetx@gmail.com> MIME-Version: 1.0 Sender: linux-pm-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-pm@vger.kernel.org The new CPUIDLE driver uses the Tegra's CLK API and that driver won't strictly depend on CONFIG_PM_SLEEP, hence add the required stubs in order to allow compiling of the new driver with the CONFIG_PM_SLEEP=n. Signed-off-by: Dmitry Osipenko --- include/linux/clk/tegra.h | 13 +++++++++++++ 1 file changed, 13 insertions(+) diff --git a/include/linux/clk/tegra.h b/include/linux/clk/tegra.h index 6a7cbc3cfadc..2b1b35240074 100644 --- a/include/linux/clk/tegra.h +++ b/include/linux/clk/tegra.h @@ -108,6 +108,19 @@ static inline void tegra_cpu_clock_resume(void) tegra_cpu_car_ops->resume(); } +#else +static inline bool tegra_cpu_rail_off_ready(void) +{ + return false; +} + +static inline void tegra_cpu_clock_suspend(void) +{ +} + +static inline void tegra_cpu_clock_resume(void) +{ +} #endif extern void tegra210_xusb_pll_hw_control_enable(void); From patchwork Tue Oct 15 17:00:07 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Dmitry Osipenko X-Patchwork-Id: 11191263 Return-Path: Received: from mail.kernel.org (pdx-korg-mail-1.web.codeaurora.org [172.30.200.123]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id CD2391390 for ; Tue, 15 Oct 2019 17:02:35 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.kernel.org (Postfix) with ESMTP id AC2EF217F9 for ; Tue, 15 Oct 2019 17:02:35 +0000 (UTC) Authentication-Results: mail.kernel.org; dkim=pass (2048-bit key) header.d=gmail.com header.i=@gmail.com header.b="rPkfL2mr" Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S2388625AbfJORCb (ORCPT ); Tue, 15 Oct 2019 13:02:31 -0400 Received: from mail-lf1-f67.google.com ([209.85.167.67]:39263 "EHLO mail-lf1-f67.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S2388490AbfJORBv (ORCPT ); Tue, 15 Oct 2019 13:01:51 -0400 Received: by mail-lf1-f67.google.com with SMTP id 195so2117202lfj.6; Tue, 15 Oct 2019 10:01:49 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=dz3WKDPiIUb4/FxW8Zr/Vd4hYvS9IVQYUuzS70hcV3w=; b=rPkfL2mrjxvsc/Uy5m5Kqpy4xiGpkxUs4EGn42b5nPxzpFWMiWSFgoanng8FB26YV1 f8XHzpG0RTmQkSAytxOh8WWkt37AQSh9Ko19Qo63mwL7n3NNzlMYYBmdBpRJxabiuf4Q BvyDWl8Ktn0btvDAkwgR5IPcbtgdrqTMFQXbwk56mIpiH7aBEqLMBKF0lKiUY5BvsPvv 6w2z9p4FTogPesAocXCtVWajBVbk1GLpZbKqsr9L4JKFxafllKywFFNBayhs2VNdbrIt IFVQq4wSFroJlY/N16gBS2/TE4J6yic+eCZwpdmoqmkHyNlFMX5nggYfT9UnAUsv3a+s 0gyg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=dz3WKDPiIUb4/FxW8Zr/Vd4hYvS9IVQYUuzS70hcV3w=; b=Ry5GXbFZ1BYbZrophbUOqJ2fOEt6heT3yAwrrJivPAag2OLECsRaNrK4oR34x3hdYh QCfJ2P7bPdNcgn2MBYZXOIuLaqjtPii35ZEffpQ829dxF7CFApXkKtwjzi7l7oHK1HNs MpzFAm+B/lk6ymzpXTYMW2ZSISH7OngdgLZXFIjcOqFZfFipgrOLL1YLxv7kQQQjE0M0 oKm201VsXKIDzSQVixTKEIx6IBbwwTmC0mq5FtnHNPPldMeR65wfvV/VZ7Ne5ALV67Dt 8Ww4VHW15H/zbff6icuUTTX0MbAUkaxU97mdF83YWVvzxgFw+pB+D6w3itV7HiSz9L4u 1lag== X-Gm-Message-State: APjAAAUlIheiyKwkHRimw9SySfgE+AU/nDusO0YaL9e3JtHHuTvH2TNo QztRXw8OF+8HNSNoaRLcEBQ= X-Google-Smtp-Source: APXvYqwD/ObSmMTlkh6dGt9Nz+GxrpgcUOSoy/Xk2r6mRJURV62hkWRaiezWN6MOqvhReDQWNIIQUw== X-Received: by 2002:a19:f712:: with SMTP id z18mr19746654lfe.166.1571158909238; Tue, 15 Oct 2019 10:01:49 -0700 (PDT) Received: from localhost.localdomain ([94.29.10.250]) by smtp.gmail.com with ESMTPSA id t6sm5144992ljd.102.2019.10.15.10.01.48 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 15 Oct 2019 10:01:48 -0700 (PDT) From: Dmitry Osipenko To: Thierry Reding , Jonathan Hunter , Peter De Schrijver , "Rafael J. Wysocki" , Daniel Lezcano Cc: linux-pm@vger.kernel.org, linux-tegra@vger.kernel.org, linux-kernel@vger.kernel.org Subject: [PATCH v6 10/18] arm: tegra20: cpuidle: Handle case where secondary CPU hangs on entering LP2 Date: Tue, 15 Oct 2019 20:00:07 +0300 Message-Id: <20191015170015.1135-11-digetx@gmail.com> X-Mailer: git-send-email 2.23.0 In-Reply-To: <20191015170015.1135-1-digetx@gmail.com> References: <20191015170015.1135-1-digetx@gmail.com> MIME-Version: 1.0 Sender: linux-pm-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-pm@vger.kernel.org It is possible that something may go wrong with the secondary CPU, in that case it is much nicer to get a dump of the flow-controller state before hanging machine. Signed-off-by: Dmitry Osipenko --- arch/arm/mach-tegra/cpuidle-tegra20.c | 46 +++++++++++++++++++++++++-- 1 file changed, 44 insertions(+), 2 deletions(-) diff --git a/arch/arm/mach-tegra/cpuidle-tegra20.c b/arch/arm/mach-tegra/cpuidle-tegra20.c index 77702dd42479..bc5873e92af5 100644 --- a/arch/arm/mach-tegra/cpuidle-tegra20.c +++ b/arch/arm/mach-tegra/cpuidle-tegra20.c @@ -83,14 +83,56 @@ static inline void tegra20_wake_cpu1_from_reset(void) } #endif +static void tegra20_report_cpus_state(void) +{ + unsigned int cpu, lcpu; + + pr_err("secondary CPU taking too long to park\n"); + + for_each_cpu(lcpu, cpu_possible_mask) { + cpu = cpu_logical_map(lcpu); + + pr_err("cpu%u: online=%d flowctrl_csr=0x%08x\n", + cpu, cpu_online(lcpu), flowctrl_read_cpu_csr(cpu)); + } +} + +static int tegra20_wait_for_secondary_cpu_parking(void) +{ + unsigned int retries = 3; + + while (retries--) { + ktime_t timeout = ktime_add_ms(ktime_get(), 500); + + /* + * The primary CPU0 core shall wait for the secondaries + * shutdown in order to power-off CPU's cluster safely. + * The timeout value depends on the current CPU frequency, + * it takes about 40-150us in average and over 1000us in + * a worst case scenario. + */ + do { + if (tegra_cpu_rail_off_ready()) + return 0; + + } while (ktime_before(ktime_get(), timeout)); + + tegra20_report_cpus_state(); + } + + pr_err("timed out waiting secondaries to park\n"); + + return -ETIMEDOUT; +} + static bool tegra20_cpu_cluster_power_down(struct cpuidle_device *dev, struct cpuidle_driver *drv, int index) { bool ret; - while (!tegra_cpu_rail_off_ready()) - cpu_relax(); + if (tegra20_wait_for_secondary_cpu_parking()) + return false; ret = !tegra_pm_enter_lp2(); From patchwork Tue Oct 15 17:00:08 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Dmitry Osipenko X-Patchwork-Id: 11191261 Return-Path: Received: from mail.kernel.org (pdx-korg-mail-1.web.codeaurora.org [172.30.200.123]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id C094D1668 for ; Tue, 15 Oct 2019 17:02:29 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.kernel.org (Postfix) with ESMTP id A04ED2168B for ; Tue, 15 Oct 2019 17:02:29 +0000 (UTC) Authentication-Results: mail.kernel.org; dkim=pass (2048-bit key) header.d=gmail.com header.i=@gmail.com header.b="Mo4SxdTQ" Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S2388520AbfJORBx (ORCPT ); Tue, 15 Oct 2019 13:01:53 -0400 Received: from mail-lf1-f68.google.com ([209.85.167.68]:42139 "EHLO mail-lf1-f68.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S2388503AbfJORBw (ORCPT ); Tue, 15 Oct 2019 13:01:52 -0400 Received: by mail-lf1-f68.google.com with SMTP id c195so15062344lfg.9; Tue, 15 Oct 2019 10:01:51 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=Omi0XtqN8Kc5VZbYU+UoqGDpANl8X11C5I6N+y6qX+s=; b=Mo4SxdTQu5aZ5xPEC6HrNLXPT2lhQgbDswpxq6q51db6RbKUyCiGOY0GfU0NKCskMy CF5aDRuUqQ+LKizZv0yLHdtvUZ4+edLb6+WBN76r2oecSd1rxRnuDD7GVhjwhEZeu2Gn PHVMpbsM5ntAEAoy7ZNa9c67PV9g2vsS+u7jIBlUqlSUdO5cVJENE3HOX1MfUly8SQiG tG8Ksz4GNX5Wm4dKgIRj2I0d/beDsUAuEea2qSDQrmFKvd4RwsQFhPzSkYCM+ZDMpu7n vBfgc1jqVwRkPJPpZMq9AXU1FXzCennoYtltVP25jDcu9Mv8flDPy493sz2QQ1kEWK/Z 5s3Q== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=Omi0XtqN8Kc5VZbYU+UoqGDpANl8X11C5I6N+y6qX+s=; b=jOG6i5AynHRToSS3FJcdzfjAwJY4HkQIQAqbNmk4IvlSTvaGZNqpuXFJnvzZuVhV7i qFMBuDe11fIuaYwXVZ2F6H0hFpEWZ/Wkoc5AmG5ixv1tKwtZZSeC0D/4NLJSbmCDrmM4 i3B9LMd5VMCPwW4PSTHAA2ie2gvDvRp0VMNb2kQ0lhay0zCqgWS1vxi2I3c1i/O47Iq/ Z/TdDOSRby+2bTAgBc+Pb/ySAtuIUhHS6PXtSCM0KSnDJ0p6dNs9Fu/e5rgOPsN4oBjV RHoKJVLmgCFEz3nkEtulbcnZ0DI2wjSucALhtSNY12vYLQCkz8YLXfiFpqEqlT+Q6SvJ KuiQ== X-Gm-Message-State: APjAAAV/BH33gX15EF70L4U9O1cgJ14wviP0SJ+FN5jZ5pVy+bcwW2n+ KlP8bBu+U4aAND643MT4Mpk= X-Google-Smtp-Source: APXvYqzwopfSYJZIWLREJUlXfvyJhS8zttW57hQ82Sj+eXZJE2pnYU5hBddOMCd7TKM/lOIvK2JGTg== X-Received: by 2002:a05:6512:482:: with SMTP id v2mr19924709lfq.72.1571158910329; Tue, 15 Oct 2019 10:01:50 -0700 (PDT) Received: from localhost.localdomain ([94.29.10.250]) by smtp.gmail.com with ESMTPSA id t6sm5144992ljd.102.2019.10.15.10.01.49 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 15 Oct 2019 10:01:49 -0700 (PDT) From: Dmitry Osipenko To: Thierry Reding , Jonathan Hunter , Peter De Schrijver , "Rafael J. Wysocki" , Daniel Lezcano Cc: linux-pm@vger.kernel.org, linux-tegra@vger.kernel.org, linux-kernel@vger.kernel.org Subject: [PATCH v6 11/18] arm: tegra20: cpuidle: Make abort_flag atomic Date: Tue, 15 Oct 2019 20:00:08 +0300 Message-Id: <20191015170015.1135-12-digetx@gmail.com> X-Mailer: git-send-email 2.23.0 In-Reply-To: <20191015170015.1135-1-digetx@gmail.com> References: <20191015170015.1135-1-digetx@gmail.com> MIME-Version: 1.0 Sender: linux-pm-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-pm@vger.kernel.org Replace memory accessors with atomic API just to make code consistent with the abort_barrier. The new variant may be even more correct now since atomic_read() will prevent compiler from generating wrong things like carrying abort_flag value in a register instead of re-fetching it from memory. Signed-off-by: Dmitry Osipenko --- arch/arm/mach-tegra/cpuidle-tegra20.c | 9 +++++---- 1 file changed, 5 insertions(+), 4 deletions(-) diff --git a/arch/arm/mach-tegra/cpuidle-tegra20.c b/arch/arm/mach-tegra/cpuidle-tegra20.c index bc5873e92af5..fe80f1988120 100644 --- a/arch/arm/mach-tegra/cpuidle-tegra20.c +++ b/arch/arm/mach-tegra/cpuidle-tegra20.c @@ -32,7 +32,7 @@ #include "sleep.h" #ifdef CONFIG_PM_SLEEP -static bool abort_flag; +static atomic_t abort_flag; static atomic_t abort_barrier; static int tegra20_idle_lp2_coupled(struct cpuidle_device *dev, struct cpuidle_driver *drv, @@ -167,13 +167,14 @@ static int tegra20_idle_lp2_coupled(struct cpuidle_device *dev, bool entered_lp2 = false; if (tegra_pending_sgi()) - WRITE_ONCE(abort_flag, true); + atomic_set(&abort_flag, 1); cpuidle_coupled_parallel_barrier(dev, &abort_barrier); - if (abort_flag) { + if (atomic_read(&abort_flag)) { cpuidle_coupled_parallel_barrier(dev, &abort_barrier); - abort_flag = false; /* clean flag for next coming */ + /* clean flag for next coming */ + atomic_set(&abort_flag, 0); return -EINTR; } From patchwork Tue Oct 15 17:00:09 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Dmitry Osipenko X-Patchwork-Id: 11191247 Return-Path: Received: from mail.kernel.org (pdx-korg-mail-1.web.codeaurora.org [172.30.200.123]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id 25ACA912 for ; Tue, 15 Oct 2019 17:01:58 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.kernel.org (Postfix) with ESMTP id 056C821835 for ; Tue, 15 Oct 2019 17:01:58 +0000 (UTC) Authentication-Results: mail.kernel.org; dkim=pass (2048-bit key) header.d=gmail.com header.i=@gmail.com header.b="F52AQVkz" Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S2388448AbfJORBz (ORCPT ); Tue, 15 Oct 2019 13:01:55 -0400 Received: from mail-lj1-f196.google.com ([209.85.208.196]:35583 "EHLO mail-lj1-f196.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1726379AbfJORBz (ORCPT ); Tue, 15 Oct 2019 13:01:55 -0400 Received: by mail-lj1-f196.google.com with SMTP id m7so21041543lji.2; Tue, 15 Oct 2019 10:01:51 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=0El1r5sR/3XS90TExiIvdI2lmehipmygt0wHnvPAxUQ=; b=F52AQVkzmm6cIIRIypc9mBwhZ7fvyTDY7hcqPeur1+oEE3ovBfJU1MvsVBIWxL22Ee Qh2JXMr5LuNmYxVkcYFi7OpDcve1+wOQwswv1hY+akPnalpDaUUmm6Ym7qlHQXN7Teot SA2fem0EyOAFSHJ9991h6xHNubcbb+KUT55JgqsoeP9+hTSnU8dI9KsiC6Z3G0akg5Fi dNXRqA23sbJ4K79BX68XQlCJPSbcTKqQ/lmfULmG5J7Eqnhs0hWveC+vTp6nN9IwKsbb ugMhT3KBW9jnvPBNGWlat46n2YDnQcDC6kYNBKc1r1RPREWw6KOm9BMSGmmKGzMdzngK HVtg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=0El1r5sR/3XS90TExiIvdI2lmehipmygt0wHnvPAxUQ=; b=Q+j2cleNcHjPlMzqnjyDfXLQGRl3ReEKJxleNDvef5GD2WkjMGPEh5vlLvJ/IyOjV4 S8XeMesX/689zhZ5ty3NJzrLRzvcGyVjuaf12REIka8rUnoUDW7ViVBC97kDaOmBlPf1 17ubFZ/h3BN6M8cELYg+FCngbp4Bv7ZejWCxOdPymp77FA3/fdFcLXzivme+OdbaIHNE Tcq/FEw3KP1NE+LQwNZqpsoTmLRp+6QG4Ob+BvB21WaHPp2iAB4pa+N5cgh7WMMIJFcp vCombeJADKhsm+NBVXLe6JXdqkBn4nHHT0XS0OyCw53W0govl+ClJggfKHHMqXg3wUTl RHlA== X-Gm-Message-State: APjAAAU1v5Bve6WP8zo3N17UcsMEXf8Lf7cu/empy3w8CerDFa4s3WGU fiu6IvlxquwPKPd9EP/BdiU= X-Google-Smtp-Source: APXvYqz53Re3jOt2H62WWYr1iivI8KBu3qJtHSQkcLZcdLSKLbTaDCkqbRpPCXJSPKcloiZf5brhfQ== X-Received: by 2002:a05:651c:113b:: with SMTP id e27mr22344296ljo.125.1571158911288; Tue, 15 Oct 2019 10:01:51 -0700 (PDT) Received: from localhost.localdomain ([94.29.10.250]) by smtp.gmail.com with ESMTPSA id t6sm5144992ljd.102.2019.10.15.10.01.50 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 15 Oct 2019 10:01:50 -0700 (PDT) From: Dmitry Osipenko To: Thierry Reding , Jonathan Hunter , Peter De Schrijver , "Rafael J. Wysocki" , Daniel Lezcano Cc: linux-pm@vger.kernel.org, linux-tegra@vger.kernel.org, linux-kernel@vger.kernel.org Subject: [PATCH v6 12/18] arm: tegra20/30: cpuidle: Remove unnecessary memory barrier Date: Tue, 15 Oct 2019 20:00:09 +0300 Message-Id: <20191015170015.1135-13-digetx@gmail.com> X-Mailer: git-send-email 2.23.0 In-Reply-To: <20191015170015.1135-1-digetx@gmail.com> References: <20191015170015.1135-1-digetx@gmail.com> MIME-Version: 1.0 Sender: linux-pm-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-pm@vger.kernel.org There is no good justification for smp_rmb() after returning from LP2 because there are no memory operations that require SMP synchronization. Thus remove the confusing barrier. Signed-off-by: Dmitry Osipenko --- arch/arm/mach-tegra/cpuidle-tegra20.c | 2 -- arch/arm/mach-tegra/cpuidle-tegra30.c | 2 -- 2 files changed, 4 deletions(-) diff --git a/arch/arm/mach-tegra/cpuidle-tegra20.c b/arch/arm/mach-tegra/cpuidle-tegra20.c index fe80f1988120..af2cd339db43 100644 --- a/arch/arm/mach-tegra/cpuidle-tegra20.c +++ b/arch/arm/mach-tegra/cpuidle-tegra20.c @@ -193,8 +193,6 @@ static int tegra20_idle_lp2_coupled(struct cpuidle_device *dev, local_fiq_enable(); - smp_rmb(); - return entered_lp2 ? index : 0; } #endif diff --git a/arch/arm/mach-tegra/cpuidle-tegra30.c b/arch/arm/mach-tegra/cpuidle-tegra30.c index a4f0add46a27..80ae64bcdf50 100644 --- a/arch/arm/mach-tegra/cpuidle-tegra30.c +++ b/arch/arm/mach-tegra/cpuidle-tegra30.c @@ -113,8 +113,6 @@ static int tegra30_idle_lp2(struct cpuidle_device *dev, local_fiq_enable(); - smp_rmb(); - return (entered_lp2) ? index : 0; } #endif From patchwork Tue Oct 15 17:00:10 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Dmitry Osipenko X-Patchwork-Id: 11191249 Return-Path: Received: from mail.kernel.org (pdx-korg-mail-1.web.codeaurora.org [172.30.200.123]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id 174EB1668 for ; Tue, 15 Oct 2019 17:02:00 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.kernel.org (Postfix) with ESMTP id D0C5E20873 for ; Tue, 15 Oct 2019 17:01:59 +0000 (UTC) Authentication-Results: mail.kernel.org; dkim=pass (2048-bit key) header.d=gmail.com header.i=@gmail.com header.b="H4We6h2a" Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S2388551AbfJORB6 (ORCPT ); Tue, 15 Oct 2019 13:01:58 -0400 Received: from mail-lj1-f193.google.com ([209.85.208.193]:39655 "EHLO mail-lj1-f193.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S2388528AbfJORB4 (ORCPT ); Tue, 15 Oct 2019 13:01:56 -0400 Received: by mail-lj1-f193.google.com with SMTP id y3so21047543ljj.6; Tue, 15 Oct 2019 10:01:53 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=O0Vhg8YqL92dUrJS9GJsRoY1ODBOge9j4BuASSGanK4=; b=H4We6h2aSJRj33uHcEQJUkelKMQmA/dhkPaMxSN2Ry81Azcu+tWqyVz4B3uEBXrql1 OX6jZe9emkg6ckh/gjkCxrClAlDSienYxUo1d2DdEGo76GHSkD8qSUlN8OT+5OGB8pqd 8Ej6jW/O0Qi+x+YoOznR1Ssmy+oEI6lZuszXZbZPPW1yypoiWyP0u2izz1SLrD4PkYtz ixX7VMrr+ExfSY2bxdsy6eDJ7LRGmObbH9YgGIaLhLsUG2S2gynzpvfBxcsC6Nm108K0 AQaB/jENiZWxLkYWvqtJp1HkNa7ldsdw8wAHWoz9DwWNxKKQZEeOjcDVPIvnpALuPNje Oc1Q== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=O0Vhg8YqL92dUrJS9GJsRoY1ODBOge9j4BuASSGanK4=; b=Vj8HWEeEWLWsCodpg8apBOUxElQ36kNv5qgXwYdrt8e6N2mbiVL+aJdY9M9scRG0rZ +63GEu422TyCI9M3/IkkglS4LD0eVd5NYP9Poa331/6X5y96jin7kaXUlPxSVwIBW3/S oKjbeddKmDI1jWAf37BQbZ1D+xA2JlMYFj7XRlr6hcBc73Hey44MQ+YkP1fMkWptL1h1 3G46Dy4Fxid7SNeXtEDx3lmd18LMf5jPysW3mpgBqvSQLAzrmUHXtzVdP+Zh/WQETyIo tGUXQoqAI4PsLu9irRUFpy07BE+/vBDTjpC/1nFELU4MVgAplDXLdtfrww+AVfOIm4n/ c7qQ== X-Gm-Message-State: APjAAAUBASfl6ir5SDDoAs6exsz+dk6I1hds+esjwxLPgAOchytfwywn DTsc/J9iA3f5ALZNmTEGf+s= X-Google-Smtp-Source: APXvYqzJqI20HGXrV+2fShbWwmsZQkaub6B44kBp6kfmxhrECc+5IMvpuDbdEHvKtvIgpAnqmLD+tA== X-Received: by 2002:a05:651c:102e:: with SMTP id w14mr16254366ljm.159.1571158912474; Tue, 15 Oct 2019 10:01:52 -0700 (PDT) Received: from localhost.localdomain ([94.29.10.250]) by smtp.gmail.com with ESMTPSA id t6sm5144992ljd.102.2019.10.15.10.01.51 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 15 Oct 2019 10:01:51 -0700 (PDT) From: Dmitry Osipenko To: Thierry Reding , Jonathan Hunter , Peter De Schrijver , "Rafael J. Wysocki" , Daniel Lezcano Cc: linux-pm@vger.kernel.org, linux-tegra@vger.kernel.org, linux-kernel@vger.kernel.org Subject: [PATCH v6 13/18] cpuidle: Refactor and move NVIDIA Tegra20 driver into drivers/cpuidle/ Date: Tue, 15 Oct 2019 20:00:10 +0300 Message-Id: <20191015170015.1135-14-digetx@gmail.com> X-Mailer: git-send-email 2.23.0 In-Reply-To: <20191015170015.1135-1-digetx@gmail.com> References: <20191015170015.1135-1-digetx@gmail.com> MIME-Version: 1.0 Sender: linux-pm-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-pm@vger.kernel.org The driver's code is refactored in a way that will make it easy to support Tegra30/114/124 SoCs by this driver later on. The functionality is equal to the old Tegra20 driver, only the code's structure changed a tad and it's a platform driver now. Signed-off-by: Dmitry Osipenko --- arch/arm/mach-tegra/Makefile | 3 - arch/arm/mach-tegra/cpuidle-tegra20.c | 215 ---------------------- arch/arm/mach-tegra/cpuidle.c | 14 +- arch/arm/mach-tegra/cpuidle.h | 4 - drivers/cpuidle/Kconfig.arm | 8 + drivers/cpuidle/Makefile | 1 + drivers/cpuidle/cpuidle-tegra.c | 251 ++++++++++++++++++++++++++ include/soc/tegra/cpuidle.h | 2 +- 8 files changed, 263 insertions(+), 235 deletions(-) delete mode 100644 arch/arm/mach-tegra/cpuidle-tegra20.c create mode 100644 drivers/cpuidle/cpuidle-tegra.c diff --git a/arch/arm/mach-tegra/Makefile b/arch/arm/mach-tegra/Makefile index 965862608ff6..8425bb5608d5 100644 --- a/arch/arm/mach-tegra/Makefile +++ b/arch/arm/mach-tegra/Makefile @@ -12,9 +12,6 @@ obj-y += sleep-tegra20.o obj-y += sleep-tegra30.o obj-$(CONFIG_CPU_IDLE) += cpuidle.o obj-$(CONFIG_ARCH_TEGRA_2x_SOC) += pm-tegra20.o -ifeq ($(CONFIG_CPU_IDLE),y) -obj-$(CONFIG_ARCH_TEGRA_2x_SOC) += cpuidle-tegra20.o -endif obj-$(CONFIG_ARCH_TEGRA_3x_SOC) += pm-tegra30.o ifeq ($(CONFIG_CPU_IDLE),y) obj-$(CONFIG_ARCH_TEGRA_3x_SOC) += cpuidle-tegra30.o diff --git a/arch/arm/mach-tegra/cpuidle-tegra20.c b/arch/arm/mach-tegra/cpuidle-tegra20.c deleted file mode 100644 index af2cd339db43..000000000000 --- a/arch/arm/mach-tegra/cpuidle-tegra20.c +++ /dev/null @@ -1,215 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0-or-later -/* - * CPU idle driver for Tegra CPUs - * - * Copyright (c) 2010-2012, NVIDIA Corporation. - * Copyright (c) 2011 Google, Inc. - * Author: Colin Cross - * Gary King - * - * Rework for 3.3 by Peter De Schrijver - */ - -#include -#include -#include -#include -#include -#include -#include - -#include -#include - -#include -#include -#include - -#include "cpuidle.h" -#include "iomap.h" -#include "irq.h" -#include "reset.h" -#include "sleep.h" - -#ifdef CONFIG_PM_SLEEP -static atomic_t abort_flag; -static atomic_t abort_barrier; -static int tegra20_idle_lp2_coupled(struct cpuidle_device *dev, - struct cpuidle_driver *drv, - int index); -#define TEGRA20_MAX_STATES 2 -#else -#define TEGRA20_MAX_STATES 1 -#endif - -static struct cpuidle_driver tegra_idle_driver = { - .name = "tegra_idle", - .owner = THIS_MODULE, - .states = { - ARM_CPUIDLE_WFI_STATE_PWR(600), -#ifdef CONFIG_PM_SLEEP - { - .enter = tegra20_idle_lp2_coupled, - .exit_latency = 5000, - .target_residency = 10000, - .power_usage = 0, - .flags = CPUIDLE_FLAG_COUPLED | - CPUIDLE_FLAG_TIMER_STOP, - .name = "powered-down", - .desc = "CPU power gated", - }, -#endif - }, - .state_count = TEGRA20_MAX_STATES, - .safe_state_index = 0, -}; - -#ifdef CONFIG_PM_SLEEP -#ifdef CONFIG_SMP -static void tegra20_wake_cpu1_from_reset(void) -{ - /* enable cpu clock on cpu */ - tegra_enable_cpu_clock(1); - - /* take the CPU out of reset */ - tegra_cpu_out_of_reset(1); - - /* unhalt the cpu */ - flowctrl_write_cpu_halt(1, 0); -} -#else -static inline void tegra20_wake_cpu1_from_reset(void) -{ -} -#endif - -static void tegra20_report_cpus_state(void) -{ - unsigned int cpu, lcpu; - - pr_err("secondary CPU taking too long to park\n"); - - for_each_cpu(lcpu, cpu_possible_mask) { - cpu = cpu_logical_map(lcpu); - - pr_err("cpu%u: online=%d flowctrl_csr=0x%08x\n", - cpu, cpu_online(lcpu), flowctrl_read_cpu_csr(cpu)); - } -} - -static int tegra20_wait_for_secondary_cpu_parking(void) -{ - unsigned int retries = 3; - - while (retries--) { - ktime_t timeout = ktime_add_ms(ktime_get(), 500); - - /* - * The primary CPU0 core shall wait for the secondaries - * shutdown in order to power-off CPU's cluster safely. - * The timeout value depends on the current CPU frequency, - * it takes about 40-150us in average and over 1000us in - * a worst case scenario. - */ - do { - if (tegra_cpu_rail_off_ready()) - return 0; - - } while (ktime_before(ktime_get(), timeout)); - - tegra20_report_cpus_state(); - } - - pr_err("timed out waiting secondaries to park\n"); - - return -ETIMEDOUT; -} - -static bool tegra20_cpu_cluster_power_down(struct cpuidle_device *dev, - struct cpuidle_driver *drv, - int index) -{ - bool ret; - - if (tegra20_wait_for_secondary_cpu_parking()) - return false; - - ret = !tegra_pm_enter_lp2(); - - if (cpu_online(1)) - tegra20_wake_cpu1_from_reset(); - - return ret; -} - -#ifdef CONFIG_SMP -static bool tegra20_idle_enter_lp2_cpu_1(struct cpuidle_device *dev, - struct cpuidle_driver *drv, - int index) -{ - cpu_suspend(dev->cpu, tegra_pm_park_secondary_cpu); - - return true; -} -#else -static inline bool tegra20_idle_enter_lp2_cpu_1(struct cpuidle_device *dev, - struct cpuidle_driver *drv, - int index) -{ - return true; -} -#endif - -static int tegra20_idle_lp2_coupled(struct cpuidle_device *dev, - struct cpuidle_driver *drv, - int index) -{ - bool entered_lp2 = false; - - if (tegra_pending_sgi()) - atomic_set(&abort_flag, 1); - - cpuidle_coupled_parallel_barrier(dev, &abort_barrier); - - if (atomic_read(&abort_flag)) { - cpuidle_coupled_parallel_barrier(dev, &abort_barrier); - /* clean flag for next coming */ - atomic_set(&abort_flag, 0); - return -EINTR; - } - - local_fiq_disable(); - - tegra_pm_set_cpu_in_lp2(); - cpu_pm_enter(); - - if (dev->cpu == 0) - entered_lp2 = tegra20_cpu_cluster_power_down(dev, drv, index); - else - entered_lp2 = tegra20_idle_enter_lp2_cpu_1(dev, drv, index); - - cpu_pm_exit(); - tegra_pm_clear_cpu_in_lp2(); - - local_fiq_enable(); - - return entered_lp2 ? index : 0; -} -#endif - -/* - * Tegra20 HW appears to have a bug such that PCIe device interrupts, whether - * they are legacy IRQs or MSI, are lost when LP2 is enabled. To work around - * this, simply disable LP2 if the PCI driver and DT node are both enabled. - */ -void tegra20_cpuidle_pcie_irqs_in_use(void) -{ - pr_info_once( - "Disabling cpuidle LP2 state, since PCIe IRQs are in use\n"); - tegra_idle_driver.states[1].disabled = true; -} - -int __init tegra20_cpuidle_init(void) -{ - return cpuidle_register(&tegra_idle_driver, cpu_possible_mask); -} diff --git a/arch/arm/mach-tegra/cpuidle.c b/arch/arm/mach-tegra/cpuidle.c index d565c44cfc93..eee85d517783 100644 --- a/arch/arm/mach-tegra/cpuidle.c +++ b/arch/arm/mach-tegra/cpuidle.c @@ -14,6 +14,7 @@ #include #include +#include #include @@ -23,8 +24,7 @@ void __init tegra_cpuidle_init(void) { switch (tegra_get_chip_id()) { case TEGRA20: - if (IS_ENABLED(CONFIG_ARCH_TEGRA_2x_SOC)) - tegra20_cpuidle_init(); + platform_device_register_simple("tegra-cpuidle", -1, NULL, 0); break; case TEGRA30: if (IS_ENABLED(CONFIG_ARCH_TEGRA_3x_SOC)) @@ -38,13 +38,3 @@ void __init tegra_cpuidle_init(void) break; } } - -void tegra_cpuidle_pcie_irqs_in_use(void) -{ - switch (tegra_get_chip_id()) { - case TEGRA20: - if (IS_ENABLED(CONFIG_ARCH_TEGRA_2x_SOC)) - tegra20_cpuidle_pcie_irqs_in_use(); - break; - } -} diff --git a/arch/arm/mach-tegra/cpuidle.h b/arch/arm/mach-tegra/cpuidle.h index 4e1f459f5bd8..eeb37baf18e1 100644 --- a/arch/arm/mach-tegra/cpuidle.h +++ b/arch/arm/mach-tegra/cpuidle.h @@ -7,15 +7,11 @@ #define __MACH_TEGRA_CPUIDLE_H #ifdef CONFIG_CPU_IDLE -int tegra20_cpuidle_init(void); -void tegra20_cpuidle_pcie_irqs_in_use(void); int tegra30_cpuidle_init(void); int tegra114_cpuidle_init(void); void tegra_cpuidle_init(void); -void tegra_cpuidle_pcie_irqs_in_use(void); #else static inline void tegra_cpuidle_init(void) {} -static inline void tegra_cpuidle_pcie_irqs_in_use(void) {} #endif #endif diff --git a/drivers/cpuidle/Kconfig.arm b/drivers/cpuidle/Kconfig.arm index d8530475493c..6952bf7bb260 100644 --- a/drivers/cpuidle/Kconfig.arm +++ b/drivers/cpuidle/Kconfig.arm @@ -86,3 +86,11 @@ config ARM_MVEBU_V7_CPUIDLE depends on ARCH_MVEBU && !ARM64 help Select this to enable cpuidle on Armada 370, 38x and XP processors. + +config ARM_TEGRA_CPUIDLE + bool "CPU Idle Driver for NVIDIA Tegra SoCs" + depends on ARCH_TEGRA && !ARM64 + select ARCH_NEEDS_CPU_IDLE_COUPLED if SMP + select ARM_CPU_SUSPEND + help + Select this to enable cpuidle for NVIDIA Tegra20/30/114/124 SoCs. diff --git a/drivers/cpuidle/Makefile b/drivers/cpuidle/Makefile index ee70d5cc5b99..a15e4808d295 100644 --- a/drivers/cpuidle/Makefile +++ b/drivers/cpuidle/Makefile @@ -22,6 +22,7 @@ obj-$(CONFIG_ARM_AT91_CPUIDLE) += cpuidle-at91.o obj-$(CONFIG_ARM_EXYNOS_CPUIDLE) += cpuidle-exynos.o obj-$(CONFIG_ARM_CPUIDLE) += cpuidle-arm.o obj-$(CONFIG_ARM_PSCI_CPUIDLE) += cpuidle-psci.o +obj-$(CONFIG_ARM_TEGRA_CPUIDLE) += cpuidle-tegra.o ############################################################################### # MIPS drivers diff --git a/drivers/cpuidle/cpuidle-tegra.c b/drivers/cpuidle/cpuidle-tegra.c new file mode 100644 index 000000000000..491fc90387c3 --- /dev/null +++ b/drivers/cpuidle/cpuidle-tegra.c @@ -0,0 +1,251 @@ +// SPDX-License-Identifier: GPL-2.0-only +/* + * CPU idle driver for Tegra CPUs + * + * Copyright (c) 2010-2013, NVIDIA Corporation. + * Copyright (c) 2011 Google, Inc. + * Author: Colin Cross + * Gary King + * + * Rework for 3.3 by Peter De Schrijver + * + * Tegra20/124 driver unification by Dmitry Osipenko + */ + +#define pr_fmt(fmt) "tegra-cpuidle: " fmt + +#include +#include +#include +#include +#include +#include +#include +#include + +#include + +#include +#include +#include +#include +#include + +#include +#include +#include + +enum { + TEGRA_C1, + TEGRA_CC6, + TEGRA_STATE_COUNT, +}; + +static atomic_t tegra_idle_barrier; +static atomic_t tegra_abort_flag; + +static void tegra_cpuidle_report_cpus_state(void) +{ + unsigned int cpu, lcpu; + + pr_err("secondary CPU taking too long to park\n"); + + for_each_cpu(lcpu, cpu_possible_mask) { + cpu = cpu_logical_map(lcpu); + + pr_err("cpu%u: online=%d flowctrl_csr=0x%08x\n", + cpu, cpu_online(lcpu), flowctrl_read_cpu_csr(cpu)); + } +} + +static int tegra_cpuidle_wait_for_secondary_cpus_parking(void) +{ + unsigned int retries = 3; + + while (retries--) { + ktime_t timeout = ktime_add_ms(ktime_get(), 500); + + /* + * The primary CPU0 core shall wait for the secondaries + * shutdown in order to power-off CPU's cluster safely. + * The timeout value depends on the current CPU frequency, + * it takes about 40-150us in average and over 1000us in + * a worst case scenario. + */ + do { + if (tegra_cpu_rail_off_ready()) + return 0; + + } while (ktime_before(ktime_get(), timeout)); + + tegra_cpuidle_report_cpus_state(); + } + + pr_err("timed out waiting secondaries to park\n"); + + return -ETIMEDOUT; +} + +static void tegra_cpuidle_unpark_secondary_cpus(void) +{ + unsigned int cpu, lcpu; + + for_each_cpu(lcpu, cpu_online_mask) { + cpu = cpu_logical_map(lcpu); + + if (cpu > 0) { + tegra_enable_cpu_clock(cpu); + tegra_cpu_out_of_reset(cpu); + flowctrl_write_cpu_halt(cpu, 0); + } + } +} + +static int tegra_cpuidle_cc6_enter(unsigned int cpu) +{ + int ret; + + if (cpu > 0) { + ret = cpu_suspend(cpu, tegra_pm_park_secondary_cpu); + } else { + ret = tegra_cpuidle_wait_for_secondary_cpus_parking(); + if (!ret) + ret = tegra_pm_enter_lp2(); + + tegra_cpuidle_unpark_secondary_cpus(); + } + + return ret; +} + +static int tegra_cpuidle_coupled_barrier(struct cpuidle_device *dev) +{ + if (tegra_pending_sgi()) { + /* + * CPU got local interrupt that will be lost after GIC's + * shutdown because GIC driver doesn't save/restore the + * pending SGI state across CPU cluster PM. Abort and retry + * next time. + */ + atomic_set(&tegra_abort_flag, 1); + } + + cpuidle_coupled_parallel_barrier(dev, &tegra_idle_barrier); + + if (atomic_read(&tegra_abort_flag)) { + cpuidle_coupled_parallel_barrier(dev, &tegra_idle_barrier); + atomic_set(&tegra_abort_flag, 0); + return -EINTR; + } + + return 0; +} + +static int tegra_cpuidle_state_enter(struct cpuidle_device *dev, + int index, unsigned int cpu) +{ + int ret; + + /* + * CC6 state is the "CPU cluster power-off" state. In order to + * enter this state, at first the secondary CPU cores need to be + * parked into offline mode, then the last CPU should clean out + * remaining dirty cache lines into DRAM and trigger Flow Controller + * logic that turns off the cluster's power domain (which includes + * CPU cores, GIC and L2 cache). + */ + if (index == TEGRA_CC6) { + ret = tegra_cpuidle_coupled_barrier(dev); + if (ret) + return ret; + } + + local_fiq_disable(); + tegra_pm_set_cpu_in_lp2(); + cpu_pm_enter(); + + switch (index) { + case TEGRA_CC6: + ret = tegra_cpuidle_cc6_enter(cpu); + break; + default: + ret = -EINVAL; + break; + } + + cpu_pm_exit(); + tegra_pm_clear_cpu_in_lp2(); + local_fiq_enable(); + + return ret; +} + +static int tegra_cpuidle_enter(struct cpuidle_device *dev, + struct cpuidle_driver *drv, + int index) +{ + unsigned int cpu = cpu_logical_map(dev->cpu); + int err; + + err = tegra_cpuidle_state_enter(dev, index, cpu); + if (err && err != -EINTR) + pr_err_once("cpu%u failed to enter idle state %d err: %d\n", + cpu, index, err); + + return err ? -1 : index; +} + +static struct cpuidle_driver tegra_idle_driver = { + .name = "tegra_idle", + .states = { + [TEGRA_C1] = ARM_CPUIDLE_WFI_STATE_PWR(600), + [TEGRA_CC6] = { + .enter = tegra_cpuidle_enter, + .exit_latency = 5000, + .target_residency = 10000, + .power_usage = 0, + .flags = CPUIDLE_FLAG_TIMER_STOP | + CPUIDLE_FLAG_COUPLED, + .name = "CC6", + .desc = "CPU cluster powered off", + }, + }, + .state_count = TEGRA_STATE_COUNT, + .safe_state_index = TEGRA_C1, +}; + +/* + * Tegra20 HW appears to have a bug such that PCIe device interrupts, whether + * they are legacy IRQs or MSI, are lost when CC6 is enabled. To work around + * this, simply disable CC6 if the PCI driver and DT node are both enabled. + */ +void tegra_cpuidle_pcie_irqs_in_use(void) +{ + if (tegra_idle_driver.states[TEGRA_CC6].disabled || + tegra_get_chip_id() != TEGRA20) + return; + + pr_info("disabling CC6 state, since PCIe IRQs are in use\n"); + tegra_idle_driver.states[TEGRA_CC6].disabled = true; +} + +static int tegra_cpuidle_probe(struct platform_device *pdev) +{ + /* + * Required suspend-resume functionality, which is provided by the + * Tegra-arch core and PMC driver, is unavailable if PM-sleep option + * is disabled. + */ + if (!IS_ENABLED(CONFIG_PM_SLEEP)) + tegra_idle_driver.states[TEGRA_CC6].disabled = true; + + return cpuidle_register(&tegra_idle_driver, cpu_possible_mask); +} + +static struct platform_driver tegra_cpuidle_driver = { + .probe = tegra_cpuidle_probe, + .driver = { + .name = "tegra-cpuidle", + }, +}; +builtin_platform_driver(tegra_cpuidle_driver); diff --git a/include/soc/tegra/cpuidle.h b/include/soc/tegra/cpuidle.h index 029ba1f4b2cc..5665975015d8 100644 --- a/include/soc/tegra/cpuidle.h +++ b/include/soc/tegra/cpuidle.h @@ -6,7 +6,7 @@ #ifndef __SOC_TEGRA_CPUIDLE_H__ #define __SOC_TEGRA_CPUIDLE_H__ -#if defined(CONFIG_ARM) && defined(CONFIG_ARCH_TEGRA) && defined(CONFIG_CPU_IDLE) +#ifdef CONFIG_ARM_TEGRA_CPUIDLE void tegra_cpuidle_pcie_irqs_in_use(void); #else static inline void tegra_cpuidle_pcie_irqs_in_use(void) From patchwork Tue Oct 15 17:00:11 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Dmitry Osipenko X-Patchwork-Id: 11191259 Return-Path: Received: from mail.kernel.org (pdx-korg-mail-1.web.codeaurora.org [172.30.200.123]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id 20AE2912 for ; Tue, 15 Oct 2019 17:02:29 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.kernel.org (Postfix) with ESMTP id E1738217F9 for ; Tue, 15 Oct 2019 17:02:28 +0000 (UTC) Authentication-Results: mail.kernel.org; dkim=pass (2048-bit key) header.d=gmail.com header.i=@gmail.com header.b="UN3O9d/y" Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1727011AbfJORCY (ORCPT ); Tue, 15 Oct 2019 13:02:24 -0400 Received: from mail-lj1-f193.google.com ([209.85.208.193]:43140 "EHLO mail-lj1-f193.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S2388545AbfJORB6 (ORCPT ); Tue, 15 Oct 2019 13:01:58 -0400 Received: by mail-lj1-f193.google.com with SMTP id n14so20998607ljj.10; Tue, 15 Oct 2019 10:01:54 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=GBfqez/NC0zUa0JkEckLp1uECqLJh7gqSYevgAPR1OU=; b=UN3O9d/yzaGOSCRzyD8RuPNrZXQUJHavSdIA6NE8JwVgfrZiw+GWpfMeY9tAA8gTLD vUliHPpp6PL3h5WVCo09dMHsG3k6Y+MeApBOlxKU6PR/9NK4nww3ZH/92+FWH/l4f71l K80Z2AiXu+lsw52kFKe/AiQ2GgoIV8qtdWIDWz4Jo+NVrfqC83OPTt8o8z7mX9ndwp8b Sx8nKdR8tvcSXkcsgVoccqfgvZGMG2Ee9vk8f1cdsUfkJilPCvdAGeB5u87noE6E+td+ j3v/Uv9O20uf8gBkOpVo+E2Km1VTFJXfMU6Gq/ZQTa10D10ZVxwM5a0ZVfRq1EMFsQHH PH1g== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=GBfqez/NC0zUa0JkEckLp1uECqLJh7gqSYevgAPR1OU=; b=Mf5YaymhaIn5VwBMhNPylxsc5rRo7BtTXAcggJYbJuYqiLT1fcjpnCnkTIpQDmYt7G cJKSO1Q4DUMiSgJpJc6tdtCw4BwpVK6VI0BVcu0x3wLrZh325s0ZaBnjU6L5tccvegFl 7WTVktjPXsvOo1HQW8Jtu1o7ibhLvcbdDW5AyfsGsq9xrzM2UMcxPRdrDS7mMWPKMLMP E10mDHPTxEmCWItdVaaCVP3GI6Iw+TZfHgIXlxpiAUB6OK9rY6cTd3EUCJ1NJrwM8jy7 SmxLNO2zdzq6nCraqQNe7xgUJZIdjxguyFxTQCorHK0/BwCpF6M8rvfSdkD+IGDBCVy3 2ljg== X-Gm-Message-State: APjAAAWWard3TqOeRdxACNLTjn+qMDUtqfkiuu4A/uIXE4twaycHHq/0 MixdbkOv28AOZEF1mjFIITo= X-Google-Smtp-Source: APXvYqyeX6ARqKp4fTpB21tc5mBPA1bgyB5E1URdm4Y+qsC8Ba+1WevGIP9WxKYRlu1grzB3KIoPzg== X-Received: by 2002:a2e:8593:: with SMTP id b19mr23089440lji.34.1571158913617; Tue, 15 Oct 2019 10:01:53 -0700 (PDT) Received: from localhost.localdomain ([94.29.10.250]) by smtp.gmail.com with ESMTPSA id t6sm5144992ljd.102.2019.10.15.10.01.52 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 15 Oct 2019 10:01:52 -0700 (PDT) From: Dmitry Osipenko To: Thierry Reding , Jonathan Hunter , Peter De Schrijver , "Rafael J. Wysocki" , Daniel Lezcano Cc: linux-pm@vger.kernel.org, linux-tegra@vger.kernel.org, linux-kernel@vger.kernel.org Subject: [PATCH v6 14/18] cpuidle: tegra: Squash Tegra30 driver into the common driver Date: Tue, 15 Oct 2019 20:00:11 +0300 Message-Id: <20191015170015.1135-15-digetx@gmail.com> X-Mailer: git-send-email 2.23.0 In-Reply-To: <20191015170015.1135-1-digetx@gmail.com> References: <20191015170015.1135-1-digetx@gmail.com> MIME-Version: 1.0 Sender: linux-pm-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-pm@vger.kernel.org Tegra20 and Terga30 SoCs have common C1 and CC6 idling states and thus share the same code paths, there is no point in having separate drivers for a similar hardware. This patch merely moves functionality of the old driver into the new, although the CC6 state is kept disabled for now since old driver had a rudimentary support for this state (allowing to enter into CC6 only when secondary CPUs are put offline), while new driver can provide a full-featured support. The new feature will be enabled by another patch. Signed-off-by: Dmitry Osipenko --- arch/arm/mach-tegra/Makefile | 3 - arch/arm/mach-tegra/cpuidle-tegra30.c | 123 -------------------------- arch/arm/mach-tegra/cpuidle.c | 5 +- arch/arm/mach-tegra/cpuidle.h | 1 - drivers/cpuidle/cpuidle-tegra.c | 75 ++++++++++++++-- 5 files changed, 71 insertions(+), 136 deletions(-) delete mode 100644 arch/arm/mach-tegra/cpuidle-tegra30.c diff --git a/arch/arm/mach-tegra/Makefile b/arch/arm/mach-tegra/Makefile index 8425bb5608d5..99c5f4274e5c 100644 --- a/arch/arm/mach-tegra/Makefile +++ b/arch/arm/mach-tegra/Makefile @@ -13,9 +13,6 @@ obj-y += sleep-tegra30.o obj-$(CONFIG_CPU_IDLE) += cpuidle.o obj-$(CONFIG_ARCH_TEGRA_2x_SOC) += pm-tegra20.o obj-$(CONFIG_ARCH_TEGRA_3x_SOC) += pm-tegra30.o -ifeq ($(CONFIG_CPU_IDLE),y) -obj-$(CONFIG_ARCH_TEGRA_3x_SOC) += cpuidle-tegra30.o -endif obj-$(CONFIG_SMP) += platsmp.o obj-$(CONFIG_HOTPLUG_CPU) += hotplug.o diff --git a/arch/arm/mach-tegra/cpuidle-tegra30.c b/arch/arm/mach-tegra/cpuidle-tegra30.c deleted file mode 100644 index 80ae64bcdf50..000000000000 --- a/arch/arm/mach-tegra/cpuidle-tegra30.c +++ /dev/null @@ -1,123 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0-or-later -/* - * CPU idle driver for Tegra CPUs - * - * Copyright (c) 2010-2012, NVIDIA Corporation. - * Copyright (c) 2011 Google, Inc. - * Author: Colin Cross - * Gary King - * - * Rework for 3.3 by Peter De Schrijver - */ - -#include -#include -#include -#include -#include -#include - -#include - -#include -#include -#include - -#include "cpuidle.h" -#include "sleep.h" - -#ifdef CONFIG_PM_SLEEP -static int tegra30_idle_lp2(struct cpuidle_device *dev, - struct cpuidle_driver *drv, - int index); -#endif - -static struct cpuidle_driver tegra_idle_driver = { - .name = "tegra_idle", - .owner = THIS_MODULE, -#ifdef CONFIG_PM_SLEEP - .state_count = 2, -#else - .state_count = 1, -#endif - .states = { - [0] = ARM_CPUIDLE_WFI_STATE_PWR(600), -#ifdef CONFIG_PM_SLEEP - [1] = { - .enter = tegra30_idle_lp2, - .exit_latency = 2000, - .target_residency = 2200, - .power_usage = 0, - .flags = CPUIDLE_FLAG_TIMER_STOP, - .name = "powered-down", - .desc = "CPU power gated", - }, -#endif - }, -}; - -#ifdef CONFIG_PM_SLEEP -static bool tegra30_cpu_cluster_power_down(struct cpuidle_device *dev, - struct cpuidle_driver *drv, - int index) -{ - /* All CPUs entering LP2 is not working. - * Don't let CPU0 enter LP2 when any secondary CPU is online. - */ - if (num_online_cpus() > 1 || !tegra_cpu_rail_off_ready()) { - cpu_do_idle(); - return false; - } - - return !tegra_pm_enter_lp2(); -} - -#ifdef CONFIG_SMP -static bool tegra30_cpu_core_power_down(struct cpuidle_device *dev, - struct cpuidle_driver *drv, - int index) -{ - smp_wmb(); - - cpu_suspend(0, tegra30_pm_secondary_cpu_suspend); - - return true; -} -#else -static inline bool tegra30_cpu_core_power_down(struct cpuidle_device *dev, - struct cpuidle_driver *drv, - int index) -{ - return true; -} -#endif - -static int tegra30_idle_lp2(struct cpuidle_device *dev, - struct cpuidle_driver *drv, - int index) -{ - bool entered_lp2 = false; - - local_fiq_disable(); - - tegra_pm_set_cpu_in_lp2(); - cpu_pm_enter(); - - if (dev->cpu == 0) - entered_lp2 = tegra30_cpu_cluster_power_down(dev, drv, index); - else - entered_lp2 = tegra30_cpu_core_power_down(dev, drv, index); - - cpu_pm_exit(); - tegra_pm_clear_cpu_in_lp2(); - - local_fiq_enable(); - - return (entered_lp2) ? index : 0; -} -#endif - -int __init tegra30_cpuidle_init(void) -{ - return cpuidle_register(&tegra_idle_driver, NULL); -} diff --git a/arch/arm/mach-tegra/cpuidle.c b/arch/arm/mach-tegra/cpuidle.c index eee85d517783..fa0dcf3c2c45 100644 --- a/arch/arm/mach-tegra/cpuidle.c +++ b/arch/arm/mach-tegra/cpuidle.c @@ -24,11 +24,8 @@ void __init tegra_cpuidle_init(void) { switch (tegra_get_chip_id()) { case TEGRA20: - platform_device_register_simple("tegra-cpuidle", -1, NULL, 0); - break; case TEGRA30: - if (IS_ENABLED(CONFIG_ARCH_TEGRA_3x_SOC)) - tegra30_cpuidle_init(); + platform_device_register_simple("tegra-cpuidle", -1, NULL, 0); break; case TEGRA114: case TEGRA124: diff --git a/arch/arm/mach-tegra/cpuidle.h b/arch/arm/mach-tegra/cpuidle.h index eeb37baf18e1..5423a05a69f6 100644 --- a/arch/arm/mach-tegra/cpuidle.h +++ b/arch/arm/mach-tegra/cpuidle.h @@ -7,7 +7,6 @@ #define __MACH_TEGRA_CPUIDLE_H #ifdef CONFIG_CPU_IDLE -int tegra30_cpuidle_init(void); int tegra114_cpuidle_init(void); void tegra_cpuidle_init(void); #else diff --git a/drivers/cpuidle/cpuidle-tegra.c b/drivers/cpuidle/cpuidle-tegra.c index 491fc90387c3..1a2cff5d4ff3 100644 --- a/drivers/cpuidle/cpuidle-tegra.c +++ b/drivers/cpuidle/cpuidle-tegra.c @@ -37,6 +37,7 @@ enum { TEGRA_C1, + TEGRA_C7, TEGRA_CC6, TEGRA_STATE_COUNT, }; @@ -118,6 +119,11 @@ static int tegra_cpuidle_cc6_enter(unsigned int cpu) return ret; } +static int tegra_cpuidle_c7_enter(void) +{ + return cpu_suspend(0, tegra30_pm_secondary_cpu_suspend); +} + static int tegra_cpuidle_coupled_barrier(struct cpuidle_device *dev) { if (tegra_pending_sgi()) { @@ -165,6 +171,9 @@ static int tegra_cpuidle_state_enter(struct cpuidle_device *dev, cpu_pm_enter(); switch (index) { + case TEGRA_C7: + ret = tegra_cpuidle_c7_enter(); + break; case TEGRA_CC6: ret = tegra_cpuidle_cc6_enter(cpu); break; @@ -180,6 +189,28 @@ static int tegra_cpuidle_state_enter(struct cpuidle_device *dev, return ret; } +static int tegra_cpuidle_adjust_state_index(struct cpuidle_device *dev, + struct cpuidle_driver *drv, + int index, unsigned int cpu) +{ + /* + * On Tegra30 CPU0 can't be power-gated while secondary CPUs + * are active because it gates the whole CPU cluster. + */ + if (cpu != 0 || index != TEGRA_C7 || tegra_get_chip_id() != TEGRA30) + return index; + + if (!IS_ENABLED(CONFIG_PM_SLEEP) || num_online_cpus() > 1) + index = TEGRA_C1; + else + index = TEGRA_CC6; + + if (drv->states[index].disabled || dev->states_usage[index].disable) + index = -1; + + return index; +} + static int tegra_cpuidle_enter(struct cpuidle_device *dev, struct cpuidle_driver *drv, int index) @@ -187,10 +218,17 @@ static int tegra_cpuidle_enter(struct cpuidle_device *dev, unsigned int cpu = cpu_logical_map(dev->cpu); int err; - err = tegra_cpuidle_state_enter(dev, index, cpu); - if (err && err != -EINTR) - pr_err_once("cpu%u failed to enter idle state %d err: %d\n", - cpu, index, err); + index = tegra_cpuidle_adjust_state_index(dev, drv, index, cpu); + if (index < 0) + return index; + + if (index == TEGRA_C1) + err = arm_cpuidle_simple_enter(dev, drv, index); + else + err = tegra_cpuidle_state_enter(dev, index, cpu); + + if (err && (err != -EINTR || index != TEGRA_CC6)) + pr_err_once("failed to enter state %d err: %d\n", index, err); return err ? -1 : index; } @@ -199,6 +237,15 @@ static struct cpuidle_driver tegra_idle_driver = { .name = "tegra_idle", .states = { [TEGRA_C1] = ARM_CPUIDLE_WFI_STATE_PWR(600), + [TEGRA_C7] = { + .enter = tegra_cpuidle_enter, + .exit_latency = 2000, + .target_residency = 2200, + .power_usage = 100, + .flags = CPUIDLE_FLAG_TIMER_STOP, + .name = "C7", + .desc = "CPU core powered off", + }, [TEGRA_CC6] = { .enter = tegra_cpuidle_enter, .exit_latency = 5000, @@ -236,8 +283,26 @@ static int tegra_cpuidle_probe(struct platform_device *pdev) * Tegra-arch core and PMC driver, is unavailable if PM-sleep option * is disabled. */ - if (!IS_ENABLED(CONFIG_PM_SLEEP)) + if (!IS_ENABLED(CONFIG_PM_SLEEP)) { + tegra_idle_driver.states[TEGRA_C7].disabled = true; + tegra_idle_driver.states[TEGRA_CC6].disabled = true; + } + + /* + * Generic WFI state (also known as C1 or LP3) and the coupled CPU + * cluster power-off (CC6 or LP2) states are common for all Tegra SoCs. + */ + switch (tegra_get_chip_id()) { + case TEGRA20: + /* Tegra20 isn't capable to power-off individual CPU cores */ + tegra_idle_driver.states[TEGRA_C7].disabled = true; + break; + case TEGRA30: tegra_idle_driver.states[TEGRA_CC6].disabled = true; + break; + default: + return -EINVAL; + } return cpuidle_register(&tegra_idle_driver, cpu_possible_mask); } From patchwork Tue Oct 15 17:00:12 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Dmitry Osipenko X-Patchwork-Id: 11191257 Return-Path: Received: from mail.kernel.org (pdx-korg-mail-1.web.codeaurora.org [172.30.200.123]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id 90EF5912 for ; Tue, 15 Oct 2019 17:02:24 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.kernel.org (Postfix) with ESMTP id 6F544218DE for ; Tue, 15 Oct 2019 17:02:24 +0000 (UTC) Authentication-Results: mail.kernel.org; dkim=pass (2048-bit key) header.d=gmail.com header.i=@gmail.com header.b="qHRbHEAH" Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S2388549AbfJORB6 (ORCPT ); Tue, 15 Oct 2019 13:01:58 -0400 Received: from mail-lj1-f194.google.com ([209.85.208.194]:35588 "EHLO mail-lj1-f194.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S2388540AbfJORB5 (ORCPT ); Tue, 15 Oct 2019 13:01:57 -0400 Received: by mail-lj1-f194.google.com with SMTP id m7so21041738lji.2; Tue, 15 Oct 2019 10:01:55 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=OMLeb4rCRknKwJs2ldIvPlE4Vxnf8XUAiOeAjO+3B/E=; b=qHRbHEAHSKjIsdIVNhFyZ8C9xJli6HjJrmNPlxXNgIudVULdjbjEIMpb4W6Lwyv3OV ASpbuRqSx9yxiybq/Sx3AD3761Pgdf4VR/6X6AZvNLqcfx1om9owTpFkOjqcGXhxdHQ9 56F3yPgl2ydfJzyTVEDkqO5PUAl6m2QQnpLXLg8ipnI+WPwr8hFTXxT9FuKxOWfuLmC6 2mwtY6WtLYnbMNx3iW1fea/+zFdv8oiB9KsbwE2/n1o8pxfCgfy+KtGMVzd2Q+TbakAt CbTRgur0cb1/VP9xpuv6Fjr9oncFCZPMu5fzo5l8FZEyVYH/+aPMCYi683syF1qpGYa9 8J7g== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=OMLeb4rCRknKwJs2ldIvPlE4Vxnf8XUAiOeAjO+3B/E=; b=DrZD3oSful6wycVDxzzd7LcoMl0r8Ish7BMXNMlrCFw7IYv3kgogZcqP7qY3LbbLKg OxKmvaD9kDGumBqfdZLo28HOHQ1yXv5p0DvDsWtCMFIgUwYNIR4DFnhD2ohjOCL5bgU7 z4exh+BVTwR3aOCdKUxbiQV92DzZyDR9NEyg3tXzwHtd6khGHMjmlNqm1KIcgUsprvbG zJCZVJN+XofA8BTw4cnVZKuzP6gNiPrfDx4PzHkaUdjqcmS8skQeV3FAMSjJyKgeo3Go AeRGlPvBsNOyaStFdhvF3eI5X22a/DhB+kKD7U9Q4EhuKCvaxo162CFncz7a6Zq8KdJ1 9f4A== X-Gm-Message-State: APjAAAU+3BEUML3vhWRJrwU2xJQ3KKppD9jF52hDzJSDs//G8cPYEFpP ShIVIcuARb8WzPX7+vVRtkc= X-Google-Smtp-Source: APXvYqxPQFCF9LkpmQlTPq4C97WzGBzvjuaDG0tT65ZcTvYvFaKaYV9TlLRRD8DYZ0fQq31FiyQqxg== X-Received: by 2002:a2e:a41a:: with SMTP id p26mr206241ljn.49.1571158914703; Tue, 15 Oct 2019 10:01:54 -0700 (PDT) Received: from localhost.localdomain ([94.29.10.250]) by smtp.gmail.com with ESMTPSA id t6sm5144992ljd.102.2019.10.15.10.01.53 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 15 Oct 2019 10:01:54 -0700 (PDT) From: Dmitry Osipenko To: Thierry Reding , Jonathan Hunter , Peter De Schrijver , "Rafael J. Wysocki" , Daniel Lezcano Cc: linux-pm@vger.kernel.org, linux-tegra@vger.kernel.org, linux-kernel@vger.kernel.org Subject: [PATCH v6 15/18] cpuidle: tegra: Support CPU cluster power-down state on Tegra30 Date: Tue, 15 Oct 2019 20:00:12 +0300 Message-Id: <20191015170015.1135-16-digetx@gmail.com> X-Mailer: git-send-email 2.23.0 In-Reply-To: <20191015170015.1135-1-digetx@gmail.com> References: <20191015170015.1135-1-digetx@gmail.com> MIME-Version: 1.0 Sender: linux-pm-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-pm@vger.kernel.org The new Tegra CPU Idle driver now has a unified code path for the coupled CC6 (LP2) state, this allows to enable the deepest idling state on Tegra30 SoC where the whole CPU cluster is power-gated. Signed-off-by: Dmitry Osipenko --- drivers/cpuidle/cpuidle-tegra.c | 1 - 1 file changed, 1 deletion(-) diff --git a/drivers/cpuidle/cpuidle-tegra.c b/drivers/cpuidle/cpuidle-tegra.c index 1a2cff5d4ff3..e38a2f6c11e1 100644 --- a/drivers/cpuidle/cpuidle-tegra.c +++ b/drivers/cpuidle/cpuidle-tegra.c @@ -298,7 +298,6 @@ static int tegra_cpuidle_probe(struct platform_device *pdev) tegra_idle_driver.states[TEGRA_C7].disabled = true; break; case TEGRA30: - tegra_idle_driver.states[TEGRA_CC6].disabled = true; break; default: return -EINVAL; From patchwork Tue Oct 15 17:00:13 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Dmitry Osipenko X-Patchwork-Id: 11191253 Return-Path: Received: from mail.kernel.org (pdx-korg-mail-1.web.codeaurora.org [172.30.200.123]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id 9B126912 for ; Tue, 15 Oct 2019 17:02:22 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.kernel.org (Postfix) with ESMTP id 6728A20872 for ; Tue, 15 Oct 2019 17:02:22 +0000 (UTC) Authentication-Results: mail.kernel.org; dkim=pass (2048-bit key) header.d=gmail.com header.i=@gmail.com header.b="qV46jwy2" Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S2388562AbfJORCA (ORCPT ); Tue, 15 Oct 2019 13:02:00 -0400 Received: from mail-lj1-f193.google.com ([209.85.208.193]:35592 "EHLO mail-lj1-f193.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1727222AbfJORB7 (ORCPT ); Tue, 15 Oct 2019 13:01:59 -0400 Received: by mail-lj1-f193.google.com with SMTP id m7so21041831lji.2; Tue, 15 Oct 2019 10:01:56 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=9O5kYyQN8oIqr0+gKrvy9SPLYSojJu8kKimkkU31J8k=; b=qV46jwy243jqIJHzrPKDQ6mqOEdvhi+j0AkjJpT2lBzG6//dJ5ka38nAANBCYnhaQB y8y3f4dM83Sm6CfzolxC2IvNzN1ofUGzEvZnjBESsx61QHBQ9o8TjL6UCazSGkgtTIaw KyhZsXOYhx8z/CKpuNywYA7XlOcebK6mW5YcAWzSZCvaEGITlKu8Nm7QEhs1UNlDlggt j3Cu66W1YScbMmjki1fqr2ynbyq09Ey/cye0DLjuOKy9LARd+MWqtXRzP/hkEw8nUvcL G6xlrz6Kpikz0Mx3CqMZ0+ZY9sw9I2rfNiQLOBddY3SA3LRaS/AJy4EjtUkUZsaFRrnQ kZmw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=9O5kYyQN8oIqr0+gKrvy9SPLYSojJu8kKimkkU31J8k=; b=Nv31z6mcJnfnnbvyrOOq0B3Bfrl0j0OFGRpoGOqjBL3PTqxix0pd/7izVBMibKiRb3 /lPKO9ERTmNqQ1HImvN/I+qayf+kW8gPY8qTHNc9dH7M9VTUN48fuO1kXVaioUie5Kvm 7V9+i9RjPmws6rn5y6n7aoZRAEzwZQ1RRCmT64APIIPphzevZAsSRHNRMclJApNnQnkU r7G1qS281KaQvYyckRCbDpOtMCMOBHeTXJbNUNQ+vJlBKZLLaFwcIx19AFUvxC0KeDFp TU8ypgzMdrFpl5236ULYNNK4ppSAj8g9ZhM6y56UC28oUagx9UR8lfU0CC+DoreluThC JCOg== X-Gm-Message-State: APjAAAUCNGguE4VGFQ5weLydSUWp9rKvB+nhGcwyffDTdMZ8mpHV2env LYdCnIPWE21kFj8oYhQx0xQ= X-Google-Smtp-Source: APXvYqyiu/8Vwm5bf96zyfCxW/SVAn7lJ6aeZ8YfIo4B5L7hNEyF79lSMwx0rs48pupidnwCt7acnA== X-Received: by 2002:a2e:9848:: with SMTP id e8mr23506906ljj.128.1571158915861; Tue, 15 Oct 2019 10:01:55 -0700 (PDT) Received: from localhost.localdomain ([94.29.10.250]) by smtp.gmail.com with ESMTPSA id t6sm5144992ljd.102.2019.10.15.10.01.54 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 15 Oct 2019 10:01:55 -0700 (PDT) From: Dmitry Osipenko To: Thierry Reding , Jonathan Hunter , Peter De Schrijver , "Rafael J. Wysocki" , Daniel Lezcano Cc: linux-pm@vger.kernel.org, linux-tegra@vger.kernel.org, linux-kernel@vger.kernel.org Subject: [PATCH v6 16/18] cpuidle: tegra: Squash Tegra114 driver into the common driver Date: Tue, 15 Oct 2019 20:00:13 +0300 Message-Id: <20191015170015.1135-17-digetx@gmail.com> X-Mailer: git-send-email 2.23.0 In-Reply-To: <20191015170015.1135-1-digetx@gmail.com> References: <20191015170015.1135-1-digetx@gmail.com> MIME-Version: 1.0 Sender: linux-pm-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-pm@vger.kernel.org Tegra20/30/114/124 SoCs have common idling states, thus there is no much point in having separate drivers for a similar hardware. This patch moves Tegra114/124 arch/ drivers into the common driver without any functional changes. The CC6 state is kept disabled on Tegra114/124 because the core Tegra PM code needs some more work in order to support that state. Signed-off-by: Dmitry Osipenko --- arch/arm/mach-tegra/Makefile | 7 -- arch/arm/mach-tegra/cpuidle-tegra114.c | 90 -------------------------- arch/arm/mach-tegra/cpuidle.c | 37 ----------- arch/arm/mach-tegra/cpuidle.h | 16 ----- arch/arm/mach-tegra/tegra.c | 6 +- drivers/cpuidle/cpuidle-tegra.c | 44 ++++++++++++- 6 files changed, 47 insertions(+), 153 deletions(-) delete mode 100644 arch/arm/mach-tegra/cpuidle-tegra114.c delete mode 100644 arch/arm/mach-tegra/cpuidle.c delete mode 100644 arch/arm/mach-tegra/cpuidle.h diff --git a/arch/arm/mach-tegra/Makefile b/arch/arm/mach-tegra/Makefile index 99c5f4274e5c..07572b5373b8 100644 --- a/arch/arm/mach-tegra/Makefile +++ b/arch/arm/mach-tegra/Makefile @@ -10,19 +10,12 @@ obj-y += sleep.o obj-y += tegra.o obj-y += sleep-tegra20.o obj-y += sleep-tegra30.o -obj-$(CONFIG_CPU_IDLE) += cpuidle.o obj-$(CONFIG_ARCH_TEGRA_2x_SOC) += pm-tegra20.o obj-$(CONFIG_ARCH_TEGRA_3x_SOC) += pm-tegra30.o obj-$(CONFIG_SMP) += platsmp.o obj-$(CONFIG_HOTPLUG_CPU) += hotplug.o obj-$(CONFIG_ARCH_TEGRA_114_SOC) += pm-tegra30.o -ifeq ($(CONFIG_CPU_IDLE),y) -obj-$(CONFIG_ARCH_TEGRA_114_SOC) += cpuidle-tegra114.o -endif obj-$(CONFIG_ARCH_TEGRA_124_SOC) += pm-tegra30.o -ifeq ($(CONFIG_CPU_IDLE),y) -obj-$(CONFIG_ARCH_TEGRA_124_SOC) += cpuidle-tegra114.o -endif obj-$(CONFIG_ARCH_TEGRA_2x_SOC) += board-paz00.o diff --git a/arch/arm/mach-tegra/cpuidle-tegra114.c b/arch/arm/mach-tegra/cpuidle-tegra114.c deleted file mode 100644 index 858c30cc5dc7..000000000000 --- a/arch/arm/mach-tegra/cpuidle-tegra114.c +++ /dev/null @@ -1,90 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0-only -/* - * Copyright (c) 2013, NVIDIA Corporation. All rights reserved. - */ - -#include -#include -#include -#include -#include -#include - -#include - -#include - -#include -#include -#include -#include - -#include "cpuidle.h" -#include "sleep.h" - -#ifdef CONFIG_PM_SLEEP -#define TEGRA114_MAX_STATES 2 -#else -#define TEGRA114_MAX_STATES 1 -#endif - -#ifdef CONFIG_PM_SLEEP -static int tegra114_idle_power_down(struct cpuidle_device *dev, - struct cpuidle_driver *drv, - int index) -{ - local_fiq_disable(); - - tegra_pm_set_cpu_in_lp2(); - cpu_pm_enter(); - - call_firmware_op(prepare_idle, TF_PM_MODE_LP2_NOFLUSH_L2); - - /* Do suspend by ourselves if the firmware does not implement it */ - if (call_firmware_op(do_idle, 0) == -ENOSYS) - cpu_suspend(0, tegra30_pm_secondary_cpu_suspend); - - cpu_pm_exit(); - tegra_pm_clear_cpu_in_lp2(); - - local_fiq_enable(); - - return index; -} - -static void tegra114_idle_enter_s2idle(struct cpuidle_device *dev, - struct cpuidle_driver *drv, - int index) -{ - tegra114_idle_power_down(dev, drv, index); -} -#endif - -static struct cpuidle_driver tegra_idle_driver = { - .name = "tegra_idle", - .owner = THIS_MODULE, - .state_count = TEGRA114_MAX_STATES, - .states = { - [0] = ARM_CPUIDLE_WFI_STATE_PWR(600), -#ifdef CONFIG_PM_SLEEP - [1] = { - .enter = tegra114_idle_power_down, - .enter_s2idle = tegra114_idle_enter_s2idle, - .exit_latency = 500, - .target_residency = 1000, - .flags = CPUIDLE_FLAG_TIMER_STOP, - .power_usage = 0, - .name = "powered-down", - .desc = "CPU power gated", - }, -#endif - }, -}; - -int __init tegra114_cpuidle_init(void) -{ - if (!psci_smp_available()) - return cpuidle_register(&tegra_idle_driver, NULL); - - return 0; -} diff --git a/arch/arm/mach-tegra/cpuidle.c b/arch/arm/mach-tegra/cpuidle.c deleted file mode 100644 index fa0dcf3c2c45..000000000000 --- a/arch/arm/mach-tegra/cpuidle.c +++ /dev/null @@ -1,37 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0-or-later -/* - * arch/arm/mach-tegra/cpuidle.c - * - * CPU idle driver for Tegra CPUs - * - * Copyright (c) 2010-2012, NVIDIA Corporation. - * Copyright (c) 2011 Google, Inc. - * Author: Colin Cross - * Gary King - * - * Rework for 3.3 by Peter De Schrijver - */ - -#include -#include -#include - -#include - -#include "cpuidle.h" - -void __init tegra_cpuidle_init(void) -{ - switch (tegra_get_chip_id()) { - case TEGRA20: - case TEGRA30: - platform_device_register_simple("tegra-cpuidle", -1, NULL, 0); - break; - case TEGRA114: - case TEGRA124: - if (IS_ENABLED(CONFIG_ARCH_TEGRA_114_SOC) || - IS_ENABLED(CONFIG_ARCH_TEGRA_124_SOC)) - tegra114_cpuidle_init(); - break; - } -} diff --git a/arch/arm/mach-tegra/cpuidle.h b/arch/arm/mach-tegra/cpuidle.h deleted file mode 100644 index 5423a05a69f6..000000000000 --- a/arch/arm/mach-tegra/cpuidle.h +++ /dev/null @@ -1,16 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0-only */ -/* - * Copyright (c) 2012, NVIDIA Corporation. All rights reserved. - */ - -#ifndef __MACH_TEGRA_CPUIDLE_H -#define __MACH_TEGRA_CPUIDLE_H - -#ifdef CONFIG_CPU_IDLE -int tegra114_cpuidle_init(void); -void tegra_cpuidle_init(void); -#else -static inline void tegra_cpuidle_init(void) {} -#endif - -#endif diff --git a/arch/arm/mach-tegra/tegra.c b/arch/arm/mach-tegra/tegra.c index 00aaf495bbf7..f1ce2857a251 100644 --- a/arch/arm/mach-tegra/tegra.c +++ b/arch/arm/mach-tegra/tegra.c @@ -36,11 +36,11 @@ #include #include #include +#include #include #include "board.h" #include "common.h" -#include "cpuidle.h" #include "iomap.h" #include "pm.h" #include "reset.h" @@ -85,7 +85,6 @@ static void __init tegra_dt_init(void) static void __init tegra_dt_init_late(void) { tegra_init_suspend(); - tegra_cpuidle_init(); if (IS_ENABLED(CONFIG_ARCH_TEGRA_2x_SOC) && of_machine_is_compatible("compal,paz00")) @@ -94,6 +93,9 @@ static void __init tegra_dt_init_late(void) if (IS_ENABLED(CONFIG_ARCH_TEGRA_2x_SOC) && of_machine_is_compatible("nvidia,tegra20")) platform_device_register_simple("tegra20-cpufreq", -1, NULL, 0); + + if (IS_ENABLED(CONFIG_ARM_TEGRA_CPUIDLE) && !psci_smp_available()) + platform_device_register_simple("tegra-cpuidle", -1, NULL, 0); } static const char * const tegra_dt_board_compat[] = { diff --git a/drivers/cpuidle/cpuidle-tegra.c b/drivers/cpuidle/cpuidle-tegra.c index e38a2f6c11e1..412d21fd13ed 100644 --- a/drivers/cpuidle/cpuidle-tegra.c +++ b/drivers/cpuidle/cpuidle-tegra.c @@ -24,6 +24,7 @@ #include #include +#include #include #include @@ -32,6 +33,7 @@ #include #include +#include #include #include @@ -45,6 +47,11 @@ enum { static atomic_t tegra_idle_barrier; static atomic_t tegra_abort_flag; +static inline bool tegra_cpuidle_using_firmware(void) +{ + return firmware_ops->prepare_idle && firmware_ops->do_idle; +} + static void tegra_cpuidle_report_cpus_state(void) { unsigned int cpu, lcpu; @@ -121,6 +128,16 @@ static int tegra_cpuidle_cc6_enter(unsigned int cpu) static int tegra_cpuidle_c7_enter(void) { + int err; + + if (tegra_cpuidle_using_firmware()) { + err = call_firmware_op(prepare_idle, TF_PM_MODE_LP2_NOFLUSH_L2); + if (err) + return err; + + return call_firmware_op(do_idle, 0); + } + return cpu_suspend(0, tegra30_pm_secondary_cpu_suspend); } @@ -233,6 +250,13 @@ static int tegra_cpuidle_enter(struct cpuidle_device *dev, return err ? -1 : index; } +static void tegra114_enter_s2idle(struct cpuidle_device *dev, + struct cpuidle_driver *drv, + int index) +{ + tegra_cpuidle_enter(dev, drv, index); +} + static struct cpuidle_driver tegra_idle_driver = { .name = "tegra_idle", .states = { @@ -276,6 +300,15 @@ void tegra_cpuidle_pcie_irqs_in_use(void) tegra_idle_driver.states[TEGRA_CC6].disabled = true; } +static void tegra_cpuidle_setup_tegra114_c7_state(void) +{ + struct cpuidle_state *s = &tegra_idle_driver.states[TEGRA_C7]; + + s->enter_s2idle = tegra114_enter_s2idle; + s->target_residency = 1000; + s->exit_latency = 500; +} + static int tegra_cpuidle_probe(struct platform_device *pdev) { /* @@ -284,7 +317,9 @@ static int tegra_cpuidle_probe(struct platform_device *pdev) * is disabled. */ if (!IS_ENABLED(CONFIG_PM_SLEEP)) { - tegra_idle_driver.states[TEGRA_C7].disabled = true; + if (!tegra_cpuidle_using_firmware()) + tegra_idle_driver.states[TEGRA_C7].disabled = true; + tegra_idle_driver.states[TEGRA_CC6].disabled = true; } @@ -299,6 +334,13 @@ static int tegra_cpuidle_probe(struct platform_device *pdev) break; case TEGRA30: break; + case TEGRA114: + case TEGRA124: + tegra_cpuidle_setup_tegra114_c7_state(); + + /* coupled CC6 (LP2) state isn't implemented yet */ + tegra_idle_driver.states[TEGRA_CC6].disabled = true; + break; default: return -EINVAL; } From patchwork Tue Oct 15 17:00:14 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Dmitry Osipenko X-Patchwork-Id: 11191255 Return-Path: Received: from mail.kernel.org (pdx-korg-mail-1.web.codeaurora.org [172.30.200.123]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id 121D31668 for ; Tue, 15 Oct 2019 17:02:23 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.kernel.org (Postfix) with ESMTP id E5762218DE for ; Tue, 15 Oct 2019 17:02:22 +0000 (UTC) Authentication-Results: mail.kernel.org; dkim=pass (2048-bit key) header.d=gmail.com header.i=@gmail.com header.b="PIG2Les4" Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S2388560AbfJORCA (ORCPT ); Tue, 15 Oct 2019 13:02:00 -0400 Received: from mail-lf1-f68.google.com ([209.85.167.68]:35037 "EHLO mail-lf1-f68.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S2388546AbfJORB7 (ORCPT ); Tue, 15 Oct 2019 13:01:59 -0400 Received: by mail-lf1-f68.google.com with SMTP id w6so15080510lfl.2; Tue, 15 Oct 2019 10:01:57 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=mx03JaUQ9G9VpAUwSu0CjLskQfozJmwIlVovMAmKChM=; b=PIG2Les45wYklyfs/SVsxXfYiVm3RlxCFb6PPOZtF6Td2EJLhdXjxPbrvMcT+pxRHe 2mz/C4H7igKZ0DaDmcPs9NlN0cu5KM7LYruGgeY4GNDGpMPNyKBDR/8MDLSWFAAEDeEj vXZea1pU0cMDqGB2CEcKIgafpjlz9pWJI1Ne1G1qY4/f8cTvDo1bL4OWMVRo4O1R7D7D YoPduTEM/6aIJAih3R61xYjWNoVpW77JxrTb5dKx70v8+tmWm4AHNVGspcjbKNfTwaNe Qsa4Wam05NxAeywoGk2/+D0GpU8t2pJywD1xlDlZnSyECbb46c9pexGynKvbTn1rvp8t 4ysQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=mx03JaUQ9G9VpAUwSu0CjLskQfozJmwIlVovMAmKChM=; b=C6rGIyh/PBtyN6KgtF81x+w4I225HHurdeYKl/EJhoqoxKaj7uNVrrCG+r8sbSAGAg bqABmyYCI0a7jBfz3iknuKg4ROqjdGrP1ORffqTM8Ue1Qzsq7vVU98dMbLzZyBFmek4E Mv7kf2v5dywPzeqpfRyf0jTN/xiI5ge3WGuMiPSeElC+vBkjLLGLA1RF6JZY1y2u2VmN VufjPMVPm76Yj5kS2HUBKku0po4kRQsnXYz7uRl2Yt81ZyI9rhDvR8Lpk/2R0zeDXlFh oUNdbLClKNG44LQX4S19gyeneQ96CMplvjblwJ4gQsu7VdgZEakt0GV3ZcgSLpj36whG PORw== X-Gm-Message-State: APjAAAWsh/Mzt75D2ZwcaL62vM6B0VJLPCMSe9jlqncAtyYwUoZehEZE OjqIsLdwq04ui3j7R9C0JQM= X-Google-Smtp-Source: APXvYqxMxBYG20YAb0fGS9TNYIAzXvzBRSWDTBvLt0Guvr9miFOHDHZbOAnwwUO/6vaYt/HcZhnttQ== X-Received: by 2002:a19:855:: with SMTP id 82mr2714520lfi.44.1571158916970; Tue, 15 Oct 2019 10:01:56 -0700 (PDT) Received: from localhost.localdomain ([94.29.10.250]) by smtp.gmail.com with ESMTPSA id t6sm5144992ljd.102.2019.10.15.10.01.55 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 15 Oct 2019 10:01:56 -0700 (PDT) From: Dmitry Osipenko To: Thierry Reding , Jonathan Hunter , Peter De Schrijver , "Rafael J. Wysocki" , Daniel Lezcano Cc: linux-pm@vger.kernel.org, linux-tegra@vger.kernel.org, linux-kernel@vger.kernel.org Subject: [PATCH v6 17/18] ARM: multi_v7_defconfig: Enable Tegra cpuidle driver Date: Tue, 15 Oct 2019 20:00:14 +0300 Message-Id: <20191015170015.1135-18-digetx@gmail.com> X-Mailer: git-send-email 2.23.0 In-Reply-To: <20191015170015.1135-1-digetx@gmail.com> References: <20191015170015.1135-1-digetx@gmail.com> MIME-Version: 1.0 Sender: linux-pm-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-pm@vger.kernel.org The Tegra CPU Idle driver was moved out into driver/cpuidle/ directory and it is now a proper platform driver. Signed-off-by: Dmitry Osipenko --- arch/arm/configs/multi_v7_defconfig | 1 + 1 file changed, 1 insertion(+) diff --git a/arch/arm/configs/multi_v7_defconfig b/arch/arm/configs/multi_v7_defconfig index e039680d3c72..e15cc31aeaf3 100644 --- a/arch/arm/configs/multi_v7_defconfig +++ b/arch/arm/configs/multi_v7_defconfig @@ -110,6 +110,7 @@ CONFIG_CPU_IDLE=y CONFIG_ARM_CPUIDLE=y CONFIG_ARM_ZYNQ_CPUIDLE=y CONFIG_ARM_EXYNOS_CPUIDLE=y +CONFIG_ARM_TEGRA_CPUIDLE=y CONFIG_KERNEL_MODE_NEON=y CONFIG_RASPBERRYPI_FIRMWARE=y CONFIG_TRUSTED_FOUNDATIONS=y From patchwork Tue Oct 15 17:00:15 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Dmitry Osipenko X-Patchwork-Id: 11191251 Return-Path: Received: from mail.kernel.org (pdx-korg-mail-1.web.codeaurora.org [172.30.200.123]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id 760531390 for ; Tue, 15 Oct 2019 17:02:21 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.kernel.org (Postfix) with ESMTP id 54E0820872 for ; Tue, 15 Oct 2019 17:02:21 +0000 (UTC) Authentication-Results: mail.kernel.org; dkim=pass (2048-bit key) header.d=gmail.com header.i=@gmail.com header.b="I0uSfxw7" Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S2388572AbfJORCB (ORCPT ); Tue, 15 Oct 2019 13:02:01 -0400 Received: from mail-lf1-f68.google.com ([209.85.167.68]:40181 "EHLO mail-lf1-f68.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S2388553AbfJORCA (ORCPT ); Tue, 15 Oct 2019 13:02:00 -0400 Received: by mail-lf1-f68.google.com with SMTP id d17so15077526lfa.7; Tue, 15 Oct 2019 10:01:59 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=0lHQRX/0nej0WuuBggHgivhPJMPJeSRnbCLnwWmZEkg=; b=I0uSfxw7E6O85wleD5CO8/aLWXAEpIhpGNZ4IdvldsuHrbgDFfGSzoJek714RHNVNA qDeHjnKxKWfm60TcwVnlqhLaxutweNOskPuxwG2FlJAzGZ+0PylA4s7xK98x/tbWKIc3 LULTwzyrdRbP/r5yZiL27fEAlNzeObyJsOvDiXpKXsUom/ZmAgar/JG0hTairjr+NBU0 ZfnFnSfqHsfYKws1oGO7TWpo/iz6zFKCP3v4bBQZ3OTEk+y4YckpL4DsifNEWRwjLKrP JyP9DCSrTX5Dp/l4dnotzvm1sqMuAqTgLhGqMl0hY3TJuLtfTJv+mAuVMOaQF0tOMXEp bZvA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=0lHQRX/0nej0WuuBggHgivhPJMPJeSRnbCLnwWmZEkg=; b=m5dCwSqGXfvb/7KqdOqQsDTHu6/l21wIbNg9z6F+qa7w3ioC1PP9iwNlA5SnGWbd0B mxo1u0W8UXUFFB34b4za+v7bnYHpBy4WHcWAKQkYDZrSezPLAM8F32lt1jTuMpT5MI+R 18QuoigwiRKzeRgUHCD6f0YtjDOucCVZZAOVVE+J0pSByvwwcrIj9O4xuXY5H8XDhgtQ py8YVB2/Tp5YWXOjnRLnwuXXlPMW7crIQ1m2Y1R21OcrzDQWu7hjw2p6M/G1cm0UQJH9 1v0+gjtAdLq24YNFB7fXdB3DTM12LvEFJhaoUxLkFdy0d7AUIQ3knYnuB/OxD2vHkr1f hSeQ== X-Gm-Message-State: APjAAAWrSNAJZg2j3yyxvFp1tvxvXVhKPaSuS9aSgmHV5eRB1I5/inDl Q1xYRWsB2sIGxzaTQ18tC/s= X-Google-Smtp-Source: APXvYqznpEti9qfmzCeGOL24bxtmbcLEOCVrfTdn3PE4L4pNOoxytWOTRLVSglovOOV/v40G2x1D0w== X-Received: by 2002:a19:6f0e:: with SMTP id k14mr22038282lfc.79.1571158918342; Tue, 15 Oct 2019 10:01:58 -0700 (PDT) Received: from localhost.localdomain ([94.29.10.250]) by smtp.gmail.com with ESMTPSA id t6sm5144992ljd.102.2019.10.15.10.01.56 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 15 Oct 2019 10:01:57 -0700 (PDT) From: Dmitry Osipenko To: Thierry Reding , Jonathan Hunter , Peter De Schrijver , "Rafael J. Wysocki" , Daniel Lezcano Cc: linux-pm@vger.kernel.org, linux-tegra@vger.kernel.org, linux-kernel@vger.kernel.org Subject: [PATCH v6 18/18] ARM: tegra: Enable Tegra cpuidle driver in tegra_defconfig Date: Tue, 15 Oct 2019 20:00:15 +0300 Message-Id: <20191015170015.1135-19-digetx@gmail.com> X-Mailer: git-send-email 2.23.0 In-Reply-To: <20191015170015.1135-1-digetx@gmail.com> References: <20191015170015.1135-1-digetx@gmail.com> MIME-Version: 1.0 Sender: linux-pm-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-pm@vger.kernel.org The Tegra CPU Idle driver was moved out into driver/cpuidle/ directory and it is now a proper platform driver. Signed-off-by: Dmitry Osipenko --- arch/arm/configs/tegra_defconfig | 1 + 1 file changed, 1 insertion(+) diff --git a/arch/arm/configs/tegra_defconfig b/arch/arm/configs/tegra_defconfig index 8f5c6a5b444c..9a2f11a780a8 100644 --- a/arch/arm/configs/tegra_defconfig +++ b/arch/arm/configs/tegra_defconfig @@ -25,6 +25,7 @@ CONFIG_CPU_FREQ=y CONFIG_CPU_FREQ_DEFAULT_GOV_ONDEMAND=y CONFIG_CPUFREQ_DT=y CONFIG_CPU_IDLE=y +CONFIG_ARM_TEGRA_CPUIDLE=y CONFIG_VFP=y CONFIG_NEON=y CONFIG_TRUSTED_FOUNDATIONS=y